1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2008 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 /**
29  *
30  * This header file defines the work queue entry (wqe) data structure.
31  * Since this is a commonly used structure that depends on structures
32  * from several hardware blocks, those definitions have been placed
33  * in this file to create a single point of definition of the wqe
34  * format.
35  * Data structures are still named according to the block that they
36  * relate to.
37  *
38  */
39 
40 #ifndef __CVMX_WQE_H__
41 #define __CVMX_WQE_H__
42 
43 #include <asm/octeon/cvmx-packet.h>
44 
45 
46 #define OCT_TAG_TYPE_STRING(x)						\
47 	(((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" :		\
48 		(((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" :	\
49 			(((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" :	\
50 				"NULL_NULL")))
51 
52 /**
53  * HW decode / err_code in work queue entry
54  */
55 typedef union {
56 	uint64_t u64;
57 
58 	/* Use this struct if the hardware determines that the packet is IP */
59 	struct {
60 #ifdef __BIG_ENDIAN_BITFIELD
61 		/* HW sets this to the number of buffers used by this packet */
62 		uint64_t bufs:8;
63 		/* HW sets to the number of L2 bytes prior to the IP */
64 		uint64_t ip_offset:8;
65 		/* set to 1 if we found DSA/VLAN in the L2 */
66 		uint64_t vlan_valid:1;
67 		/* Set to 1 if the DSA/VLAN tag is stacked */
68 		uint64_t vlan_stacked:1;
69 		uint64_t unassigned:1;
70 		/* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
71 		uint64_t vlan_cfi:1;
72 		/* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
73 		uint64_t vlan_id:12;
74 		/* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
75 		uint64_t pr:4;
76 		uint64_t unassigned2:8;
77 		/* the packet needs to be decompressed */
78 		uint64_t dec_ipcomp:1;
79 		/* the packet is either TCP or UDP */
80 		uint64_t tcp_or_udp:1;
81 		/* the packet needs to be decrypted (ESP or AH) */
82 		uint64_t dec_ipsec:1;
83 		/* the packet is IPv6 */
84 		uint64_t is_v6:1;
85 
86 		/*
87 		 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
88 		 * software, etc.).
89 		 */
90 
91 		/*
92 		 * reserved for software use, hardware will clear on
93 		 * packet creation.
94 		 */
95 		uint64_t software:1;
96 		/* exceptional conditions below */
97 		/* the receive interface hardware detected an L4 error
98 		 * (only applies if !is_frag) (only applies if
99 		 * !rcv_error && !not_IP && !IP_exc && !is_frag)
100 		 * failure indicated in err_code below, decode:
101 		 *
102 		 * - 1 = Malformed L4
103 		 * - 2 = L4 Checksum Error: the L4 checksum value is
104 		 * - 3 = UDP Length Error: The UDP length field would
105 		 *	 make the UDP data longer than what remains in
106 		 *	 the IP packet (as defined by the IP header
107 		 *	 length field).
108 		 * - 4 = Bad L4 Port: either the source or destination
109 		 *	 TCP/UDP port is 0.
110 		 * - 8 = TCP FIN Only: the packet is TCP and only the
111 		 *	 FIN flag set.
112 		 * - 9 = TCP No Flags: the packet is TCP and no flags
113 		 *	 are set.
114 		 * - 10 = TCP FIN RST: the packet is TCP and both FIN
115 		 *	  and RST are set.
116 		 * - 11 = TCP SYN URG: the packet is TCP and both SYN
117 		 *	  and URG are set.
118 		 * - 12 = TCP SYN RST: the packet is TCP and both SYN
119 		 *	  and RST are set.
120 		 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
121 		 *	  and FIN are set.
122 		 */
123 		uint64_t L4_error:1;
124 		/* set if the packet is a fragment */
125 		uint64_t is_frag:1;
126 		/* the receive interface hardware detected an IP error
127 		 * / exception (only applies if !rcv_error && !not_IP)
128 		 * failure indicated in err_code below, decode:
129 		 *
130 		 * - 1 = Not IP: the IP version field is neither 4 nor
131 		 *	 6.
132 		 * - 2 = IPv4 Header Checksum Error: the IPv4 header
133 		 *	 has a checksum violation.
134 		 * - 3 = IP Malformed Header: the packet is not long
135 		 *	 enough to contain the IP header.
136 		 * - 4 = IP Malformed: the packet is not long enough
137 		 *	 to contain the bytes indicated by the IP
138 		 *	 header. Pad is allowed.
139 		 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
140 		 *	 Hop Count field are zero.
141 		 * - 6 = IP Options
142 		 */
143 		uint64_t IP_exc:1;
144 		/*
145 		 * Set if the hardware determined that the packet is a
146 		 * broadcast.
147 		 */
148 		uint64_t is_bcast:1;
149 		/*
150 		 * St if the hardware determined that the packet is a
151 		 * multi-cast.
152 		 */
153 		uint64_t is_mcast:1;
154 		/*
155 		 * Set if the packet may not be IP (must be zero in
156 		 * this case).
157 		 */
158 		uint64_t not_IP:1;
159 		/*
160 		 * The receive interface hardware detected a receive
161 		 * error (must be zero in this case).
162 		 */
163 		uint64_t rcv_error:1;
164 		/* lower err_code = first-level descriptor of the
165 		 * work */
166 		/* zero for packet submitted by hardware that isn't on
167 		 * the slow path */
168 		/* type is cvmx_pip_err_t */
169 		uint64_t err_code:8;
170 #else
171 	        uint64_t err_code:8;
172 	        uint64_t rcv_error:1;
173 	        uint64_t not_IP:1;
174 	        uint64_t is_mcast:1;
175 	        uint64_t is_bcast:1;
176 	        uint64_t IP_exc:1;
177 	        uint64_t is_frag:1;
178 	        uint64_t L4_error:1;
179 	        uint64_t software:1;
180 	        uint64_t is_v6:1;
181 	        uint64_t dec_ipsec:1;
182 	        uint64_t tcp_or_udp:1;
183 	        uint64_t dec_ipcomp:1;
184 	        uint64_t unassigned2:4;
185 	        uint64_t unassigned2a:4;
186 	        uint64_t pr:4;
187 	        uint64_t vlan_id:12;
188 	        uint64_t vlan_cfi:1;
189 	        uint64_t unassigned:1;
190 	        uint64_t vlan_stacked:1;
191 	        uint64_t vlan_valid:1;
192 	        uint64_t ip_offset:8;
193 	        uint64_t bufs:8;
194 #endif
195 	} s;
196 	struct {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 		uint64_t bufs:8;
199 		uint64_t ip_offset:8;
200 		uint64_t vlan_valid:1;
201 		uint64_t vlan_stacked:1;
202 		uint64_t unassigned:1;
203 		uint64_t vlan_cfi:1;
204 		uint64_t vlan_id:12;
205 		uint64_t port:12;		/* MAC/PIP port number. */
206 		uint64_t dec_ipcomp:1;
207 		uint64_t tcp_or_udp:1;
208 		uint64_t dec_ipsec:1;
209 		uint64_t is_v6:1;
210 		uint64_t software:1;
211 		uint64_t L4_error:1;
212 		uint64_t is_frag:1;
213 		uint64_t IP_exc:1;
214 		uint64_t is_bcast:1;
215 		uint64_t is_mcast:1;
216 		uint64_t not_IP:1;
217 		uint64_t rcv_error:1;
218 		uint64_t err_code:8;
219 #else
220 		uint64_t err_code:8;
221 		uint64_t rcv_error:1;
222 		uint64_t not_IP:1;
223 		uint64_t is_mcast:1;
224 		uint64_t is_bcast:1;
225 		uint64_t IP_exc:1;
226 		uint64_t is_frag:1;
227 		uint64_t L4_error:1;
228 		uint64_t software:1;
229 		uint64_t is_v6:1;
230 		uint64_t dec_ipsec:1;
231 		uint64_t tcp_or_udp:1;
232 		uint64_t dec_ipcomp:1;
233 		uint64_t port:12;
234 		uint64_t vlan_id:12;
235 		uint64_t vlan_cfi:1;
236 		uint64_t unassigned:1;
237 		uint64_t vlan_stacked:1;
238 		uint64_t vlan_valid:1;
239 		uint64_t ip_offset:8;
240 		uint64_t bufs:8;
241 #endif
242 	} s_cn68xx;
243 
244 	/* use this to get at the 16 vlan bits */
245 	struct {
246 #ifdef __BIG_ENDIAN_BITFIELD
247 		uint64_t unused1:16;
248 		uint64_t vlan:16;
249 		uint64_t unused2:32;
250 #else
251 	        uint64_t unused2:32;
252 	        uint64_t vlan:16;
253 	        uint64_t unused1:16;
254 
255 #endif
256 	} svlan;
257 
258 	/*
259 	 * use this struct if the hardware could not determine that
260 	 * the packet is ip.
261 	 */
262 	struct {
263 #ifdef __BIG_ENDIAN_BITFIELD
264 		/*
265 		 * HW sets this to the number of buffers used by this
266 		 * packet.
267 		 */
268 		uint64_t bufs:8;
269 		uint64_t unused:8;
270 		/* set to 1 if we found DSA/VLAN in the L2 */
271 		uint64_t vlan_valid:1;
272 		/* Set to 1 if the DSA/VLAN tag is stacked */
273 		uint64_t vlan_stacked:1;
274 		uint64_t unassigned:1;
275 		/*
276 		 * HW sets to the DSA/VLAN CFI flag (valid when
277 		 * vlan_valid)
278 		 */
279 		uint64_t vlan_cfi:1;
280 		/*
281 		 * HW sets to the DSA/VLAN_ID field (valid when
282 		 * vlan_valid).
283 		 */
284 		uint64_t vlan_id:12;
285 		/*
286 		 * Ring Identifier (if PCIe). Requires
287 		 * PIP_GBL_CTL[RING_EN]=1
288 		 */
289 		uint64_t pr:4;
290 		uint64_t unassigned2:12;
291 		/*
292 		 * reserved for software use, hardware will clear on
293 		 * packet creation.
294 		 */
295 		uint64_t software:1;
296 		uint64_t unassigned3:1;
297 		/*
298 		 * set if the hardware determined that the packet is
299 		 * rarp.
300 		 */
301 		uint64_t is_rarp:1;
302 		/*
303 		 * set if the hardware determined that the packet is
304 		 * arp
305 		 */
306 		uint64_t is_arp:1;
307 		/*
308 		 * set if the hardware determined that the packet is a
309 		 * broadcast.
310 		 */
311 		uint64_t is_bcast:1;
312 		/*
313 		 * set if the hardware determined that the packet is a
314 		 * multi-cast
315 		 */
316 		uint64_t is_mcast:1;
317 		/*
318 		 * set if the packet may not be IP (must be one in
319 		 * this case)
320 		 */
321 		uint64_t not_IP:1;
322 		/* The receive interface hardware detected a receive
323 		 * error.  Failure indicated in err_code below,
324 		 * decode:
325 		 *
326 		 * - 1 = partial error: a packet was partially
327 		 *	 received, but internal buffering / bandwidth
328 		 *	 was not adequate to receive the entire
329 		 *	 packet.
330 		 * - 2 = jabber error: the RGMII packet was too large
331 		 *	 and is truncated.
332 		 * - 3 = overrun error: the RGMII packet is longer
333 		 *	 than allowed and had an FCS error.
334 		 * - 4 = oversize error: the RGMII packet is longer
335 		 *	 than allowed.
336 		 * - 5 = alignment error: the RGMII packet is not an
337 		 *	 integer number of bytes
338 		 *	 and had an FCS error (100M and 10M only).
339 		 * - 6 = fragment error: the RGMII packet is shorter
340 		 *	 than allowed and had an FCS error.
341 		 * - 7 = GMX FCS error: the RGMII packet had an FCS
342 		 *	 error.
343 		 * - 8 = undersize error: the RGMII packet is shorter
344 		 *	 than allowed.
345 		 * - 9 = extend error: the RGMII packet had an extend
346 		 *	 error.
347 		 * - 10 = length mismatch error: the RGMII packet had
348 		 *	  a length that did not match the length field
349 		 *	  in the L2 HDR.
350 		 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
351 		 *	  packet had one or more data reception errors
352 		 *	  (RXERR) or the SPI4 packet had one or more
353 		 *	  DIP4 errors.
354 		 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
355 		 *	  packet was not large enough to cover the
356 		 *	  skipped bytes or the SPI4 packet was
357 		 *	  terminated with an About EOPS.
358 		 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
359 		 *	  RGMII packet had a studder error (data not
360 		 *	  repeated - 10/100M only) or the SPI4 packet
361 		 *	  was sent to an NXA.
362 		 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
363 		 * - 17 = Skip error: a packet was not large enough to
364 		 *	  cover the skipped bytes.
365 		 * - 18 = L2 header malformed: the packet is not long
366 		 *	  enough to contain the L2.
367 		 */
368 
369 		uint64_t rcv_error:1;
370 		/*
371 		 * lower err_code = first-level descriptor of the
372 		 * work
373 		 */
374 		/*
375 		 * zero for packet submitted by hardware that isn't on
376 		 * the slow path
377 		 */
378 		/* type is cvmx_pip_err_t (union, so can't use directly */
379 		uint64_t err_code:8;
380 #else
381 	        uint64_t err_code:8;
382 	        uint64_t rcv_error:1;
383 	        uint64_t not_IP:1;
384 	        uint64_t is_mcast:1;
385 	        uint64_t is_bcast:1;
386 	        uint64_t is_arp:1;
387 	        uint64_t is_rarp:1;
388 	        uint64_t unassigned3:1;
389 	        uint64_t software:1;
390 	        uint64_t unassigned2:4;
391 	        uint64_t unassigned2a:8;
392 	        uint64_t pr:4;
393 	        uint64_t vlan_id:12;
394 	        uint64_t vlan_cfi:1;
395 	        uint64_t unassigned:1;
396 	        uint64_t vlan_stacked:1;
397 	        uint64_t vlan_valid:1;
398 	        uint64_t unused:8;
399 	        uint64_t bufs:8;
400 #endif
401 	} snoip;
402 
403 } cvmx_pip_wqe_word2;
404 
405 union cvmx_pip_wqe_word0 {
406 	struct {
407 #ifdef __BIG_ENDIAN_BITFIELD
408 		/**
409 		 * raw chksum result generated by the HW
410 		 */
411 		uint16_t hw_chksum;
412 		/**
413 		 * Field unused by hardware - available for software
414 		 */
415 		uint8_t unused;
416 		/**
417 		 * Next pointer used by hardware for list maintenance.
418 		 * May be written/read by HW before the work queue
419 		 * entry is scheduled to a PP (Only 36 bits used in
420 		 * Octeon 1)
421 		 */
422 		uint64_t next_ptr:40;
423 #else
424 		uint64_t next_ptr:40;
425 		uint8_t unused;
426 		uint16_t hw_chksum;
427 #endif
428 	} cn38xx;
429 	struct {
430 #ifdef __BIG_ENDIAN_BITFIELD
431 		uint64_t l4ptr:8;       /* 56..63 */
432 		uint64_t unused0:8;     /* 48..55 */
433 		uint64_t l3ptr:8;       /* 40..47 */
434 		uint64_t l2ptr:8;       /* 32..39 */
435 		uint64_t unused1:18;    /* 14..31 */
436 		uint64_t bpid:6;        /* 8..13 */
437 		uint64_t unused2:2;     /* 6..7 */
438 		uint64_t pknd:6;        /* 0..5 */
439 #else
440 		uint64_t pknd:6;        /* 0..5 */
441 		uint64_t unused2:2;     /* 6..7 */
442 		uint64_t bpid:6;        /* 8..13 */
443 		uint64_t unused1:18;    /* 14..31 */
444 		uint64_t l2ptr:8;       /* 32..39 */
445 		uint64_t l3ptr:8;       /* 40..47 */
446 		uint64_t unused0:8;     /* 48..55 */
447 		uint64_t l4ptr:8;       /* 56..63 */
448 #endif
449 	} cn68xx;
450 };
451 
452 union cvmx_wqe_word0 {
453 	uint64_t u64;
454 	union cvmx_pip_wqe_word0 pip;
455 };
456 
457 union cvmx_wqe_word1 {
458 	uint64_t u64;
459 	struct {
460 #ifdef __BIG_ENDIAN_BITFIELD
461 		uint64_t len:16;
462 		uint64_t varies:14;
463 		/**
464 		 * the type of the tag (ORDERED, ATOMIC, NULL)
465 		 */
466 		uint64_t tag_type:2;
467 		uint64_t tag:32;
468 #else
469 		uint64_t tag:32;
470 		uint64_t tag_type:2;
471 		uint64_t varies:14;
472 		uint64_t len:16;
473 #endif
474 	};
475 	struct {
476 #ifdef __BIG_ENDIAN_BITFIELD
477 		uint64_t len:16;
478 		uint64_t zero_0:1;
479 		/**
480 		 * HW sets this to what it thought the priority of
481 		 * the input packet was
482 		 */
483 		uint64_t qos:3;
484 
485 		uint64_t zero_1:1;
486 		/**
487 		 * the group that the work queue entry will be scheduled to
488 		 */
489 		uint64_t grp:6;
490 		uint64_t zero_2:3;
491 		uint64_t tag_type:2;
492 		uint64_t tag:32;
493 #else
494 		uint64_t tag:32;
495 		uint64_t tag_type:2;
496 		uint64_t zero_2:3;
497 		uint64_t grp:6;
498 		uint64_t zero_1:1;
499 		uint64_t qos:3;
500 		uint64_t zero_0:1;
501 		uint64_t len:16;
502 #endif
503 	} cn68xx;
504 	struct {
505 #ifdef __BIG_ENDIAN_BITFIELD
506 		/**
507 		 * HW sets to the total number of bytes in the packet
508 		 */
509 		uint64_t len:16;
510 		/**
511 		 * HW sets this to input physical port
512 		 */
513 		uint64_t ipprt:6;
514 
515 		/**
516 		 * HW sets this to what it thought the priority of
517 		 * the input packet was
518 		 */
519 		uint64_t qos:3;
520 
521 		/**
522 		 * the group that the work queue entry will be scheduled to
523 		 */
524 		uint64_t grp:4;
525 		/**
526 		 * the type of the tag (ORDERED, ATOMIC, NULL)
527 		 */
528 		uint64_t tag_type:3;
529 		/**
530 		 * the synchronization/ordering tag
531 		 */
532 		uint64_t tag:32;
533 #else
534 		uint64_t tag:32;
535 		uint64_t tag_type:2;
536 		uint64_t zero_2:1;
537 		uint64_t grp:4;
538 		uint64_t qos:3;
539 		uint64_t ipprt:6;
540 		uint64_t len:16;
541 #endif
542 	} cn38xx;
543 };
544 
545 /**
546  * Work queue entry format
547  *
548  * must be 8-byte aligned
549  */
550 struct cvmx_wqe {
551 
552     /*****************************************************************
553      * WORD 0
554      *	HW WRITE: the following 64 bits are filled by HW when a packet arrives
555      */
556 	union cvmx_wqe_word0 word0;
557 
558     /*****************************************************************
559      * WORD 1
560      *	HW WRITE: the following 64 bits are filled by HW when a packet arrives
561      */
562 	union cvmx_wqe_word1 word1;
563 
564     /**
565      * WORD 2 HW WRITE: the following 64-bits are filled in by
566      *	 hardware when a packet arrives This indicates a variety of
567      *	 status and error conditions.
568      */
569 	cvmx_pip_wqe_word2 word2;
570 
571     /**
572      * Pointer to the first segment of the packet.
573      */
574 	union cvmx_buf_ptr packet_ptr;
575 
576     /**
577      *	 HW WRITE: octeon will fill in a programmable amount from the
578      *		   packet, up to (at most, but perhaps less) the amount
579      *		   needed to fill the work queue entry to 128 bytes
580      *
581      *	 If the packet is recognized to be IP, the hardware starts
582      *	 (except that the IPv4 header is padded for appropriate
583      *	 alignment) writing here where the IP header starts.  If the
584      *	 packet is not recognized to be IP, the hardware starts
585      *	 writing the beginning of the packet here.
586      */
587 	uint8_t packet_data[96];
588 
589     /**
590      * If desired, SW can make the work Q entry any length. For the
591      * purposes of discussion here, Assume 128B always, as this is all that
592      * the hardware deals with.
593      *
594      */
595 
596 } CVMX_CACHE_LINE_ALIGNED;
597 
cvmx_wqe_get_port(struct cvmx_wqe * work)598 static inline int cvmx_wqe_get_port(struct cvmx_wqe *work)
599 {
600 	int port;
601 
602 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
603 		port = work->word2.s_cn68xx.port;
604 	else
605 		port = work->word1.cn38xx.ipprt;
606 
607 	return port;
608 }
609 
cvmx_wqe_set_port(struct cvmx_wqe * work,int port)610 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
611 {
612 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
613 		work->word2.s_cn68xx.port = port;
614 	else
615 		work->word1.cn38xx.ipprt = port;
616 }
617 
cvmx_wqe_get_grp(struct cvmx_wqe * work)618 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
619 {
620 	int grp;
621 
622 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
623 		grp = work->word1.cn68xx.grp;
624 	else
625 		grp = work->word1.cn38xx.grp;
626 
627 	return grp;
628 }
629 
cvmx_wqe_set_grp(struct cvmx_wqe * work,int grp)630 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
631 {
632 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
633 		work->word1.cn68xx.grp = grp;
634 	else
635 		work->word1.cn38xx.grp = grp;
636 }
637 
cvmx_wqe_get_qos(struct cvmx_wqe * work)638 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
639 {
640 	int qos;
641 
642 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
643 		qos = work->word1.cn68xx.qos;
644 	else
645 		qos = work->word1.cn38xx.qos;
646 
647 	return qos;
648 }
649 
cvmx_wqe_set_qos(struct cvmx_wqe * work,int qos)650 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
651 {
652 	if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
653 		work->word1.cn68xx.qos = qos;
654 	else
655 		work->word1.cn38xx.qos = qos;
656 }
657 
658 #endif /* __CVMX_WQE_H__ */
659