1 // Copyright 2024, Linaro Limited 2 // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 // 5 // PL011 QEMU Device Model 6 // 7 // This library implements a device model for the PrimeCell® UART (PL011) 8 // device in QEMU. 9 // 10 #![doc = include_str!("../README.md")] 11 //! # Library crate 12 //! 13 //! See [`PL011State`](crate::device::PL011State) for the device model type and 14 //! the [`registers`] module for register types. 15 16 #![deny( 17 rustdoc::broken_intra_doc_links, 18 rustdoc::redundant_explicit_links, 19 clippy::correctness, 20 clippy::suspicious, 21 clippy::complexity, 22 clippy::perf, 23 clippy::cargo, 24 clippy::nursery, 25 clippy::style, 26 // restriction group 27 clippy::dbg_macro, 28 clippy::as_underscore, 29 clippy::assertions_on_result_states, 30 // pedantic group 31 clippy::doc_markdown, 32 clippy::borrow_as_ptr, 33 clippy::cast_lossless, 34 clippy::option_if_let_else, 35 clippy::missing_const_for_fn, 36 clippy::cognitive_complexity, 37 clippy::missing_safety_doc, 38 )] 39 #![allow(clippy::result_unit_err)] 40 41 extern crate bilge; 42 extern crate bilge_impl; 43 extern crate qemu_api; 44 45 use qemu_api::c_str; 46 47 pub mod device; 48 pub mod device_class; 49 pub mod memory_ops; 50 51 pub const TYPE_PL011: &::std::ffi::CStr = c_str!("pl011"); 52 pub const TYPE_PL011_LUMINARY: &::std::ffi::CStr = c_str!("pl011_luminary"); 53 54 /// Offset of each register from the base memory address of the device. 55 /// 56 /// # Source 57 /// ARM DDI 0183G, Table 3-1 p.3-3 58 #[doc(alias = "offset")] 59 #[allow(non_camel_case_types)] 60 #[repr(u64)] 61 #[derive(Debug)] 62 pub enum RegisterOffset { 63 /// Data Register 64 /// 65 /// A write to this register initiates the actual data transmission 66 #[doc(alias = "UARTDR")] 67 DR = 0x000, 68 /// Receive Status Register or Error Clear Register 69 #[doc(alias = "UARTRSR")] 70 #[doc(alias = "UARTECR")] 71 RSR = 0x004, 72 /// Flag Register 73 /// 74 /// A read of this register shows if transmission is complete 75 #[doc(alias = "UARTFR")] 76 FR = 0x018, 77 /// Fractional Baud Rate Register 78 /// 79 /// responsible for baud rate speed 80 #[doc(alias = "UARTFBRD")] 81 FBRD = 0x028, 82 /// `IrDA` Low-Power Counter Register 83 #[doc(alias = "UARTILPR")] 84 ILPR = 0x020, 85 /// Integer Baud Rate Register 86 /// 87 /// Responsible for baud rate speed 88 #[doc(alias = "UARTIBRD")] 89 IBRD = 0x024, 90 /// line control register (data frame format) 91 #[doc(alias = "UARTLCR_H")] 92 LCR_H = 0x02C, 93 /// Toggle UART, transmission or reception 94 #[doc(alias = "UARTCR")] 95 CR = 0x030, 96 /// Interrupt FIFO Level Select Register 97 #[doc(alias = "UARTIFLS")] 98 FLS = 0x034, 99 /// Interrupt Mask Set/Clear Register 100 #[doc(alias = "UARTIMSC")] 101 IMSC = 0x038, 102 /// Raw Interrupt Status Register 103 #[doc(alias = "UARTRIS")] 104 RIS = 0x03C, 105 /// Masked Interrupt Status Register 106 #[doc(alias = "UARTMIS")] 107 MIS = 0x040, 108 /// Interrupt Clear Register 109 #[doc(alias = "UARTICR")] 110 ICR = 0x044, 111 /// DMA control Register 112 #[doc(alias = "UARTDMACR")] 113 DMACR = 0x048, 114 ///// Reserved, offsets `0x04C` to `0x07C`. 115 //Reserved = 0x04C, 116 } 117 118 impl core::convert::TryFrom<u64> for RegisterOffset { 119 type Error = u64; 120 try_from(value: u64) -> Result<Self, Self::Error>121 fn try_from(value: u64) -> Result<Self, Self::Error> { 122 macro_rules! case { 123 ($($discriminant:ident),*$(,)*) => { 124 /* check that matching on all macro arguments compiles, which means we are not 125 * missing any enum value; if the type definition ever changes this will stop 126 * compiling. 127 */ 128 const fn _assert_exhaustive(val: RegisterOffset) { 129 match val { 130 $(RegisterOffset::$discriminant => (),)* 131 } 132 } 133 134 match value { 135 $(x if x == Self::$discriminant as u64 => Ok(Self::$discriminant),)* 136 _ => Err(value), 137 } 138 } 139 } 140 case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR } 141 } 142 } 143 144 pub mod registers { 145 //! Device registers exposed as typed structs which are backed by arbitrary 146 //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. 147 //! 148 //! All PL011 registers are essentially 32-bit wide, but are typed here as 149 //! bitmaps with only the necessary width. That is, if a struct bitmap 150 //! in this module is for example 16 bits long, it should be conceived 151 //! as a 32-bit register where the unmentioned higher bits are always 152 //! unused thus treated as zero when read or written. 153 use bilge::prelude::*; 154 155 // TODO: FIFO Mode has different semantics 156 /// Data Register, `UARTDR` 157 /// 158 /// The `UARTDR` register is the data register. 159 /// 160 /// For words to be transmitted: 161 /// 162 /// - if the FIFOs are enabled, data written to this location is pushed onto 163 /// the transmit 164 /// FIFO 165 /// - if the FIFOs are not enabled, data is stored in the transmitter 166 /// holding register (the 167 /// bottom word of the transmit FIFO). 168 /// 169 /// The write operation initiates transmission from the UART. The data is 170 /// prefixed with a start bit, appended with the appropriate parity bit 171 /// (if parity is enabled), and a stop bit. The resultant word is then 172 /// transmitted. 173 /// 174 /// For received words: 175 /// 176 /// - if the FIFOs are enabled, the data byte and the 4-bit status (break, 177 /// frame, parity, 178 /// and overrun) is pushed onto the 12-bit wide receive FIFO 179 /// - if the FIFOs are not enabled, the data byte and status are stored in 180 /// the receiving 181 /// holding register (the bottom word of the receive FIFO). 182 /// 183 /// The received data byte is read by performing reads from the `UARTDR` 184 /// register along with the corresponding status information. The status 185 /// information can also be read by a read of the `UARTRSR/UARTECR` 186 /// register. 187 /// 188 /// # Note 189 /// 190 /// You must disable the UART before any of the control registers are 191 /// reprogrammed. When the UART is disabled in the middle of 192 /// transmission or reception, it completes the current character before 193 /// stopping. 194 /// 195 /// # Source 196 /// ARM DDI 0183G 3.3.1 Data Register, UARTDR 197 #[bitsize(16)] 198 #[derive(Clone, Copy, DebugBits, FromBits)] 199 #[doc(alias = "UARTDR")] 200 pub struct Data { 201 _reserved: u4, 202 pub data: u8, 203 pub framing_error: bool, 204 pub parity_error: bool, 205 pub break_error: bool, 206 pub overrun_error: bool, 207 } 208 209 // TODO: FIFO Mode has different semantics 210 /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` 211 /// 212 /// The UARTRSR/UARTECR register is the receive status register/error clear 213 /// register. Receive status can also be read from the `UARTRSR` 214 /// register. If the status is read from this register, then the status 215 /// information for break, framing and parity corresponds to the 216 /// data character read from the [Data register](Data), `UARTDR` prior to 217 /// reading the UARTRSR register. The status information for overrun is 218 /// set immediately when an overrun condition occurs. 219 /// 220 /// 221 /// # Note 222 /// The received data character must be read first from the [Data 223 /// Register](Data), `UARTDR` before reading the error status associated 224 /// with that data character from the `UARTRSR` register. This read 225 /// sequence cannot be reversed, because the `UARTRSR` register is 226 /// updated only when a read occurs from the `UARTDR` register. However, 227 /// the status information can also be obtained by reading the `UARTDR` 228 /// register 229 /// 230 /// # Source 231 /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, 232 /// UARTRSR/UARTECR 233 #[bitsize(8)] 234 #[derive(Clone, Copy, DebugBits, FromBits)] 235 pub struct ReceiveStatusErrorClear { 236 pub framing_error: bool, 237 pub parity_error: bool, 238 pub break_error: bool, 239 pub overrun_error: bool, 240 _reserved_unpredictable: u4, 241 } 242 243 impl ReceiveStatusErrorClear { reset(&mut self)244 pub fn reset(&mut self) { 245 // All the bits are cleared to 0 on reset. 246 *self = 0.into(); 247 } 248 } 249 250 impl Default for ReceiveStatusErrorClear { default() -> Self251 fn default() -> Self { 252 0.into() 253 } 254 } 255 256 #[bitsize(16)] 257 #[derive(Clone, Copy, DebugBits, FromBits)] 258 /// Flag Register, `UARTFR` 259 #[doc(alias = "UARTFR")] 260 pub struct Flags { 261 /// CTS Clear to send. This bit is the complement of the UART clear to 262 /// send, `nUARTCTS`, modem status input. That is, the bit is 1 263 /// when `nUARTCTS` is LOW. 264 pub clear_to_send: bool, 265 /// DSR Data set ready. This bit is the complement of the UART data set 266 /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when 267 /// `nUARTDSR` is LOW. 268 pub data_set_ready: bool, 269 /// DCD Data carrier detect. This bit is the complement of the UART data 270 /// carrier detect, `nUARTDCD`, modem status input. That is, the bit is 271 /// 1 when `nUARTDCD` is LOW. 272 pub data_carrier_detect: bool, 273 /// BUSY UART busy. If this bit is set to 1, the UART is busy 274 /// transmitting data. This bit remains set until the complete 275 /// byte, including all the stop bits, has been sent from the 276 /// shift register. This bit is set as soon as the transmit FIFO 277 /// becomes non-empty, regardless of whether the UART is enabled 278 /// or not. 279 pub busy: bool, 280 /// RXFE Receive FIFO empty. The meaning of this bit depends on the 281 /// state of the FEN bit in the UARTLCR_H register. If the FIFO 282 /// is disabled, this bit is set when the receive holding 283 /// register is empty. If the FIFO is enabled, the RXFE bit is 284 /// set when the receive FIFO is empty. 285 pub receive_fifo_empty: bool, 286 /// TXFF Transmit FIFO full. The meaning of this bit depends on the 287 /// state of the FEN bit in the UARTLCR_H register. If the FIFO 288 /// is disabled, this bit is set when the transmit holding 289 /// register is full. If the FIFO is enabled, the TXFF bit is 290 /// set when the transmit FIFO is full. 291 pub transmit_fifo_full: bool, 292 /// RXFF Receive FIFO full. The meaning of this bit depends on the state 293 /// of the FEN bit in the UARTLCR_H register. If the FIFO is 294 /// disabled, this bit is set when the receive holding register 295 /// is full. If the FIFO is enabled, the RXFF bit is set when 296 /// the receive FIFO is full. 297 pub receive_fifo_full: bool, 298 /// Transmit FIFO empty. The meaning of this bit depends on the state of 299 /// the FEN bit in the [Line Control register](LineControl), 300 /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the 301 /// transmit holding register is empty. If the FIFO is enabled, 302 /// the TXFE bit is set when the transmit FIFO is empty. This 303 /// bit does not indicate if there is data in the transmit shift 304 /// register. 305 pub transmit_fifo_empty: bool, 306 /// `RI`, is `true` when `nUARTRI` is `LOW`. 307 pub ring_indicator: bool, 308 _reserved_zero_no_modify: u7, 309 } 310 311 impl Flags { reset(&mut self)312 pub fn reset(&mut self) { 313 // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1 314 self.set_receive_fifo_full(false); 315 self.set_transmit_fifo_full(false); 316 self.set_busy(false); 317 self.set_receive_fifo_empty(true); 318 self.set_transmit_fifo_empty(true); 319 } 320 } 321 322 impl Default for Flags { default() -> Self323 fn default() -> Self { 324 let mut ret: Self = 0.into(); 325 ret.reset(); 326 ret 327 } 328 } 329 330 #[bitsize(16)] 331 #[derive(Clone, Copy, DebugBits, FromBits)] 332 /// Line Control Register, `UARTLCR_H` 333 #[doc(alias = "UARTLCR_H")] 334 pub struct LineControl { 335 /// 15:8 - Reserved, do not modify, read as zero. 336 _reserved_zero_no_modify: u8, 337 /// 7 SPS Stick parity select. 338 /// 0 = stick parity is disabled 339 /// 1 = either: 340 /// • if the EPS bit is 0 then the parity bit is transmitted and checked 341 /// as a 1 • if the EPS bit is 1 then the parity bit is 342 /// transmitted and checked as a 0. This bit has no effect when 343 /// the PEN bit disables parity checking and generation. See Table 3-11 344 /// on page 3-14 for the parity truth table. 345 pub sticky_parity: bool, 346 /// WLEN Word length. These bits indicate the number of data bits 347 /// transmitted or received in a frame as follows: b11 = 8 bits 348 /// b10 = 7 bits 349 /// b01 = 6 bits 350 /// b00 = 5 bits. 351 pub word_length: WordLength, 352 /// FEN Enable FIFOs: 353 /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 354 /// 1-byte-deep holding registers 1 = transmit and receive FIFO 355 /// buffers are enabled (FIFO mode). 356 pub fifos_enabled: Mode, 357 /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits 358 /// are transmitted at the end of the frame. The receive 359 /// logic does not check for two stop bits being received. 360 pub two_stops_bits: bool, 361 /// EPS Even parity select. Controls the type of parity the UART uses 362 /// during transmission and reception: 363 /// - 0 = odd parity. The UART generates or checks for an odd number of 364 /// 1s in the data and parity bits. 365 /// - 1 = even parity. The UART generates or checks for an even number 366 /// of 1s in the data and parity bits. 367 /// This bit has no effect when the `PEN` bit disables parity checking 368 /// and generation. See Table 3-11 on page 3-14 for the parity 369 /// truth table. 370 pub parity: Parity, 371 /// 1 PEN Parity enable: 372 /// 373 /// - 0 = parity is disabled and no parity bit added to the data frame 374 /// - 1 = parity checking and generation is enabled. 375 /// 376 /// See Table 3-11 on page 3-14 for the parity truth table. 377 pub parity_enabled: bool, 378 /// BRK Send break. 379 /// 380 /// If this bit is set to `1`, a low-level is continually output on the 381 /// `UARTTXD` output, after completing transmission of the 382 /// current character. For the proper execution of the break command, 383 /// the software must set this bit for at least two complete 384 /// frames. For normal use, this bit must be cleared to `0`. 385 pub send_break: bool, 386 } 387 388 impl LineControl { reset(&mut self)389 pub fn reset(&mut self) { 390 // All the bits are cleared to 0 when reset. 391 *self = 0.into(); 392 } 393 } 394 395 impl Default for LineControl { default() -> Self396 fn default() -> Self { 397 0.into() 398 } 399 } 400 401 #[bitsize(1)] 402 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 403 /// `EPS` "Even parity select", field of [Line Control 404 /// register](LineControl). 405 pub enum Parity { 406 /// - 0 = odd parity. The UART generates or checks for an odd number of 407 /// 1s in the data and parity bits. 408 Odd = 0, 409 /// - 1 = even parity. The UART generates or checks for an even number 410 /// of 1s in the data and parity bits. 411 Even = 1, 412 } 413 414 #[bitsize(1)] 415 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 416 /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control 417 /// register](LineControl). 418 pub enum Mode { 419 /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 420 /// 1-byte-deep holding registers 421 Character = 0, 422 /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode). 423 FIFO = 1, 424 } 425 426 impl From<Mode> for bool { from(val: Mode) -> Self427 fn from(val: Mode) -> Self { 428 matches!(val, Mode::FIFO) 429 } 430 } 431 432 #[bitsize(2)] 433 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 434 /// `WLEN` Word length, field of [Line Control register](LineControl). 435 /// 436 /// These bits indicate the number of data bits transmitted or received in a 437 /// frame as follows: 438 pub enum WordLength { 439 /// b11 = 8 bits 440 _8Bits = 0b11, 441 /// b10 = 7 bits 442 _7Bits = 0b10, 443 /// b01 = 6 bits 444 _6Bits = 0b01, 445 /// b00 = 5 bits. 446 _5Bits = 0b00, 447 } 448 449 /// Control Register, `UARTCR` 450 /// 451 /// The `UARTCR` register is the control register. All the bits are cleared 452 /// to `0` on reset except for bits `9` and `8` that are set to `1`. 453 /// 454 /// # Source 455 /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 456 #[bitsize(16)] 457 #[doc(alias = "UARTCR")] 458 #[derive(Clone, Copy, DebugBits, FromBits)] 459 pub struct Control { 460 /// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled 461 /// in the middle of transmission or reception, it completes the current 462 /// character before stopping. 1 = the UART is enabled. Data 463 /// transmission and reception occurs for either UART signals or SIR 464 /// signals depending on the setting of the SIREN bit. 465 pub enable_uart: bool, 466 /// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT` 467 /// remains LOW (no light pulse generated), and signal transitions on 468 /// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is 469 /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, 470 /// in the marking state. Signal transitions on UARTRXD or modem status 471 /// inputs have no effect. This bit has no effect if the UARTEN bit 472 /// disables the UART. 473 pub enable_sir: bool, 474 /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding 475 /// mode. If this bit is cleared to 0, low-level bits are transmitted as 476 /// an active high pulse with a width of 3/ 16th of the bit period. If 477 /// this bit is set to 1, low-level bits are transmitted with a pulse 478 /// width that is 3 times the period of the IrLPBaud16 input signal, 479 /// regardless of the selected bit rate. Setting this bit uses less 480 /// power, but might reduce transmission distances. 481 pub sir_lowpower_irda_mode: u1, 482 /// Reserved, do not modify, read as zero. 483 _reserved_zero_no_modify: u4, 484 /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is 485 /// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR 486 /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed 487 /// through to the SIRIN path. The SIRTEST bit in the test register must 488 /// be set to 1 to override the normal half-duplex SIR operation. This 489 /// must be the requirement for accessing the test registers during 490 /// normal operation, and SIRTEST must be cleared to 0 when loopback 491 /// testing is finished. This feature reduces the amount of external 492 /// coupling required during system test. If this bit is set to 1, and 493 /// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the 494 /// UARTRXD path. In either SIR mode or UART mode, when this bit is set, 495 /// the modem outputs are also fed through to the modem inputs. This bit 496 /// is cleared to 0 on reset, to disable loopback. 497 pub enable_loopback: bool, 498 /// `TXE` Transmit enable. If this bit is set to 1, the transmit section 499 /// of the UART is enabled. Data transmission occurs for either UART 500 /// signals, or SIR signals depending on the setting of the SIREN bit. 501 /// When the UART is disabled in the middle of transmission, it 502 /// completes the current character before stopping. 503 pub enable_transmit: bool, 504 /// `RXE` Receive enable. If this bit is set to 1, the receive section 505 /// of the UART is enabled. Data reception occurs for either UART 506 /// signals or SIR signals depending on the setting of the SIREN bit. 507 /// When the UART is disabled in the middle of reception, it completes 508 /// the current character before stopping. 509 pub enable_receive: bool, 510 /// `DTR` Data transmit ready. This bit is the complement of the UART 511 /// data transmit ready, `nUARTDTR`, modem status output. That is, when 512 /// the bit is programmed to a 1 then `nUARTDTR` is LOW. 513 pub data_transmit_ready: bool, 514 /// `RTS` Request to send. This bit is the complement of the UART 515 /// request to send, `nUARTRTS`, modem status output. That is, when the 516 /// bit is programmed to a 1 then `nUARTRTS` is LOW. 517 pub request_to_send: bool, 518 /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`) 519 /// modem status output. That is, when the bit is programmed to a 1 the 520 /// output is 0. For DTE this can be used as Data Carrier Detect (DCD). 521 pub out_1: bool, 522 /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`) 523 /// modem status output. That is, when the bit is programmed to a 1, the 524 /// output is 0. For DTE this can be used as Ring Indicator (RI). 525 pub out_2: bool, 526 /// `RTSEn` RTS hardware flow control enable. If this bit is set to 1, 527 /// RTS hardware flow control is enabled. Data is only requested when 528 /// there is space in the receive FIFO for it to be received. 529 pub rts_hardware_flow_control_enable: bool, 530 /// `CTSEn` CTS hardware flow control enable. If this bit is set to 1, 531 /// CTS hardware flow control is enabled. Data is only transmitted when 532 /// the `nUARTCTS` signal is asserted. 533 pub cts_hardware_flow_control_enable: bool, 534 } 535 536 impl Control { reset(&mut self)537 pub fn reset(&mut self) { 538 *self = 0.into(); 539 self.set_enable_receive(true); 540 self.set_enable_transmit(true); 541 } 542 } 543 544 impl Default for Control { default() -> Self545 fn default() -> Self { 546 let mut ret: Self = 0.into(); 547 ret.reset(); 548 ret 549 } 550 } 551 552 /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC 553 pub const INT_OE: u32 = 1 << 10; 554 pub const INT_BE: u32 = 1 << 9; 555 pub const INT_PE: u32 = 1 << 8; 556 pub const INT_FE: u32 = 1 << 7; 557 pub const INT_RT: u32 = 1 << 6; 558 pub const INT_TX: u32 = 1 << 5; 559 pub const INT_RX: u32 = 1 << 4; 560 pub const INT_DSR: u32 = 1 << 3; 561 pub const INT_DCD: u32 = 1 << 2; 562 pub const INT_CTS: u32 = 1 << 1; 563 pub const INT_RI: u32 = 1 << 0; 564 pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE; 565 pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS; 566 567 #[repr(u32)] 568 pub enum Interrupt { 569 OE = 1 << 10, 570 BE = 1 << 9, 571 PE = 1 << 8, 572 FE = 1 << 7, 573 RT = 1 << 6, 574 TX = 1 << 5, 575 RX = 1 << 4, 576 DSR = 1 << 3, 577 DCD = 1 << 2, 578 CTS = 1 << 1, 579 RI = 1 << 0, 580 } 581 582 impl Interrupt { 583 pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE; 584 pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS; 585 } 586 } 587 588 // TODO: You must disable the UART before any of the control registers are 589 // reprogrammed. When the UART is disabled in the middle of transmission or 590 // reception, it completes the current character before stopping 591