xref: /openbmc/u-boot/drivers/usb/musb/musb_hcd.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Mentor USB OTG Core host controller driver.
4  *
5  * Copyright (c) 2008 Texas Instruments
6  *
7  * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
8  */
9 
10 #include <common.h>
11 #include <usb.h>
12 #include "musb_hcd.h"
13 
14 /* MSC control transfers */
15 #define USB_MSC_BBB_RESET 	0xFF
16 #define USB_MSC_BBB_GET_MAX_LUN	0xFE
17 
18 /* Endpoint configuration information */
19 static const struct musb_epinfo epinfo[3] = {
20 	{MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
21 	{MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In  - 512 Bytes */
22 	{MUSB_INTR_EP, 0, 64}   /* EP2 - Interrupt IN - 64 Bytes */
23 };
24 
25 /* --- Virtual Root Hub ---------------------------------------------------- */
26 #ifdef MUSB_NO_MULTIPOINT
27 static int rh_devnum;
28 static u32 port_status;
29 
30 #include <usbroothubdes.h>
31 
32 #endif
33 
34 /*
35  * This function writes the data toggle value.
36  */
write_toggle(struct usb_device * dev,u8 ep,u8 dir_out)37 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
38 {
39 	u16 toggle = usb_gettoggle(dev, ep, dir_out);
40 	u16 csr;
41 
42 	if (dir_out) {
43 		csr = readw(&musbr->txcsr);
44 		if (!toggle) {
45 			if (csr & MUSB_TXCSR_MODE)
46 				csr = MUSB_TXCSR_CLRDATATOG;
47 			else
48 				csr = 0;
49 			writew(csr, &musbr->txcsr);
50 		} else {
51 			csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
52 			writew(csr, &musbr->txcsr);
53 			csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
54 			writew(csr, &musbr->txcsr);
55 		}
56 	} else {
57 		if (!toggle) {
58 			csr = readw(&musbr->txcsr);
59 			if (csr & MUSB_TXCSR_MODE)
60 				csr = MUSB_RXCSR_CLRDATATOG;
61 			else
62 				csr = 0;
63 			writew(csr, &musbr->rxcsr);
64 		} else {
65 			csr = readw(&musbr->rxcsr);
66 			csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
67 			writew(csr, &musbr->rxcsr);
68 			csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
69 			writew(csr, &musbr->rxcsr);
70 		}
71 	}
72 }
73 
74 /*
75  * This function checks if RxStall has occurred on the endpoint. If a RxStall
76  * has occurred, the RxStall is cleared and 1 is returned. If RxStall has
77  * not occurred, 0 is returned.
78  */
check_stall(u8 ep,u8 dir_out)79 static u8 check_stall(u8 ep, u8 dir_out)
80 {
81 	u16 csr;
82 
83 	/* For endpoint 0 */
84 	if (!ep) {
85 		csr = readw(&musbr->txcsr);
86 		if (csr & MUSB_CSR0_H_RXSTALL) {
87 			csr &= ~MUSB_CSR0_H_RXSTALL;
88 			writew(csr, &musbr->txcsr);
89 			return 1;
90 		}
91 	} else { /* For non-ep0 */
92 		if (dir_out) { /* is it tx ep */
93 			csr = readw(&musbr->txcsr);
94 			if (csr & MUSB_TXCSR_H_RXSTALL) {
95 				csr &= ~MUSB_TXCSR_H_RXSTALL;
96 				writew(csr, &musbr->txcsr);
97 				return 1;
98 			}
99 		} else { /* is it rx ep */
100 			csr = readw(&musbr->rxcsr);
101 			if (csr & MUSB_RXCSR_H_RXSTALL) {
102 				csr &= ~MUSB_RXCSR_H_RXSTALL;
103 				writew(csr, &musbr->rxcsr);
104 				return 1;
105 			}
106 		}
107 	}
108 	return 0;
109 }
110 
111 /*
112  * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
113  * error and -2 for stall.
114  */
wait_until_ep0_ready(struct usb_device * dev,u32 bit_mask)115 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
116 {
117 	u16 csr;
118 	int result = 1;
119 	int timeout = CONFIG_USB_MUSB_TIMEOUT;
120 
121 	while (result > 0) {
122 		csr = readw(&musbr->txcsr);
123 		if (csr & MUSB_CSR0_H_ERROR) {
124 			csr &= ~MUSB_CSR0_H_ERROR;
125 			writew(csr, &musbr->txcsr);
126 			dev->status = USB_ST_CRC_ERR;
127 			result = -1;
128 			break;
129 		}
130 
131 		switch (bit_mask) {
132 		case MUSB_CSR0_TXPKTRDY:
133 			if (!(csr & MUSB_CSR0_TXPKTRDY)) {
134 				if (check_stall(MUSB_CONTROL_EP, 0)) {
135 					dev->status = USB_ST_STALLED;
136 					result = -2;
137 				} else
138 					result = 0;
139 			}
140 			break;
141 
142 		case MUSB_CSR0_RXPKTRDY:
143 			if (check_stall(MUSB_CONTROL_EP, 0)) {
144 				dev->status = USB_ST_STALLED;
145 				result = -2;
146 			} else
147 				if (csr & MUSB_CSR0_RXPKTRDY)
148 					result = 0;
149 			break;
150 
151 		case MUSB_CSR0_H_REQPKT:
152 			if (!(csr & MUSB_CSR0_H_REQPKT)) {
153 				if (check_stall(MUSB_CONTROL_EP, 0)) {
154 					dev->status = USB_ST_STALLED;
155 					result = -2;
156 				} else
157 					result = 0;
158 			}
159 			break;
160 		}
161 
162 		/* Check the timeout */
163 		if (--timeout)
164 			udelay(1);
165 		else {
166 			dev->status = USB_ST_CRC_ERR;
167 			result = -1;
168 			break;
169 		}
170 	}
171 
172 	return result;
173 }
174 
175 /*
176  * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
177  */
wait_until_txep_ready(struct usb_device * dev,u8 ep)178 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
179 {
180 	u16 csr;
181 	int timeout = CONFIG_USB_MUSB_TIMEOUT;
182 
183 	do {
184 		if (check_stall(ep, 1)) {
185 			dev->status = USB_ST_STALLED;
186 			return 0;
187 		}
188 
189 		csr = readw(&musbr->txcsr);
190 		if (csr & MUSB_TXCSR_H_ERROR) {
191 			dev->status = USB_ST_CRC_ERR;
192 			return 0;
193 		}
194 
195 		/* Check the timeout */
196 		if (--timeout)
197 			udelay(1);
198 		else {
199 			dev->status = USB_ST_CRC_ERR;
200 			return -1;
201 		}
202 
203 	} while (csr & MUSB_TXCSR_TXPKTRDY);
204 	return 1;
205 }
206 
207 /*
208  * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
209  */
wait_until_rxep_ready(struct usb_device * dev,u8 ep)210 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
211 {
212 	u16 csr;
213 	int timeout = CONFIG_USB_MUSB_TIMEOUT;
214 
215 	do {
216 		if (check_stall(ep, 0)) {
217 			dev->status = USB_ST_STALLED;
218 			return 0;
219 		}
220 
221 		csr = readw(&musbr->rxcsr);
222 		if (csr & MUSB_RXCSR_H_ERROR) {
223 			dev->status = USB_ST_CRC_ERR;
224 			return 0;
225 		}
226 
227 		/* Check the timeout */
228 		if (--timeout)
229 			udelay(1);
230 		else {
231 			dev->status = USB_ST_CRC_ERR;
232 			return -1;
233 		}
234 
235 	} while (!(csr & MUSB_RXCSR_RXPKTRDY));
236 	return 1;
237 }
238 
239 /*
240  * This function performs the setup phase of the control transfer
241  */
ctrlreq_setup_phase(struct usb_device * dev,struct devrequest * setup)242 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
243 {
244 	int result;
245 	u16 csr;
246 
247 	/* write the control request to ep0 fifo */
248 	write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
249 
250 	/* enable transfer of setup packet */
251 	csr = readw(&musbr->txcsr);
252 	csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
253 	writew(csr, &musbr->txcsr);
254 
255 	/* wait until the setup packet is transmitted */
256 	result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
257 	dev->act_len = 0;
258 	return result;
259 }
260 
261 /*
262  * This function handles the control transfer in data phase
263  */
ctrlreq_in_data_phase(struct usb_device * dev,u32 len,void * buffer)264 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
265 {
266 	u16 csr;
267 	u32 rxlen = 0;
268 	u32 nextlen = 0;
269 	u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
270 	u8  *rxbuff = (u8 *)buffer;
271 	u8  rxedlength;
272 	int result;
273 
274 	while (rxlen < len) {
275 		/* Determine the next read length */
276 		nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
277 
278 		/* Set the ReqPkt bit */
279 		csr = readw(&musbr->txcsr);
280 		writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
281 		result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
282 		if (result < 0)
283 			return result;
284 
285 		/* Actual number of bytes received by usb */
286 		rxedlength = readb(&musbr->rxcount);
287 
288 		/* Read the data from the RxFIFO */
289 		read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
290 
291 		/* Clear the RxPktRdy Bit */
292 		csr = readw(&musbr->txcsr);
293 		csr &= ~MUSB_CSR0_RXPKTRDY;
294 		writew(csr, &musbr->txcsr);
295 
296 		/* short packet? */
297 		if (rxedlength != nextlen) {
298 			dev->act_len += rxedlength;
299 			break;
300 		}
301 		rxlen += nextlen;
302 		dev->act_len = rxlen;
303 	}
304 	return 0;
305 }
306 
307 /*
308  * This function handles the control transfer out data phase
309  */
ctrlreq_out_data_phase(struct usb_device * dev,u32 len,void * buffer)310 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
311 {
312 	u16 csr;
313 	u32 txlen = 0;
314 	u32 nextlen = 0;
315 	u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
316 	u8  *txbuff = (u8 *)buffer;
317 	int result = 0;
318 
319 	while (txlen < len) {
320 		/* Determine the next write length */
321 		nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
322 
323 		/* Load the data to send in FIFO */
324 		write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
325 
326 		/* Set TXPKTRDY bit */
327 		csr = readw(&musbr->txcsr);
328 
329 		csr |= MUSB_CSR0_TXPKTRDY;
330 #if !defined(CONFIG_SOC_DM365)
331 		csr |= MUSB_CSR0_H_DIS_PING;
332 #endif
333 		writew(csr, &musbr->txcsr);
334 		result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
335 		if (result < 0)
336 			break;
337 
338 		txlen += nextlen;
339 		dev->act_len = txlen;
340 	}
341 	return result;
342 }
343 
344 /*
345  * This function handles the control transfer out status phase
346  */
ctrlreq_out_status_phase(struct usb_device * dev)347 static int ctrlreq_out_status_phase(struct usb_device *dev)
348 {
349 	u16 csr;
350 	int result;
351 
352 	/* Set the StatusPkt bit */
353 	csr = readw(&musbr->txcsr);
354 	csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
355 #if !defined(CONFIG_SOC_DM365)
356 	csr |= MUSB_CSR0_H_DIS_PING;
357 #endif
358 	writew(csr, &musbr->txcsr);
359 
360 	/* Wait until TXPKTRDY bit is cleared */
361 	result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
362 	return result;
363 }
364 
365 /*
366  * This function handles the control transfer in status phase
367  */
ctrlreq_in_status_phase(struct usb_device * dev)368 static int ctrlreq_in_status_phase(struct usb_device *dev)
369 {
370 	u16 csr;
371 	int result;
372 
373 	/* Set the StatusPkt bit and ReqPkt bit */
374 	csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
375 #if !defined(CONFIG_SOC_DM365)
376 	csr |= MUSB_CSR0_H_DIS_PING;
377 #endif
378 	writew(csr, &musbr->txcsr);
379 	result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
380 
381 	/* clear StatusPkt bit and RxPktRdy bit */
382 	csr = readw(&musbr->txcsr);
383 	csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
384 	writew(csr, &musbr->txcsr);
385 	return result;
386 }
387 
388 /*
389  * determines the speed of the device (High/Full/Slow)
390  */
get_dev_speed(struct usb_device * dev)391 static u8 get_dev_speed(struct usb_device *dev)
392 {
393 	return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
394 		((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
395 						MUSB_TYPE_SPEED_FULL);
396 }
397 
398 /*
399  * configure the hub address and the port address.
400  */
config_hub_port(struct usb_device * dev,u8 ep)401 static void config_hub_port(struct usb_device *dev, u8 ep)
402 {
403 	u8 chid;
404 	u8 hub;
405 
406 	/* Find out the nearest parent which is high speed */
407 	while (dev->parent->parent != NULL)
408 		if (get_dev_speed(dev->parent) !=  MUSB_TYPE_SPEED_HIGH)
409 			dev = dev->parent;
410 		else
411 			break;
412 
413 	/* determine the port address at that hub */
414 	hub = dev->parent->devnum;
415 	for (chid = 0; chid < USB_MAXCHILDREN; chid++)
416 		if (dev->parent->children[chid] == dev)
417 			break;
418 
419 #ifndef MUSB_NO_MULTIPOINT
420 	/* configure the hub address and the port address */
421 	writeb(hub, &musbr->tar[ep].txhubaddr);
422 	writeb((chid + 1), &musbr->tar[ep].txhubport);
423 	writeb(hub, &musbr->tar[ep].rxhubaddr);
424 	writeb((chid + 1), &musbr->tar[ep].rxhubport);
425 #endif
426 }
427 
428 #ifdef MUSB_NO_MULTIPOINT
429 
musb_port_reset(int do_reset)430 static void musb_port_reset(int do_reset)
431 {
432 	u8 power = readb(&musbr->power);
433 
434 	if (do_reset) {
435 		power &= 0xf0;
436 		writeb(power | MUSB_POWER_RESET, &musbr->power);
437 		port_status |= USB_PORT_STAT_RESET;
438 		port_status &= ~USB_PORT_STAT_ENABLE;
439 		udelay(30000);
440 	} else {
441 		writeb(power & ~MUSB_POWER_RESET, &musbr->power);
442 
443 		power = readb(&musbr->power);
444 		if (power & MUSB_POWER_HSMODE)
445 			port_status |= USB_PORT_STAT_HIGH_SPEED;
446 
447 		port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
448 		port_status |= USB_PORT_STAT_ENABLE
449 			| (USB_PORT_STAT_C_RESET << 16)
450 			| (USB_PORT_STAT_C_ENABLE << 16);
451 	}
452 }
453 
454 /*
455  * root hub control
456  */
musb_submit_rh_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * cmd)457 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
458 			      void *buffer, int transfer_len,
459 			      struct devrequest *cmd)
460 {
461 	int leni = transfer_len;
462 	int len = 0;
463 	int stat = 0;
464 	u32 datab[4];
465 	const u8 *data_buf = (u8 *) datab;
466 	u16 bmRType_bReq;
467 	u16 wValue;
468 	u16 wIndex;
469 	u16 wLength;
470 	u16 int_usb;
471 
472 	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
473 		debug("Root-Hub submit IRQ: NOT implemented\n");
474 		return 0;
475 	}
476 
477 	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
478 	wValue = swap_16(cmd->value);
479 	wIndex = swap_16(cmd->index);
480 	wLength = swap_16(cmd->length);
481 
482 	debug("--- HUB ----------------------------------------\n");
483 	debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
484 	    bmRType_bReq, wValue, wIndex, wLength);
485 	debug("------------------------------------------------\n");
486 
487 	switch (bmRType_bReq) {
488 	case RH_GET_STATUS:
489 		debug("RH_GET_STATUS\n");
490 
491 		*(__u16 *) data_buf = swap_16(1);
492 		len = 2;
493 		break;
494 
495 	case RH_GET_STATUS | RH_INTERFACE:
496 		debug("RH_GET_STATUS | RH_INTERFACE\n");
497 
498 		*(__u16 *) data_buf = swap_16(0);
499 		len = 2;
500 		break;
501 
502 	case RH_GET_STATUS | RH_ENDPOINT:
503 		debug("RH_GET_STATUS | RH_ENDPOINT\n");
504 
505 		*(__u16 *) data_buf = swap_16(0);
506 		len = 2;
507 		break;
508 
509 	case RH_GET_STATUS | RH_CLASS:
510 		debug("RH_GET_STATUS | RH_CLASS\n");
511 
512 		*(__u32 *) data_buf = swap_32(0);
513 		len = 4;
514 		break;
515 
516 	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
517 		debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
518 
519 		int_usb = readw(&musbr->intrusb);
520 		if (int_usb & MUSB_INTR_CONNECT) {
521 			port_status |= USB_PORT_STAT_CONNECTION
522 				| (USB_PORT_STAT_C_CONNECTION << 16);
523 			port_status |= USB_PORT_STAT_HIGH_SPEED
524 				| USB_PORT_STAT_ENABLE;
525 		}
526 
527 		if (port_status & USB_PORT_STAT_RESET)
528 			musb_port_reset(0);
529 
530 		*(__u32 *) data_buf = swap_32(port_status);
531 		len = 4;
532 		break;
533 
534 	case RH_CLEAR_FEATURE | RH_ENDPOINT:
535 		debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
536 
537 		switch (wValue) {
538 		case RH_ENDPOINT_STALL:
539 			debug("C_HUB_ENDPOINT_STALL\n");
540 			len = 0;
541 			break;
542 		}
543 		port_status &= ~(1 << wValue);
544 		break;
545 
546 	case RH_CLEAR_FEATURE | RH_CLASS:
547 		debug("RH_CLEAR_FEATURE | RH_CLASS\n");
548 
549 		switch (wValue) {
550 		case RH_C_HUB_LOCAL_POWER:
551 			debug("C_HUB_LOCAL_POWER\n");
552 			len = 0;
553 			break;
554 
555 		case RH_C_HUB_OVER_CURRENT:
556 			debug("C_HUB_OVER_CURRENT\n");
557 			len = 0;
558 			break;
559 		}
560 		port_status &= ~(1 << wValue);
561 		break;
562 
563 	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
564 		debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
565 
566 		switch (wValue) {
567 		case RH_PORT_ENABLE:
568 			len = 0;
569 			break;
570 
571 		case RH_PORT_SUSPEND:
572 			len = 0;
573 			break;
574 
575 		case RH_PORT_POWER:
576 			len = 0;
577 			break;
578 
579 		case RH_C_PORT_CONNECTION:
580 			len = 0;
581 			break;
582 
583 		case RH_C_PORT_ENABLE:
584 			len = 0;
585 			break;
586 
587 		case RH_C_PORT_SUSPEND:
588 			len = 0;
589 			break;
590 
591 		case RH_C_PORT_OVER_CURRENT:
592 			len = 0;
593 			break;
594 
595 		case RH_C_PORT_RESET:
596 			len = 0;
597 			break;
598 
599 		default:
600 			debug("invalid wValue\n");
601 			stat = USB_ST_STALLED;
602 		}
603 
604 		port_status &= ~(1 << wValue);
605 		break;
606 
607 	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
608 		debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
609 
610 		switch (wValue) {
611 		case RH_PORT_SUSPEND:
612 			len = 0;
613 			break;
614 
615 		case RH_PORT_RESET:
616 			musb_port_reset(1);
617 			len = 0;
618 			break;
619 
620 		case RH_PORT_POWER:
621 			len = 0;
622 			break;
623 
624 		case RH_PORT_ENABLE:
625 			len = 0;
626 			break;
627 
628 		default:
629 			debug("invalid wValue\n");
630 			stat = USB_ST_STALLED;
631 		}
632 
633 		port_status |= 1 << wValue;
634 		break;
635 
636 	case RH_SET_ADDRESS:
637 		debug("RH_SET_ADDRESS\n");
638 
639 		rh_devnum = wValue;
640 		len = 0;
641 		break;
642 
643 	case RH_GET_DESCRIPTOR:
644 		debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
645 
646 		switch (wValue) {
647 		case (USB_DT_DEVICE << 8):	/* device descriptor */
648 			len = min_t(unsigned int,
649 				    leni, min_t(unsigned int,
650 						sizeof(root_hub_dev_des),
651 						wLength));
652 			data_buf = root_hub_dev_des;
653 			break;
654 
655 		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
656 			len = min_t(unsigned int,
657 				    leni, min_t(unsigned int,
658 						sizeof(root_hub_config_des),
659 						wLength));
660 			data_buf = root_hub_config_des;
661 			break;
662 
663 		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
664 			len = min_t(unsigned int,
665 				    leni, min_t(unsigned int,
666 						sizeof(root_hub_str_index0),
667 						wLength));
668 			data_buf = root_hub_str_index0;
669 			break;
670 
671 		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
672 			len = min_t(unsigned int,
673 				    leni, min_t(unsigned int,
674 						sizeof(root_hub_str_index1),
675 						wLength));
676 			data_buf = root_hub_str_index1;
677 			break;
678 
679 		default:
680 			debug("invalid wValue\n");
681 			stat = USB_ST_STALLED;
682 		}
683 
684 		break;
685 
686 	case RH_GET_DESCRIPTOR | RH_CLASS: {
687 		u8 *_data_buf = (u8 *) datab;
688 		debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
689 
690 		_data_buf[0] = 0x09;	/* min length; */
691 		_data_buf[1] = 0x29;
692 		_data_buf[2] = 0x1;	/* 1 port */
693 		_data_buf[3] = 0x01;	/* per-port power switching */
694 		_data_buf[3] |= 0x10;	/* no overcurrent reporting */
695 
696 		/* Corresponds to data_buf[4-7] */
697 		_data_buf[4] = 0;
698 		_data_buf[5] = 5;
699 		_data_buf[6] = 0;
700 		_data_buf[7] = 0x02;
701 		_data_buf[8] = 0xff;
702 
703 		len = min_t(unsigned int, leni,
704 			    min_t(unsigned int, data_buf[0], wLength));
705 		break;
706 	}
707 
708 	case RH_GET_CONFIGURATION:
709 		debug("RH_GET_CONFIGURATION\n");
710 
711 		*(__u8 *) data_buf = 0x01;
712 		len = 1;
713 		break;
714 
715 	case RH_SET_CONFIGURATION:
716 		debug("RH_SET_CONFIGURATION\n");
717 
718 		len = 0;
719 		break;
720 
721 	default:
722 		debug("*** *** *** unsupported root hub command *** *** ***\n");
723 		stat = USB_ST_STALLED;
724 	}
725 
726 	len = min_t(int, len, leni);
727 	if (buffer != data_buf)
728 		memcpy(buffer, data_buf, len);
729 
730 	dev->act_len = len;
731 	dev->status = stat;
732 	debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
733 
734 	return stat;
735 }
736 
musb_rh_init(void)737 static void musb_rh_init(void)
738 {
739 	rh_devnum = 0;
740 	port_status = 0;
741 }
742 
743 #else
744 
musb_rh_init(void)745 static void musb_rh_init(void) {}
746 
747 #endif
748 
749 /*
750  * do a control transfer
751  */
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)752 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
753 			int len, struct devrequest *setup)
754 {
755 	int devnum = usb_pipedevice(pipe);
756 	u8  devspeed;
757 
758 #ifdef MUSB_NO_MULTIPOINT
759 	/* Control message is for the HUB? */
760 	if (devnum == rh_devnum) {
761 		int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
762 		if (stat)
763 			return stat;
764 	}
765 #endif
766 
767 	/* select control endpoint */
768 	writeb(MUSB_CONTROL_EP, &musbr->index);
769 	readw(&musbr->txcsr);
770 
771 #ifndef MUSB_NO_MULTIPOINT
772 	/* target addr and (for multipoint) hub addr/port */
773 	writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
774 	writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
775 #endif
776 
777 	/* configure the hub address and the port number as required */
778 	devspeed = get_dev_speed(dev);
779 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
780 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
781 		config_hub_port(dev, MUSB_CONTROL_EP);
782 		writeb(devspeed << 6, &musbr->txtype);
783 	} else {
784 		writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
785 #ifndef MUSB_NO_MULTIPOINT
786 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
787 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
788 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
789 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
790 #endif
791 	}
792 
793 	/* Control transfer setup phase */
794 	if (ctrlreq_setup_phase(dev, setup) < 0)
795 		return 0;
796 
797 	switch (setup->request) {
798 	case USB_REQ_GET_DESCRIPTOR:
799 	case USB_REQ_GET_CONFIGURATION:
800 	case USB_REQ_GET_INTERFACE:
801 	case USB_REQ_GET_STATUS:
802 	case USB_MSC_BBB_GET_MAX_LUN:
803 		/* control transfer in-data-phase */
804 		if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
805 			return 0;
806 		/* control transfer out-status-phase */
807 		if (ctrlreq_out_status_phase(dev) < 0)
808 			return 0;
809 		break;
810 
811 	case USB_REQ_SET_ADDRESS:
812 	case USB_REQ_SET_CONFIGURATION:
813 	case USB_REQ_SET_FEATURE:
814 	case USB_REQ_SET_INTERFACE:
815 	case USB_REQ_CLEAR_FEATURE:
816 	case USB_MSC_BBB_RESET:
817 		/* control transfer in status phase */
818 		if (ctrlreq_in_status_phase(dev) < 0)
819 			return 0;
820 		break;
821 
822 	case USB_REQ_SET_DESCRIPTOR:
823 		/* control transfer out data phase */
824 		if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
825 			return 0;
826 		/* control transfer in status phase */
827 		if (ctrlreq_in_status_phase(dev) < 0)
828 			return 0;
829 		break;
830 
831 	default:
832 		/* unhandled control transfer */
833 		return -1;
834 	}
835 
836 	dev->status = 0;
837 	dev->act_len = len;
838 
839 #ifdef MUSB_NO_MULTIPOINT
840 	/* Set device address to USB_FADDR register */
841 	if (setup->request == USB_REQ_SET_ADDRESS)
842 		writeb(dev->devnum, &musbr->faddr);
843 #endif
844 
845 	return len;
846 }
847 
848 /*
849  * do a bulk transfer
850  */
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)851 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
852 					void *buffer, int len)
853 {
854 	int dir_out = usb_pipeout(pipe);
855 	int ep = usb_pipeendpoint(pipe);
856 #ifndef MUSB_NO_MULTIPOINT
857 	int devnum = usb_pipedevice(pipe);
858 #endif
859 	u8  type;
860 	u16 csr;
861 	u32 txlen = 0;
862 	u32 nextlen = 0;
863 	u8  devspeed;
864 
865 	/* select bulk endpoint */
866 	writeb(MUSB_BULK_EP, &musbr->index);
867 
868 #ifndef MUSB_NO_MULTIPOINT
869 	/* write the address of the device */
870 	if (dir_out)
871 		writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
872 	else
873 		writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
874 #endif
875 
876 	/* configure the hub address and the port number as required */
877 	devspeed = get_dev_speed(dev);
878 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
879 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
880 		/*
881 		 * MUSB is in high speed and the destination device is full
882 		 * speed device. So configure the hub address and port
883 		 * address registers.
884 		 */
885 		config_hub_port(dev, MUSB_BULK_EP);
886 	} else {
887 #ifndef MUSB_NO_MULTIPOINT
888 		if (dir_out) {
889 			writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
890 			writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
891 		} else {
892 			writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
893 			writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
894 		}
895 #endif
896 		devspeed = musb_cfg.musb_speed;
897 	}
898 
899 	/* Write the saved toggle bit value */
900 	write_toggle(dev, ep, dir_out);
901 
902 	if (dir_out) { /* bulk-out transfer */
903 		/* Program the TxType register */
904 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
905 			   (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
906 			   (ep & MUSB_TYPE_REMOTE_END);
907 		writeb(type, &musbr->txtype);
908 
909 		/* Write maximum packet size to the TxMaxp register */
910 		writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
911 		while (txlen < len) {
912 			nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
913 					(len-txlen) : dev->epmaxpacketout[ep];
914 
915 			/* Write the data to the FIFO */
916 			write_fifo(MUSB_BULK_EP, nextlen,
917 					(void *)(((u8 *)buffer) + txlen));
918 
919 			/* Set the TxPktRdy bit */
920 			csr = readw(&musbr->txcsr);
921 			writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
922 
923 			/* Wait until the TxPktRdy bit is cleared */
924 			if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
925 				readw(&musbr->txcsr);
926 				usb_settoggle(dev, ep, dir_out,
927 				(csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
928 				dev->act_len = txlen;
929 				return 0;
930 			}
931 			txlen += nextlen;
932 		}
933 
934 		/* Keep a copy of the data toggle bit */
935 		csr = readw(&musbr->txcsr);
936 		usb_settoggle(dev, ep, dir_out,
937 				(csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
938 	} else { /* bulk-in transfer */
939 		/* Write the saved toggle bit value */
940 		write_toggle(dev, ep, dir_out);
941 
942 		/* Program the RxType register */
943 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
944 			   (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
945 			   (ep & MUSB_TYPE_REMOTE_END);
946 		writeb(type, &musbr->rxtype);
947 
948 		/* Write the maximum packet size to the RxMaxp register */
949 		writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
950 		while (txlen < len) {
951 			nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
952 					(len-txlen) : dev->epmaxpacketin[ep];
953 
954 			/* Set the ReqPkt bit */
955 			csr = readw(&musbr->rxcsr);
956 			writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
957 
958 			/* Wait until the RxPktRdy bit is set */
959 			if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
960 				csr = readw(&musbr->rxcsr);
961 				usb_settoggle(dev, ep, dir_out,
962 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
963 				csr &= ~MUSB_RXCSR_RXPKTRDY;
964 				writew(csr, &musbr->rxcsr);
965 				dev->act_len = txlen;
966 				return 0;
967 			}
968 
969 			/* Read the data from the FIFO */
970 			read_fifo(MUSB_BULK_EP, nextlen,
971 					(void *)(((u8 *)buffer) + txlen));
972 
973 			/* Clear the RxPktRdy bit */
974 			csr =  readw(&musbr->rxcsr);
975 			csr &= ~MUSB_RXCSR_RXPKTRDY;
976 			writew(csr, &musbr->rxcsr);
977 			txlen += nextlen;
978 		}
979 
980 		/* Keep a copy of the data toggle bit */
981 		csr = readw(&musbr->rxcsr);
982 		usb_settoggle(dev, ep, dir_out,
983 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
984 	}
985 
986 	/* bulk transfer is complete */
987 	dev->status = 0;
988 	dev->act_len = len;
989 	return 0;
990 }
991 
992 /*
993  * This function initializes the usb controller module.
994  */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)995 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
996 {
997 	u8  power;
998 	u32 timeout;
999 
1000 	musb_rh_init();
1001 
1002 	if (musb_platform_init() == -1)
1003 		return -1;
1004 
1005 	/* Configure all the endpoint FIFO's and start usb controller */
1006 	musbr = musb_cfg.regs;
1007 	musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1008 	musb_start();
1009 
1010 	/*
1011 	 * Wait until musb is enabled in host mode with a timeout. There
1012 	 * should be a usb device connected.
1013 	 */
1014 	timeout = musb_cfg.timeout;
1015 	while (--timeout)
1016 		if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1017 			break;
1018 
1019 	/* if musb core is not in host mode, then return */
1020 	if (!timeout)
1021 		return -1;
1022 
1023 	/* start usb bus reset */
1024 	power = readb(&musbr->power);
1025 	writeb(power | MUSB_POWER_RESET, &musbr->power);
1026 
1027 	/* After initiating a usb reset, wait for about 20ms to 30ms */
1028 	udelay(30000);
1029 
1030 	/* stop usb bus reset */
1031 	power = readb(&musbr->power);
1032 	power &= ~MUSB_POWER_RESET;
1033 	writeb(power, &musbr->power);
1034 
1035 	/* Determine if the connected device is a high/full/low speed device */
1036 	musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1037 			MUSB_TYPE_SPEED_HIGH :
1038 			((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1039 			MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1040 	return 0;
1041 }
1042 
1043 /*
1044  * This function stops the operation of the davinci usb module.
1045  */
usb_lowlevel_stop(int index)1046 int usb_lowlevel_stop(int index)
1047 {
1048 	/* Reset the USB module */
1049 	musb_platform_deinit();
1050 	writeb(0, &musbr->devctl);
1051 	return 0;
1052 }
1053 
1054 /*
1055  * This function supports usb interrupt transfers. Currently, usb interrupt
1056  * transfers are not supported.
1057  */
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval)1058 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1059 				void *buffer, int len, int interval)
1060 {
1061 	int dir_out = usb_pipeout(pipe);
1062 	int ep = usb_pipeendpoint(pipe);
1063 #ifndef MUSB_NO_MULTIPOINT
1064 	int devnum = usb_pipedevice(pipe);
1065 #endif
1066 	u8  type;
1067 	u16 csr;
1068 	u32 txlen = 0;
1069 	u32 nextlen = 0;
1070 	u8  devspeed;
1071 
1072 	/* select interrupt endpoint */
1073 	writeb(MUSB_INTR_EP, &musbr->index);
1074 
1075 #ifndef MUSB_NO_MULTIPOINT
1076 	/* write the address of the device */
1077 	if (dir_out)
1078 		writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1079 	else
1080 		writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1081 #endif
1082 
1083 	/* configure the hub address and the port number as required */
1084 	devspeed = get_dev_speed(dev);
1085 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1086 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
1087 		/*
1088 		 * MUSB is in high speed and the destination device is full
1089 		 * speed device. So configure the hub address and port
1090 		 * address registers.
1091 		 */
1092 		config_hub_port(dev, MUSB_INTR_EP);
1093 	} else {
1094 #ifndef MUSB_NO_MULTIPOINT
1095 		if (dir_out) {
1096 			writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1097 			writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1098 		} else {
1099 			writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1100 			writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1101 		}
1102 #endif
1103 		devspeed = musb_cfg.musb_speed;
1104 	}
1105 
1106 	/* Write the saved toggle bit value */
1107 	write_toggle(dev, ep, dir_out);
1108 
1109 	if (!dir_out) { /* intrrupt-in transfer */
1110 		/* Write the saved toggle bit value */
1111 		write_toggle(dev, ep, dir_out);
1112 		writeb(interval, &musbr->rxinterval);
1113 
1114 		/* Program the RxType register */
1115 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1116 			   (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1117 			   (ep & MUSB_TYPE_REMOTE_END);
1118 		writeb(type, &musbr->rxtype);
1119 
1120 		/* Write the maximum packet size to the RxMaxp register */
1121 		writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1122 
1123 		while (txlen < len) {
1124 			nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1125 					(len-txlen) : dev->epmaxpacketin[ep];
1126 
1127 			/* Set the ReqPkt bit */
1128 			csr = readw(&musbr->rxcsr);
1129 			writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1130 
1131 			/* Wait until the RxPktRdy bit is set */
1132 			if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1133 				csr = readw(&musbr->rxcsr);
1134 				usb_settoggle(dev, ep, dir_out,
1135 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1136 				csr &= ~MUSB_RXCSR_RXPKTRDY;
1137 				writew(csr, &musbr->rxcsr);
1138 				dev->act_len = txlen;
1139 				return 0;
1140 			}
1141 
1142 			/* Read the data from the FIFO */
1143 			read_fifo(MUSB_INTR_EP, nextlen,
1144 					(void *)(((u8 *)buffer) + txlen));
1145 
1146 			/* Clear the RxPktRdy bit */
1147 			csr =  readw(&musbr->rxcsr);
1148 			csr &= ~MUSB_RXCSR_RXPKTRDY;
1149 			writew(csr, &musbr->rxcsr);
1150 			txlen += nextlen;
1151 		}
1152 
1153 		/* Keep a copy of the data toggle bit */
1154 		csr = readw(&musbr->rxcsr);
1155 		usb_settoggle(dev, ep, dir_out,
1156 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1157 	}
1158 
1159 	/* interrupt transfer is complete */
1160 	dev->irq_status = 0;
1161 	dev->irq_act_len = len;
1162 	dev->irq_handle(dev);
1163 	dev->status = 0;
1164 	dev->act_len = len;
1165 	return 0;
1166 }
1167