1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Synopsys DesignWare Multimedia Card Interface driver
4 * (Based on NXP driver for lpc 31xx)
5 *
6 * Copyright (C) 2009 NXP Semiconductors
7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 */
9
10 #ifndef _DW_MMC_H_
11 #define _DW_MMC_H_
12
13 #include <linux/scatterlist.h>
14 #include <linux/mmc/core.h>
15 #include <linux/dmaengine.h>
16 #include <linux/reset.h>
17 #include <linux/fault-inject.h>
18 #include <linux/hrtimer.h>
19 #include <linux/interrupt.h>
20
21 enum dw_mci_state {
22 STATE_IDLE = 0,
23 STATE_SENDING_CMD,
24 STATE_SENDING_DATA,
25 STATE_DATA_BUSY,
26 STATE_SENDING_STOP,
27 STATE_DATA_ERROR,
28 STATE_SENDING_CMD11,
29 STATE_WAITING_CMD11_DONE,
30 };
31
32 enum {
33 EVENT_CMD_COMPLETE = 0,
34 EVENT_XFER_COMPLETE,
35 EVENT_DATA_COMPLETE,
36 EVENT_DATA_ERROR,
37 };
38
39 enum dw_mci_cookie {
40 COOKIE_UNMAPPED,
41 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
42 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
43 };
44
45 struct mmc_data;
46
47 enum {
48 TRANS_MODE_PIO = 0,
49 TRANS_MODE_IDMAC,
50 TRANS_MODE_EDMAC
51 };
52
53 struct dw_mci_dma_slave {
54 struct dma_chan *ch;
55 enum dma_transfer_direction direction;
56 };
57
58 /**
59 * struct dw_mci - MMC controller state shared between all slots
60 * @lock: Spinlock protecting the queue and associated data.
61 * @irq_lock: Spinlock protecting the INTMASK setting.
62 * @regs: Pointer to MMIO registers.
63 * @fifo_reg: Pointer to MMIO registers for data FIFO
64 * @sg: Scatterlist entry currently being processed by PIO code, if any.
65 * @sg_miter: PIO mapping scatterlist iterator.
66 * @mrq: The request currently being processed on @slot,
67 * or NULL if the controller is idle.
68 * @cmd: The command currently being sent to the card, or NULL.
69 * @data: The data currently being transferred, or NULL if no data
70 * transfer is in progress.
71 * @stop_abort: The command currently prepared for stoping transfer.
72 * @prev_blksz: The former transfer blksz record.
73 * @timing: Record of current ios timing.
74 * @use_dma: Which DMA channel is in use for the current transfer, zero
75 * denotes PIO mode.
76 * @using_dma: Whether DMA is in use for the current transfer.
77 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
78 * @sg_dma: Bus address of DMA buffer.
79 * @sg_cpu: Virtual address of DMA buffer.
80 * @dma_ops: Pointer to platform-specific DMA callbacks.
81 * @cmd_status: Snapshot of SR taken upon completion of the current
82 * @ring_size: Buffer size for idma descriptors.
83 * command. Only valid when EVENT_CMD_COMPLETE is pending.
84 * @dms: structure of slave-dma private data.
85 * @phy_regs: physical address of controller's register map
86 * @data_status: Snapshot of SR taken upon completion of the current
87 * data transfer. Only valid when EVENT_DATA_COMPLETE or
88 * EVENT_DATA_ERROR is pending.
89 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
90 * to be sent.
91 * @dir_status: Direction of current transfer.
92 * @tasklet: Tasklet running the request state machine.
93 * @pending_events: Bitmask of events flagged by the interrupt handler
94 * to be processed by the tasklet.
95 * @completed_events: Bitmask of events which the state machine has
96 * processed.
97 * @state: Tasklet state.
98 * @queue: List of slots waiting for access to the controller.
99 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
100 * rate and timeout calculations.
101 * @current_speed: Configured rate of the controller.
102 * @minimum_speed: Stored minimum rate of the controller.
103 * @fifoth_val: The value of FIFOTH register.
104 * @verid: Denote Version ID.
105 * @dev: Device associated with the MMC controller.
106 * @pdata: Platform data associated with the MMC controller.
107 * @drv_data: Driver specific data for identified variant of the controller
108 * @priv: Implementation defined private data.
109 * @biu_clk: Pointer to bus interface unit clock instance.
110 * @ciu_clk: Pointer to card interface unit clock instance.
111 * @slot: Slots sharing this MMC controller.
112 * @fifo_depth: depth of FIFO.
113 * @data_addr_override: override fifo reg offset with this value.
114 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
115 * Set as true if alignment is needed.
116 * @data_shift: log2 of FIFO item size.
117 * @part_buf_start: Start index in part_buf.
118 * @part_buf_count: Bytes of partial data in part_buf.
119 * @part_buf: Simple buffer for partial fifo reads/writes.
120 * @push_data: Pointer to FIFO push function.
121 * @pull_data: Pointer to FIFO pull function.
122 * @quirks: Set of quirks that apply to specific versions of the IP.
123 * @vqmmc_enabled: Status of vqmmc, should be true or false.
124 * @irq_flags: The flags to be passed to request_irq.
125 * @irq: The irq value to be passed to request_irq.
126 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
127 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
128 * @cto_timer: Timer for broken command transfer over scheme.
129 * @dto_timer: Timer for broken data transfer over scheme.
130 *
131 * Locking
132 * =======
133 *
134 * @lock is a softirq-safe spinlock protecting @queue as well as
135 * @slot, @mrq and @state. These must always be updated
136 * at the same time while holding @lock.
137 * The @mrq field of struct dw_mci_slot is also protected by @lock,
138 * and must always be written at the same time as the slot is added to
139 * @queue.
140 *
141 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
142 * to allow the interrupt handler to modify it directly. Held for only long
143 * enough to read-modify-write INTMASK and no other locks are grabbed when
144 * holding this one.
145 *
146 * @pending_events and @completed_events are accessed using atomic bit
147 * operations, so they don't need any locking.
148 *
149 * None of the fields touched by the interrupt handler need any
150 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
151 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
152 * interrupts must be disabled and @data_status updated with a
153 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
154 * CMDRDY interrupt must be disabled and @cmd_status updated with a
155 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
156 * bytes_xfered field of @data must be written. This is ensured by
157 * using barriers.
158 */
159 struct dw_mci {
160 spinlock_t lock;
161 spinlock_t irq_lock;
162 void __iomem *regs;
163 void __iomem *fifo_reg;
164 u32 data_addr_override;
165 bool wm_aligned;
166
167 struct scatterlist *sg;
168 struct sg_mapping_iter sg_miter;
169
170 struct mmc_request *mrq;
171 struct mmc_command *cmd;
172 struct mmc_data *data;
173 struct mmc_command stop_abort;
174 unsigned int prev_blksz;
175 unsigned char timing;
176
177 /* DMA interface members*/
178 int use_dma;
179 int using_dma;
180 int dma_64bit_address;
181
182 dma_addr_t sg_dma;
183 void *sg_cpu;
184 const struct dw_mci_dma_ops *dma_ops;
185 /* For idmac */
186 unsigned int ring_size;
187
188 /* For edmac */
189 struct dw_mci_dma_slave *dms;
190 /* Registers's physical base address */
191 resource_size_t phy_regs;
192
193 u32 cmd_status;
194 u32 data_status;
195 u32 stop_cmdr;
196 u32 dir_status;
197 struct tasklet_struct tasklet;
198 unsigned long pending_events;
199 unsigned long completed_events;
200 enum dw_mci_state state;
201 struct list_head queue;
202
203 u32 bus_hz;
204 u32 current_speed;
205 u32 minimum_speed;
206 u32 fifoth_val;
207 u16 verid;
208 struct device *dev;
209 struct dw_mci_board *pdata;
210 const struct dw_mci_drv_data *drv_data;
211 void *priv;
212 struct clk *biu_clk;
213 struct clk *ciu_clk;
214 struct dw_mci_slot *slot;
215
216 /* FIFO push and pull */
217 int fifo_depth;
218 int data_shift;
219 u8 part_buf_start;
220 u8 part_buf_count;
221 union {
222 u16 part_buf16;
223 u32 part_buf32;
224 u64 part_buf;
225 };
226 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
227 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
228
229 u32 quirks;
230 bool vqmmc_enabled;
231 unsigned long irq_flags; /* IRQ flags */
232 int irq;
233
234 int sdio_id0;
235
236 struct timer_list cmd11_timer;
237 struct timer_list cto_timer;
238 struct timer_list dto_timer;
239
240 #ifdef CONFIG_FAULT_INJECTION
241 struct fault_attr fail_data_crc;
242 struct hrtimer fault_timer;
243 #endif
244 };
245
246 /* DMA ops for Internal/External DMAC interface */
247 struct dw_mci_dma_ops {
248 /* DMA Ops */
249 int (*init)(struct dw_mci *host);
250 int (*start)(struct dw_mci *host, unsigned int sg_len);
251 void (*complete)(void *host);
252 void (*stop)(struct dw_mci *host);
253 void (*cleanup)(struct dw_mci *host);
254 void (*exit)(struct dw_mci *host);
255 };
256
257 struct dma_pdata;
258
259 /* Board platform data */
260 struct dw_mci_board {
261 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
262
263 u32 caps; /* Capabilities */
264 u32 caps2; /* More capabilities */
265 u32 pm_caps; /* PM capabilities */
266 /*
267 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
268 * but note that this may not be reliable after a bootloader has used
269 * it.
270 */
271 unsigned int fifo_depth;
272
273 /* delay in mS before detecting cards after interrupt */
274 u32 detect_delay_ms;
275
276 struct reset_control *rstc;
277 struct dw_mci_dma_ops *dma_ops;
278 struct dma_pdata *data;
279 };
280
281 /* Support for longer data read timeout */
282 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
283 /* Force 32-bit access to the FIFO */
284 #define DW_MMC_QUIRK_FIFO64_32 BIT(1)
285
286 #define DW_MMC_240A 0x240a
287 #define DW_MMC_280A 0x280a
288
289 #define SDMMC_CTRL 0x000
290 #define SDMMC_PWREN 0x004
291 #define SDMMC_CLKDIV 0x008
292 #define SDMMC_CLKSRC 0x00c
293 #define SDMMC_CLKENA 0x010
294 #define SDMMC_TMOUT 0x014
295 #define SDMMC_CTYPE 0x018
296 #define SDMMC_BLKSIZ 0x01c
297 #define SDMMC_BYTCNT 0x020
298 #define SDMMC_INTMASK 0x024
299 #define SDMMC_CMDARG 0x028
300 #define SDMMC_CMD 0x02c
301 #define SDMMC_RESP0 0x030
302 #define SDMMC_RESP1 0x034
303 #define SDMMC_RESP2 0x038
304 #define SDMMC_RESP3 0x03c
305 #define SDMMC_MINTSTS 0x040
306 #define SDMMC_RINTSTS 0x044
307 #define SDMMC_STATUS 0x048
308 #define SDMMC_FIFOTH 0x04c
309 #define SDMMC_CDETECT 0x050
310 #define SDMMC_WRTPRT 0x054
311 #define SDMMC_GPIO 0x058
312 #define SDMMC_TCBCNT 0x05c
313 #define SDMMC_TBBCNT 0x060
314 #define SDMMC_DEBNCE 0x064
315 #define SDMMC_USRID 0x068
316 #define SDMMC_VERID 0x06c
317 #define SDMMC_HCON 0x070
318 #define SDMMC_UHS_REG 0x074
319 #define SDMMC_RST_N 0x078
320 #define SDMMC_BMOD 0x080
321 #define SDMMC_PLDMND 0x084
322 #define SDMMC_DBADDR 0x088
323 #define SDMMC_IDSTS 0x08c
324 #define SDMMC_IDINTEN 0x090
325 #define SDMMC_DSCADDR 0x094
326 #define SDMMC_BUFADDR 0x098
327 #define SDMMC_CDTHRCTL 0x100
328 #define SDMMC_UHS_REG_EXT 0x108
329 #define SDMMC_DDR_REG 0x10c
330 #define SDMMC_ENABLE_SHIFT 0x110
331 #define SDMMC_DATA(x) (x)
332 /*
333 * Registers to support idmac 64-bit address mode
334 */
335 #define SDMMC_DBADDRL 0x088
336 #define SDMMC_DBADDRU 0x08c
337 #define SDMMC_IDSTS64 0x090
338 #define SDMMC_IDINTEN64 0x094
339 #define SDMMC_DSCADDRL 0x098
340 #define SDMMC_DSCADDRU 0x09c
341 #define SDMMC_BUFADDRL 0x0A0
342 #define SDMMC_BUFADDRU 0x0A4
343
344 /*
345 * Data offset is difference according to Version
346 * Lower than 2.40a : data register offest is 0x100
347 */
348 #define DATA_OFFSET 0x100
349 #define DATA_240A_OFFSET 0x200
350
351 /* shift bit field */
352 #define _SBF(f, v) ((v) << (f))
353
354 /* Control register defines */
355 #define SDMMC_CTRL_USE_IDMAC BIT(25)
356 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
357 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
358 #define SDMMC_CTRL_SEND_CCSD BIT(9)
359 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
360 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
361 #define SDMMC_CTRL_READ_WAIT BIT(6)
362 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
363 #define SDMMC_CTRL_INT_ENABLE BIT(4)
364 #define SDMMC_CTRL_DMA_RESET BIT(2)
365 #define SDMMC_CTRL_FIFO_RESET BIT(1)
366 #define SDMMC_CTRL_RESET BIT(0)
367 /* Clock Enable register defines */
368 #define SDMMC_CLKEN_LOW_PWR BIT(16)
369 #define SDMMC_CLKEN_ENABLE BIT(0)
370 /* time-out register defines */
371 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
372 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
373 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
374 #define SDMMC_TMOUT_RESP_MSK 0xFF
375 /* card-type register defines */
376 #define SDMMC_CTYPE_8BIT BIT(16)
377 #define SDMMC_CTYPE_4BIT BIT(0)
378 #define SDMMC_CTYPE_1BIT 0
379 /* Interrupt status & mask register defines */
380 #define SDMMC_INT_SDIO(n) BIT(16 + (n))
381 #define SDMMC_INT_EBE BIT(15)
382 #define SDMMC_INT_ACD BIT(14)
383 #define SDMMC_INT_SBE BIT(13)
384 #define SDMMC_INT_HLE BIT(12)
385 #define SDMMC_INT_FRUN BIT(11)
386 #define SDMMC_INT_HTO BIT(10)
387 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
388 #define SDMMC_INT_DRTO BIT(9)
389 #define SDMMC_INT_RTO BIT(8)
390 #define SDMMC_INT_DCRC BIT(7)
391 #define SDMMC_INT_RCRC BIT(6)
392 #define SDMMC_INT_RXDR BIT(5)
393 #define SDMMC_INT_TXDR BIT(4)
394 #define SDMMC_INT_DATA_OVER BIT(3)
395 #define SDMMC_INT_CMD_DONE BIT(2)
396 #define SDMMC_INT_RESP_ERR BIT(1)
397 #define SDMMC_INT_CD BIT(0)
398 #define SDMMC_INT_ERROR 0xbfc2
399 /* Command register defines */
400 #define SDMMC_CMD_START BIT(31)
401 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
402 #define SDMMC_CMD_VOLT_SWITCH BIT(28)
403 #define SDMMC_CMD_CCS_EXP BIT(23)
404 #define SDMMC_CMD_CEATA_RD BIT(22)
405 #define SDMMC_CMD_UPD_CLK BIT(21)
406 #define SDMMC_CMD_INIT BIT(15)
407 #define SDMMC_CMD_STOP BIT(14)
408 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
409 #define SDMMC_CMD_SEND_STOP BIT(12)
410 #define SDMMC_CMD_STRM_MODE BIT(11)
411 #define SDMMC_CMD_DAT_WR BIT(10)
412 #define SDMMC_CMD_DAT_EXP BIT(9)
413 #define SDMMC_CMD_RESP_CRC BIT(8)
414 #define SDMMC_CMD_RESP_LONG BIT(7)
415 #define SDMMC_CMD_RESP_EXP BIT(6)
416 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
417 /* Status register defines */
418 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
419 #define SDMMC_STATUS_DMA_REQ BIT(31)
420 #define SDMMC_STATUS_BUSY BIT(9)
421 /* FIFOTH register defines */
422 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
423 ((r) & 0xFFF) << 16 | \
424 ((t) & 0xFFF))
425 /* HCON register defines */
426 #define DMA_INTERFACE_IDMA (0x0)
427 #define DMA_INTERFACE_DWDMA (0x1)
428 #define DMA_INTERFACE_GDMA (0x2)
429 #define DMA_INTERFACE_NODMA (0x3)
430 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
431 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
432 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
433 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
434 /* Internal DMAC interrupt defines */
435 #define SDMMC_IDMAC_INT_AI BIT(9)
436 #define SDMMC_IDMAC_INT_NI BIT(8)
437 #define SDMMC_IDMAC_INT_CES BIT(5)
438 #define SDMMC_IDMAC_INT_DU BIT(4)
439 #define SDMMC_IDMAC_INT_FBE BIT(2)
440 #define SDMMC_IDMAC_INT_RI BIT(1)
441 #define SDMMC_IDMAC_INT_TI BIT(0)
442 /* Internal DMAC bus mode bits */
443 #define SDMMC_IDMAC_ENABLE BIT(7)
444 #define SDMMC_IDMAC_FB BIT(1)
445 #define SDMMC_IDMAC_SWRESET BIT(0)
446 /* H/W reset */
447 #define SDMMC_RST_HWACTIVE 0x1
448 /* Version ID register define */
449 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
450 /* Card read threshold */
451 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
452 #define SDMMC_CARD_WR_THR_EN BIT(2)
453 #define SDMMC_CARD_RD_THR_EN BIT(0)
454 /* UHS-1 register defines */
455 #define SDMMC_UHS_DDR BIT(16)
456 #define SDMMC_UHS_18V BIT(0)
457 /* DDR register defines */
458 #define SDMMC_DDR_HS400 BIT(31)
459 /* Enable shift register defines */
460 #define SDMMC_ENABLE_PHASE BIT(0)
461 /* All ctrl reset bits */
462 #define SDMMC_CTRL_ALL_RESET_FLAGS \
463 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
464
465 /* FIFO register access macros. These should not change the data endian-ness
466 * as they are written to memory to be dealt with by the upper layers
467 */
468 #define mci_fifo_readw(__reg) __raw_readw(__reg)
469 #define mci_fifo_readl(__reg) __raw_readl(__reg)
470 #define mci_fifo_readq(__reg) __raw_readq(__reg)
471
472 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
473 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
474 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
475
476 /*
477 * Some dw_mmc devices have 64-bit FIFOs, but expect them to be
478 * accessed using two 32-bit accesses. If such controller is used
479 * with a 64-bit kernel, this has to be done explicitly.
480 */
mci_fifo_l_readq(void __iomem * addr)481 static inline u64 mci_fifo_l_readq(void __iomem *addr)
482 {
483 u64 ans;
484 u32 proxy[2];
485
486 proxy[0] = mci_fifo_readl(addr);
487 proxy[1] = mci_fifo_readl(addr + 4);
488 memcpy(&ans, proxy, 8);
489 return ans;
490 }
491
mci_fifo_l_writeq(void __iomem * addr,u64 value)492 static inline void mci_fifo_l_writeq(void __iomem *addr, u64 value)
493 {
494 u32 proxy[2];
495
496 memcpy(proxy, &value, 8);
497 mci_fifo_writel(addr, proxy[0]);
498 mci_fifo_writel(addr + 4, proxy[1]);
499 }
500
501 /* Register access macros */
502 #define mci_readl(dev, reg) \
503 readl_relaxed((dev)->regs + SDMMC_##reg)
504 #define mci_writel(dev, reg, value) \
505 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
506
507 /* 16-bit FIFO access macros */
508 #define mci_readw(dev, reg) \
509 readw_relaxed((dev)->regs + SDMMC_##reg)
510 #define mci_writew(dev, reg, value) \
511 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
512
513 /* 64-bit FIFO access macros */
514 #ifdef readq
515 #define mci_readq(dev, reg) \
516 readq_relaxed((dev)->regs + SDMMC_##reg)
517 #define mci_writeq(dev, reg, value) \
518 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
519 #else
520 /*
521 * Dummy readq implementation for architectures that don't define it.
522 *
523 * We would assume that none of these architectures would configure
524 * the IP block with a 64bit FIFO width, so this code will never be
525 * executed on those machines. Defining these macros here keeps the
526 * rest of the code free from ifdefs.
527 */
528 #define mci_readq(dev, reg) \
529 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
530 #define mci_writeq(dev, reg, value) \
531 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
532
533 #define __raw_writeq(__value, __reg) \
534 (*(volatile u64 __force *)(__reg) = (__value))
535 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
536 #endif
537
538 extern int dw_mci_probe(struct dw_mci *host);
539 extern void dw_mci_remove(struct dw_mci *host);
540 #ifdef CONFIG_PM
541 extern int dw_mci_runtime_suspend(struct device *device);
542 extern int dw_mci_runtime_resume(struct device *device);
543 #endif
544
545 /**
546 * struct dw_mci_slot - MMC slot state
547 * @mmc: The mmc_host representing this slot.
548 * @host: The MMC controller this slot is using.
549 * @ctype: Card type for this slot.
550 * @mrq: mmc_request currently being processed or waiting to be
551 * processed, or NULL when the slot is idle.
552 * @queue_node: List node for placing this node in the @queue list of
553 * &struct dw_mci.
554 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
555 * @__clk_old: The last clock value that was requested from core.
556 * Keeping track of this helps us to avoid spamming the console.
557 * @flags: Random state bits associated with the slot.
558 * @id: Number of this slot.
559 * @sdio_id: Number of this slot in the SDIO interrupt registers.
560 */
561 struct dw_mci_slot {
562 struct mmc_host *mmc;
563 struct dw_mci *host;
564
565 u32 ctype;
566
567 struct mmc_request *mrq;
568 struct list_head queue_node;
569
570 unsigned int clock;
571 unsigned int __clk_old;
572
573 unsigned long flags;
574 #define DW_MMC_CARD_PRESENT 0
575 #define DW_MMC_CARD_NEED_INIT 1
576 #define DW_MMC_CARD_NO_LOW_PWR 2
577 #define DW_MMC_CARD_NO_USE_HOLD 3
578 #define DW_MMC_CARD_NEEDS_POLL 4
579 int id;
580 int sdio_id;
581 };
582
583 /**
584 * dw_mci driver data - dw-mshc implementation specific driver data.
585 * @caps: mmc subsystem specified capabilities of the controller(s).
586 * @num_caps: number of capabilities specified by @caps.
587 * @common_caps: mmc subsystem specified capabilities applicable to all of
588 * the controllers
589 * @init: early implementation specific initialization.
590 * @set_ios: handle bus specific extensions.
591 * @parse_dt: parse implementation specific device tree properties.
592 * @execute_tuning: implementation specific tuning procedure.
593 * @set_data_timeout: implementation specific timeout.
594 * @get_drto_clks: implementation specific cycle count for data read timeout.
595 *
596 * Provide controller implementation specific extensions. The usage of this
597 * data structure is fully optional and usage of each member in this structure
598 * is optional as well.
599 */
600 struct dw_mci_drv_data {
601 unsigned long *caps;
602 u32 num_caps;
603 u32 common_caps;
604 int (*init)(struct dw_mci *host);
605 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
606 int (*parse_dt)(struct dw_mci *host);
607 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
608 int (*prepare_hs400_tuning)(struct dw_mci *host,
609 struct mmc_ios *ios);
610 int (*switch_voltage)(struct mmc_host *mmc,
611 struct mmc_ios *ios);
612 void (*set_data_timeout)(struct dw_mci *host,
613 unsigned int timeout_ns);
614 u32 (*get_drto_clks)(struct dw_mci *host);
615 };
616 #endif /* _DW_MMC_H_ */
617