1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Support for Intel Camera Imaging ISP subsystem.
4  * Copyright (c) 2015, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  */
15 
16 #ifndef __CSI_RX_PRIVATE_H_INCLUDED__
17 #define __CSI_RX_PRIVATE_H_INCLUDED__
18 
19 #include "rx_csi_defs.h"
20 #include "mipi_backend_defs.h"
21 #include "csi_rx.h"
22 
23 #include "device_access.h"	/* ia_css_device_load_uint32 */
24 
25 #include "assert_support.h" /* assert */
26 #include "print_support.h" /* print */
27 
28 /*****************************************************
29  *
30  * Device level interface (DLI).
31  *
32  *****************************************************/
33 /**
34  * @brief Load the register value.
35  * Refer to "csi_rx_public.h" for details.
36  */
csi_rx_fe_ctrl_reg_load(const csi_rx_frontend_ID_t ID,const hrt_address reg)37 static inline hrt_data csi_rx_fe_ctrl_reg_load(
38     const csi_rx_frontend_ID_t ID,
39     const hrt_address reg)
40 {
41 	assert(ID < N_CSI_RX_FRONTEND_ID);
42 	assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
43 	return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(
44 					     hrt_data));
45 }
46 
47 /**
48  * @brief Store a value to the register.
49  * Refer to "ibuf_ctrl_public.h" for details.
50  */
csi_rx_fe_ctrl_reg_store(const csi_rx_frontend_ID_t ID,const hrt_address reg,const hrt_data value)51 static inline void csi_rx_fe_ctrl_reg_store(
52     const csi_rx_frontend_ID_t ID,
53     const hrt_address reg,
54     const hrt_data value)
55 {
56 	assert(ID < N_CSI_RX_FRONTEND_ID);
57 	assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
58 
59 	ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
60 				   value);
61 }
62 
63 /**
64  * @brief Load the register value.
65  * Refer to "csi_rx_public.h" for details.
66  */
csi_rx_be_ctrl_reg_load(const csi_rx_backend_ID_t ID,const hrt_address reg)67 static inline hrt_data csi_rx_be_ctrl_reg_load(
68     const csi_rx_backend_ID_t ID,
69     const hrt_address reg)
70 {
71 	assert(ID < N_CSI_RX_BACKEND_ID);
72 	assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
73 	return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(
74 					     hrt_data));
75 }
76 
77 /**
78  * @brief Store a value to the register.
79  * Refer to "ibuf_ctrl_public.h" for details.
80  */
csi_rx_be_ctrl_reg_store(const csi_rx_backend_ID_t ID,const hrt_address reg,const hrt_data value)81 static inline void csi_rx_be_ctrl_reg_store(
82     const csi_rx_backend_ID_t ID,
83     const hrt_address reg,
84     const hrt_data value)
85 {
86 	assert(ID < N_CSI_RX_BACKEND_ID);
87 	assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
88 
89 	ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
90 				   value);
91 }
92 
93 /* end of DLI */
94 
95 /*****************************************************
96  *
97  * Native command interface (NCI).
98  *
99  *****************************************************/
100 /**
101  * @brief Get the state of the csi rx fe dlane process.
102  * Refer to "csi_rx_public.h" for details.
103  */
csi_rx_fe_ctrl_get_dlane_state(const csi_rx_frontend_ID_t ID,const u32 lane,csi_rx_fe_ctrl_lane_t * dlane_state)104 static inline void csi_rx_fe_ctrl_get_dlane_state(
105     const csi_rx_frontend_ID_t ID,
106     const u32 lane,
107     csi_rx_fe_ctrl_lane_t *dlane_state)
108 {
109 	dlane_state->termen =
110 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
111 	dlane_state->settle =
112 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
113 }
114 
115 /**
116  * @brief Get the csi rx fe state.
117  * Refer to "csi_rx_public.h" for details.
118  */
csi_rx_fe_ctrl_get_state(const csi_rx_frontend_ID_t ID,csi_rx_fe_ctrl_state_t * state)119 static inline void csi_rx_fe_ctrl_get_state(
120     const csi_rx_frontend_ID_t ID,
121     csi_rx_fe_ctrl_state_t *state)
122 {
123 	u32 i;
124 
125 	state->enable =
126 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
127 	state->nof_enable_lanes =
128 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX);
129 	state->error_handling =
130 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX);
131 	state->status =
132 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX);
133 	state->status_dlane_hs =
134 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX);
135 	state->status_dlane_lp =
136 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX);
137 	state->clane.termen =
138 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX);
139 	state->clane.settle =
140 	    csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX);
141 
142 	/*
143 	 * Get the values of the register-set per
144 	 * dlane.
145 	 */
146 	for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
147 		csi_rx_fe_ctrl_get_dlane_state(
148 		    ID,
149 		    i,
150 		    &state->dlane[i]);
151 	}
152 }
153 
154 /**
155  * @brief dump the csi rx fe state.
156  * Refer to "csi_rx_public.h" for details.
157  */
csi_rx_fe_ctrl_dump_state(const csi_rx_frontend_ID_t ID,csi_rx_fe_ctrl_state_t * state)158 static inline void csi_rx_fe_ctrl_dump_state(
159     const csi_rx_frontend_ID_t ID,
160     csi_rx_fe_ctrl_state_t *state)
161 {
162 	u32 i;
163 
164 	ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID,
165 		     state->enable);
166 	ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID,
167 		     state->nof_enable_lanes);
168 	ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID,
169 		     state->error_handling);
170 	ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status);
171 	ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID,
172 		     state->status_dlane_hs);
173 	ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID,
174 		     state->status_dlane_lp);
175 	ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID,
176 		     state->clane.termen);
177 	ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID,
178 		     state->clane.settle);
179 
180 	/*
181 	 * Get the values of the register-set per
182 	 * dlane.
183 	 */
184 	for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
185 		ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i,
186 			     state->dlane[i].termen);
187 		ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i,
188 			     state->dlane[i].settle);
189 	}
190 }
191 
192 /**
193  * @brief Get the csi rx be state.
194  * Refer to "csi_rx_public.h" for details.
195  */
csi_rx_be_ctrl_get_state(const csi_rx_backend_ID_t ID,csi_rx_be_ctrl_state_t * state)196 static inline void csi_rx_be_ctrl_get_state(
197     const csi_rx_backend_ID_t ID,
198     csi_rx_be_ctrl_state_t *state)
199 {
200 	u32 i;
201 
202 	state->enable =
203 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
204 
205 	state->status =
206 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
207 
208 	for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
209 		state->comp_format_reg[i] =
210 		    csi_rx_be_ctrl_reg_load(ID,
211 					    _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i);
212 	}
213 
214 	state->raw16 =
215 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX);
216 
217 	state->raw18 =
218 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX);
219 	state->force_raw8 =
220 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX);
221 	state->irq_status =
222 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX);
223 #if 0 /* device access error for these registers */
224 	/* ToDo: rootcause this failure */
225 	state->custom_mode_enable =
226 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX);
227 
228 	state->custom_mode_data_state =
229 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
230 	for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
231 		state->pec[i] =
232 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
233 	}
234 	state->custom_mode_valid_eop_config =
235 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX);
236 #endif
237 	state->global_lut_disregard_reg =
238 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX);
239 	state->packet_status_stall =
240 	    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX);
241 	/*
242 	 * Get the values of the register-set per
243 	 * lut.
244 	 */
245 	for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
246 		state->short_packet_lut_entry[i] =
247 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i);
248 	}
249 	for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
250 		state->long_packet_lut_entry[i] =
251 		    csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i);
252 	}
253 }
254 
255 /**
256  * @brief Dump the csi rx be state.
257  * Refer to "csi_rx_public.h" for details.
258  */
csi_rx_be_ctrl_dump_state(const csi_rx_backend_ID_t ID,csi_rx_be_ctrl_state_t * state)259 static inline void csi_rx_be_ctrl_dump_state(
260     const csi_rx_backend_ID_t ID,
261     csi_rx_be_ctrl_state_t *state)
262 {
263 	u32 i;
264 
265 	ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable);
266 	ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status);
267 
268 	for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
269 		ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n",
270 			     ID, i, state->status);
271 	}
272 	ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16);
273 	ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18);
274 	ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID,
275 		     state->force_raw8);
276 	ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID,
277 		     state->irq_status);
278 #if 0   /* ToDo:Getting device access error for this register */
279 	for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
280 		ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i,
281 			     state->pec[i]);
282 	}
283 #endif
284 	ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n",
285 		     ID, state->global_lut_disregard_reg);
286 	ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID,
287 		     state->packet_status_stall);
288 	/*
289 	 * Get the values of the register-set per
290 	 * lut.
291 	 */
292 	for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
293 		ia_css_print("CSI RX BE STATE Controller ID %d Short packet entry %d short packet lut id 0x%x\n",
294 			     ID, i,
295 			     state->short_packet_lut_entry[i]);
296 	}
297 	for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
298 		ia_css_print("CSI RX BE STATE Controller ID %d Long packet entry %d long packet lut id 0x%x\n",
299 			     ID, i,
300 			     state->long_packet_lut_entry[i]);
301 	}
302 }
303 
304 /* end of NCI */
305 
306 #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */
307