1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Components shared between ASoC and HDA CS35L56 drivers
4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/gpio/consumer.h>
9 #include <linux/regmap.h>
10 #include <linux/regulator/consumer.h>
11 #include <linux/types.h>
12
13 #include "cs35l56.h"
14
15 static const struct reg_sequence cs35l56_patch[] = {
16 /* These are not reset by a soft-reset, so patch to defaults. */
17 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
18 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
19 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
20 };
21
cs35l56_set_patch(struct cs35l56_base * cs35l56_base)22 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
23 {
24 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
25 ARRAY_SIZE(cs35l56_patch));
26 }
27 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
28
29 static const struct reg_default cs35l56_reg_defaults[] = {
30 { CS35L56_ASP1_ENABLES1, 0x00000000 },
31 { CS35L56_ASP1_CONTROL1, 0x00000028 },
32 { CS35L56_ASP1_CONTROL2, 0x18180200 },
33 { CS35L56_ASP1_CONTROL3, 0x00000002 },
34 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
35 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
36 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
37 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
38
39 /* no defaults for ASP1TX mixer */
40
41 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
42 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
43 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
44 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
45 { CS35L56_IRQ1_CFG, 0x00000000 },
46 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
47 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
48 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
49 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
50 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
51 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
52 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
53 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
54 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
55 };
56
cs35l56_is_dsp_memory(unsigned int reg)57 static bool cs35l56_is_dsp_memory(unsigned int reg)
58 {
59 switch (reg) {
60 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
61 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
62 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
63 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
64 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
65 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
66 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
67 return true;
68 default:
69 return false;
70 }
71 }
72
cs35l56_readable_reg(struct device * dev,unsigned int reg)73 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
74 {
75 switch (reg) {
76 case CS35L56_DEVID:
77 case CS35L56_REVID:
78 case CS35L56_RELID:
79 case CS35L56_OTPID:
80 case CS35L56_SFT_RESET:
81 case CS35L56_GLOBAL_ENABLES:
82 case CS35L56_BLOCK_ENABLES:
83 case CS35L56_BLOCK_ENABLES2:
84 case CS35L56_REFCLK_INPUT:
85 case CS35L56_GLOBAL_SAMPLE_RATE:
86 case CS35L56_ASP1_ENABLES1:
87 case CS35L56_ASP1_CONTROL1:
88 case CS35L56_ASP1_CONTROL2:
89 case CS35L56_ASP1_CONTROL3:
90 case CS35L56_ASP1_FRAME_CONTROL1:
91 case CS35L56_ASP1_FRAME_CONTROL5:
92 case CS35L56_ASP1_DATA_CONTROL1:
93 case CS35L56_ASP1_DATA_CONTROL5:
94 case CS35L56_DACPCM1_INPUT:
95 case CS35L56_DACPCM2_INPUT:
96 case CS35L56_ASP1TX1_INPUT:
97 case CS35L56_ASP1TX2_INPUT:
98 case CS35L56_ASP1TX3_INPUT:
99 case CS35L56_ASP1TX4_INPUT:
100 case CS35L56_DSP1RX1_INPUT:
101 case CS35L56_DSP1RX2_INPUT:
102 case CS35L56_SWIRE_DP3_CH1_INPUT:
103 case CS35L56_SWIRE_DP3_CH2_INPUT:
104 case CS35L56_SWIRE_DP3_CH3_INPUT:
105 case CS35L56_SWIRE_DP3_CH4_INPUT:
106 case CS35L56_IRQ1_CFG:
107 case CS35L56_IRQ1_STATUS:
108 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
109 case CS35L56_IRQ1_EINT_18:
110 case CS35L56_IRQ1_EINT_20:
111 case CS35L56_IRQ1_MASK_1:
112 case CS35L56_IRQ1_MASK_2:
113 case CS35L56_IRQ1_MASK_4:
114 case CS35L56_IRQ1_MASK_8:
115 case CS35L56_IRQ1_MASK_18:
116 case CS35L56_IRQ1_MASK_20:
117 case CS35L56_DSP_VIRTUAL1_MBOX_1:
118 case CS35L56_DSP_VIRTUAL1_MBOX_2:
119 case CS35L56_DSP_VIRTUAL1_MBOX_3:
120 case CS35L56_DSP_VIRTUAL1_MBOX_4:
121 case CS35L56_DSP_VIRTUAL1_MBOX_5:
122 case CS35L56_DSP_VIRTUAL1_MBOX_6:
123 case CS35L56_DSP_VIRTUAL1_MBOX_7:
124 case CS35L56_DSP_VIRTUAL1_MBOX_8:
125 case CS35L56_DSP_RESTRICT_STS1:
126 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
127 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
128 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
129 case CS35L56_DSP1_SCRATCH1:
130 case CS35L56_DSP1_SCRATCH2:
131 case CS35L56_DSP1_SCRATCH3:
132 case CS35L56_DSP1_SCRATCH4:
133 return true;
134 default:
135 return cs35l56_is_dsp_memory(reg);
136 }
137 }
138
cs35l56_precious_reg(struct device * dev,unsigned int reg)139 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
140 {
141 switch (reg) {
142 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
143 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
144 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
145 return true;
146 default:
147 return false;
148 }
149 }
150
cs35l56_volatile_reg(struct device * dev,unsigned int reg)151 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
152 {
153 switch (reg) {
154 case CS35L56_DEVID:
155 case CS35L56_REVID:
156 case CS35L56_RELID:
157 case CS35L56_OTPID:
158 case CS35L56_SFT_RESET:
159 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
160 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
161 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
162 case CS35L56_REFCLK_INPUT: /* owned by firmware */
163 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
164 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
165 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
166 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
167 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
168 case CS35L56_IRQ1_STATUS:
169 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
170 case CS35L56_IRQ1_EINT_18:
171 case CS35L56_IRQ1_EINT_20:
172 case CS35L56_DSP_VIRTUAL1_MBOX_1:
173 case CS35L56_DSP_VIRTUAL1_MBOX_2:
174 case CS35L56_DSP_VIRTUAL1_MBOX_3:
175 case CS35L56_DSP_VIRTUAL1_MBOX_4:
176 case CS35L56_DSP_VIRTUAL1_MBOX_5:
177 case CS35L56_DSP_VIRTUAL1_MBOX_6:
178 case CS35L56_DSP_VIRTUAL1_MBOX_7:
179 case CS35L56_DSP_VIRTUAL1_MBOX_8:
180 case CS35L56_DSP_RESTRICT_STS1:
181 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
182 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
183 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
184 case CS35L56_DSP1_SCRATCH1:
185 case CS35L56_DSP1_SCRATCH2:
186 case CS35L56_DSP1_SCRATCH3:
187 case CS35L56_DSP1_SCRATCH4:
188 return true;
189 case CS35L56_MAIN_RENDER_USER_MUTE:
190 case CS35L56_MAIN_RENDER_USER_VOLUME:
191 case CS35L56_MAIN_POSTURE_NUMBER:
192 return false;
193 default:
194 return cs35l56_is_dsp_memory(reg);
195 }
196 }
197
198 /*
199 * The firmware boot sequence can overwrite the ASP1 config registers so that
200 * they don't match regmap's view of their values. Rewrite the values from the
201 * regmap cache into the hardware registers.
202 */
cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base * cs35l56_base)203 int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base)
204 {
205 struct reg_sequence asp1_regs[] = {
206 { .reg = CS35L56_ASP1_ENABLES1 },
207 { .reg = CS35L56_ASP1_CONTROL1 },
208 { .reg = CS35L56_ASP1_CONTROL2 },
209 { .reg = CS35L56_ASP1_CONTROL3 },
210 { .reg = CS35L56_ASP1_FRAME_CONTROL1 },
211 { .reg = CS35L56_ASP1_FRAME_CONTROL5 },
212 { .reg = CS35L56_ASP1_DATA_CONTROL1 },
213 { .reg = CS35L56_ASP1_DATA_CONTROL5 },
214 };
215 int i, ret;
216
217 /* Read values from regmap cache into a write sequence */
218 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) {
219 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def);
220 if (ret)
221 goto err;
222 }
223
224 /* Write the values cache-bypassed so that they will be written to silicon */
225 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs,
226 ARRAY_SIZE(asp1_regs));
227 if (ret)
228 goto err;
229
230 return 0;
231
232 err:
233 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret);
234
235 return ret;
236 }
237 EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED);
238
cs35l56_mbox_send(struct cs35l56_base * cs35l56_base,unsigned int command)239 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
240 {
241 unsigned int val;
242 int ret;
243
244 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
245 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
246 val, (val == 0),
247 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
248 if (ret) {
249 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
250 return ret;
251 }
252
253 return 0;
254 }
255 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
256
cs35l56_firmware_shutdown(struct cs35l56_base * cs35l56_base)257 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
258 {
259 int ret;
260 unsigned int reg;
261 unsigned int val;
262
263 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
264 if (ret)
265 return ret;
266
267 if (cs35l56_base->rev < CS35L56_REVID_B0)
268 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
269 else
270 reg = CS35L56_DSP1_PM_CUR_STATE;
271
272 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,
273 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
274 CS35L56_HALO_STATE_POLL_US,
275 CS35L56_HALO_STATE_TIMEOUT_US);
276 if (ret < 0)
277 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
278 val, ret);
279 return ret;
280 }
281 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
282
cs35l56_wait_for_firmware_boot(struct cs35l56_base * cs35l56_base)283 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
284 {
285 unsigned int reg;
286 unsigned int val;
287 int read_ret, poll_ret;
288
289 if (cs35l56_base->rev < CS35L56_REVID_B0)
290 reg = CS35L56_DSP1_HALO_STATE_A1;
291 else
292 reg = CS35L56_DSP1_HALO_STATE;
293
294 /*
295 * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
296 * I2C until it has booted which would terminate the poll
297 */
298 poll_ret = read_poll_timeout(regmap_read, read_ret,
299 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
300 CS35L56_HALO_STATE_POLL_US,
301 CS35L56_HALO_STATE_TIMEOUT_US,
302 false,
303 cs35l56_base->regmap, reg, &val);
304
305 if (poll_ret) {
306 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
307 read_ret, val);
308 return -EIO;
309 }
310
311 return 0;
312 }
313 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
314
cs35l56_wait_control_port_ready(void)315 void cs35l56_wait_control_port_ready(void)
316 {
317 /* Wait for control port to be ready (datasheet tIRS). */
318 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
319 }
320 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
321
cs35l56_wait_min_reset_pulse(void)322 void cs35l56_wait_min_reset_pulse(void)
323 {
324 /* Satisfy minimum reset pulse width spec */
325 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
326 }
327 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
328
329 static const struct reg_sequence cs35l56_system_reset_seq[] = {
330 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
331 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
332 };
333
cs35l56_system_reset(struct cs35l56_base * cs35l56_base,bool is_soundwire)334 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
335 {
336 /*
337 * Must enter cache-only first so there can't be any more register
338 * accesses other than the controlled system reset sequence below.
339 */
340 regcache_cache_only(cs35l56_base->regmap, true);
341 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
342 cs35l56_system_reset_seq,
343 ARRAY_SIZE(cs35l56_system_reset_seq));
344
345 /* On SoundWire the registers won't be accessible until it re-enumerates. */
346 if (is_soundwire)
347 return;
348
349 cs35l56_wait_control_port_ready();
350 regcache_cache_only(cs35l56_base->regmap, false);
351 }
352 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
353
cs35l56_irq_request(struct cs35l56_base * cs35l56_base,int irq)354 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
355 {
356 int ret;
357
358 if (irq < 1)
359 return 0;
360
361 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
362 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
363 "cs35l56", cs35l56_base);
364 if (!ret)
365 cs35l56_base->irq = irq;
366 else
367 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
368
369 return ret;
370 }
371 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
372
cs35l56_irq(int irq,void * data)373 irqreturn_t cs35l56_irq(int irq, void *data)
374 {
375 struct cs35l56_base *cs35l56_base = data;
376 unsigned int status1 = 0, status8 = 0, status20 = 0;
377 unsigned int mask1, mask8, mask20;
378 unsigned int val;
379 int rv;
380
381 irqreturn_t ret = IRQ_NONE;
382
383 if (!cs35l56_base->init_done)
384 return IRQ_NONE;
385
386 mutex_lock(&cs35l56_base->irq_lock);
387
388 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
389 if (rv < 0) {
390 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
391 goto err_unlock;
392 }
393
394 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
395 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
396 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
397 goto err;
398 }
399
400 /* Ack interrupts */
401 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
402 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
403 status1 &= ~mask1;
404 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
405
406 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
407 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
408 status8 &= ~mask8;
409 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
410
411 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
412 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
413 status20 &= ~mask20;
414 /* We don't want EINT20 but they default to unmasked: force mask */
415 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
416
417 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
418
419 /* Check to see if unmasked bits are active */
420 if (!status1 && !status8 && !status20)
421 goto err;
422
423 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
424 dev_crit(cs35l56_base->dev, "Amp short error\n");
425
426 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
427 dev_crit(cs35l56_base->dev, "Overtemp error\n");
428
429 ret = IRQ_HANDLED;
430
431 err:
432 pm_runtime_put(cs35l56_base->dev);
433 err_unlock:
434 mutex_unlock(&cs35l56_base->irq_lock);
435
436 return ret;
437 }
438 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
439
cs35l56_is_fw_reload_needed(struct cs35l56_base * cs35l56_base)440 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
441 {
442 unsigned int val;
443 int ret;
444
445 /* Nothing to re-patch if we haven't done any patching yet. */
446 if (!cs35l56_base->fw_patched)
447 return false;
448
449 /*
450 * If we have control of RESET we will have asserted it so the firmware
451 * will need re-patching.
452 */
453 if (cs35l56_base->reset_gpio)
454 return true;
455
456 /*
457 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
458 * can't be used here to test for memory retention.
459 * Assume that tuning must be re-loaded.
460 */
461 if (cs35l56_base->secured)
462 return true;
463
464 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
465 if (ret) {
466 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
467 return ret;
468 }
469
470 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
471 if (ret)
472 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
473 else
474 ret = !!(val & CS35L56_FIRMWARE_MISSING);
475
476 pm_runtime_put_autosuspend(cs35l56_base->dev);
477
478 return ret;
479 }
480 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
481
482 static const struct reg_sequence cs35l56_hibernate_seq[] = {
483 /* This must be the last register access */
484 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
485 };
486
487 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
488 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
489 };
490
cs35l56_runtime_suspend_common(struct cs35l56_base * cs35l56_base)491 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
492 {
493 unsigned int val;
494 int ret;
495
496 if (!cs35l56_base->init_done)
497 return 0;
498
499 /* Firmware must have entered a power-save state */
500 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
501 CS35L56_TRANSDUCER_ACTUAL_PS,
502 val, (val >= CS35L56_PS3),
503 CS35L56_PS3_POLL_US,
504 CS35L56_PS3_TIMEOUT_US);
505 if (ret)
506 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
507
508 /* Clear BOOT_DONE so it can be used to detect a reboot */
509 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
510
511 if (!cs35l56_base->can_hibernate) {
512 regcache_cache_only(cs35l56_base->regmap, true);
513 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
514
515 return 0;
516 }
517
518 /*
519 * Enable auto-hibernate. If it is woken by some other wake source
520 * it will automatically return to hibernate.
521 */
522 cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE);
523
524 /*
525 * Must enter cache-only first so there can't be any more register
526 * accesses other than the controlled hibernate sequence below.
527 */
528 regcache_cache_only(cs35l56_base->regmap, true);
529
530 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
531 cs35l56_hibernate_seq,
532 ARRAY_SIZE(cs35l56_hibernate_seq));
533
534 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
535
536 return 0;
537 }
538 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
539
cs35l56_runtime_resume_common(struct cs35l56_base * cs35l56_base,bool is_soundwire)540 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
541 {
542 unsigned int val;
543 int ret;
544
545 if (!cs35l56_base->init_done)
546 return 0;
547
548 if (!cs35l56_base->can_hibernate)
549 goto out_sync;
550
551 if (!is_soundwire) {
552 /*
553 * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C.
554 * Must be done before releasing cache-only.
555 */
556 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
557 cs35l56_hibernate_wake_seq,
558 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
559
560 cs35l56_wait_control_port_ready();
561 }
562
563 out_sync:
564 regcache_cache_only(cs35l56_base->regmap, false);
565
566 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
567 if (ret) {
568 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
569 goto err;
570 }
571
572 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
573 if (ret)
574 goto err;
575
576 /* BOOT_DONE will be 1 if the amp reset */
577 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
578 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
579 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
580 regcache_mark_dirty(cs35l56_base->regmap);
581 }
582
583 regcache_sync(cs35l56_base->regmap);
584
585 dev_dbg(cs35l56_base->dev, "Resumed");
586
587 return 0;
588
589 err:
590 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
591 CS35L56_MBOX_CMD_HIBERNATE_NOW);
592
593 regcache_cache_only(cs35l56_base->regmap, true);
594
595 return ret;
596 }
597 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
598
599 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
600 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
601 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
602 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
603 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
604 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
605 };
606
cs35l56_init_cs_dsp(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)607 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
608 {
609 cs_dsp->num = 1;
610 cs_dsp->type = WMFW_HALO;
611 cs_dsp->rev = 0;
612 cs_dsp->dev = cs35l56_base->dev;
613 cs_dsp->regmap = cs35l56_base->regmap;
614 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
615 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
616 cs_dsp->mem = cs35l56_dsp1_regions;
617 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
618 cs_dsp->no_core_startstop = true;
619 }
620 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
621
cs35l56_hw_init(struct cs35l56_base * cs35l56_base)622 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
623 {
624 int ret;
625 unsigned int devid, revid, otpid, secured;
626
627 /*
628 * If the system is not using a reset_gpio then issue a
629 * dummy read to force a wakeup.
630 */
631 if (!cs35l56_base->reset_gpio)
632 regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);
633
634 cs35l56_wait_control_port_ready();
635
636 /*
637 * The HALO_STATE register is in different locations on Ax and B0
638 * devices so the REVID needs to be determined before waiting for the
639 * firmware to boot.
640 */
641 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid);
642 if (ret < 0) {
643 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
644 return ret;
645 }
646 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
647
648 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
649 if (ret)
650 return ret;
651
652 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid);
653 if (ret < 0) {
654 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
655 return ret;
656 }
657 devid &= CS35L56_DEVID_MASK;
658
659 switch (devid) {
660 case 0x35A56:
661 break;
662 default:
663 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
664 return ret;
665 }
666
667 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
668 if (ret) {
669 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
670 return ret;
671 }
672
673 /* When any bus is restricted treat the device as secured */
674 if (secured & CS35L56_RESTRICTED_MASK)
675 cs35l56_base->secured = true;
676
677 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
678 if (ret < 0) {
679 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
680 return ret;
681 }
682
683 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
684 cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid);
685
686 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
687 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
688 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
689 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
690 0);
691 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
692 CS35L56_TEMP_ERR_EINT1_MASK,
693 0);
694
695 return 0;
696 }
697 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
698
cs35l56_get_speaker_id(struct cs35l56_base * cs35l56_base)699 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
700 {
701 struct gpio_descs *descs;
702 int speaker_id;
703 int i, ret;
704
705 /* Read the speaker type qualifier from the motherboard GPIOs */
706 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
707 if (!descs) {
708 return -ENOENT;
709 } else if (IS_ERR(descs)) {
710 ret = PTR_ERR(descs);
711 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
712 }
713
714 speaker_id = 0;
715 for (i = 0; i < descs->ndescs; i++) {
716 ret = gpiod_get_value_cansleep(descs->desc[i]);
717 if (ret < 0) {
718 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
719 goto err;
720 }
721
722 speaker_id |= (ret << i);
723 }
724
725 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
726 ret = speaker_id;
727 err:
728 gpiod_put_array(descs);
729
730 return ret;
731 }
732 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED);
733
734 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
735 [0x0C] = 128000,
736 [0x0F] = 256000,
737 [0x11] = 384000,
738 [0x12] = 512000,
739 [0x15] = 768000,
740 [0x17] = 1024000,
741 [0x1A] = 1500000,
742 [0x1B] = 1536000,
743 [0x1C] = 2000000,
744 [0x1D] = 2048000,
745 [0x1E] = 2400000,
746 [0x20] = 3000000,
747 [0x21] = 3072000,
748 [0x23] = 4000000,
749 [0x24] = 4096000,
750 [0x25] = 4800000,
751 [0x27] = 6000000,
752 [0x28] = 6144000,
753 [0x29] = 6250000,
754 [0x2A] = 6400000,
755 [0x2E] = 8000000,
756 [0x2F] = 8192000,
757 [0x30] = 9600000,
758 [0x32] = 12000000,
759 [0x33] = 12288000,
760 [0x37] = 13500000,
761 [0x38] = 19200000,
762 [0x39] = 22579200,
763 [0x3B] = 24576000,
764 };
765
cs35l56_get_bclk_freq_id(unsigned int freq)766 int cs35l56_get_bclk_freq_id(unsigned int freq)
767 {
768 int i;
769
770 if (freq == 0)
771 return -EINVAL;
772
773 /* The BCLK frequency must be a valid PLL REFCLK */
774 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
775 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
776 return i;
777 }
778
779 return -EINVAL;
780 }
781 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
782
783 static const char * const cs35l56_supplies[/* auto-sized */] = {
784 "VDD_P",
785 "VDD_IO",
786 "VDD_A",
787 };
788
cs35l56_fill_supply_names(struct regulator_bulk_data * data)789 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
790 {
791 int i;
792
793 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
794 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
795 data[i].supply = cs35l56_supplies[i];
796 }
797 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
798
799 const char * const cs35l56_tx_input_texts[] = {
800 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
801 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
802 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
803 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
804 };
805 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
806
807 const unsigned int cs35l56_tx_input_values[] = {
808 CS35L56_INPUT_SRC_NONE,
809 CS35L56_INPUT_SRC_ASP1RX1,
810 CS35L56_INPUT_SRC_ASP1RX2,
811 CS35L56_INPUT_SRC_VMON,
812 CS35L56_INPUT_SRC_IMON,
813 CS35L56_INPUT_SRC_ERR_VOL,
814 CS35L56_INPUT_SRC_CLASSH,
815 CS35L56_INPUT_SRC_VDDBMON,
816 CS35L56_INPUT_SRC_VBSTMON,
817 CS35L56_INPUT_SRC_DSP1TX1,
818 CS35L56_INPUT_SRC_DSP1TX2,
819 CS35L56_INPUT_SRC_DSP1TX3,
820 CS35L56_INPUT_SRC_DSP1TX4,
821 CS35L56_INPUT_SRC_DSP1TX5,
822 CS35L56_INPUT_SRC_DSP1TX6,
823 CS35L56_INPUT_SRC_DSP1TX7,
824 CS35L56_INPUT_SRC_DSP1TX8,
825 CS35L56_INPUT_SRC_TEMPMON,
826 CS35L56_INPUT_SRC_INTERPOLATOR,
827 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
828 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
829 };
830 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
831
832 struct regmap_config cs35l56_regmap_i2c = {
833 .reg_bits = 32,
834 .val_bits = 32,
835 .reg_stride = 4,
836 .reg_format_endian = REGMAP_ENDIAN_BIG,
837 .val_format_endian = REGMAP_ENDIAN_BIG,
838 .max_register = CS35L56_DSP1_PMEM_5114,
839 .reg_defaults = cs35l56_reg_defaults,
840 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
841 .volatile_reg = cs35l56_volatile_reg,
842 .readable_reg = cs35l56_readable_reg,
843 .precious_reg = cs35l56_precious_reg,
844 .cache_type = REGCACHE_MAPLE,
845 };
846 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
847
848 struct regmap_config cs35l56_regmap_spi = {
849 .reg_bits = 32,
850 .val_bits = 32,
851 .pad_bits = 16,
852 .reg_stride = 4,
853 .reg_format_endian = REGMAP_ENDIAN_BIG,
854 .val_format_endian = REGMAP_ENDIAN_BIG,
855 .max_register = CS35L56_DSP1_PMEM_5114,
856 .reg_defaults = cs35l56_reg_defaults,
857 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
858 .volatile_reg = cs35l56_volatile_reg,
859 .readable_reg = cs35l56_readable_reg,
860 .precious_reg = cs35l56_precious_reg,
861 .cache_type = REGCACHE_MAPLE,
862 };
863 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
864
865 struct regmap_config cs35l56_regmap_sdw = {
866 .reg_bits = 32,
867 .val_bits = 32,
868 .reg_stride = 4,
869 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
870 .val_format_endian = REGMAP_ENDIAN_BIG,
871 .max_register = CS35L56_DSP1_PMEM_5114,
872 .reg_defaults = cs35l56_reg_defaults,
873 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
874 .volatile_reg = cs35l56_volatile_reg,
875 .readable_reg = cs35l56_readable_reg,
876 .precious_reg = cs35l56_precious_reg,
877 .cache_type = REGCACHE_MAPLE,
878 };
879 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
880
881 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
882 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
883 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
884 MODULE_LICENSE("GPL");
885