1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "accel/tcg/cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/target_page.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 #include "trace.h" 56 57 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 if (is_a64(env)) { 63 env->pc = value; 64 env->thumb = false; 65 } else { 66 env->regs[15] = value & ~1; 67 env->thumb = value & 1; 68 } 69 } 70 71 static vaddr arm_cpu_get_pc(CPUState *cs) 72 { 73 ARMCPU *cpu = ARM_CPU(cs); 74 CPUARMState *env = &cpu->env; 75 76 if (is_a64(env)) { 77 return env->pc; 78 } else { 79 return env->regs[15]; 80 } 81 } 82 83 #ifdef CONFIG_TCG 84 void arm_cpu_synchronize_from_tb(CPUState *cs, 85 const TranslationBlock *tb) 86 { 87 /* The program counter is always up to date with CF_PCREL. */ 88 if (!(tb_cflags(tb) & CF_PCREL)) { 89 CPUARMState *env = cpu_env(cs); 90 /* 91 * It's OK to look at env for the current mode here, because it's 92 * never possible for an AArch64 TB to chain to an AArch32 TB. 93 */ 94 if (is_a64(env)) { 95 env->pc = tb->pc; 96 } else { 97 env->regs[15] = tb->pc; 98 } 99 } 100 } 101 102 void arm_restore_state_to_opc(CPUState *cs, 103 const TranslationBlock *tb, 104 const uint64_t *data) 105 { 106 CPUARMState *env = cpu_env(cs); 107 108 if (is_a64(env)) { 109 if (tb_cflags(tb) & CF_PCREL) { 110 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->pc = data[0]; 113 } 114 env->condexec_bits = 0; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } else { 117 if (tb_cflags(tb) & CF_PCREL) { 118 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 119 } else { 120 env->regs[15] = data[0]; 121 } 122 env->condexec_bits = data[1]; 123 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 124 } 125 } 126 127 int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 128 { 129 return arm_env_mmu_index(cpu_env(cs)); 130 } 131 132 #endif /* CONFIG_TCG */ 133 134 #ifndef CONFIG_USER_ONLY 135 /* 136 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 137 * IRQ without Superpriority. Moreover, if the GIC is configured so that 138 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 139 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 140 * unconditionally. 141 */ 142 static bool arm_cpu_has_work(CPUState *cs) 143 { 144 ARMCPU *cpu = ARM_CPU(cs); 145 146 return (cpu->power_state != PSCI_OFF) 147 && cpu_test_interrupt(cs, 148 CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 149 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 150 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 151 | CPU_INTERRUPT_EXITTB); 152 } 153 #endif /* !CONFIG_USER_ONLY */ 154 155 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 156 void *opaque) 157 { 158 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 159 160 entry->hook = hook; 161 entry->opaque = opaque; 162 163 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 164 } 165 166 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 167 void *opaque) 168 { 169 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 170 171 entry->hook = hook; 172 entry->opaque = opaque; 173 174 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 175 } 176 177 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 178 { 179 /* Reset a single ARMCPRegInfo register */ 180 ARMCPRegInfo *ri = value; 181 ARMCPU *cpu = opaque; 182 183 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 184 return; 185 } 186 187 if (ri->resetfn) { 188 ri->resetfn(&cpu->env, ri); 189 return; 190 } 191 192 /* A zero offset is never possible as it would be regs[0] 193 * so we use it to indicate that reset is being handled elsewhere. 194 * This is basically only used for fields in non-core coprocessors 195 * (like the pxa2xx ones). 196 */ 197 if (ri->fieldoffset) { 198 raw_write(&cpu->env, ri, ri->resetvalue); 199 } 200 } 201 202 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 203 { 204 /* Purely an assertion check: we've already done reset once, 205 * so now check that running the reset for the cpreg doesn't 206 * change its value. This traps bugs where two different cpregs 207 * both try to reset the same state field but to different values. 208 */ 209 ARMCPRegInfo *ri = value; 210 ARMCPU *cpu = opaque; 211 uint64_t oldvalue, newvalue; 212 213 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 214 return; 215 } 216 217 oldvalue = read_raw_cp_reg(&cpu->env, ri); 218 cp_reg_reset(key, value, opaque); 219 newvalue = read_raw_cp_reg(&cpu->env, ri); 220 assert(oldvalue == newvalue); 221 } 222 223 static void arm_cpu_reset_hold(Object *obj, ResetType type) 224 { 225 CPUState *cs = CPU(obj); 226 ARMCPU *cpu = ARM_CPU(cs); 227 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 228 CPUARMState *env = &cpu->env; 229 230 trace_arm_cpu_reset(arm_cpu_mp_affinity(cpu)); 231 232 if (acc->parent_phases.hold) { 233 acc->parent_phases.hold(obj, type); 234 } 235 236 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 237 238 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 239 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 240 241 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 242 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 243 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 244 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 245 246 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 247 248 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 249 /* 64 bit CPUs always start in 64 bit mode */ 250 env->aarch64 = true; 251 #if defined(CONFIG_USER_ONLY) 252 env->pstate = PSTATE_MODE_EL0t; 253 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 254 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 255 /* Enable all PAC keys. */ 256 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 257 SCTLR_EnDA | SCTLR_EnDB); 258 /* Trap on btype=3 for PACIxSP. */ 259 env->cp15.sctlr_el[1] |= SCTLR_BT0; 260 /* Trap on implementation defined registers. */ 261 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 262 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 263 } 264 /* and to the FP/Neon instructions */ 265 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 266 CPACR_EL1, FPEN, 3); 267 /* and to the SVE instructions, with default vector length */ 268 if (cpu_isar_feature(aa64_sve, cpu)) { 269 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 270 CPACR_EL1, ZEN, 3); 271 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 272 } 273 /* and for SME instructions, with default vector length, and TPIDR2 */ 274 if (cpu_isar_feature(aa64_sme, cpu)) { 275 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 276 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 277 CPACR_EL1, SMEN, 3); 278 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 279 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 280 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 281 SMCR, FA64, 1); 282 } 283 } 284 /* 285 * Enable 48-bit address space (TODO: take reserved_va into account). 286 * Enable TBI0 but not TBI1. 287 * Note that this must match useronly_clean_ptr. 288 */ 289 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 290 291 /* Enable MTE */ 292 if (cpu_isar_feature(aa64_mte, cpu)) { 293 /* Enable tag access, but leave TCF0 as No Effect (0). */ 294 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 295 /* 296 * Exclude all tags, so that tag 0 is always used. 297 * This corresponds to Linux current->thread.gcr_incl = 0. 298 * 299 * Set RRND, so that helper_irg() will generate a seed later. 300 * Here in cpu_reset(), the crypto subsystem has not yet been 301 * initialized. 302 */ 303 env->cp15.gcr_el1 = 0x1ffff; 304 } 305 /* 306 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 307 * This is not yet exposed from the Linux kernel in any way. 308 */ 309 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 310 /* Disable access to Debug Communication Channel (DCC). */ 311 env->cp15.mdscr_el1 |= 1 << 12; 312 /* Enable FEAT_MOPS */ 313 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 314 /* For Linux, GCSPR_EL0 is always readable. */ 315 if (cpu_isar_feature(aa64_gcs, cpu)) { 316 env->cp15.gcscr_el[0] = GCSCRE0_NTR; 317 } 318 #else 319 /* Reset into the highest available EL */ 320 if (arm_feature(env, ARM_FEATURE_EL3)) { 321 env->pstate = PSTATE_MODE_EL3h; 322 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 323 env->pstate = PSTATE_MODE_EL2h; 324 } else { 325 env->pstate = PSTATE_MODE_EL1h; 326 } 327 328 /* Sample rvbar at reset. */ 329 env->cp15.rvbar = cpu->rvbar_prop; 330 env->pc = env->cp15.rvbar; 331 #endif 332 } else { 333 #if defined(CONFIG_USER_ONLY) 334 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 335 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 336 CPACR, CP10, 3); 337 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 338 CPACR, CP11, 3); 339 #endif 340 if (arm_feature(env, ARM_FEATURE_V8)) { 341 env->cp15.rvbar = cpu->rvbar_prop; 342 env->regs[15] = cpu->rvbar_prop; 343 } 344 } 345 346 #if defined(CONFIG_USER_ONLY) 347 env->uncached_cpsr = ARM_CPU_MODE_USR; 348 /* For user mode we must enable access to coprocessors */ 349 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 350 #else 351 352 /* 353 * If the highest available EL is EL2, AArch32 will start in Hyp 354 * mode; otherwise it starts in SVC. Note that if we start in 355 * AArch64 then these values in the uncached_cpsr will be ignored. 356 */ 357 if (arm_feature(env, ARM_FEATURE_EL2) && 358 !arm_feature(env, ARM_FEATURE_EL3)) { 359 env->uncached_cpsr = ARM_CPU_MODE_HYP; 360 } else { 361 env->uncached_cpsr = ARM_CPU_MODE_SVC; 362 } 363 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 364 365 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 366 * executing as AArch32 then check if highvecs are enabled and 367 * adjust the PC accordingly. 368 */ 369 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 370 env->regs[15] = 0xFFFF0000; 371 } 372 373 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 374 #endif 375 376 if (arm_feature(env, ARM_FEATURE_M)) { 377 #ifndef CONFIG_USER_ONLY 378 uint32_t initial_msp; /* Loaded from 0x0 */ 379 uint32_t initial_pc; /* Loaded from 0x4 */ 380 uint8_t *rom; 381 uint32_t vecbase; 382 #endif 383 384 if (cpu_isar_feature(aa32_lob, cpu)) { 385 /* 386 * LTPSIZE is constant 4 if MVE not implemented, and resets 387 * to an UNKNOWN value if MVE is implemented. We choose to 388 * always reset to 4. 389 */ 390 env->v7m.ltpsize = 4; 391 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 392 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 393 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 394 } 395 396 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 397 env->v7m.secure = true; 398 } else { 399 /* This bit resets to 0 if security is supported, but 1 if 400 * it is not. The bit is not present in v7M, but we set it 401 * here so we can avoid having to make checks on it conditional 402 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 403 */ 404 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 405 /* 406 * Set NSACR to indicate "NS access permitted to everything"; 407 * this avoids having to have all the tests of it being 408 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 409 * v8.1M the guest-visible value of NSACR in a CPU without the 410 * Security Extension is 0xcff. 411 */ 412 env->v7m.nsacr = 0xcff; 413 } 414 415 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 416 * that it resets to 1, so QEMU always does that rather than making 417 * it dependent on CPU model. In v8M it is RES1. 418 */ 419 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 420 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 421 if (arm_feature(env, ARM_FEATURE_V8)) { 422 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 423 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 424 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 425 } 426 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 427 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 428 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 429 } 430 431 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 432 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 433 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 434 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 435 } 436 437 #ifndef CONFIG_USER_ONLY 438 /* Unlike A/R profile, M profile defines the reset LR value */ 439 env->regs[14] = 0xffffffff; 440 441 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 442 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 443 444 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 445 vecbase = env->v7m.vecbase[env->v7m.secure]; 446 rom = rom_ptr_for_as(cs->as, vecbase, 8); 447 if (rom) { 448 /* Address zero is covered by ROM which hasn't yet been 449 * copied into physical memory. 450 */ 451 initial_msp = ldl_p(rom); 452 initial_pc = ldl_p(rom + 4); 453 } else { 454 /* Address zero not covered by a ROM blob, or the ROM blob 455 * is in non-modifiable memory and this is a second reset after 456 * it got copied into memory. In the latter case, rom_ptr 457 * will return a NULL pointer and we should use ldl_phys instead. 458 */ 459 initial_msp = ldl_phys(cs->as, vecbase); 460 initial_pc = ldl_phys(cs->as, vecbase + 4); 461 } 462 463 qemu_log_mask(CPU_LOG_INT, 464 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 465 initial_msp, initial_pc); 466 467 env->regs[13] = initial_msp & 0xFFFFFFFC; 468 env->regs[15] = initial_pc & ~1; 469 env->thumb = initial_pc & 1; 470 #else 471 /* 472 * For user mode we run non-secure and with access to the FPU. 473 * The FPU context is active (ie does not need further setup) 474 * and is owned by non-secure. 475 */ 476 env->v7m.secure = false; 477 env->v7m.nsacr = 0xcff; 478 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 479 env->v7m.fpccr[M_REG_S] &= 480 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 481 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 482 #endif 483 } 484 485 /* M profile requires that reset clears the exclusive monitor; 486 * A profile does not, but clearing it makes more sense than having it 487 * set with an exclusive access on address zero. 488 */ 489 arm_clear_exclusive(env); 490 491 if (arm_feature(env, ARM_FEATURE_PMSA)) { 492 if (cpu->pmsav7_dregion > 0) { 493 if (arm_feature(env, ARM_FEATURE_V8)) { 494 memset(env->pmsav8.rbar[M_REG_NS], 0, 495 sizeof(*env->pmsav8.rbar[M_REG_NS]) 496 * cpu->pmsav7_dregion); 497 memset(env->pmsav8.rlar[M_REG_NS], 0, 498 sizeof(*env->pmsav8.rlar[M_REG_NS]) 499 * cpu->pmsav7_dregion); 500 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 501 memset(env->pmsav8.rbar[M_REG_S], 0, 502 sizeof(*env->pmsav8.rbar[M_REG_S]) 503 * cpu->pmsav7_dregion); 504 memset(env->pmsav8.rlar[M_REG_S], 0, 505 sizeof(*env->pmsav8.rlar[M_REG_S]) 506 * cpu->pmsav7_dregion); 507 } 508 } else if (arm_feature(env, ARM_FEATURE_V7)) { 509 memset(env->pmsav7.drbar, 0, 510 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 511 memset(env->pmsav7.drsr, 0, 512 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 513 memset(env->pmsav7.dracr, 0, 514 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 515 } 516 } 517 518 if (cpu->pmsav8r_hdregion > 0) { 519 memset(env->pmsav8.hprbar, 0, 520 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 521 memset(env->pmsav8.hprlar, 0, 522 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 523 } 524 525 env->pmsav7.rnr[M_REG_NS] = 0; 526 env->pmsav7.rnr[M_REG_S] = 0; 527 env->pmsav8.mair0[M_REG_NS] = 0; 528 env->pmsav8.mair0[M_REG_S] = 0; 529 env->pmsav8.mair1[M_REG_NS] = 0; 530 env->pmsav8.mair1[M_REG_S] = 0; 531 } 532 533 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 534 if (cpu->sau_sregion > 0) { 535 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 536 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 537 } 538 env->sau.rnr = 0; 539 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 540 * the Cortex-M33 does. 541 */ 542 env->sau.ctrl = 0; 543 } 544 545 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 546 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 547 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 548 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 549 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA]); 550 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA_F16]); 551 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 552 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 553 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); 554 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 555 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 559 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 560 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 561 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 562 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 563 564 #ifndef CONFIG_USER_ONLY 565 if (kvm_enabled()) { 566 kvm_arm_reset_vcpu(cpu); 567 } 568 #endif 569 570 if (tcg_enabled()) { 571 hw_breakpoint_update_all(cpu); 572 hw_watchpoint_update_all(cpu); 573 574 arm_rebuild_hflags(env); 575 } 576 } 577 578 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 579 { 580 ARMCPU *cpu = ARM_CPU(cpustate); 581 CPUARMState *env = &cpu->env; 582 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 583 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 584 585 trace_arm_emulate_firmware_reset(arm_cpu_mp_affinity(cpu), target_el); 586 587 /* 588 * Check we have the EL we're aiming for. If that is the 589 * highest implemented EL, then cpu_reset has already done 590 * all the work. 591 */ 592 switch (target_el) { 593 case 3: 594 assert(have_el3); 595 return; 596 case 2: 597 assert(have_el2); 598 if (!have_el3) { 599 return; 600 } 601 break; 602 case 1: 603 if (!have_el3 && !have_el2) { 604 return; 605 } 606 break; 607 default: 608 g_assert_not_reached(); 609 } 610 611 if (have_el3) { 612 /* 613 * Set the EL3 state so code can run at EL2. This should match 614 * the requirements set by Linux in its booting spec. 615 */ 616 if (env->aarch64) { 617 env->cp15.scr_el3 |= SCR_RW; 618 if (cpu_isar_feature(aa64_pauth, cpu)) { 619 env->cp15.scr_el3 |= SCR_API | SCR_APK; 620 } 621 if (cpu_isar_feature(aa64_mte, cpu)) { 622 env->cp15.scr_el3 |= SCR_ATA; 623 } 624 if (cpu_isar_feature(aa64_sve, cpu)) { 625 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 626 env->vfp.zcr_el[3] = 0xf; 627 } 628 if (cpu_isar_feature(aa64_sme, cpu)) { 629 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 630 env->cp15.scr_el3 |= SCR_ENTP2; 631 env->vfp.smcr_el[3] = 0xf; 632 if (cpu_isar_feature(aa64_sme2, cpu)) { 633 env->vfp.smcr_el[3] |= R_SMCR_EZT0_MASK; 634 } 635 } 636 if (cpu_isar_feature(aa64_hcx, cpu)) { 637 env->cp15.scr_el3 |= SCR_HXEN; 638 } 639 if (cpu_isar_feature(aa64_fgt, cpu)) { 640 env->cp15.scr_el3 |= SCR_FGTEN; 641 } 642 if (cpu_isar_feature(aa64_gcs, cpu)) { 643 env->cp15.scr_el3 |= SCR_GCSEN; 644 } 645 if (cpu_isar_feature(aa64_tcr2, cpu)) { 646 env->cp15.scr_el3 |= SCR_TCR2EN; 647 } 648 if (cpu_isar_feature(aa64_sctlr2, cpu)) { 649 env->cp15.scr_el3 |= SCR_SCTLR2EN; 650 } 651 if (cpu_isar_feature(aa64_s1pie, cpu) || 652 cpu_isar_feature(aa64_s2pie, cpu)) { 653 env->cp15.scr_el3 |= SCR_PIEN; 654 } 655 if (cpu_isar_feature(aa64_aie, cpu)) { 656 env->cp15.scr_el3 |= SCR_AIEN; 657 } 658 if (cpu_isar_feature(aa64_mec, cpu)) { 659 env->cp15.scr_el3 |= SCR_MECEN; 660 } 661 } 662 663 if (target_el == 2) { 664 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 665 env->cp15.scr_el3 |= SCR_HCE; 666 } 667 668 /* Put CPU into non-secure state */ 669 env->cp15.scr_el3 |= SCR_NS; 670 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 671 env->cp15.nsacr |= 3 << 10; 672 } 673 674 if (have_el2 && target_el < 2) { 675 /* Set EL2 state so code can run at EL1. */ 676 if (env->aarch64) { 677 env->cp15.hcr_el2 |= HCR_RW; 678 } 679 } 680 681 /* Set the CPU to the desired state */ 682 if (env->aarch64) { 683 env->pstate = aarch64_pstate_mode(target_el, true); 684 } else { 685 static const uint32_t mode_for_el[] = { 686 0, 687 ARM_CPU_MODE_SVC, 688 ARM_CPU_MODE_HYP, 689 ARM_CPU_MODE_SVC, 690 }; 691 692 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 693 } 694 } 695 696 697 #ifndef CONFIG_USER_ONLY 698 static void arm_cpu_set_irq(void *opaque, int irq, int level) 699 { 700 ARMCPU *cpu = opaque; 701 CPUARMState *env = &cpu->env; 702 CPUState *cs = CPU(cpu); 703 static const int mask[] = { 704 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 705 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 706 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 707 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 708 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 709 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 710 }; 711 712 if (!arm_feature(env, ARM_FEATURE_EL2) && 713 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 714 /* 715 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 716 * have EL2 support we don't care. (Unless the guest is doing something 717 * silly this will only be calls saying "level is still 0".) 718 */ 719 return; 720 } 721 722 if (level) { 723 env->irq_line_state |= mask[irq]; 724 } else { 725 env->irq_line_state &= ~mask[irq]; 726 } 727 728 switch (irq) { 729 case ARM_CPU_VIRQ: 730 arm_cpu_update_virq(cpu); 731 break; 732 case ARM_CPU_VFIQ: 733 arm_cpu_update_vfiq(cpu); 734 break; 735 case ARM_CPU_VINMI: 736 arm_cpu_update_vinmi(cpu); 737 break; 738 case ARM_CPU_IRQ: 739 case ARM_CPU_FIQ: 740 case ARM_CPU_NMI: 741 if (level) { 742 cpu_interrupt(cs, mask[irq]); 743 } else { 744 cpu_reset_interrupt(cs, mask[irq]); 745 } 746 break; 747 default: 748 g_assert_not_reached(); 749 } 750 } 751 752 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 753 { 754 ARMCPU *cpu = ARM_CPU(cs); 755 CPUARMState *env = &cpu->env; 756 757 cpu_synchronize_state(cs); 758 return arm_cpu_data_is_big_endian(env); 759 } 760 761 #ifdef CONFIG_TCG 762 bool arm_cpu_exec_halt(CPUState *cs) 763 { 764 bool leave_halt = cpu_has_work(cs); 765 766 if (leave_halt) { 767 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 768 ARMCPU *cpu = ARM_CPU(cs); 769 if (cpu->wfxt_timer) { 770 timer_del(cpu->wfxt_timer); 771 } 772 } 773 return leave_halt; 774 } 775 #endif 776 777 static void arm_wfxt_timer_cb(void *opaque) 778 { 779 ARMCPU *cpu = opaque; 780 CPUState *cs = CPU(cpu); 781 782 /* 783 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 784 * to return true (so we will come out of halt even with no other 785 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 786 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 787 */ 788 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 789 } 790 #endif 791 792 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 793 { 794 ARMCPU *ac = ARM_CPU(cpu); 795 CPUARMState *env = &ac->env; 796 bool sctlr_b = arm_sctlr_b(env); 797 798 if (is_a64(env)) { 799 info->cap_arch = CS_ARCH_ARM64; 800 info->cap_insn_unit = 4; 801 info->cap_insn_split = 4; 802 } else { 803 int cap_mode; 804 if (env->thumb) { 805 info->cap_insn_unit = 2; 806 info->cap_insn_split = 4; 807 cap_mode = CS_MODE_THUMB; 808 } else { 809 info->cap_insn_unit = 4; 810 info->cap_insn_split = 4; 811 cap_mode = CS_MODE_ARM; 812 } 813 if (arm_feature(env, ARM_FEATURE_V8)) { 814 cap_mode |= CS_MODE_V8; 815 } 816 if (arm_feature(env, ARM_FEATURE_M)) { 817 cap_mode |= CS_MODE_MCLASS; 818 } 819 info->cap_arch = CS_ARCH_ARM; 820 info->cap_mode = cap_mode; 821 } 822 823 info->endian = BFD_ENDIAN_LITTLE; 824 if (bswap_code(sctlr_b)) { 825 info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 826 } 827 info->flags &= ~INSN_ARM_BE32; 828 #ifndef CONFIG_USER_ONLY 829 if (sctlr_b) { 830 info->flags |= INSN_ARM_BE32; 831 } 832 #endif 833 } 834 835 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 836 { 837 ARMCPU *cpu = ARM_CPU(cs); 838 CPUARMState *env = &cpu->env; 839 uint64_t psr = pstate_read(env); 840 int i, j; 841 int el = arm_current_el(env); 842 uint64_t hcr = arm_hcr_el2_eff(env); 843 const char *ns_status; 844 bool sve; 845 846 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 847 for (i = 0; i < 32; i++) { 848 if (i == 31) { 849 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 850 } else { 851 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 852 (i + 2) % 3 ? " " : "\n"); 853 } 854 } 855 856 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 857 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 858 } else { 859 ns_status = ""; 860 } 861 qemu_fprintf(f, "PSTATE=%016" PRIx64 " %c%c%c%c %sEL%d%c", 862 psr, 863 psr & PSTATE_N ? 'N' : '-', 864 psr & PSTATE_Z ? 'Z' : '-', 865 psr & PSTATE_C ? 'C' : '-', 866 psr & PSTATE_V ? 'V' : '-', 867 ns_status, 868 el, 869 psr & PSTATE_SP ? 'h' : 't'); 870 871 if (cpu_isar_feature(aa64_sme, cpu)) { 872 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 873 env->svcr, 874 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 875 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 876 } 877 if (cpu_isar_feature(aa64_bti, cpu)) { 878 qemu_fprintf(f, " BTYPE=%d", (int)(psr & PSTATE_BTYPE) >> 10); 879 } 880 qemu_fprintf(f, "%s%s%s", 881 (hcr & HCR_NV) ? " NV" : "", 882 (hcr & HCR_NV1) ? " NV1" : "", 883 (hcr & HCR_NV2) ? " NV2" : ""); 884 if (!(flags & CPU_DUMP_FPU)) { 885 qemu_fprintf(f, "\n"); 886 return; 887 } 888 if (fp_exception_el(env, el) != 0) { 889 qemu_fprintf(f, " FPU disabled\n"); 890 return; 891 } 892 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 893 vfp_get_fpcr(env), vfp_get_fpsr(env)); 894 895 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 896 sve = sme_exception_el(env, el) == 0; 897 } else if (cpu_isar_feature(aa64_sve, cpu)) { 898 sve = sve_exception_el(env, el) == 0; 899 } else { 900 sve = false; 901 } 902 903 if (sve) { 904 int zcr_len = sve_vqm1_for_el(env, el); 905 906 for (i = 0; i <= FFR_PRED_NUM; i++) { 907 bool eol; 908 if (i == FFR_PRED_NUM) { 909 qemu_fprintf(f, "FFR="); 910 /* It's last, so end the line. */ 911 eol = true; 912 } else { 913 qemu_fprintf(f, "P%02d=", i); 914 switch (zcr_len) { 915 case 0: 916 eol = i % 8 == 7; 917 break; 918 case 1: 919 eol = i % 6 == 5; 920 break; 921 case 2: 922 case 3: 923 eol = i % 3 == 2; 924 break; 925 default: 926 /* More than one quadword per predicate. */ 927 eol = true; 928 break; 929 } 930 } 931 for (j = zcr_len / 4; j >= 0; j--) { 932 int digits; 933 if (j * 4 + 4 <= zcr_len + 1) { 934 digits = 16; 935 } else { 936 digits = (zcr_len % 4 + 1) * 4; 937 } 938 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 939 env->vfp.pregs[i].p[j], 940 j ? ":" : eol ? "\n" : " "); 941 } 942 } 943 944 if (zcr_len == 0) { 945 /* 946 * With vl=16, there are only 37 columns per register, 947 * so output two registers per line. 948 */ 949 for (i = 0; i < 32; i++) { 950 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 951 i, env->vfp.zregs[i].d[1], 952 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 953 } 954 } else { 955 for (i = 0; i < 32; i++) { 956 qemu_fprintf(f, "Z%02d=", i); 957 for (j = zcr_len; j >= 0; j--) { 958 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 959 env->vfp.zregs[i].d[j * 2 + 1], 960 env->vfp.zregs[i].d[j * 2 + 0], 961 j ? ":" : "\n"); 962 } 963 } 964 } 965 } else { 966 for (i = 0; i < 32; i++) { 967 uint64_t *q = aa64_vfp_qreg(env, i); 968 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 969 i, q[1], q[0], (i & 1 ? "\n" : " ")); 970 } 971 } 972 973 if (cpu_isar_feature(aa64_sme, cpu) && 974 FIELD_EX64(env->svcr, SVCR, ZA) && 975 sme_exception_el(env, el) == 0) { 976 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 977 int svl = (zcr_len + 1) * 16; 978 int svl_lg10 = svl < 100 ? 2 : 3; 979 980 for (i = 0; i < svl; i++) { 981 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 982 for (j = zcr_len; j >= 0; --j) { 983 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 984 env->za_state.za[i].d[2 * j + 1], 985 env->za_state.za[i].d[2 * j], 986 j ? ':' : '\n'); 987 } 988 } 989 } 990 } 991 992 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 993 { 994 ARMCPU *cpu = ARM_CPU(cs); 995 CPUARMState *env = &cpu->env; 996 int i; 997 998 if (is_a64(env)) { 999 aarch64_cpu_dump_state(cs, f, flags); 1000 return; 1001 } 1002 1003 for (i = 0; i < 16; i++) { 1004 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1005 if ((i % 4) == 3) { 1006 qemu_fprintf(f, "\n"); 1007 } else { 1008 qemu_fprintf(f, " "); 1009 } 1010 } 1011 1012 if (arm_feature(env, ARM_FEATURE_M)) { 1013 uint32_t xpsr = xpsr_read(env); 1014 const char *mode; 1015 const char *ns_status = ""; 1016 1017 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1018 ns_status = env->v7m.secure ? "S " : "NS "; 1019 } 1020 1021 if (xpsr & XPSR_EXCP) { 1022 mode = "handler"; 1023 } else { 1024 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1025 mode = "unpriv-thread"; 1026 } else { 1027 mode = "priv-thread"; 1028 } 1029 } 1030 1031 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1032 xpsr, 1033 xpsr & XPSR_N ? 'N' : '-', 1034 xpsr & XPSR_Z ? 'Z' : '-', 1035 xpsr & XPSR_C ? 'C' : '-', 1036 xpsr & XPSR_V ? 'V' : '-', 1037 xpsr & XPSR_T ? 'T' : 'A', 1038 ns_status, 1039 mode); 1040 } else { 1041 uint32_t psr = cpsr_read(env); 1042 const char *ns_status = ""; 1043 1044 if (arm_feature(env, ARM_FEATURE_EL3) && 1045 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1046 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1047 } 1048 1049 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1050 psr, 1051 psr & CPSR_N ? 'N' : '-', 1052 psr & CPSR_Z ? 'Z' : '-', 1053 psr & CPSR_C ? 'C' : '-', 1054 psr & CPSR_V ? 'V' : '-', 1055 psr & CPSR_T ? 'T' : 'A', 1056 ns_status, 1057 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1058 } 1059 1060 if (flags & CPU_DUMP_FPU) { 1061 int numvfpregs = 0; 1062 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1063 numvfpregs = 32; 1064 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1065 numvfpregs = 16; 1066 } 1067 for (i = 0; i < numvfpregs; i++) { 1068 uint64_t v = *aa32_vfp_dreg(env, i); 1069 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1070 i * 2, (uint32_t)v, 1071 i * 2 + 1, (uint32_t)(v >> 32), 1072 i, v); 1073 } 1074 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1075 if (cpu_isar_feature(aa32_mve, cpu)) { 1076 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1077 } 1078 } 1079 } 1080 1081 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1082 { 1083 uint32_t Aff1 = idx / clustersz; 1084 uint32_t Aff0 = idx % clustersz; 1085 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1086 } 1087 1088 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1089 { 1090 return cpu->mp_affinity; 1091 } 1092 1093 static void arm_cpu_initfn(Object *obj) 1094 { 1095 ARMCPU *cpu = ARM_CPU(obj); 1096 1097 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1098 NULL, g_free); 1099 1100 QLIST_INIT(&cpu->pre_el_change_hooks); 1101 QLIST_INIT(&cpu->el_change_hooks); 1102 1103 #ifdef CONFIG_USER_ONLY 1104 # ifdef TARGET_AARCH64 1105 /* 1106 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1107 * These values were chosen to fit within the default signal frame. 1108 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1109 * and our corresponding cpu property. 1110 */ 1111 cpu->sve_default_vq = 4; 1112 cpu->sme_default_vq = 2; 1113 # endif 1114 #else 1115 /* Our inbound IRQ and FIQ lines */ 1116 if (kvm_enabled()) { 1117 /* 1118 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1119 * them to maintain the same interface as non-KVM CPUs. 1120 */ 1121 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1122 } else { 1123 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1124 } 1125 1126 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1127 ARRAY_SIZE(cpu->gt_timer_outputs)); 1128 1129 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1130 "gicv3-maintenance-interrupt", 1); 1131 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1132 "pmu-interrupt", 1); 1133 #endif 1134 1135 /* DTB consumers generally don't in fact care what the 'compatible' 1136 * string is, so always provide some string and trust that a hypothetical 1137 * picky DTB consumer will also provide a helpful error message. 1138 */ 1139 cpu->dtb_compatible = "qemu,unknown"; 1140 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1141 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1142 1143 if (tcg_enabled() || hvf_enabled()) { 1144 /* TCG and HVF implement PSCI 1.1 */ 1145 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1146 } 1147 } 1148 1149 /* 1150 * 0 means "unset, use the default value". That default might vary depending 1151 * on the CPU type, and is set in the realize fn. 1152 */ 1153 #ifndef CONFIG_USER_ONLY 1154 static const Property arm_cpu_gt_cntfrq_property = 1155 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1156 1157 static const Property arm_cpu_reset_cbar_property = 1158 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1159 1160 static const Property arm_cpu_reset_hivecs_property = 1161 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1162 1163 static const Property arm_cpu_has_el2_property = 1164 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1165 1166 static const Property arm_cpu_has_el3_property = 1167 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1168 #endif 1169 1170 static const Property arm_cpu_cfgend_property = 1171 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1172 1173 static const Property arm_cpu_has_vfp_property = 1174 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1175 1176 static const Property arm_cpu_has_vfp_d32_property = 1177 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1178 1179 static const Property arm_cpu_has_neon_property = 1180 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1181 1182 static const Property arm_cpu_has_dsp_property = 1183 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1184 1185 #ifndef CONFIG_USER_ONLY 1186 static const Property arm_cpu_has_mpu_property = 1187 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1188 1189 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1190 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1191 * the right value for that particular CPU type, and we don't want 1192 * to override that with an incorrect constant value. 1193 */ 1194 static const Property arm_cpu_pmsav7_dregion_property = 1195 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1196 pmsav7_dregion, 1197 qdev_prop_uint32, uint32_t); 1198 #endif 1199 1200 static bool arm_get_pmu(Object *obj, Error **errp) 1201 { 1202 ARMCPU *cpu = ARM_CPU(obj); 1203 1204 return cpu->has_pmu; 1205 } 1206 1207 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1208 { 1209 ARMCPU *cpu = ARM_CPU(obj); 1210 1211 if (value) { 1212 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1213 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1214 return; 1215 } 1216 set_feature(&cpu->env, ARM_FEATURE_PMU); 1217 } else { 1218 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1219 } 1220 cpu->has_pmu = value; 1221 } 1222 1223 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1224 { 1225 ARMCPU *cpu = ARM_CPU(obj); 1226 1227 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1228 } 1229 1230 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1231 { 1232 ARMCPU *cpu = ARM_CPU(obj); 1233 1234 /* 1235 * At this time, this property is only allowed if KVM is enabled. This 1236 * restriction allows us to avoid fixing up functionality that assumes a 1237 * uniform execution state like do_interrupt. 1238 */ 1239 if (value == false) { 1240 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1241 error_setg(errp, "'aarch64' feature cannot be disabled " 1242 "unless KVM is enabled and 32-bit EL1 " 1243 "is supported"); 1244 return; 1245 } 1246 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1247 } else { 1248 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1249 } 1250 } 1251 1252 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1253 { 1254 /* 1255 * The exact approach to calculating guest ticks is: 1256 * 1257 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1258 * NANOSECONDS_PER_SECOND); 1259 * 1260 * We don't do that. Rather we intentionally use integer division 1261 * truncation below and in the caller for the conversion of host monotonic 1262 * time to guest ticks to provide the exact inverse for the semantics of 1263 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1264 * it loses precision when representing frequencies where 1265 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1266 * provide an exact inverse leads to scheduling timers with negative 1267 * periods, which in turn leads to sticky behaviour in the guest. 1268 * 1269 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1270 * cannot become zero. 1271 */ 1272 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1273 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1274 } 1275 1276 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1277 { 1278 CPUARMState *env = &cpu->env; 1279 bool no_aa32 = false; 1280 1281 /* 1282 * Some features automatically imply others: set the feature 1283 * bits explicitly for these cases. 1284 */ 1285 1286 if (arm_feature(env, ARM_FEATURE_M)) { 1287 set_feature(env, ARM_FEATURE_PMSA); 1288 } 1289 1290 if (arm_feature(env, ARM_FEATURE_V8)) { 1291 if (arm_feature(env, ARM_FEATURE_M)) { 1292 set_feature(env, ARM_FEATURE_V7); 1293 } else { 1294 set_feature(env, ARM_FEATURE_V7VE); 1295 } 1296 } 1297 1298 /* 1299 * There exist AArch64 cpus without AArch32 support. When KVM 1300 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1301 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1302 * As a general principle, we also do not make ID register 1303 * consistency checks anywhere unless using TCG, because only 1304 * for TCG would a consistency-check failure be a QEMU bug. 1305 */ 1306 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1307 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1308 } 1309 1310 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1311 /* 1312 * v7 Virtualization Extensions. In real hardware this implies 1313 * EL2 and also the presence of the Security Extensions. 1314 * For QEMU, for backwards-compatibility we implement some 1315 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1316 * include the various other features that V7VE implies. 1317 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1318 * Security Extensions is ARM_FEATURE_EL3. 1319 */ 1320 assert(!tcg_enabled() || no_aa32 || 1321 cpu_isar_feature(aa32_arm_div, cpu)); 1322 set_feature(env, ARM_FEATURE_LPAE); 1323 set_feature(env, ARM_FEATURE_V7); 1324 } 1325 if (arm_feature(env, ARM_FEATURE_V7)) { 1326 set_feature(env, ARM_FEATURE_VAPA); 1327 set_feature(env, ARM_FEATURE_THUMB2); 1328 set_feature(env, ARM_FEATURE_MPIDR); 1329 if (!arm_feature(env, ARM_FEATURE_M)) { 1330 set_feature(env, ARM_FEATURE_V6K); 1331 } else { 1332 set_feature(env, ARM_FEATURE_V6); 1333 } 1334 1335 /* 1336 * Always define VBAR for V7 CPUs even if it doesn't exist in 1337 * non-EL3 configs. This is needed by some legacy boards. 1338 */ 1339 set_feature(env, ARM_FEATURE_VBAR); 1340 } 1341 if (arm_feature(env, ARM_FEATURE_V6K)) { 1342 set_feature(env, ARM_FEATURE_V6); 1343 set_feature(env, ARM_FEATURE_MVFR); 1344 } 1345 if (arm_feature(env, ARM_FEATURE_V6)) { 1346 set_feature(env, ARM_FEATURE_V5); 1347 if (!arm_feature(env, ARM_FEATURE_M)) { 1348 assert(!tcg_enabled() || no_aa32 || 1349 cpu_isar_feature(aa32_jazelle, cpu)); 1350 set_feature(env, ARM_FEATURE_AUXCR); 1351 } 1352 } 1353 if (arm_feature(env, ARM_FEATURE_V5)) { 1354 set_feature(env, ARM_FEATURE_V4T); 1355 } 1356 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1357 set_feature(env, ARM_FEATURE_V7MP); 1358 } 1359 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1360 set_feature(env, ARM_FEATURE_CBAR); 1361 } 1362 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1363 !arm_feature(env, ARM_FEATURE_M)) { 1364 set_feature(env, ARM_FEATURE_THUMB_DSP); 1365 } 1366 } 1367 1368 static void arm_cpu_post_init(Object *obj) 1369 { 1370 ARMCPU *cpu = ARM_CPU(obj); 1371 1372 /* 1373 * Some features imply others. Figure this out now, because we 1374 * are going to look at the feature bits in deciding which 1375 * properties to add. 1376 */ 1377 arm_cpu_propagate_feature_implications(cpu); 1378 1379 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1380 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 1381 aarch64_cpu_set_aarch64); 1382 object_property_set_description(obj, "aarch64", 1383 "Set on/off to enable/disable aarch64 " 1384 "execution state "); 1385 } 1386 #ifndef CONFIG_USER_ONLY 1387 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1388 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1389 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1390 } 1391 1392 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1393 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1394 } 1395 1396 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1397 object_property_add_uint64_ptr(obj, "rvbar", 1398 &cpu->rvbar_prop, 1399 OBJ_PROP_FLAG_READWRITE); 1400 } 1401 1402 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1403 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1404 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1405 */ 1406 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1407 1408 object_property_add_link(obj, "secure-memory", 1409 TYPE_MEMORY_REGION, 1410 (Object **)&cpu->secure_memory, 1411 qdev_prop_allow_set_link_before_realize, 1412 OBJ_PROP_LINK_STRONG); 1413 } 1414 1415 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1416 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1417 } 1418 #endif 1419 1420 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1421 cpu->has_pmu = true; 1422 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1423 } 1424 1425 /* 1426 * Allow user to turn off VFP and Neon support, but only for TCG -- 1427 * KVM does not currently allow us to lie to the guest about its 1428 * ID/feature registers, so the guest always sees what the host has. 1429 */ 1430 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1431 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1432 cpu->has_vfp = true; 1433 cpu->has_vfp_d32 = true; 1434 if (tcg_enabled() || qtest_enabled()) { 1435 qdev_property_add_static(DEVICE(obj), 1436 &arm_cpu_has_vfp_property); 1437 } 1438 } 1439 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1440 cpu->has_vfp = true; 1441 if (tcg_enabled() || qtest_enabled()) { 1442 qdev_property_add_static(DEVICE(obj), 1443 &arm_cpu_has_vfp_property); 1444 } 1445 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1446 cpu->has_vfp_d32 = true; 1447 /* 1448 * The permitted values of the SIMDReg bits [3:0] on 1449 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1450 * make sure that has_vfp_d32 can not be set to false. 1451 */ 1452 if ((tcg_enabled() || qtest_enabled()) 1453 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1454 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1455 qdev_property_add_static(DEVICE(obj), 1456 &arm_cpu_has_vfp_d32_property); 1457 } 1458 } 1459 } 1460 1461 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1462 cpu->has_neon = true; 1463 if (!kvm_enabled()) { 1464 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1465 } 1466 } 1467 1468 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1469 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1470 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1471 } 1472 1473 #ifndef CONFIG_USER_ONLY 1474 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1475 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1476 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1477 qdev_property_add_static(DEVICE(obj), 1478 &arm_cpu_pmsav7_dregion_property); 1479 } 1480 } 1481 1482 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1483 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1484 qdev_prop_allow_set_link_before_realize, 1485 OBJ_PROP_LINK_STRONG); 1486 /* 1487 * M profile: initial value of the Secure VTOR. We can't just use 1488 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1489 * the property to be set after realize. 1490 */ 1491 object_property_add_uint32_ptr(obj, "init-svtor", 1492 &cpu->init_svtor, 1493 OBJ_PROP_FLAG_READWRITE); 1494 } 1495 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1496 /* 1497 * Initial value of the NS VTOR (for cores without the Security 1498 * extension, this is the only VTOR) 1499 */ 1500 object_property_add_uint32_ptr(obj, "init-nsvtor", 1501 &cpu->init_nsvtor, 1502 OBJ_PROP_FLAG_READWRITE); 1503 } 1504 1505 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1506 object_property_add_uint32_ptr(obj, "psci-conduit", 1507 &cpu->psci_conduit, 1508 OBJ_PROP_FLAG_READWRITE); 1509 1510 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1511 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1512 } 1513 1514 if (kvm_enabled()) { 1515 kvm_arm_add_vcpu_properties(cpu); 1516 } 1517 1518 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1519 cpu_isar_feature(aa64_mte, cpu)) { 1520 object_property_add_link(obj, "tag-memory", 1521 TYPE_MEMORY_REGION, 1522 (Object **)&cpu->tag_memory, 1523 qdev_prop_allow_set_link_before_realize, 1524 OBJ_PROP_LINK_STRONG); 1525 1526 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1527 object_property_add_link(obj, "secure-tag-memory", 1528 TYPE_MEMORY_REGION, 1529 (Object **)&cpu->secure_tag_memory, 1530 qdev_prop_allow_set_link_before_realize, 1531 OBJ_PROP_LINK_STRONG); 1532 } 1533 } 1534 #endif 1535 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1536 } 1537 1538 static void arm_cpu_finalizefn(Object *obj) 1539 { 1540 ARMCPU *cpu = ARM_CPU(obj); 1541 ARMELChangeHook *hook, *next; 1542 1543 g_hash_table_destroy(cpu->cp_regs); 1544 1545 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1546 QLIST_REMOVE(hook, node); 1547 g_free(hook); 1548 } 1549 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1550 QLIST_REMOVE(hook, node); 1551 g_free(hook); 1552 } 1553 #ifndef CONFIG_USER_ONLY 1554 if (cpu->pmu_timer) { 1555 timer_free(cpu->pmu_timer); 1556 } 1557 if (cpu->wfxt_timer) { 1558 timer_free(cpu->wfxt_timer); 1559 } 1560 #endif 1561 } 1562 1563 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1564 { 1565 Error *local_err = NULL; 1566 1567 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1568 arm_cpu_sve_finalize(cpu, &local_err); 1569 if (local_err != NULL) { 1570 error_propagate(errp, local_err); 1571 return; 1572 } 1573 1574 /* 1575 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1576 * FEAT_SME_FA64 is present). However our implementation currently 1577 * assumes it, so if the user asked for sve=off then turn off SME also. 1578 * (KVM doesn't currently support SME at all.) 1579 */ 1580 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1581 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1582 } 1583 1584 arm_cpu_sme_finalize(cpu, &local_err); 1585 if (local_err != NULL) { 1586 error_propagate(errp, local_err); 1587 return; 1588 } 1589 1590 arm_cpu_pauth_finalize(cpu, &local_err); 1591 if (local_err != NULL) { 1592 error_propagate(errp, local_err); 1593 return; 1594 } 1595 1596 arm_cpu_lpa2_finalize(cpu, &local_err); 1597 if (local_err != NULL) { 1598 error_propagate(errp, local_err); 1599 return; 1600 } 1601 } 1602 1603 if (kvm_enabled()) { 1604 kvm_arm_steal_time_finalize(cpu, &local_err); 1605 if (local_err != NULL) { 1606 error_propagate(errp, local_err); 1607 return; 1608 } 1609 } 1610 } 1611 1612 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1613 { 1614 CPUState *cs = CPU(dev); 1615 ARMCPU *cpu = ARM_CPU(dev); 1616 ARMISARegisters *isar = &cpu->isar; 1617 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1618 CPUARMState *env = &cpu->env; 1619 Error *local_err = NULL; 1620 1621 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1622 /* Use pc-relative instructions in system-mode */ 1623 tcg_cflags_set(cs, CF_PCREL); 1624 #endif 1625 1626 /* If we needed to query the host kernel for the CPU features 1627 * then it's possible that might have failed in the initfn, but 1628 * this is the first point where we can report it. 1629 */ 1630 if (cpu->host_cpu_probe_failed) { 1631 if (!kvm_enabled() && !hvf_enabled()) { 1632 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1633 } else { 1634 error_setg(errp, "Failed to retrieve host CPU features"); 1635 } 1636 return; 1637 } 1638 1639 if (!cpu->gt_cntfrq_hz) { 1640 /* 1641 * 0 means "the board didn't set a value, use the default". (We also 1642 * get here for the CONFIG_USER_ONLY case.) 1643 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 1644 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 1645 * which gives a 16ns tick period. 1646 * 1647 * We will use the back-compat value: 1648 * - for QEMU CPU types added before we standardized on 1GHz 1649 * - for versioned machine types with a version of 9.0 or earlier 1650 */ 1651 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 1652 cpu->backcompat_cntfrq) { 1653 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 1654 } else { 1655 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 1656 } 1657 } 1658 1659 #ifndef CONFIG_USER_ONLY 1660 /* The NVIC and M-profile CPU are two halves of a single piece of 1661 * hardware; trying to use one without the other is a command line 1662 * error and will result in segfaults if not caught here. 1663 */ 1664 if (arm_feature(env, ARM_FEATURE_M)) { 1665 if (!env->nvic) { 1666 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1667 return; 1668 } 1669 } else { 1670 if (env->nvic) { 1671 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1672 return; 1673 } 1674 } 1675 1676 if (!tcg_enabled() && !qtest_enabled()) { 1677 /* 1678 * We assume that no accelerator except TCG (and the "not really an 1679 * accelerator" qtest) can handle these features, because Arm hardware 1680 * virtualization can't virtualize them. 1681 * 1682 * Catch all the cases which might cause us to create more than one 1683 * address space for the CPU (otherwise we will assert() later in 1684 * cpu_address_space_init()). 1685 */ 1686 if (arm_feature(env, ARM_FEATURE_M)) { 1687 error_setg(errp, 1688 "Cannot enable %s when using an M-profile guest CPU", 1689 current_accel_name()); 1690 return; 1691 } 1692 if (cpu->has_el3) { 1693 error_setg(errp, 1694 "Cannot enable %s when guest CPU has EL3 enabled", 1695 current_accel_name()); 1696 return; 1697 } 1698 if (cpu->tag_memory) { 1699 error_setg(errp, 1700 "Cannot enable %s when guest CPUs has MTE enabled", 1701 current_accel_name()); 1702 return; 1703 } 1704 } 1705 1706 { 1707 uint64_t scale = gt_cntfrq_period_ns(cpu); 1708 1709 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1710 arm_gt_ptimer_cb, cpu); 1711 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1712 arm_gt_vtimer_cb, cpu); 1713 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1714 arm_gt_htimer_cb, cpu); 1715 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1716 arm_gt_stimer_cb, cpu); 1717 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1718 arm_gt_hvtimer_cb, cpu); 1719 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1720 arm_gt_sel2timer_cb, cpu); 1721 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1722 arm_gt_sel2vtimer_cb, cpu); 1723 } 1724 #endif 1725 1726 cpu_exec_realizefn(cs, &local_err); 1727 if (local_err != NULL) { 1728 error_propagate(errp, local_err); 1729 return; 1730 } 1731 1732 arm_cpu_finalize_features(cpu, &local_err); 1733 if (local_err != NULL) { 1734 error_propagate(errp, local_err); 1735 return; 1736 } 1737 1738 #ifdef CONFIG_USER_ONLY 1739 /* 1740 * User mode relies on IC IVAU instructions to catch modification of 1741 * dual-mapped code. 1742 * 1743 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 1744 * IC IVAU even if the emulated processor does not normally require it. 1745 */ 1746 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 1747 #endif 1748 1749 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1750 cpu->has_vfp != cpu->has_neon) { 1751 /* 1752 * This is an architectural requirement for AArch64; AArch32 is 1753 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1754 */ 1755 error_setg(errp, 1756 "AArch64 CPUs must have both VFP and Neon or neither"); 1757 return; 1758 } 1759 1760 if (cpu->has_vfp_d32 != cpu->has_neon) { 1761 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 1762 return; 1763 } 1764 1765 if (!cpu->has_vfp_d32) { 1766 uint32_t u; 1767 1768 u = cpu->isar.mvfr0; 1769 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 1770 cpu->isar.mvfr0 = u; 1771 } 1772 1773 if (!cpu->has_vfp) { 1774 uint32_t u; 1775 1776 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); 1777 1778 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); 1779 1780 u = GET_IDREG(isar, ID_ISAR6); 1781 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1782 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1783 SET_IDREG(isar, ID_ISAR6, u); 1784 1785 u = cpu->isar.mvfr0; 1786 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1787 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1788 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1789 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1790 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1791 if (!arm_feature(env, ARM_FEATURE_M)) { 1792 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1793 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1794 } 1795 cpu->isar.mvfr0 = u; 1796 1797 u = cpu->isar.mvfr1; 1798 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1799 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1800 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1801 if (arm_feature(env, ARM_FEATURE_M)) { 1802 u = FIELD_DP32(u, MVFR1, FP16, 0); 1803 } 1804 cpu->isar.mvfr1 = u; 1805 1806 u = cpu->isar.mvfr2; 1807 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1808 cpu->isar.mvfr2 = u; 1809 } 1810 1811 if (!cpu->has_neon) { 1812 uint64_t t; 1813 uint32_t u; 1814 1815 unset_feature(env, ARM_FEATURE_NEON); 1816 1817 t = GET_IDREG(isar, ID_AA64ISAR0); 1818 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1819 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1820 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1821 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1822 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1823 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1824 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1825 SET_IDREG(isar, ID_AA64ISAR0, t); 1826 1827 t = GET_IDREG(isar, ID_AA64ISAR1); 1828 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1829 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1830 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1831 SET_IDREG(isar, ID_AA64ISAR1, t); 1832 1833 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); 1834 1835 u = GET_IDREG(isar, ID_ISAR5); 1836 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1837 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1838 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1839 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1840 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1841 SET_IDREG(isar, ID_ISAR5, u); 1842 1843 u = GET_IDREG(isar, ID_ISAR6); 1844 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1845 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1846 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1847 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1848 SET_IDREG(isar, ID_ISAR6, u); 1849 1850 if (!arm_feature(env, ARM_FEATURE_M)) { 1851 u = cpu->isar.mvfr1; 1852 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1853 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1854 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1855 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1856 cpu->isar.mvfr1 = u; 1857 1858 u = cpu->isar.mvfr2; 1859 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1860 cpu->isar.mvfr2 = u; 1861 } 1862 } 1863 1864 if (!cpu->has_neon && !cpu->has_vfp) { 1865 uint32_t u; 1866 1867 FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); 1868 1869 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0); 1870 1871 u = cpu->isar.mvfr0; 1872 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1873 cpu->isar.mvfr0 = u; 1874 1875 /* Despite the name, this field covers both VFP and Neon */ 1876 u = cpu->isar.mvfr1; 1877 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1878 cpu->isar.mvfr1 = u; 1879 } 1880 1881 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1882 uint32_t u; 1883 1884 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1885 1886 FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); 1887 1888 u = GET_IDREG(isar, ID_ISAR2); 1889 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1890 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1891 SET_IDREG(isar, ID_ISAR2, u); 1892 1893 u = GET_IDREG(isar, ID_ISAR3); 1894 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1895 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1896 SET_IDREG(isar, ID_ISAR3, u); 1897 } 1898 1899 1900 #ifndef CONFIG_USER_ONLY 1901 { 1902 int pagebits; 1903 if (arm_feature(env, ARM_FEATURE_V7) && 1904 !arm_feature(env, ARM_FEATURE_M) && 1905 !arm_feature(env, ARM_FEATURE_PMSA)) { 1906 /* 1907 * v7VMSA drops support for the old ARMv5 tiny pages, 1908 * so we can use 4K pages. 1909 */ 1910 pagebits = 12; 1911 } else { 1912 /* 1913 * For CPUs which might have tiny 1K pages, or which have an 1914 * MPU and might have small region sizes, stick with 1K pages. 1915 */ 1916 pagebits = 10; 1917 } 1918 if (!set_preferred_target_page_bits(pagebits)) { 1919 /* 1920 * This can only ever happen for hotplugging a CPU, or if 1921 * the board code incorrectly creates a CPU which it has 1922 * promised via minimum_page_size that it will not. 1923 */ 1924 error_setg(errp, "This CPU requires a smaller page size " 1925 "than the system is using"); 1926 return; 1927 } 1928 } 1929 #endif 1930 1931 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1932 * We don't support setting cluster ID ([16..23]) (known as Aff2 1933 * in later ARM ARM versions), or any of the higher affinity level fields, 1934 * so these bits always RAZ. 1935 */ 1936 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1937 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 1938 ARM_DEFAULT_CPUS_PER_CLUSTER); 1939 } 1940 1941 if (cpu->reset_hivecs) { 1942 cpu->reset_sctlr |= (1 << 13); 1943 } 1944 1945 if (cpu->cfgend) { 1946 if (arm_feature(env, ARM_FEATURE_V7)) { 1947 cpu->reset_sctlr |= SCTLR_EE; 1948 } else { 1949 cpu->reset_sctlr |= SCTLR_B; 1950 } 1951 } 1952 1953 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1954 /* If the has_el3 CPU property is disabled then we need to disable the 1955 * feature. 1956 */ 1957 unset_feature(env, ARM_FEATURE_EL3); 1958 1959 /* 1960 * Disable the security extension feature bits in the processor 1961 * feature registers as well. 1962 */ 1963 FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); 1964 FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0); 1965 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); 1966 1967 /* Disable the realm management extension, which requires EL3. */ 1968 FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0); 1969 } 1970 1971 if (!cpu->has_el2) { 1972 unset_feature(env, ARM_FEATURE_EL2); 1973 } 1974 1975 if (!cpu->has_pmu) { 1976 unset_feature(env, ARM_FEATURE_PMU); 1977 } 1978 if (arm_feature(env, ARM_FEATURE_PMU)) { 1979 pmu_init(cpu); 1980 1981 if (!kvm_enabled()) { 1982 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1983 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1984 } 1985 1986 #ifndef CONFIG_USER_ONLY 1987 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1988 cpu); 1989 #endif 1990 } else { 1991 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); 1992 FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0); 1993 cpu->pmceid0 = 0; 1994 cpu->pmceid1 = 0; 1995 } 1996 1997 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1998 /* 1999 * Disable the hypervisor feature bits in the processor feature 2000 * registers if we don't have EL2. 2001 */ 2002 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); 2003 FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); 2004 } 2005 2006 if (cpu_isar_feature(aa64_mte, cpu)) { 2007 /* 2008 * The architectural range of GM blocksize is 2-6, however qemu 2009 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2010 */ 2011 if (tcg_enabled()) { 2012 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2013 } 2014 2015 #ifndef CONFIG_USER_ONLY 2016 /* 2017 * If we run with TCG and do not have tag-memory provided by 2018 * the machine, then reduce MTE support to instructions enabled at EL0. 2019 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2020 */ 2021 if (tcg_enabled() && cpu->tag_memory == NULL) { 2022 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); 2023 } 2024 2025 /* 2026 * If MTE is supported by the host, however it should not be 2027 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2028 */ 2029 if (kvm_enabled() && !cpu->kvm_mte) { 2030 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); 2031 } 2032 #endif 2033 } 2034 2035 #ifndef CONFIG_USER_ONLY 2036 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2037 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2038 arm_wfxt_timer_cb, cpu); 2039 } 2040 #endif 2041 2042 if (tcg_enabled()) { 2043 /* 2044 * Don't report some architectural features in the ID registers 2045 * where TCG does not yet implement it (not even a minimal 2046 * stub version). This avoids guests falling over when they 2047 * try to access the non-existent system registers for them. 2048 */ 2049 /* FEAT_SPE (Statistical Profiling Extension) */ 2050 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); 2051 /* FEAT_TRBE (Trace Buffer Extension) */ 2052 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); 2053 /* FEAT_TRF (Self-hosted Trace Extension) */ 2054 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); 2055 FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0); 2056 /* Trace Macrocell system register access */ 2057 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); 2058 FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0); 2059 /* Memory mapped trace */ 2060 FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0); 2061 /* FEAT_AMU (Activity Monitors Extension) */ 2062 FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); 2063 FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); 2064 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2065 FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); 2066 } 2067 2068 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2069 * to false or by setting pmsav7-dregion to 0. 2070 */ 2071 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2072 cpu->has_mpu = false; 2073 cpu->pmsav7_dregion = 0; 2074 cpu->pmsav8r_hdregion = 0; 2075 } 2076 2077 if (arm_feature(env, ARM_FEATURE_PMSA) && 2078 arm_feature(env, ARM_FEATURE_V7)) { 2079 uint32_t nr = cpu->pmsav7_dregion; 2080 2081 if (nr > 0xff) { 2082 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2083 return; 2084 } 2085 2086 if (nr) { 2087 if (arm_feature(env, ARM_FEATURE_V8)) { 2088 /* PMSAv8 */ 2089 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2090 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2091 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2092 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2093 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2094 } 2095 } else { 2096 env->pmsav7.drbar = g_new0(uint32_t, nr); 2097 env->pmsav7.drsr = g_new0(uint32_t, nr); 2098 env->pmsav7.dracr = g_new0(uint32_t, nr); 2099 } 2100 } 2101 2102 if (cpu->pmsav8r_hdregion > 0xff) { 2103 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2104 cpu->pmsav8r_hdregion); 2105 return; 2106 } 2107 2108 if (cpu->pmsav8r_hdregion) { 2109 env->pmsav8.hprbar = g_new0(uint32_t, 2110 cpu->pmsav8r_hdregion); 2111 env->pmsav8.hprlar = g_new0(uint32_t, 2112 cpu->pmsav8r_hdregion); 2113 } 2114 } 2115 2116 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2117 uint32_t nr = cpu->sau_sregion; 2118 2119 if (nr > 0xff) { 2120 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2121 return; 2122 } 2123 2124 if (nr) { 2125 env->sau.rbar = g_new0(uint32_t, nr); 2126 env->sau.rlar = g_new0(uint32_t, nr); 2127 } 2128 } 2129 2130 if (arm_feature(env, ARM_FEATURE_EL3)) { 2131 set_feature(env, ARM_FEATURE_VBAR); 2132 } 2133 2134 #ifndef CONFIG_USER_ONLY 2135 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2136 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2137 } 2138 #endif 2139 2140 register_cp_regs_for_features(cpu); 2141 arm_cpu_register_gdb_regs_for_features(cpu); 2142 arm_cpu_register_gdb_commands(cpu); 2143 2144 arm_init_cpreg_list(cpu); 2145 2146 #ifndef CONFIG_USER_ONLY 2147 MachineState *ms = MACHINE(qdev_get_machine()); 2148 unsigned int smp_cpus = ms->smp.cpus; 2149 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2150 2151 /* 2152 * We must set cs->num_ases to the final value before 2153 * the first call to cpu_address_space_init. 2154 */ 2155 if (cpu->tag_memory != NULL) { 2156 cs->num_ases = 3 + has_secure; 2157 } else { 2158 cs->num_ases = 1 + has_secure; 2159 } 2160 2161 if (has_secure) { 2162 if (!cpu->secure_memory) { 2163 cpu->secure_memory = cs->memory; 2164 } 2165 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2166 cpu->secure_memory); 2167 } 2168 2169 if (cpu->tag_memory != NULL) { 2170 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2171 cpu->tag_memory); 2172 if (has_secure) { 2173 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2174 cpu->secure_tag_memory); 2175 } 2176 } 2177 2178 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2179 2180 /* No core_count specified, default to smp_cpus. */ 2181 if (cpu->core_count == -1) { 2182 cpu->core_count = smp_cpus; 2183 } 2184 #endif 2185 2186 if (tcg_enabled()) { 2187 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2188 2189 /* 2190 * We only support DCZ blocklen that fits on one page. 2191 * 2192 * Architectually this is always true. However TARGET_PAGE_SIZE 2193 * is variable and, for compatibility with -machine virt-2.7, 2194 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2195 * But even then, while the largest architectural DCZ blocklen 2196 * is 2KiB, no cpu actually uses such a large blocklen. 2197 */ 2198 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2199 2200 /* 2201 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2202 * both nibbles of each byte storing tag data may be written at once. 2203 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2204 */ 2205 if (cpu_isar_feature(aa64_mte, cpu)) { 2206 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2207 } 2208 } 2209 2210 qemu_init_vcpu(cs); 2211 cpu_reset(cs); 2212 2213 acc->parent_realize(dev, errp); 2214 } 2215 2216 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2217 { 2218 ObjectClass *oc; 2219 char *typename; 2220 char **cpuname; 2221 const char *cpunamestr; 2222 2223 cpuname = g_strsplit(cpu_model, ",", 1); 2224 cpunamestr = cpuname[0]; 2225 #ifdef CONFIG_USER_ONLY 2226 /* For backwards compatibility usermode emulation allows "-cpu any", 2227 * which has the same semantics as "-cpu max". 2228 */ 2229 if (!strcmp(cpunamestr, "any")) { 2230 cpunamestr = "max"; 2231 } 2232 #endif 2233 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2234 oc = object_class_by_name(typename); 2235 g_strfreev(cpuname); 2236 g_free(typename); 2237 2238 return oc; 2239 } 2240 2241 static const Property arm_cpu_properties[] = { 2242 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2243 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2244 mp_affinity, ARM64_AFFINITY_INVALID), 2245 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2246 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2247 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2248 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2249 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2250 backcompat_pauth_default_use_qarma5, false), 2251 }; 2252 2253 static const gchar *arm_gdb_arch_name(CPUState *cs) 2254 { 2255 ARMCPU *cpu = ARM_CPU(cs); 2256 2257 if (arm_gdbstub_is_aarch64(cpu)) { 2258 return "aarch64"; 2259 } 2260 return "arm"; 2261 } 2262 2263 static const char *arm_gdb_get_core_xml_file(CPUState *cs) 2264 { 2265 ARMCPU *cpu = ARM_CPU(cs); 2266 CPUARMState *env = &cpu->env; 2267 2268 if (arm_gdbstub_is_aarch64(cpu)) { 2269 return "aarch64-core.xml"; 2270 } 2271 if (arm_feature(env, ARM_FEATURE_M)) { 2272 return "arm-m-profile.xml"; 2273 } 2274 return "arm-core.xml"; 2275 } 2276 2277 #ifdef CONFIG_USER_ONLY 2278 /** 2279 * aarch64_untagged_addr: 2280 * 2281 * Remove any address tag from @x. This is explicitly related to the 2282 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 2283 * 2284 * There should be a better place to put this, but we need this in 2285 * include/accel/tcg/cpu-ldst.h, and not some place linux-user specific. 2286 * 2287 * Note that arm-*-user will never set tagged_addr_enable. 2288 */ 2289 static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x) 2290 { 2291 CPUARMState *env = cpu_env(cs); 2292 if (env->tagged_addr_enable) { 2293 /* 2294 * TBI is enabled for userspace but not kernelspace addresses. 2295 * Only clear the tag if bit 55 is clear. 2296 */ 2297 x &= sextract64(x, 0, 56); 2298 } 2299 return x; 2300 } 2301 #else 2302 #include "hw/core/sysemu-cpu-ops.h" 2303 2304 static const struct SysemuCPUOps arm_sysemu_ops = { 2305 .has_work = arm_cpu_has_work, 2306 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2307 .asidx_from_attrs = arm_asidx_from_attrs, 2308 .write_elf32_note = arm_cpu_write_elf32_note, 2309 .write_elf64_note = arm_cpu_write_elf64_note, 2310 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2311 .legacy_vmsd = &vmstate_arm_cpu, 2312 }; 2313 #endif 2314 2315 #ifdef CONFIG_TCG 2316 #ifndef CONFIG_USER_ONLY 2317 static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx, 2318 vaddr result, vaddr base) 2319 { 2320 /* 2321 * The Stage2 and Phys indexes are only used for ptw on arm32, 2322 * and all pte's are aligned, so we never produce a wrap for these. 2323 * Double check that we're not truncating a 40-bit physical address. 2324 */ 2325 assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK)); 2326 2327 if (!is_a64(cpu_env(cs))) { 2328 return (uint32_t)result; 2329 } 2330 2331 /* 2332 * TODO: For FEAT_CPA2, decide how to we want to resolve 2333 * Unpredictable_CPACHECK in AddressIncrement. 2334 */ 2335 return result; 2336 } 2337 #endif /* !CONFIG_USER_ONLY */ 2338 2339 static const TCGCPUOps arm_tcg_ops = { 2340 .mttcg_supported = true, 2341 /* ARM processors have a weak memory model */ 2342 .guest_default_memory_order = 0, 2343 2344 .initialize = arm_translate_init, 2345 .translate_code = arm_translate_code, 2346 .get_tb_cpu_state = arm_get_tb_cpu_state, 2347 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2348 .debug_excp_handler = arm_debug_excp_handler, 2349 .restore_state_to_opc = arm_restore_state_to_opc, 2350 .mmu_index = arm_cpu_mmu_index, 2351 2352 #ifdef CONFIG_USER_ONLY 2353 .record_sigsegv = arm_cpu_record_sigsegv, 2354 .record_sigbus = arm_cpu_record_sigbus, 2355 .untagged_addr = aarch64_untagged_addr, 2356 #else 2357 .tlb_fill_align = arm_cpu_tlb_fill_align, 2358 .pointer_wrap = aprofile_pointer_wrap, 2359 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2360 .cpu_exec_halt = arm_cpu_exec_halt, 2361 .cpu_exec_reset = cpu_reset, 2362 .do_interrupt = arm_cpu_do_interrupt, 2363 .do_transaction_failed = arm_cpu_do_transaction_failed, 2364 .do_unaligned_access = arm_cpu_do_unaligned_access, 2365 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2366 .debug_check_watchpoint = arm_debug_check_watchpoint, 2367 .debug_check_breakpoint = arm_debug_check_breakpoint, 2368 #endif /* !CONFIG_USER_ONLY */ 2369 }; 2370 #endif /* CONFIG_TCG */ 2371 2372 static void arm_cpu_class_init(ObjectClass *oc, const void *data) 2373 { 2374 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2375 CPUClass *cc = CPU_CLASS(acc); 2376 DeviceClass *dc = DEVICE_CLASS(oc); 2377 ResettableClass *rc = RESETTABLE_CLASS(oc); 2378 2379 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2380 &acc->parent_realize); 2381 2382 device_class_set_props(dc, arm_cpu_properties); 2383 2384 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2385 &acc->parent_phases); 2386 2387 cc->class_by_name = arm_cpu_class_by_name; 2388 cc->dump_state = arm_cpu_dump_state; 2389 cc->set_pc = arm_cpu_set_pc; 2390 cc->get_pc = arm_cpu_get_pc; 2391 cc->gdb_read_register = arm_cpu_gdb_read_register; 2392 cc->gdb_write_register = arm_cpu_gdb_write_register; 2393 #ifndef CONFIG_USER_ONLY 2394 cc->sysemu_ops = &arm_sysemu_ops; 2395 #endif 2396 cc->gdb_arch_name = arm_gdb_arch_name; 2397 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; 2398 cc->gdb_stop_before_watchpoint = true; 2399 cc->disas_set_info = arm_disas_set_info; 2400 2401 #ifdef CONFIG_TCG 2402 cc->tcg_ops = &arm_tcg_ops; 2403 #endif /* CONFIG_TCG */ 2404 } 2405 2406 static void arm_cpu_instance_init(Object *obj) 2407 { 2408 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2409 2410 acc->info->initfn(obj); 2411 arm_cpu_post_init(obj); 2412 } 2413 2414 static void cpu_register_class_init(ObjectClass *oc, const void *data) 2415 { 2416 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2417 CPUClass *cc = CPU_CLASS(acc); 2418 2419 acc->info = data; 2420 if (acc->info->deprecation_note) { 2421 cc->deprecation_note = acc->info->deprecation_note; 2422 } 2423 } 2424 2425 void arm_cpu_register(const ARMCPUInfo *info) 2426 { 2427 TypeInfo type_info = { 2428 .parent = TYPE_ARM_CPU, 2429 .instance_init = arm_cpu_instance_init, 2430 .class_init = info->class_init ?: cpu_register_class_init, 2431 .class_data = info, 2432 }; 2433 2434 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2435 type_register_static(&type_info); 2436 g_free((void *)type_info.name); 2437 } 2438 2439 static const TypeInfo arm_cpu_type_info = { 2440 .name = TYPE_ARM_CPU, 2441 .parent = TYPE_CPU, 2442 .instance_size = sizeof(ARMCPU), 2443 .instance_align = __alignof__(ARMCPU), 2444 .instance_init = arm_cpu_initfn, 2445 .instance_finalize = arm_cpu_finalizefn, 2446 .abstract = true, 2447 .class_size = sizeof(ARMCPUClass), 2448 .class_init = arm_cpu_class_init, 2449 }; 2450 2451 static void arm_cpu_register_types(void) 2452 { 2453 type_register_static(&arm_cpu_type_info); 2454 } 2455 2456 type_init(arm_cpu_register_types) 2457