1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
4
5 #include <linux/cpumask.h>
6 #include <linux/static_call.h>
7
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
14 #include <asm/msr.h>
15 #include <asm/hardirq.h>
16 #include <asm/io.h>
17
18 #define ARCH_APICTIMER_STOPS_ON_C3 1
19
20 /*
21 * Debugging macros
22 */
23 #define APIC_QUIET 0
24 #define APIC_VERBOSE 1
25 #define APIC_DEBUG 2
26
27 /* Macros for apic_extnmi which controls external NMI masking */
28 #define APIC_EXTNMI_BSP 0 /* Default */
29 #define APIC_EXTNMI_ALL 1
30 #define APIC_EXTNMI_NONE 2
31
32 /*
33 * Define the default level of output to be very little
34 * This can be turned up by using apic=verbose for more
35 * information and apic=debug for _lots_ of information.
36 * apic_verbosity is defined in apic.c
37 */
38 #define apic_printk(v, s, a...) do { \
39 if ((v) <= apic_verbosity) \
40 printk(s, ##a); \
41 } while (0)
42
43
44 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
45 extern void x86_32_probe_apic(void);
46 #else
x86_32_probe_apic(void)47 static inline void x86_32_probe_apic(void) { }
48 #endif
49
50 #ifdef CONFIG_X86_LOCAL_APIC
51
52 extern int apic_verbosity;
53 extern int local_apic_timer_c2_ok;
54
55 extern bool apic_is_disabled;
56 extern unsigned int lapic_timer_period;
57
58 extern int cpuid_to_apicid[];
59
60 extern enum apic_intr_mode_id apic_intr_mode;
61 enum apic_intr_mode_id {
62 APIC_PIC,
63 APIC_VIRTUAL_WIRE,
64 APIC_VIRTUAL_WIRE_NO_CONFIG,
65 APIC_SYMMETRIC_IO,
66 APIC_SYMMETRIC_IO_NO_ROUTING
67 };
68
69 /*
70 * With 82489DX we can't rely on apic feature bit
71 * retrieved via cpuid but still have to deal with
72 * such an apic chip so we assume that SMP configuration
73 * is found from MP table (64bit case uses ACPI mostly
74 * which set smp presence flag as well so we are safe
75 * to use this helper too).
76 */
apic_from_smp_config(void)77 static inline bool apic_from_smp_config(void)
78 {
79 return smp_found_config && !apic_is_disabled;
80 }
81
82 /*
83 * Basic functions accessing APICs.
84 */
85 #ifdef CONFIG_PARAVIRT
86 #include <asm/paravirt.h>
87 #endif
88
native_apic_mem_write(u32 reg,u32 v)89 static inline void native_apic_mem_write(u32 reg, u32 v)
90 {
91 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
92
93 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
94 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
95 ASM_OUTPUT2("0" (v), "m" (*addr)));
96 }
97
native_apic_mem_read(u32 reg)98 static inline u32 native_apic_mem_read(u32 reg)
99 {
100 return readl((void __iomem *)(APIC_BASE + reg));
101 }
102
native_apic_mem_eoi(void)103 static inline void native_apic_mem_eoi(void)
104 {
105 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
106 }
107
108 extern void native_apic_icr_write(u32 low, u32 id);
109 extern u64 native_apic_icr_read(void);
110
apic_is_x2apic_enabled(void)111 static inline bool apic_is_x2apic_enabled(void)
112 {
113 u64 msr;
114
115 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
116 return false;
117 return msr & X2APIC_ENABLE;
118 }
119
120 extern void enable_IR_x2apic(void);
121
122 extern int get_physical_broadcast(void);
123
124 extern int lapic_get_maxlvt(void);
125 extern void clear_local_APIC(void);
126 extern void disconnect_bsp_APIC(int virt_wire_setup);
127 extern void disable_local_APIC(void);
128 extern void apic_soft_disable(void);
129 extern void lapic_shutdown(void);
130 extern void sync_Arb_IDs(void);
131 extern void init_bsp_APIC(void);
132 extern void apic_intr_mode_select(void);
133 extern void apic_intr_mode_init(void);
134 extern void init_apic_mappings(void);
135 void register_lapic_address(unsigned long address);
136 extern void setup_boot_APIC_clock(void);
137 extern void setup_secondary_APIC_clock(void);
138 extern void lapic_update_tsc_freq(void);
139
140 #ifdef CONFIG_X86_64
apic_force_enable(unsigned long addr)141 static inline bool apic_force_enable(unsigned long addr)
142 {
143 return false;
144 }
145 #else
146 extern bool apic_force_enable(unsigned long addr);
147 #endif
148
149 extern void apic_ap_setup(void);
150
151 /*
152 * On 32bit this is mach-xxx local
153 */
154 #ifdef CONFIG_X86_64
155 extern int apic_is_clustered_box(void);
156 #else
apic_is_clustered_box(void)157 static inline int apic_is_clustered_box(void)
158 {
159 return 0;
160 }
161 #endif
162
163 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
164 extern void lapic_assign_system_vectors(void);
165 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
166 extern void lapic_update_legacy_vectors(void);
167 extern void lapic_online(void);
168 extern void lapic_offline(void);
169 extern bool apic_needs_pit(void);
170
171 extern void apic_send_IPI_allbutself(unsigned int vector);
172
173 #else /* !CONFIG_X86_LOCAL_APIC */
lapic_shutdown(void)174 static inline void lapic_shutdown(void) { }
175 #define local_apic_timer_c2_ok 1
init_apic_mappings(void)176 static inline void init_apic_mappings(void) { }
disable_local_APIC(void)177 static inline void disable_local_APIC(void) { }
178 # define setup_boot_APIC_clock x86_init_noop
179 # define setup_secondary_APIC_clock x86_init_noop
lapic_update_tsc_freq(void)180 static inline void lapic_update_tsc_freq(void) { }
init_bsp_APIC(void)181 static inline void init_bsp_APIC(void) { }
apic_intr_mode_select(void)182 static inline void apic_intr_mode_select(void) { }
apic_intr_mode_init(void)183 static inline void apic_intr_mode_init(void) { }
lapic_assign_system_vectors(void)184 static inline void lapic_assign_system_vectors(void) { }
lapic_assign_legacy_vector(unsigned int i,bool r)185 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
apic_needs_pit(void)186 static inline bool apic_needs_pit(void) { return true; }
187 #endif /* !CONFIG_X86_LOCAL_APIC */
188
189 #ifdef CONFIG_X86_X2APIC
native_apic_msr_write(u32 reg,u32 v)190 static inline void native_apic_msr_write(u32 reg, u32 v)
191 {
192 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
193 reg == APIC_LVR)
194 return;
195
196 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
197 }
198
native_apic_msr_eoi(void)199 static inline void native_apic_msr_eoi(void)
200 {
201 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
202 }
203
native_apic_msr_read(u32 reg)204 static inline u32 native_apic_msr_read(u32 reg)
205 {
206 u64 msr;
207
208 if (reg == APIC_DFR)
209 return -1;
210
211 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
212 return (u32)msr;
213 }
214
native_x2apic_icr_write(u32 low,u32 id)215 static inline void native_x2apic_icr_write(u32 low, u32 id)
216 {
217 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
218 }
219
native_x2apic_icr_read(void)220 static inline u64 native_x2apic_icr_read(void)
221 {
222 unsigned long val;
223
224 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
225 return val;
226 }
227
228 extern int x2apic_mode;
229 extern int x2apic_phys;
230 extern void __init x2apic_set_max_apicid(u32 apicid);
231 extern void x2apic_setup(void);
x2apic_enabled(void)232 static inline int x2apic_enabled(void)
233 {
234 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
235 }
236
237 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
238 #else /* !CONFIG_X86_X2APIC */
x2apic_setup(void)239 static inline void x2apic_setup(void) { }
x2apic_enabled(void)240 static inline int x2apic_enabled(void) { return 0; }
native_apic_msr_read(u32 reg)241 static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
242 #define x2apic_mode (0)
243 #define x2apic_supported() (0)
244 #endif /* !CONFIG_X86_X2APIC */
245 extern void __init check_x2apic(void);
246
247 struct irq_data;
248
249 /*
250 * Copyright 2004 James Cleverdon, IBM.
251 *
252 * Generic APIC sub-arch data struct.
253 *
254 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
255 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
256 * James Cleverdon.
257 */
258 struct apic {
259 /* Hotpath functions first */
260 void (*eoi)(void);
261 void (*native_eoi)(void);
262 void (*write)(u32 reg, u32 v);
263 u32 (*read)(u32 reg);
264
265 /* IPI related functions */
266 void (*wait_icr_idle)(void);
267 u32 (*safe_wait_icr_idle)(void);
268
269 void (*send_IPI)(int cpu, int vector);
270 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
271 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
272 void (*send_IPI_allbutself)(int vector);
273 void (*send_IPI_all)(int vector);
274 void (*send_IPI_self)(int vector);
275
276 enum apic_delivery_modes delivery_mode;
277
278 u32 disable_esr : 1,
279 dest_mode_logical : 1,
280 x2apic_set_max_apicid : 1,
281 nmi_to_offline_cpu : 1;
282
283 u32 (*calc_dest_apicid)(unsigned int cpu);
284
285 /* ICR related functions */
286 u64 (*icr_read)(void);
287 void (*icr_write)(u32 low, u32 high);
288
289 /* The limit of the APIC ID space. */
290 u32 max_apic_id;
291
292 /* Probe, setup and smpboot functions */
293 int (*probe)(void);
294 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
295 bool (*apic_id_registered)(void);
296
297 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
298 void (*init_apic_ldr)(void);
299 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
300 int (*cpu_present_to_apicid)(int mps_cpu);
301 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
302
303 u32 (*get_apic_id)(unsigned long x);
304 u32 (*set_apic_id)(unsigned int id);
305
306 /* wakeup_secondary_cpu */
307 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
308 /* wakeup secondary CPU using 64-bit wakeup point */
309 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
310
311 char *name;
312 };
313
314 struct apic_override {
315 void (*eoi)(void);
316 void (*native_eoi)(void);
317 void (*write)(u32 reg, u32 v);
318 u32 (*read)(u32 reg);
319 void (*send_IPI)(int cpu, int vector);
320 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
321 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
322 void (*send_IPI_allbutself)(int vector);
323 void (*send_IPI_all)(int vector);
324 void (*send_IPI_self)(int vector);
325 u64 (*icr_read)(void);
326 void (*icr_write)(u32 low, u32 high);
327 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
328 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
329 };
330
331 /*
332 * Pointer to the local APIC driver in use on this system (there's
333 * always just one such driver in use - the kernel decides via an
334 * early probing process which one it picks - and then sticks to it):
335 */
336 extern struct apic *apic;
337
338 /*
339 * APIC drivers are probed based on how they are listed in the .apicdrivers
340 * section. So the order is important and enforced by the ordering
341 * of different apic driver files in the Makefile.
342 *
343 * For the files having two apic drivers, we use apic_drivers()
344 * to enforce the order with in them.
345 */
346 #define apic_driver(sym) \
347 static const struct apic *__apicdrivers_##sym __used \
348 __aligned(sizeof(struct apic *)) \
349 __section(".apicdrivers") = { &sym }
350
351 #define apic_drivers(sym1, sym2) \
352 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
353 __aligned(sizeof(struct apic *)) \
354 __section(".apicdrivers") = { &sym1, &sym2 }
355
356 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
357
358 /*
359 * APIC functionality to boot other CPUs - only used on SMP:
360 */
361 #ifdef CONFIG_SMP
362 extern int lapic_can_unplug_cpu(void);
363 #endif
364
365 #ifdef CONFIG_X86_LOCAL_APIC
366 extern struct apic_override __x86_apic_override;
367
368 void __init apic_setup_apic_calls(void);
369 void __init apic_install_driver(struct apic *driver);
370
371 #define apic_update_callback(_callback, _fn) { \
372 __x86_apic_override._callback = _fn; \
373 apic->_callback = _fn; \
374 static_call_update(apic_call_##_callback, _fn); \
375 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
376 }
377
378 #define DECLARE_APIC_CALL(__cb) \
379 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
380
381 DECLARE_APIC_CALL(eoi);
382 DECLARE_APIC_CALL(native_eoi);
383 DECLARE_APIC_CALL(icr_read);
384 DECLARE_APIC_CALL(icr_write);
385 DECLARE_APIC_CALL(read);
386 DECLARE_APIC_CALL(send_IPI);
387 DECLARE_APIC_CALL(send_IPI_mask);
388 DECLARE_APIC_CALL(send_IPI_mask_allbutself);
389 DECLARE_APIC_CALL(send_IPI_allbutself);
390 DECLARE_APIC_CALL(send_IPI_all);
391 DECLARE_APIC_CALL(send_IPI_self);
392 DECLARE_APIC_CALL(wait_icr_idle);
393 DECLARE_APIC_CALL(wakeup_secondary_cpu);
394 DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
395 DECLARE_APIC_CALL(write);
396
apic_read(u32 reg)397 static __always_inline u32 apic_read(u32 reg)
398 {
399 return static_call(apic_call_read)(reg);
400 }
401
apic_write(u32 reg,u32 val)402 static __always_inline void apic_write(u32 reg, u32 val)
403 {
404 static_call(apic_call_write)(reg, val);
405 }
406
apic_eoi(void)407 static __always_inline void apic_eoi(void)
408 {
409 static_call(apic_call_eoi)();
410 }
411
apic_native_eoi(void)412 static __always_inline void apic_native_eoi(void)
413 {
414 static_call(apic_call_native_eoi)();
415 }
416
apic_icr_read(void)417 static __always_inline u64 apic_icr_read(void)
418 {
419 return static_call(apic_call_icr_read)();
420 }
421
apic_icr_write(u32 low,u32 high)422 static __always_inline void apic_icr_write(u32 low, u32 high)
423 {
424 static_call(apic_call_icr_write)(low, high);
425 }
426
__apic_send_IPI(int cpu,int vector)427 static __always_inline void __apic_send_IPI(int cpu, int vector)
428 {
429 static_call(apic_call_send_IPI)(cpu, vector);
430 }
431
__apic_send_IPI_mask(const struct cpumask * mask,int vector)432 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
433 {
434 static_call_mod(apic_call_send_IPI_mask)(mask, vector);
435 }
436
__apic_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)437 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
438 {
439 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
440 }
441
__apic_send_IPI_allbutself(int vector)442 static __always_inline void __apic_send_IPI_allbutself(int vector)
443 {
444 static_call(apic_call_send_IPI_allbutself)(vector);
445 }
446
__apic_send_IPI_all(int vector)447 static __always_inline void __apic_send_IPI_all(int vector)
448 {
449 static_call(apic_call_send_IPI_all)(vector);
450 }
451
__apic_send_IPI_self(int vector)452 static __always_inline void __apic_send_IPI_self(int vector)
453 {
454 static_call_mod(apic_call_send_IPI_self)(vector);
455 }
456
apic_wait_icr_idle(void)457 static __always_inline void apic_wait_icr_idle(void)
458 {
459 static_call_cond(apic_call_wait_icr_idle)();
460 }
461
safe_apic_wait_icr_idle(void)462 static __always_inline u32 safe_apic_wait_icr_idle(void)
463 {
464 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
465 }
466
apic_id_valid(u32 apic_id)467 static __always_inline bool apic_id_valid(u32 apic_id)
468 {
469 return apic_id <= apic->max_apic_id;
470 }
471
472 #else /* CONFIG_X86_LOCAL_APIC */
473
apic_read(u32 reg)474 static inline u32 apic_read(u32 reg) { return 0; }
apic_write(u32 reg,u32 val)475 static inline void apic_write(u32 reg, u32 val) { }
apic_eoi(void)476 static inline void apic_eoi(void) { }
apic_icr_read(void)477 static inline u64 apic_icr_read(void) { return 0; }
apic_icr_write(u32 low,u32 high)478 static inline void apic_icr_write(u32 low, u32 high) { }
apic_wait_icr_idle(void)479 static inline void apic_wait_icr_idle(void) { }
safe_apic_wait_icr_idle(void)480 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
apic_set_eoi_cb(void (* eoi)(void))481 static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
apic_native_eoi(void)482 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
apic_setup_apic_calls(void)483 static inline void apic_setup_apic_calls(void) { }
484
485 #define apic_update_callback(_callback, _fn) do { } while (0)
486
487 #endif /* CONFIG_X86_LOCAL_APIC */
488
489 extern void apic_ack_irq(struct irq_data *data);
490
lapic_vector_set_in_irr(unsigned int vector)491 static inline bool lapic_vector_set_in_irr(unsigned int vector)
492 {
493 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
494
495 return !!(irr & (1U << (vector % 32)));
496 }
497
default_get_apic_id(unsigned long x)498 static inline unsigned default_get_apic_id(unsigned long x)
499 {
500 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
501
502 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
503 return (x >> 24) & 0xFF;
504 else
505 return (x >> 24) & 0x0F;
506 }
507
508 /*
509 * Warm reset vector position:
510 */
511 #define TRAMPOLINE_PHYS_LOW 0x467
512 #define TRAMPOLINE_PHYS_HIGH 0x469
513
514 extern void generic_bigsmp_probe(void);
515
516 #ifdef CONFIG_X86_LOCAL_APIC
517
518 #include <asm/smp.h>
519
520 extern struct apic apic_noop;
521
read_apic_id(void)522 static inline unsigned int read_apic_id(void)
523 {
524 unsigned int reg = apic_read(APIC_ID);
525
526 return apic->get_apic_id(reg);
527 }
528
529 #ifdef CONFIG_X86_64
530 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
531 extern int default_acpi_madt_oem_check(char *, char *);
532 extern void x86_64_probe_apic(void);
533 #else
default_acpi_madt_oem_check(char * a,char * b)534 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
x86_64_probe_apic(void)535 static inline void x86_64_probe_apic(void) { }
536 #endif
537
538 extern int default_apic_id_valid(u32 apicid);
539
540 extern u32 apic_default_calc_apicid(unsigned int cpu);
541 extern u32 apic_flat_calc_apicid(unsigned int cpu);
542
543 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
544 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
545 extern int default_cpu_present_to_apicid(int mps_cpu);
546
547 void apic_send_nmi_to_offline_cpu(unsigned int cpu);
548
549 #else /* CONFIG_X86_LOCAL_APIC */
550
read_apic_id(void)551 static inline unsigned int read_apic_id(void) { return 0; }
552
553 #endif /* !CONFIG_X86_LOCAL_APIC */
554
555 #ifdef CONFIG_SMP
556 void apic_smt_update(void);
557 #else
apic_smt_update(void)558 static inline void apic_smt_update(void) { }
559 #endif
560
561 struct msi_msg;
562 struct irq_cfg;
563
564 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
565 bool dmar);
566
567 extern void ioapic_zap_locks(void);
568
569 #endif /* _ASM_X86_APIC_H */
570