1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST2300/AST2400 DDR2/DDR3 SDRAM controller initialization and calibration sequence 17 * 18 * Gary Hsu, <gary_hsu@aspeedtech.com> 19 * 20 * Release date: 2018.08.02 test release for SDK0.65 21 * 22 * Modified list from v0.23 23 * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm 24 * EC2. Remove pass 2 DQIDLY finetune process 25 * EC3. Modify ECC code 26 * EC4. Add AST2400 supporting 27 * EC5. Add SPI timing calibration for AST2400 28 * EC6. Remove AST2300-A0 PCI-e workaround 29 * EC7. Add CK duty calibration for AST2400 30 * EC8. Remove #define CONFIG_DRAM_UART_OUT, default has message output to UART5 31 * EC9. Add DRAM size auto-detection 32 * EC10. Add GPIO register clear when watchdog reboot (only for AST2400) 33 * EC11. Move the "Solve ASPM" code position of AST2300 to avoid watchdog reset 34 * 35 * Modified list from v0.53 36 * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11) 37 * 38 * Modified list from v0.56 39 * EC1. Fix read DQS input mask window too late issue if DRAM's t_DQSCK is earlier too much 40 * (ex. Nanya NT5CB64M16FP) 41 * 1. Change init value of MCR18[4] from '1' to '0' 42 * 2. Add CBR4 code to finetune MCR18[4] 43 * 44 * Modified list from v0.59 45 * EC1. Add DQS input gating window delay tuning (1/2 T) when CBR retry 46 * EC2. Modify DLL1 MAdj = 0x4C 47 * 48 * Modified list from v0.60 49 * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4. 50 * 51 * Modified list from v0.61 52 * EC1. Set for wide screen supporting, 0x1e6e2040[0] = 1 53 * 54 * Modified list from v0.62 55 * EC1. Clear MCR04[10] = 0 before doing DRAM initial 56 * EC2. Add USB2.0 port initial 57 * 58 * Modified list from v0.63 59 * EC1. Modify DDR driving on MCR6C from 0x2312 to 0x2323 60 * EC2. Reset RNG to fix RNG read 0 issue 61 * 62 * Modified list from v0.64 63 * EC1. Default assign X-DMA engine to VGA memory domain, MCR08[16] = 1. 64 * 65 * Optional define variable 66 * 1. DRAM Speed // 67 * CONFIG_DRAM_336 // 336MHz (DDR-667) 68 * CONFIG_DRAM_408 // 408MHz (DDR-800) (default) 69 * 2. ECC Function enable 70 * CONFIG_DRAM_ECC // define to enable ECC function 71 * // when enabled, must define the ECC protected memory size at 0x1e6e0054 72 * 3. UART5 message output // 73 * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 74 ****************************************************************************** 75 */ 76 77#include <config.h> 78#include <version.h> 79/****************************************************************************** 80 Calibration Macro Start 81 Usable registers: 82 r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11 83 ******************************************************************************/ 84/* PATTERN_TABLE, 85 init_delay_timer, 86 check_delay_timer, 87 clear_delay_timer, 88 record_dll2_pass_range, 89 record_dll2_pass_range_h, 90 are for DRAM calibration */ 91 92PATTERN_TABLE: 93 .word 0xff00ff00 94 .word 0xcc33cc33 95 .word 0xaa55aa55 96 .word 0x88778877 97 .word 0x92cc4d6e @ 5 98 .word 0x543d3cde 99 .word 0xf1e843c7 100 .word 0x7c61d253 101 .word 0x00000000 @ 8 102 103 .macro init_delay_timer 104 ldr r0, =0x1e782024 @ Set Timer3 Reload 105 str r2, [r0] 106 107 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 108 ldr r1, =0x00040000 109 str r1, [r0] 110 111 ldr r0, =0x1e782030 @ Enable Timer3 112 ldr r1, [r0] 113 mov r2, #7 114 orr r1, r1, r2, lsl #8 115 str r1, [r0] 116 117 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout 118 .endm 119 120 .macro check_delay_timer 121 ldr r1, [r0] 122 bic r1, r1, #0xFFFBFFFF 123 mov r2, r1, lsr #18 124 cmp r2, #0x01 125 .endm 126 127 .macro clear_delay_timer 128 ldr r0, =0x1e782030 @ Disable Timer3 129 ldr r1, [r0] 130 bic r1, r1, #0x00000F00 131 str r1, [r0] 132 133 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 134 ldr r1, =0x00040000 135 str r1, [r0] 136 .endm 137 138 .macro record_dll2_pass_range 139 ldr r1, [r0] 140 bic r2, r1, #0xFFFFFF00 141 cmp r2, r3 @ record min 142 bicgt r1, r1, #0x000000FF 143 orrgt r1, r1, r3 144 bic r2, r1, #0xFFFF00FF 145 cmp r3, r2, lsr #8 @ record max 146 bicgt r1, r1, #0x0000FF00 147 orrgt r1, r1, r3, lsl #8 148 str r1, [r0] 149 .endm 150 151 .macro record_dll2_pass_range_h 152 ldr r1, [r0] 153 bic r2, r1, #0xFF00FFFF 154 mov r2, r2, lsr #16 155 cmp r2, r3 @ record min 156 bicgt r1, r1, #0x00FF0000 157 orrgt r1, r1, r3, lsl #16 158 bic r2, r1, #0x00FFFFFF 159 cmp r3, r2, lsr #24 @ record max 160 bicgt r1, r1, #0xFF000000 161 orrgt r1, r1, r3, lsl #24 162 str r1, [r0] 163 .endm 164 165 .macro init_spi_checksum 166 ldr r0, =0x1e620084 167 ldr r1, =0x20010000 168 str r1, [r0] 169 ldr r0, =0x1e62008C 170 ldr r1, =0x20000200 171 str r1, [r0] 172 ldr r0, =0x1e620080 173 ldr r1, =0x0000000D 174 orr r2, r2, r7 175 orr r1, r1, r2, lsl #8 176 and r2, r6, #0xF 177 orr r1, r1, r2, lsl #4 178 str r1, [r0] 179 ldr r0, =0x1e620008 180 ldr r2, =0x00000800 181 .endm 182 183/****************************************************************************** 184 Calibration Macro End 185 ******************************************************************************/ 186LPC_Patch: @ load to SRAM base 0x1e720400 187 str r1, [r0] 188 str r3, [r2] 189 bic r1, r1, #0xFF 190LPC_Patch_S1: 191 subs r5, r5, #0x01 192 moveq pc, r8 193 ldr r3, [r2] 194 tst r3, #0x01 195 movne pc, r8 196 mov pc, r7 197LPC_Patch_S2: @ load to SRAM base 0x1e720480 198 str r1, [r0] 199 mov pc, r9 200LPC_Patch_E: 201 202.globl lowlevel_init 203lowlevel_init: 204 205init_dram: 206/* Test - DRAM initial time */ 207 ldr r0, =0x1e782044 208 ldr r1, =0xFFFFFFFF 209 str r1, [r0] 210 211 ldr r0, =0x1e782030 212 ldr r1, [r0] 213 bic r1, r1, #0x0000F000 214 str r1, [r0] 215 mov r2, #3 216 orr r1, r1, r2, lsl #12 217 str r1, [r0] 218/* Test - DRAM initial time */ 219 220 /*Set Scratch register Bit 7 before initialize*/ 221 ldr r0, =0x1e6e2000 222 ldr r1, =0x1688a8a8 223 str r1, [r0] 224 225 ldr r0, =0x1e6e2040 226 ldr r1, [r0] 227 orr r1, r1, #0x80 228 str r1, [r0] 229 230 /* Configure USB ports to the correct pin state */ 231 ldr r0, =0x1e6e200c @ enable portA clock 232 ldr r2, =0x00004000 233 ldr r1, [r0] 234 orr r1, r1, r2 235 str r1, [r0] 236 ldr r0, =0x1e6e2090 @ set USB2.0 port as host mode 237 ldr r1, =0x2000A000 238 str r1, [r0] 239 240 /* Fix LPC lock issue for AST2300 */ 241 ldr r0, =0x1e6e207c @ Check AST2300 242 ldr r1, [r0] 243 mov r1, r1, lsr #24 244 cmp r1, #0x01 245 bne lpc_recover_end @ not match AST2300 246 247 mov r3, #0x0 248lpc_recover_check: 249 ldr r0, =0x1e78900c @ check HICR3[4]=0x1 250 ldr r1, [r0] 251 tst r1, #0x10 252 beq lpc_recover_end 253 ldr r0, =0x1e789004 @ check HICR1[7]=0x1 254 ldr r1, [r0] 255 tst r1, #0x80 256 beq lpc_recover_end 257 ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6 258 ldr r1, [r0] 259 mov r1, r1, lsr #24 260 and r1, r1, #0xF 261 cmp r1, #0x06 262 bne lpc_recover_end 263 add r3, r3, #0x01 264 cmp r3, #0x5 @ repeat 5 times 265 ble lpc_recover_check 266 267 mov r3, #0x0 268lpc_recover_init: 269 ldr r0, =0x1e7890a4 @ set LHCR1[1:0]=0x0 270 ldr r1, =0x00000000 271 str r1, [r0] 272 add r3, r3, #0x01 273 cmp r3, #0x20 274 bge lpc_recover_end 275 ldr r1, [r0] 276 tst r1, #0x01 277 bne lpc_recover_init 278 279 ldr r0, =0x1e7890b0 @ set LHCR4[7:0]=0xFF 280 ldr r1, =0x000000FF 281 str r1, [r0] 282 ldr r0, =0x1e7890b4 @ set LHCR5[31:0]=0xFFFFFFFF 283 ldr r1, =0xFFFFFFFF 284 str r1, [r0] 285 ldr r0, =0x1e7890b8 @ set LHCR6[31:0]=0xFFFFFFFF 286 str r1, [r0] 287 288 adr r6, LPC_Patch 289 adr r7, LPC_Patch_S2 290 ldr r0, =0x1e720400 291copy_lpc_patch_1: 292 ldr r1, [r6] 293 str r1, [r0] 294 add r6, r6, #0x4 295 add r0, r0, #0x4 296 cmp r6, r7 297 bne copy_lpc_patch_1 298 299 adr r6, LPC_Patch_S2 300 adr r7, LPC_Patch_E 301 ldr r0, =0x1e720480 302copy_lpc_patch_2: 303 ldr r1, [r6] 304 str r1, [r0] 305 add r6, r6, #0x4 306 add r0, r0, #0x4 307 cmp r6, r7 308 bne copy_lpc_patch_2 309 310 ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF01 311 ldr r1, =0xFFFFFF01 312 add r2, r0, #0x4 313 mov r3, #0x01 314 mov r5, #0x10 315 adr r9, lpc_recover_end 316 adr r6, LPC_Patch 317 adr r7, LPC_Patch_S1 318 sub r6, r7, r6 319 ldr r7, =0x1e720400 320 add r7, r7, r6 321 ldr r8, =0x1e720480 322 ldr pc, =0x1e720400 323 324lpc_recover_end: 325 ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF00 326 ldr r1, =0xFFFFFF00 327 str r1, [r0] 328 /* <END> Fix LPC lock issue for AST2300 */ 329 330 /* Check Scratch Register Bit 6 */ 331 ldr r0, =0x1e6e2040 332 ldr r1, [r0] 333 bic r1, r1, #0xFFFFFFBF 334 mov r2, r1, lsr #6 335 cmp r2, #0x01 336 beq platform_exit 337 338 ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324) 339/* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */ 340 ldr r0, =0x1e6e207c @ Check Revision ID 341 ldr r1, [r0] 342 mov r1, r1, lsr #24 343 cmp r1, #0x02 344 bne set_MPLL @ not match AST2400 345 346 ldr r0, =0x1e6e2070 @ Check CLKIN freq 347 ldr r1, [r0] 348 mov r1, r1, lsr #23 349 tst r1, #0x01 350 ldrne r2, =0x017001D0 @ load PLL parameter for 25Mhz CLKIN (400:325) 351 352set_MPLL: 353 ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency 354 ldr r1, =0xFFFF 355#if defined(CONFIG_DRAM_336) 356 mov r2, r2, lsr #16 357#endif 358 and r1, r2, r1 359 str r1, [r0] 360 361/* Debug - UART console message */ 362 ldr r0, =0x1e78400c 363 mov r1, #0x83 364 str r1, [r0] 365 366 ldr r0, =0x1e6e202c 367 ldr r2, [r0] 368 mov r2, r2, lsr #12 369 tst r2, #0x01 370 ldr r0, =0x1e784000 371 moveq r1, #0x0D @ Baudrate 115200 372 movne r1, #0x01 @ Baudrate 115200, div13 373#if defined(CONFIG_DRAM_UART_38400) 374 moveq r1, #0x27 @ Baudrate 38400 375 movne r1, #0x03 @ Baudrate 38400 , div13 376#endif 377 str r1, [r0] 378 379 ldr r0, =0x1e784004 380 mov r1, #0x00 381 str r1, [r0] 382 383 ldr r0, =0x1e78400c 384 mov r1, #0x03 385 str r1, [r0] 386 387 ldr r0, =0x1e784008 388 mov r1, #0x07 389 str r1, [r0] 390 391 ldr r0, =0x1e784000 392 mov r1, #0x0D @ '\r' 393 str r1, [r0] 394 mov r1, #0x0A @ '\n' 395 str r1, [r0] 396 mov r1, #0x44 @ 'D' 397 str r1, [r0] 398 mov r1, #0x52 @ 'R' 399 str r1, [r0] 400 mov r1, #0x41 @ 'A' 401 str r1, [r0] 402 mov r1, #0x4D @ 'M' 403 str r1, [r0] 404 mov r1, #0x20 @ ' ' 405 str r1, [r0] 406 mov r1, #0x49 @ 'I' 407 str r1, [r0] 408 mov r1, #0x6E @ 'n' 409 str r1, [r0] 410 mov r1, #0x69 @ 'i' 411 str r1, [r0] 412 mov r1, #0x74 @ 't' 413 str r1, [r0] 414 mov r1, #0x2D @ '-' 415 str r1, [r0] 416 mov r1, #0x44 @ 'D' 417 str r1, [r0] 418 mov r1, #0x44 @ 'D' 419 str r1, [r0] 420 mov r1, #0x52 @ 'R' 421 str r1, [r0] 422/* Debug - UART console message */ 423 424 ldr r0, =0x1e6e2074 @ Reset Randon Number Generator 425 mov r1, #0x01 426 str r1, [r0] 427 428 /* Delay about 100us */ 429 ldr r0, =0x1e782030 @ Init Timer3 Control 430 ldr r1, [r0] 431 bic r1, r1, #0x00000F00 432 str r1, [r0] 433 434 ldr r2, =0x00000064 @ Set Timer3 Reload = 100 us 435 init_delay_timer 436delay_0: 437 check_delay_timer 438 bne delay_0 439 clear_delay_timer 440 /* end delay 100us */ 441 442 ldr r0, =0x1e6e2074 @ Recover Randon Number Generator 443 mov r1, #0x0E 444 str r1, [r0] 445 446/****************************************************************************** 447 Init DRAM common registers 448 ******************************************************************************/ 449 ldr r0, =0x1e6e0000 450 ldr r1, =0xfc600309 451 str r1, [r0] 452 453 /* Reset MMC */ 454 ldr r1, =0x00000000 455 ldr r0, =0x1e6e0004 456 str r1, [r0] 457 ldr r0, =0x1e6e0034 458 str r1, [r0] 459 ldr r0, =0x1e6e0018 460 str r1, [r0] 461 ldr r0, =0x1e6e0024 462 str r1, [r0] 463 ldr r0, =0x1e6e0064 @ REG_MADJ, power down DLL 464 str r1, [r0] 465 466 ldr r1, =0x00034C4C @ REG_MADJ, reset DLL 467 str r1, [r0] 468 469 ldr r0, =0x1e6e0068 @ REG_SADJ 470 ldr r1, =0x00001800 471 str r1, [r0] 472 473 /* Delay about 10us */ 474 ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us 475 init_delay_timer 476delay_1: 477 check_delay_timer 478 bne delay_1 479 clear_delay_timer 480 /* end delay 10us */ 481 482 ldr r0, =0x1e6e0064 @ REG_MADJ | 0xC0000, enable DLL 483 ldr r1, [r0] 484 ldr r2, =0xC0000 485 orr r1, r1, r2 486 str r1, [r0] 487 488 ldr r0, =0x1e6e0008 489 ldr r1, =0x0092040f /* VGA : remember to clear MCR04[10] = 0 */ 490 str r1, [r0] 491 492 ldr r0, =0x1e6e0018 493 ldr r1, =0x4000A120 494 str r1, [r0] 495 496 ldr r0, =0x1e6e0018 497 ldr r1, =0x00000120 498 str r1, [r0] 499 500 ldr r0, =0x1e6e0038 501 ldr r1, =0x00000000 502 str r1, [r0] 503 504 ldr r0, =0x1e6e0040 505 ldr r1, =0xFF444444 506 str r1, [r0] 507 508 ldr r0, =0x1e6e0044 509 ldr r1, =0x22222222 510 str r1, [r0] 511 512 ldr r0, =0x1e6e0048 513 ldr r1, =0x22222222 514 str r1, [r0] 515 516 ldr r0, =0x1e6e004c 517 ldr r1, =0x22222222 518 str r1, [r0] 519 520 ldr r0, =0x1e6e0050 521 ldr r1, =0x80000000 522 str r1, [r0] 523 524 ldr r0, =0x1e6e0050 525 ldr r1, =0x00000000 526 str r1, [r0] 527 528 ldr r0, =0x1e6e0054 529 ldr r1, =0x00000000 530 str r1, [r0] 531 532 ldr r0, =0x1e6e0060 @ REG_DRV 533 ldr r1, =0x000000FA @ 408 MHz 534#if defined(CONFIG_DRAM_336) 535 ldr r1, =0x000000FA 536#endif 537 str r1, [r0] 538 539 ldr r0, =0x1e6e0070 540 ldr r1, =0x00000000 541 str r1, [r0] 542 543 ldr r0, =0x1e6e0074 544 ldr r1, =0x00000000 545 str r1, [r0] 546 547 ldr r0, =0x1e6e0078 548 ldr r1, =0x00000000 549 str r1, [r0] 550 551 ldr r0, =0x1e6e007c 552 ldr r1, =0x00000000 553 str r1, [r0] 554 555 ldr r0, =0x1e6e0080 556 ldr r1, =0x00000000 557 str r1, [r0] 558 559 ldr r0, =0x1e6e0084 560 ldr r1, =0x00FFFFFF 561 str r1, [r0] 562 563 ldr r0, =0x1e6e0088 @ REG_DQIDLY 564 ldr r1, =0x00000089 @ 408 MHz 565#if defined(CONFIG_DRAM_336) 566 ldr r1, =0x00000074 567#endif 568 str r1, [r0] 569 570 ldr r0, =0x1e6e0020 @ REG_DQSIC 571 ldr r1, =0x000000E2 @ 408 MHz 572#if defined(CONFIG_DRAM_336) 573 ldr r1, =0x000000BA 574#endif 575 str r1, [r0] 576 577 /* Delay about 10us */ 578 ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us 579 init_delay_timer 580delay_2: 581 check_delay_timer 582 bne delay_2 583 clear_delay_timer 584 /* end delay 10us */ 585 586 /* Check DRAM Type by H/W Trapping */ 587 ldr r0, =0x1e6e2070 588 ldr r1, [r0] 589 bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2 590 mov r2, r1, lsr #24 591 cmp r2, #0x01 592 beq ddr2_init 593 b ddr3_init 594.LTORG 595 596/****************************************************************************** 597 DDR3 Init 598 599 tRCD = 15 ns 600 tRAS = 37.5 ns 601 tRRD = max(4 CK,10 ns) 602 tRP = 15 ns 603 tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit 604 tRTP = max(4 CK,7.5 ns) 605 tWR = 15 ns 606 tXSNR = max(10 CK,200 ns) 607 tWTR = max(4 CK,7.5 ns) 608 tFAW = 50 ns 609 tMRD = max(15 CK,20 ns) 610 ******************************************************************************/ 611ddr3_init: 612/* Debug - UART console message */ 613 ldr r0, =0x1e784000 614 mov r1, #0x33 @ '3' 615 str r1, [r0] 616 mov r1, #0x0D @ '\r' 617 str r1, [r0] 618 mov r1, #0x0A @ '\n' 619 str r1, [r0] 620/* Debug - UART console message */ 621 622 ldr r0, =0x1e6e0004 623 ldr r1, =0x00000531 @ Default set to 1Gbit 624 str r1, [r0] 625 626 ldr r0, =0x1e6e0010 @ REG_AC1 627 ldr r1, =0x33302825 @ 408 MHz 628#if defined(CONFIG_DRAM_336) 629 ldr r1, =0x22202725 630#endif 631 str r1, [r0] 632 633 /* Check DRAM CL Timing by H/W Trapping */ 634 ldr r0, =0x1e6e2070 635 ldr r1, [r0] 636 bic r1, r1, #0xF9FFFFFF 637 mov r2, r1, lsr #9 @ Set CL 638 ldr r1, =0x00020000 639 add r2, r2, r1 640 ldr r1, [r0] 641 bic r1, r1, #0xFBFFFFFF 642 mov r1, r1, lsr #6 @ Set CWL 643 orr r2, r2, r1 644 ldr r1, =0x00300000 645 add r2, r2, r1 646 647 ldr r0, =0x1e6e0014 @ REG_AC2 648 ldr r1, =0xCC00963F @ 408 MHz 649#if defined(CONFIG_DRAM_336) 650 ldr r1, =0xAA007636 651#endif 652 orr r1, r1, r2 653 str r1, [r0] 654 655 ldr r0, =0x1e6e0004 @ check 2400 mode 656 ldr r2, [r0] 657 mov r2, r2, lsr #10 658 659 ldr r0, =0x1e6e006c @ REG_IOZ 660 ldr r1, =0x00002323 @ 408 MHz 661#if defined(CONFIG_DRAM_336) 662 ldr r1, =0x00002323 663#endif 664 tst r2, #0x01 665 moveq r1, r1, lsr #8 666 str r1, [r0] 667 668 ldr r0, =0x1e6e0120 669 mov r1, #0 670 str r1, [r0] 671 tst r2, #0x01 @ check AST2300 672 beq CBRDLL1_2300_Start 673 ldr r0, =0x1e6e207c @ check AST2400 revision A0 674 ldr r1, [r0] 675 mov r1, r1, lsr #16 676 and r1, r1, #0xFF 677 cmp r1, #0x0 678 beq CBRDLL1_2300_Start 679 b CBRDLL1_2400_Start 680MCLK2X_Phase_CBR_Done_DDR3: 681 ldr r0, =0x1e6e0018 682 ldr r1, [r0] 683 orr r1, r1, #0x40 684 str r1, [r0] 685 686 ldr r0, =0x1e6e0034 687 ldr r1, =0x00000001 688 str r1, [r0] 689 690 ldr r0, =0x1e6e000c 691 ldr r1, =0x00000040 692 str r1, [r0] 693 694 /* Delay about 400us */ 695 ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us 696 init_delay_timer 697delay3_4: 698 check_delay_timer 699 bne delay3_4 700 clear_delay_timer 701 /* end delay 400us */ 702 703 /* Check DRAM CL Timing by H/W Trapping */ 704 ldr r0, =0x1e6e2070 705 ldr r1, [r0] 706 bic r1, r1, #0xF9FFFFFF 707 mov r2, r1, lsr #21 @ Set CL 708 ldr r1, =0x00000010 709 add r2, r2, r1 710 ldr r1, [r0] 711 bic r1, r1, #0xFBFFFFFF 712 mov r1, r1, lsr #7 @ Set CWL 713 orr r2, r2, r1 714 715 ldr r0, =0x1e6e002c @ REG_MRS 716 ldr r1, =0x04001700 @ 408 MHz 717#if defined(CONFIG_DRAM_336) 718 ldr r1, =0x04001500 719#endif 720 orr r1, r1, r2 721 str r1, [r0] 722 723 ldr r0, =0x1e6e0030 @ REG_EMRS 724 ldr r1, =0x00000000 @ 408 MHz 725#if defined(CONFIG_DRAM_336) 726 ldr r1, =0x00000000 727#endif 728 str r1, [r0] 729 730 ldr r0, =0x1e6e0028 @ Set EMRS2 731 ldr r1, =0x00000005 732 str r1, [r0] 733 734 ldr r0, =0x1e6e0028 @ Set EMRS3 735 ldr r1, =0x00000007 736 str r1, [r0] 737 738 ldr r0, =0x1e6e0028 @ Set EMRS 739 ldr r1, =0x00000003 740 str r1, [r0] 741 742 ldr r0, =0x1e6e0028 @ Set MRS 743 ldr r1, =0x00000001 744 str r1, [r0] 745 746 ldr r0, =0x1e6e002c @ REG_MRS 747 ldr r1, =0x04001600 @ 408 MHz 748#if defined(CONFIG_DRAM_336) 749 ldr r1, =0x04001400 750#endif 751 orr r1, r1, r2 752 str r1, [r0] 753 754 ldr r0, =0x1e6e000c @ Refresh 8 times 755 ldr r1, =0x00005C48 756 str r1, [r0] 757 758 ldr r0, =0x1e6e0028 @ Set MRS 759 ldr r1, =0x00000001 760 str r1, [r0] 761 762 ldr r0, =0x1e6e000c @ Set refresh cycle 763 ldr r1, =0x00002001 764 str r1, [r0] 765 766 ldr r0, =0x1e6e0014 767 ldr r1, [r0] 768 bic r1, r1, #0xFFF9FFFF 769 mov r2, r1, lsr #3 @ get CL 770 771 ldr r0, =0x1e6e0034 @ REG_PWC 772 ldr r1, =0x00000303 @ 408 MHz 773#if defined(CONFIG_DRAM_336) 774 ldr r1, =0x00000303 775#endif 776 orr r1, r1, r2 777 str r1, [r0] 778 779 b Calibration_Start 780.LTORG 781/****************************************************************************** 782 End DDR3 Init 783 ******************************************************************************/ 784 785/****************************************************************************** 786 DDR2 Init 787 788 tRCD = 15 ns 789 tRAS = 45 ns 790 tRRD = 10 ns 791 tRP = 15 ns 792 tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit 793 tRTP = 7.5 ns 794 tWR = 15 ns 795 tXSNR = 200 ns 796 tWTR = 7.5 ns 797 tFAW = 50 ns 798 tMRD = 4 CK 799 ******************************************************************************/ 800ddr2_init: 801/* Debug - UART console message */ 802 ldr r0, =0x1e784000 803 mov r1, #0x32 @ '2' 804 str r1, [r0] 805 mov r1, #0x0D @ '\r' 806 str r1, [r0] 807 mov r1, #0x0A @ '\n' 808 str r1, [r0] 809/* Debug - UART console message */ 810 811 ldr r0, =0x1e6e0004 812 ldr r1, =0x00000521 @ Default set to 1Gbit 813 str r1, [r0] 814 815 ldr r0, =0x1e6e0010 @ REG_AC1 816 ldr r1, =0x33302714 @ 408 MHz 817#if defined(CONFIG_DRAM_336) 818 ldr r1, =0x22201613 819#endif 820 str r1, [r0] 821 822 /* Check DRAM CL Timing by H/W Trapping */ 823 ldr r0, =0x1e6e2070 824 ldr r1, [r0] 825 bic r1, r1, #0xF9FFFFFF 826 mov r2, r1, lsr #5 @ Set CL 827 mov r1, r2, lsr #4 @ Set CWL 828 orr r2, r2, r1 829 ldr r1, =0x00110000 830 add r2, r2, r1 831 832 ldr r0, =0x1e6e0014 @ REG_AC2 833 ldr r1, =0xCC00B03F @ 408 MHz 834#if defined(CONFIG_DRAM_336) 835 ldr r1, =0xAA00903B 836#endif 837 orr r1, r1, r2 838 str r1, [r0] 839 840 ldr r0, =0x1e6e0004 @ check 2400 mode 841 ldr r2, [r0] 842 mov r2, r2, lsr #10 843 844 ldr r0, =0x1e6e006c @ REG_IOZ 845 ldr r1, =0x00002323 @ 408 MHz 846#if defined(CONFIG_DRAM_336) 847 ldr r1, =0x00002323 848#endif 849 tst r2, #0x01 850 moveq r1, r1, lsr #8 851 str r1, [r0] 852 853 ldr r0, =0x1e6e0120 854 mov r1, #1 855 str r1, [r0] 856 tst r2, #0x01 @ check AST2300 857 beq CBRDLL1_2300_Start 858 ldr r0, =0x1e6e207c @ check AST2400 revision A0 859 ldr r1, [r0] 860 mov r1, r1, lsr #16 861 and r1, r1, #0xFF 862 cmp r1, #0x0 863 beq CBRDLL1_2300_Start 864 b CBRDLL1_2400_Start 865MCLK2X_Phase_CBR_Done_DDR2: 866 867 ldr r0, =0x1e6e0034 868 ldr r1, =0x00000001 869 str r1, [r0] 870 871 ldr r0, =0x1e6e000c 872 ldr r1, =0x00000000 873 str r1, [r0] 874 875 /* Delay about 400us */ 876 ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us 877 init_delay_timer 878delay2_4: 879 check_delay_timer 880 bne delay2_4 881 clear_delay_timer 882 /* end delay 400us */ 883 884 /* Check DRAM CL Timing by H/W Trapping */ 885 ldr r0, =0x1e6e2070 886 ldr r1, [r0] 887 bic r1, r1, #0xF9FFFFFF 888 mov r2, r1, lsr #21 @ Set CL 889 ldr r1, =0x00000040 890 orr r2, r2, r1 891 892 ldr r0, =0x1e6e002c @ REG_MRS 893 ldr r1, =0x00000D02 @ 408 MHz 894#if defined(CONFIG_DRAM_336) 895 ldr r1, =0x00000B02 896#endif 897 orr r1, r1, r2 898 str r1, [r0] 899 900 ldr r0, =0x1e6e0030 @ REG_EMRS 901 ldr r1, =0x00000040 @ 408 MHz 902#if defined(CONFIG_DRAM_336) 903 ldr r1, =0x00000040 904#endif 905 str r1, [r0] 906 907 ldr r0, =0x1e6e0028 @ Set EMRS2 908 ldr r1, =0x00000005 909 str r1, [r0] 910 911 ldr r0, =0x1e6e0028 @ Set EMRS3 912 ldr r1, =0x00000007 913 str r1, [r0] 914 915 ldr r0, =0x1e6e0028 @ Set EMRS 916 ldr r1, =0x00000003 917 str r1, [r0] 918 919 ldr r0, =0x1e6e0028 @ Set MRS 920 ldr r1, =0x00000001 921 str r1, [r0] 922 923 ldr r0, =0x1e6e000c @ Refresh 8 times 924 ldr r1, =0x00005C08 925 str r1, [r0] 926 927 ldr r0, =0x1e6e002c @ REG_MRS 928 ldr r1, =0x00000C02 @ 408 MHz 929#if defined(CONFIG_DRAM_336) 930 ldr r1, =0x00000A02 931#endif 932 orr r1, r1, r2 933 str r1, [r0] 934 935 ldr r0, =0x1e6e0028 @ Set MRS 936 ldr r1, =0x00000001 937 str r1, [r0] 938 939 ldr r0, =0x1e6e0030 @ REG_EMRS 940 ldr r1, =0x000003C0 @ 408 MHz 941#if defined(CONFIG_DRAM_336) 942 ldr r1, =0x000003C0 943#endif 944 str r1, [r0] 945 946 ldr r0, =0x1e6e0028 @ Set EMRS 947 ldr r1, =0x00000003 948 str r1, [r0] 949 950 ldr r0, =0x1e6e0030 @ REG_EMRS 951 ldr r1, =0x00000040 @ 408 MHz 952#if defined(CONFIG_DRAM_336) 953 ldr r1, =0x00000040 954#endif 955 str r1, [r0] 956 957 ldr r0, =0x1e6e0028 @ Set EMRS 958 ldr r1, =0x00000003 959 str r1, [r0] 960 961 ldr r0, =0x1e6e000c @ Set refresh cycle 962 ldr r1, =0x00002001 963 str r1, [r0] 964 965 ldr r0, =0x1e6e0014 966 ldr r1, [r0] 967 bic r1, r1, #0xFFF9FFFF 968 mov r2, r1, lsr #3 @ get CL 969 970 ldr r0, =0x1e6e0034 @ REG_PWC 971 ldr r1, =0x00000503 @ 408 MHz 972#if defined(CONFIG_DRAM_336) 973 ldr r1, =0x00000503 974#endif 975 orr r1, r1, r2 976 str r1, [r0] 977 978 b Calibration_Start 979.LTORG 980/****************************************************************************** 981 End DDR2 Init 982 ******************************************************************************/ 983/****************************************************************************** 984 DDR CK duty finetune program 985 SRAM buffer definition 986 0x1E720204 : gdll golden DLL1 record 987 0x1E720208 : gduty golden duty setting record 988 0x1E72020C : gdutysum golden duty data record 989 0x1E720210 : duty record of delay 0 invert 990 0x1E720214 : duty record of delay 1 invert 991 .... 992 0x1E72024C : duty record of delay 15 invert 993 0x1E720250 : duty record of delay 0 994 0x1E720254 : duty record of delay 1 995 .... 996 0x1E72028C : duty record of delay 15 997 998 Register usage 999 r0 - r3 = free 1000 r4 = record the return pc value, do not use 1001 r5 = free 1002 r6 = free 1003 r7 = duty count 1004 r8 = gdll 1005 r9 = gduty 1006 r10 = gdutysum 1007 ******************************************************************************/ 1008CBRDLL1_2400_Start: 1009 ldr r0, =0x1e6e0120 1010 ldr r1, [r0] 1011 orr r1, r1, #0x02 1012 str r1, [r0] 1013 1014 ldr r1, =0x00000000 1015 ldr r0, =0x1e720204 1016 ldr r2, =0x1e7202a0 1017init_sram_start0: 1018 str r1, [r0] 1019 add r0, r0, #4 1020 cmp r0, r2 1021 blt init_sram_start0 1022 1023 ldr r0, =0x1e6e0034 1024 mov r1, #0x20 1025 str r1, [r0] 1026 1027 ldr r0, =0x1e6e0060 1028 ldr r1, [r0] 1029 mov r2, #0x01 1030 orr r1, r1, r2, lsl #13 1031 str r1, [r0] 1032 1033 mov r7, #0x0 @ init duty count 1034 mov r8, #0x0 @ init gdll 1035 mov r9, #0x0 @ init gduty 1036 mov r10, #0x0 @ init gdutysum 1037cbrdll1_duty_start: 1038 cmp r7, #32 1039 bge cbrdll1_duty_end 1040 1041 ldr r0, =0x1e6e0018 1042 ldr r1, =0x00008120 1043 str r1, [r0] 1044 1045 ldr r0, =0x1e6e0060 1046 ldr r1, [r0] 1047 bic r1, r1, #0x00001F00 1048 orr r1, r1, r7, lsl #8 1049 mov r2, #0x10 1050 eor r1, r1, r2, lsl #8 1051 str r1, [r0] 1052 1053 ldr r0, =0x1e6e0000 @ dummy read 1054 ldr r1, [r0] 1055 1056 b CBRDLL1_2300_Start 1057CBRDLL1_2400_Call: 1058 1059 mov r5, #0x01 @ init dqidly count 1060 mov r6, #0x00 @ init duty sum 1061cbrdll1_duty_cal_start: 1062 cmp r5, #0x05 1063 bge cbrdll1_duty_cal_end 1064 1065 ldr r0, =0x1e6e0018 1066 ldr r1, =0x00200120 1067 orr r1, r1, r5, lsl #16 1068 str r1, [r0] 1069 1070 ldr r0, =0x1e6e0000 1071 ldr r1, [r0] 1072 1073 ldr r0, =0x1e6e0018 1074 ldr r1, [r0] 1075 mov r2, #0x10 1076 orr r1, r1, r2, lsl #24 1077 str r1, [r0] 1078 1079 ldr r0, =0x1e6e0080 1080 ldr r1, =0x80000000 @ init duty cal waiting 1081cbrdll1_duty_cal_wait: 1082 ldr r2, [r0] 1083 tst r2, r1 1084 beq cbrdll1_duty_cal_wait 1085 1086 ldr r0, =0x1e6e008c 1087 ldr r2, [r0] 1088 1089 ldr r0, =0x1e720210 1090 add r0, r0, r7, lsl #2 1091 str r2, [r0] 1092 1093 ldr r1, =0xFFFF 1094 and r3, r1, r2 1095 cmp r3, r1 1096 moveq r2, r2, lsr #16 1097 and r3, r1, r2 1098 add r6, r6, r3 1099 ldr r1, =0xF000 1100 cmp r3, r1 1101 blt cbrdll1_duty_cal_end 1102 add r5, r5, #0x01 1103 b cbrdll1_duty_cal_start 1104 1105cbrdll1_duty_cal_end: 1106 mov r6, r6, lsr #2 @ get dutysum 1107 cmp r6, r10 @ check dutysum > gdutysum 1108 ble cbrdll1_duty_next 1109 ldr r0, =0x1e6e0068 1110 ldr r8, [r0] 1111 eor r9, r7, #0x10 1112 mov r10, r6 1113 1114cbrdll1_duty_next: 1115 add r7, r7, #0x01 1116 cmp r7, #16 @ check duty >= 15 1117 blt cbrdll1_duty_start 1118 ldr r0, =0xFA00 @ check gdutysum > 0xFA00 1119 cmp r10, r0 1120 blt cbrdll1_duty_start 1121 1122cbrdll1_duty_end: 1123 ldr r0, =0x1e6e0060 1124 ldr r1, [r0] 1125 bic r1, r1, #0x00001F00 1126 orr r1, r1, r9, lsl #8 1127 str r1, [r0] 1128 1129 ldr r0, =0x1e6e0068 1130 bic r8, r8, #0xFF000000 1131 bic r8, r8, #0x00FF0000 1132 str r8, [r0] 1133 1134 ldr r0, =0x1e720204 @ record result 1135 str r8, [r0] 1136 add r0, r0, #0x04 1137 str r9, [r0] 1138 add r0, r0, #0x04 1139 str r10, [r0] 1140 1141 ldr r0, =0x1e6e0018 1142 ldr r1, =0x00008120 1143 str r1, [r0] 1144 ldr r0, =0x1e6e0000 @ dummy read 1145 ldr r1, [r0] 1146 ldr r0, =0x1e6e0018 1147 ldr r1, =0x00000120 1148 str r1, [r0] 1149 1150 ldr r0, =0x1e6e0120 1151 ldr r1, [r0] 1152 cmp r1, #0x3 1153 beq MCLK2X_Phase_CBR_Done_DDR2 1154 b MCLK2X_Phase_CBR_Done_DDR3 1155 1156/****************************************************************************** 1157 MCLK2X lock to MCLK program 1158 r0 - r3 = free 1159 r5 = madjmax 1160 r6 = dllend 1161 0x1E720200 = 0x96cnt:failcnt:dllmax:dllmin 1162 ******************************************************************************/ 1163CBRDLL1_2300_Start: 1164 ldr r0, =0x1e6e0064 1165 ldr r5, [r0] 1166 and r5, r5, #0xFF @ init madjmax 1167 mov r6, r5 @ init dllend 1168 1169 ldr r1, =0x000000ff 1170 ldr r0, =0x1e720200 1171 str r1, [r0] @ init dllcnt2:dllmax:dllmin 1172 1173 mov r3, #0x0 @ init loop count 1174cbrdll1_scan_start: 1175 cmp r3, r6 1176 bge cbrdll1_scan_end 1177 1178 ldr r0, =0x1e6e0018 1179 ldr r1, =0x00008120 1180 str r1, [r0] 1181 1182 ldr r0, =0x1e6e0068 1183 mov r1, r3 1184 cmp r1, r5 1185 subge r1, r1, r5 1186 str r1, [r0] 1187 1188 ldr r0, =0x1e6e0000 @ dummy read 1189 ldr r1, [r0] 1190 1191 ldr r0, =0x1e6e0018 1192 ldr r1, =0x00000120 1193 str r1, [r0] 1194 1195 ldr r0, =0x1e6e0000 @ dummy read 1196 ldr r1, [r0] 1197 ldr r0, =0x1e6e0000 @ dummy read 1198 ldr r1, [r0] 1199 1200 ldr r0, =0x1e6e001c 1201 ldr r1, [r0] 1202 mov r1, r1, lsr #16 1203 and r1, r1, #0xFF 1204 1205 and r2, r1, #0x96 1206 cmp r2, #0x96 1207 beq cbrdll1_scan_pass @ if (mclk2x_phase & 0x96) == 0x96 1208 ldr r0, =0x1e720200 1209 ldr r1, [r0] 1210 mov r2, r1, lsr #8 1211 ands r2, r2, #0xFF @ get dllmax 1212 beq cbrdll1_scan_next @ if dllmax == 0 1213 mov r2, r1, lsr #16 1214 and r2, r2, #0xFF 1215 add r2, r2, #0x01 1216 cmp r2, #0x02 1217 movge r6, r3 1218 bic r1, r1, #0x00FF0000 1219 orr r1, r1, r2, lsl #16 1220 str r1, [r0] 1221 b cbrdll1_scan_next 1222 1223cbrdll1_scan_pass: 1224 cmp r3, #0x0 @ if dll = 0 1225 moveq r3, #0x0F 1226 addeq r6, r6, #0x10 1227 beq cbrdll1_scan_next 1228 ldr r0, =0x1e720200 1229 ldr r2, [r0] 1230 cmp r1, #0x96 1231 bne cbrdll1_scan_pass2 1232 mov r1, r2, lsr #24 1233 add r1, r1, #0x01 1234 bic r2, r2, #0xFF000000 1235 orr r2, r2, r1, lsl #24 1236 cmp r1, #0x03 @ check (phase == 0x96) count == 3 1237 bicge r2, r2, #0x0000FF00 1238 bicge r2, r2, #0x000000FF 1239 orrge r2, r2, r3, lsl #8 1240 orrge r2, r2, r3 1241 str r2, [r0] 1242 bge cbrdll1_scan_end 1243 1244cbrdll1_scan_pass2: 1245 and r1, r2, #0xFF @ if(dllmin > dll) 1246 cmp r1, r3 1247 bicgt r2, r2, #0x000000FF 1248 orrgt r2, r2, r3 1249 1250 mov r1, r2, lsr #8 @ if(dllmax < dll) 1251 and r1, r1, #0xFF 1252 cmp r1, r3 1253 biclt r2, r2, #0x0000FF00 1254 orrlt r2, r2, r3, lsl #8 1255 1256 bic r2, r2, #0x00FF0000 1257 str r2, [r0] 1258 1259cbrdll1_scan_next: 1260 add r3, r3, #0x01 1261 b cbrdll1_scan_start 1262 1263cbrdll1_scan_end: 1264 ldr r0, =0x1e720200 1265 ldr r1, [r0] 1266 mov r2, r1, lsr #8 @ get dllmax 1267 ands r2, r2, #0xFF 1268 bne cbrdll1_scan_done @ if(dllmax != 0) 1269 ldr r0, =0x1e6e0064 1270 ldr r3, [r0] 1271 bic r1, r3, #0x000C0000 1272 str r1, [r0] 1273 add r0, r0, #0x04 1274 mov r1, #0x0 1275 str r1, [r0] 1276 1277 /* Delay about 10us */ 1278 ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us 1279 init_delay_timer 1280delay0_1: 1281 check_delay_timer 1282 bne delay0_1 1283 clear_delay_timer 1284 /* end delay 10us */ 1285 1286 ldr r0, =0x1e6e0064 1287 str r3, [r0] 1288 1289 /* Delay about 10us */ 1290 ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us 1291 init_delay_timer 1292delay0_2: 1293 check_delay_timer 1294 bne delay0_2 1295 clear_delay_timer 1296 /* end delay 10us */ 1297 1298 b CBRDLL1_2300_Start 1299 1300cbrdll1_scan_done: 1301 and r1, r1, #0xFF 1302 add r1, r1, r2 1303 mov r6, r1, lsr #1 @ dll1.0 = (dllmin + dllmax) >> 1 1304 cmp r6, r5 1305 subge r6, r6, r5 1306 add r3, r6, r5, lsr #2 @ dll1.1 = dll1.0 + (MADJ >> 2) 1307 1308 ldr r0, =0x1e6e0004 1309 ldr r1, [r0] 1310 mov r1, r1, lsr #10 1311 tst r1, #0x1 1312 bne cbrdll1_scan_set_2400 1313 cmp r3, r5 1314 subge r3, r3, r5 1315 mov r2, #0x0 1316 tst r3, #0x08 1317 beq cbrdll1_scan_set_2300_2 @ if !(dll & 8) 1318cbrdll1_scan_set_2300_1: @ if (dll & 8) 1319 mov r1, #0x0 1320 tst r3, #0x08 1321 addeq r1, r1, #0x01 1322 cmp r2, #0x05 1323 addge r1, r1, #0x01 1324 cmp r1, #0x02 1325 beq cbrdll1_scan_set 1326 add r2, r2, #0x01 1327 add r3, r3, #0x01 1328 cmp r3, r5 1329 subge r3, r3, r5 1330 b cbrdll1_scan_set_2300_1 1331 1332cbrdll1_scan_set_2300_2: 1333 and r1, r3, #0x07 1334 cmp r1, #0x07 1335 beq cbrdll1_scan_set 1336 cmp r2, #0x05 1337 bge cbrdll1_scan_set 1338 add r2, r2, #0x01 1339 add r3, r3, #0x01 1340 cmp r3, r5 1341 subge r3, r3, r5 1342 b cbrdll1_scan_set_2300_2 1343 1344cbrdll1_scan_set_2400: 1345 add r3, r3, #0x05 @ dll1.1 = dll1.0 + (MADJ >> 2) + 5 1346 cmp r3, r5 1347 subge r3, r3, r5 1348 1349cbrdll1_scan_set: 1350 orr r1, r6, r3, lsl #8 1351 ldr r0, =0x1e6e0068 1352 str r1, [r0] 1353 1354 ldr r0, =0x1e6e0120 1355 ldr r1, [r0] 1356 cmp r1, #0x0 1357 beq MCLK2X_Phase_CBR_Done_DDR3 1358 cmp r1, #0x1 1359 beq MCLK2X_Phase_CBR_Done_DDR2 1360 b CBRDLL1_2400_Call 1361 1362.LTORG 1363 1364/****************************************************************************** 1365 Calibration Code Start 1366 SRAM buffer definition 1367 0x1E720000 : Pass 1, DLLI MIN value range 1368 0x1E720008 : DQS0 DLL valid range, 2nd time CBR 1369 0x1E72000C : DQS1 DLL valid range, 2nd time CBR 1370 0x1E720010 : DQ0 DLL valid range, Pass 1 1371 0x1E720014 : DQ1 DLL valid range, Pass 1 1372 .... 1373 0x1E720048 : DQ14 DLL valid range, Pass 1 1374 0x1E72004C : DQ15 DLL valid range, Pass 1 1375 0x1E720090 : DLL1 SAdj record 1376 0x1E720094 : DQL Pass1 finetune result 1377 0x1E720098 : DQH Pass1 finetune result 1378 0x1E72009C : DRAM initial time, (us) 1379 0x1E7200A0 : CBR3 retry counter 1380 0x1E7200A4 : DRAM initial time, (us) 1381 0x1E7200A8 : Released date 1382 0x1E7200AC : Released SDK version 1383 0x1E7200B0 : DQS input mask window for MCR18[4] = 0 1384 0x1E7200B4 : DQS input mask window for MCR18[4] = 1 1385 0x1E720100 : DQIDLY=00, DLL valid range 1386 0x1E720104 : DQIDLY=01, DLL valid range 1387 .... 1388 0x1E720178 : DQIDLY=30, DLL valid range 1389 0x1E72017C : DQIDLY=31, DLL valid range 1390 0x1E720180 : DQSI-MCLK2X P-phase pass record DLL2= 0-31 1391 0x1E720184 : DQSI-MCLK2X P-phase pass record DLL2=32-63 1392 0x1E720188 : DQSI-MCLK2X N-phase pass record DLL2= 0-31 1393 0x1E72018C : DQSI-MCLK2X N-phase pass record DLL2=32-63 1394 ******************************************************************************/ 1395Calibration_Start_pre: @ Toggle DQSI mask delay 1396 ldr r0, =0x1e6e0018 1397 ldr r1, [r0] 1398 eor r1, r1, #0x10 1399 str r1, [r0] 1400 1401Calibration_Start: 1402/* Init SRAM buffer */ 1403 ldr r1, =0x000000ff 1404 ldr r0, =0x1e720000 1405 ldr r2, =0x1e720100 1406init_sram_start: 1407 str r1, [r0] 1408 add r0, r0, #4 1409 cmp r0, r2 1410 blt init_sram_start 1411 1412 ldr r1, =0x00ff00ff 1413 ldr r0, =0x1e720100 1414 ldr r2, =0x1e720180 1415init_sram_start2: 1416 str r1, [r0] 1417 add r0, r0, #4 1418 cmp r0, r2 1419 blt init_sram_start2 1420 1421 ldr r1, =0x00000000 1422 ldr r0, =0x1e720180 1423 ldr r2, =0x1e720200 1424init_sram_start3: 1425 str r1, [r0] 1426 add r0, r0, #4 1427 cmp r0, r2 1428 blt init_sram_start3 1429 1430 ldr r0, =0x1e6e0068 @ save the DLL1 SAdj initial value 1431 ldr r1, [r0] 1432 ldr r0, =0x1e720090 1433 str r1, [r0] 1434 1435/* Start 1436 r0 = free 1437 r1 = free 1438 r2 = free 1439 r3 = free 1440 r4 = record the return pc value, do not use 1441 r5 = pattern table index 1442 r6 = pass count 1443 r7 = dram DLL2 parameter index (0x1e6e0068), max is 0x4C 1444*/ 1445/****************************************************************************** 1446 Fine DQI delay and DQSI-MCLK phase 1447 r8 = DQIDLY count 1448 r9 = DQSI-MCLK2X phase count 1449 r10 = pattern fail retry counter, initialize to 2 (fail 2 times) 1450 r11 = passcnt accumulator for each DQIDLY 1451 *****************************************************************************/ 1452CBR0_START: 1453/* Debug - UART console message */ 1454 ldr r0, =0x1e784000 1455 mov r1, #0x43 @ 'C' 1456 str r1, [r0] 1457 mov r1, #0x42 @ 'B' 1458 str r1, [r0] 1459 mov r1, #0x52 @ 'R' 1460 str r1, [r0] 1461 mov r1, #0x30 @ '0' 1462 str r1, [r0] 1463 mov r1, #0x2D @ '-' 1464 str r1, [r0] 1465/* Debug - UART console message */ 1466 1467 ldr r0, =0x1e6e0018 1468 ldr r1, [r0] 1469 bic r1, r1, #0xFF000000 1470 bic r1, r1, #0x00FF0000 1471 str r1, [r0] 1472 1473 ldr r0, =0x1e6e0074 @ set the testing DRAM size = 1KB 1474 ldr r1, =0x000003FF 1475 str r1, [r0] 1476 1477 mov r8, #0x00 @ init DQIDLY 1478 mov r9, #0x00 @ init DQSI-MCLK2X phase 1479 mov r11, #0x01 @ init passcnt accumulator 1480 1481cbr0_next_dqidly: 1482 cmp r9, #0x00 1483 bne cbr0_next_dqsiphase 1484 cmp r11, #0x00 1485 addeq r8, r8, #0x01 @ jump 1 stage if no pass at previous stage 1486 mov r11, #0x00 1487 add r8, r8, #0x01 1488 cmp r8, #0x1F @ max DQIDLY = 31 1489 bgt CBR0_END 1490 1491/* Debug - UART console message */ 1492 ldr r0, =0x1e784000 1493 and r1, r8, #0x07 1494 add r1, r1, #0x30 @ '0-7' 1495 str r1, [r0] 1496/* Debug - UART console message */ 1497 1498 ldr r0, =0x1e6e0018 1499 ldr r1, [r0] 1500 bic r1, r1, #0x00FF0000 1501 orr r1, r1, r8, lsl #16 1502 str r1, [r0] 1503 mov r9, #0x01 @ '1':p_phase, '0':n_phase 1504 1505 /* Delay about 3us */ @ wait DQIDLY load 1506 ldr r2, =0x00000003 @ Set Timer4 Reload = 3 us 1507 init_delay_timer 1508delay_4: 1509 check_delay_timer 1510 bne delay_4 1511 clear_delay_timer 1512 /* end delay 3us */ 1513 1514 b cbr0_dll2_scan_start 1515 1516cbr0_next_dqsiphase: 1517 ldr r0, =0x1e6e0018 1518 ldr r1, [r0] 1519 orr r1, r1, r9, lsl #23 @ set DQSI-MCLK2X phase 1520 str r1, [r0] 1521 mov r9, #0x00 1522 1523cbr0_dll2_scan_start: 1524 mov r6, #0x00 @ init pass count 1525 mov r7, #0x00 @ init DLL2 parameter index 1526 1527/**************************** 1528 DLL2 delay margin test loop 1529 ***************************/ 1530cbr0_next_dll2_parameter: 1531 ldr r0, =0x1e6e0068 @ load DLL2 parameter 1532 ldr r1, [r0] 1533 bic r1, r1, #0x00FF0000 1534 bic r1, r1, #0xFF000000 1535 orr r1, r1, r7, lsl #16 1536 str r1, [r0] 1537 ldr r2, =0x40404040 @ DLL2 max is 0x40404040 1538 cmp r7, r2 1539 bge cbr0_next_dqidly 1540 ldr r2, =0x01010101 1541 add r7, r7, r2 1542 1543/* CBRScan3() start */ 1544 adrl r5, PATTERN_TABLE @ init pattern table index 1545/**************************** 1546 Test pattern iteration loop 1547 ***************************/ 1548cbr0_next_test_pattern: 1549 mov r10, #2 @ set the retry loop = 2 of each pattern 1550 ldr r1, [r5] @ load test pattern 1551 ldr r0, =0x1e6e007c 1552 str r1, [r0] 1553 cmp r1, #0x00 @ the last data in pattern is 0x00 1554 bne cbr0_test_burst 1555 1556 and r3, r7, #0xFF 1557 sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 1558 cmp r3, #0x00 1559 beq cbr0_next_dqidly @ pass at dlli = 0, invalid 1560 add r6, r6, #0x01 @ increment pass count 1561 add r11, r11, #0x01 @ increment pass count 1562 1563 ldr r0, =0x1e720180 @ record DLL2 pass window 1564 cmp r9, #0x00 @ DQSI-MCLK2X phase check 1565 addeq r0, r0, #0x08 1566 cmp r3, #32 1567 addge r0, r0, #0x4 1568 and r1, r3, #0x1F 1569 mov r2, #0x1 1570 mov r2, r2, lsl r1 1571 ldr r1, [r0] 1572 orr r1, r1, r2 1573 str r1, [r0] 1574 1575 ldr r0, =0x1e720100 @ record DLL2 min:max value for each DQIDLY 1576 add r0, r0, r8, lsl #2 1577 cmp r9, #0x00 @ DQSI-MCLK2X phase check 1578 beq cbr0_test_pass_dqsin 1579 record_dll2_pass_range 1580 b cbr0_next_dll2_parameter 1581 1582cbr0_test_pass_dqsin: 1583 record_dll2_pass_range_h 1584 b cbr0_next_dll2_parameter 1585 1586cbr0_test_pattern_fail: 1587 cmp r6, #5 @ passcnt >= 5 1588 bge cbr0_next_dqidly 1589 ldr r0, =0x1e720100 @ reset DLL2 min:max value 1590 add r0, r0, r8, lsl #2 1591 ldr r1, [r0] 1592 ldr r2, =0xFFFF0000 1593 ldr r3, =0x000000FF 1594 cmp r9, #0x00 1595 moveq r2, r2, lsr #16 1596 moveq r3, r3, lsl #16 1597 and r1, r1, r2 1598 orr r1, r1, r3 1599 str r1, [r0] 1600 b cbr0_next_dll2_parameter @ CBRScan3() end and test result fail, go to next step 1601 1602/**************************** 1603 Test fail retry loop 1604 ***************************/ 1605cbr0_pattern_fail_retry: 1606 1607/* CBRTest3() start */ 1608cbr0_test_burst: 1609 ldr r0, =0x1e6e0070 1610 ldr r1, =0x00000000 1611 str r1, [r0] 1612 ldr r1, =0x000000C1 1613 str r1, [r0] 1614 ldr r3, =0x3000 1615cbr0_wait_engine_idle_0: 1616 ldr r2, [r0] 1617 tst r2, r3 @ D[12] = idle bit 1618 beq cbr0_wait_engine_idle_0 1619 1620 ldr r2, [r0] @ read fail bit status 1621 mov r1, #0x0 1622 str r1, [r0] 1623 mov r2, r2, lsr #13 @ D[13] = fail bit 1624 cmp r2, #0x00 1625 bne cbr0_test_fail 1626 1627cbr0_test_single: 1628 ldr r0, =0x1e6e0070 1629 ldr r1, =0x00000000 1630 str r1, [r0] 1631 ldr r1, =0x00000085 1632 str r1, [r0] 1633 ldr r3, =0x3000 1634cbr0_wait_engine_idle_1: 1635 ldr r2, [r0] 1636 tst r2, r3 @ D[12] = idle bit 1637 beq cbr0_wait_engine_idle_1 1638 1639 ldr r2, [r0] @ read fail bit status 1640 mov r1, #0x0 1641 str r1, [r0] 1642 mov r2, r2, lsr #13 @ D[13] = fail bit 1643 cmp r2, #0x00 1644 beq cbr0_test_pass 1645 1646/* CBRTest3() end */ 1647 1648cbr0_test_fail: 1649 subs r10, r10, #1 1650 bne cbr0_pattern_fail_retry 1651 b cbr0_test_pattern_fail @ CBRScan3() return(0) 1652 1653cbr0_test_pass: 1654 add r5, r5, #0x04 @ increase the test pattern index 1655 b cbr0_next_test_pattern 1656 1657CBR0_END: 1658 mov r5, #0x0 @ init DQIDLY search count 1659 mov r6, #0x0 @ init max_margin:g_margin 1660 mov r8, #0x0 @ init g_side 1661 mov r7, #0x0 @ init maximum margin DQIDLY,DQSI-MCLK2X phase 1662cbr0_search_dll_margin_s: 1663 ldr r0, =0x1e720100 1664 add r0, r0, r5, lsl #2 1665 ldr r1, [r0] 1666 and r2, r1, #0xFF @ get dllmin_p 1667 mov r1, r1, lsr #8 1668 and r3, r1, #0xFF @ get dllmax_p 1669 subs r2, r3, r2 @ get margin-P 1670 movmi r2, #0x0 1671 mov r1, r1, lsr #8 1672 and r3, r1, #0xFF @ get dllmin_n 1673 mov r1, r1, lsr #8 1674 and r1, r1, #0xFF @ get dllmax_n 1675 subs r3, r1, r3 @ get margin-N 1676 movmi r3, #0x0 1677 add r1, r2, r3 1678 cmp r1, #0x0 1679 beq cbr0_search_dll_margin_e @ if margin-P = 0 && margin-N = 0 1680 1681 ldr r9, [r0] 1682 ldr r0, =0x1e720180 1683 cmp r2, r3 1684 orrlt r5, r5, #0x80 @ margin-N > margin-P 1685 addlt r0, r0, #0x08 1686 movlt r9, r9, lsr #16 1687 movge r3, r2 @ max(margin-P/N) 1688 add r2, r3, #0x2 @ define +/- 2 steps of variation 1689 mov r1, r6, lsr #16 1690 cmp r2, r1 1691 blt cbr0_search_dll_margin_e @ if max(margin-P/N) + 2 < max_margin 1692 1693 and r1, r9, #0xFF @ r1 = dlli counter 1694 cmp r1, #32 1695 ldrge r2, [r0, #0x4] @ load pass window 1696 ldrlt r2, [r0] 1697 and r1, r1, #0x1F 1698 mov r10, #0x1 @ init test bit mask 1699 mov r10, r10, lsl r1 1700 and r1, r9, #0xFF 1701cbr0_search_dllmin_margin_s: 1702 tst r2, r10 1703 beq cbr0_search_dllmin_margin_e 1704 mov r10, r10, lsr #1 1705 cmp r1, #32 1706 ldreq r2, [r0] 1707 ldreq r10, =0x80000000 1708 subs r1, r1, #0x1 1709 bne cbr0_search_dllmin_margin_s 1710 1711cbr0_search_dllmin_margin_e: 1712 and r2, r9, #0xFF 1713 sub r11, r2, r1 @ get dllmin side margin 1714 1715 mov r9, r9, lsr #8 1716 and r1, r9, #0xFF @ r1 = dlli counter 1717 cmp r1, #32 1718 ldrge r2, [r0, #0x4] @ load pass window 1719 ldrlt r2, [r0] 1720 and r1, r1, #0x1F 1721 mov r10, #0x1 @ init test bit mask 1722 mov r10, r10, lsl r1 1723 and r1, r9, #0xFF 1724cbr0_search_dllmax_margin_s: 1725 tst r2, r10 1726 beq cbr0_search_dllmax_margin_e 1727 mov r10, r10, lsl #1 1728 cmp r1, #31 1729 ldreq r2, [r0, #0x4] 1730 ldreq r10, =0x00000001 1731 add r1, r1, #0x1 1732 cmp r1, #64 1733 bne cbr0_search_dllmax_margin_s 1734 1735cbr0_search_dllmax_margin_e: 1736 and r2, r9, #0xFF 1737 sub r1, r1, r2 @ get dllmax side margin 1738 cmp r1, r11 1739 movlt r11, r1 @ get side_margin 1740 1741cbr0_check_dll_margin: @ if max(margin-P/N) > g_margin && side_margin >= g_side && dqidly <= 20 1742 cmp r5, #20 1743 bgt cbr0_check_dll_margin2 1744 and r1, r6, #0xFF 1745 cmp r3, r1 1746 ble cbr0_check_dll_margin3 1747 cmp r11, r8 1748 bge cbr0_set_dll_margin 1749 1750cbr0_check_dll_margin2: @ if max(margin-P/N) > g_margin+1 && side_margin >= g_side) 1751 and r1, r6, #0xFF 1752 add r2, r1, #0x1 1753 cmp r3, r2 1754 ble cbr0_check_dll_margin3 1755 cmp r11, r8 1756 bge cbr0_set_dll_margin 1757 1758cbr0_check_dll_margin3: @ if side_margin > g_side && g_side < 8 1759 cmp r8, #8 1760 bge cbr0_search_dll_margin_e 1761 cmp r11, r8 1762 ble cbr0_search_dll_margin_e 1763 1764cbr0_set_dll_margin: 1765 mov r1, r6, lsr #16 1766 cmp r3, r1 1767 bicgt r6, r6, #0x00FF0000 1768 orrgt r6, r6, r3, lsl #16 1769 bic r6, r6, #0x000000FF 1770 orr r6, r6, r3 1771 mov r7, r5 1772 mov r8, r11 1773 1774cbr0_search_dll_margin_e: 1775 and r5, r5, #0x7F 1776 add r5, r5, #0x01 1777 cmp r5, #0x20 @ last DQIDLY 1778 blt cbr0_search_dll_margin_s 1779 1780 ldr r0, =0x1e6e0018 1781 ldr r1, [r0] 1782 bic r1, r1, #0x00FF0000 1783 orr r1, r1, r7, lsl #16 1784 str r1, [r0] 1785 1786 ldr r0, =0x1e6e0068 1787 ldr r1, [r0] 1788 bic r1, r1, #0x00FF0000 1789 bic r1, r1, #0xFF000000 1790 str r1, [r0] 1791 1792 /* Delay about 5us */ 1793 ldr r2, =0x00000005 @ Set Timer5 Reload = 5 us 1794 init_delay_timer 1795delay_5: 1796 check_delay_timer 1797 bne delay_5 1798 clear_delay_timer 1799 /* end delay 5us */ 1800 1801 ldr r0, =0x1e6e000c @ Set refresh cycle 1802 ldr r1, =0x00005C01 1803 str r1, [r0] 1804 1805/****************************************************************************** 1806 Fine tune per bit DQ input delay -- Pass 1, left edge align 1807 r8 = free 1808 r9 = DQ fail bit accumulator 1809 r10 = pattern fail counter, initialize to 5 (fail 5 times) 1810 r11 = free 1811 *****************************************************************************/ 1812CBR1_START: 1813/* Debug - UART console message */ 1814 ldr r0, =0x1e784000 1815 mov r1, #0x0D @ '\r' 1816 str r1, [r0] 1817 mov r1, #0x0A @ '\n' 1818 str r1, [r0] 1819 mov r1, #0x43 @ 'C' 1820 str r1, [r0] 1821 mov r1, #0x42 @ 'B' 1822 str r1, [r0] 1823 mov r1, #0x52 @ 'R' 1824 str r1, [r0] 1825 mov r1, #0x31 @ '1' 1826 str r1, [r0] 1827/* Debug - UART console message */ 1828 1829 mov r6, #0x00 @ init pass count 1830 mov r7, #0x00 @ init DLL2 parameter index 1831 1832/**************************** 1833 DLL2 delay margin test loop 1834 ***************************/ 1835cbr1_next_dll2_parameter: 1836 ldr r0, =0x1e6e0068 @ load DLL2 parameter 1837 ldr r1, [r0] 1838 bic r1, r1, #0x00FF0000 1839 bic r1, r1, #0xFF000000 1840 orr r1, r1, r7, lsl #16 1841 str r1, [r0] 1842 ldr r2, =0x40404040 @ parameter's max is to 0x40404040 1843 cmp r7, r2 1844 bge CBR1_END 1845 ldr r2, =0x01010101 1846 add r7, r7, r2 1847 1848 ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB 1849 ldr r1, =0x00000FFF 1850 str r1, [r0] 1851 1852/* CBRScan2() start */ 1853 ldr r9, =0xFFFF @ init test status 1854 adrl r5, PATTERN_TABLE @ init pattern table index 1855/**************************** 1856 Test pattern iteration loop 1857 ***************************/ 1858cbr1_next_test_pattern: 1859 mov r10, #5 @ set the retry loop of each pattern 1860 ldr r1, [r5] @ load test pattern 1861 ldr r0, =0x1e6e007c 1862 str r1, [r0] 1863 cmp r1, #0x00 @ the last data in pattern is 0x00 1864 bne cbr1_test_single 1865 1866cbr1_test_pattern_end: 1867 cmp r9, #0x00 1868 bne cbr1_test_pass_dqi 1869 cmp r6, #10 1870 bge CBR1_END 1871 b cbr1_next_dll2_parameter @ CBRScan2() end and test result fail, go to next step 1872 1873cbr1_test_pass_dqi: 1874 and r3, r7, #0xFF 1875 sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 1876 add r6, r6, #0x01 @ increment pass count 1877 ldr r0, =0x1e720010 1878 mov r8, #0x01 1879cbr1_test_pass_dqi_loop_s: 1880 tst r9, r8 1881 beq cbr1_test_pass_dqi_loop_e 1882 record_dll2_pass_range 1883 1884cbr1_test_pass_dqi_loop_e: 1885 add r0, r0, #0x04 1886 mov r8, r8, lsl #1 1887 ldr r1, =0xFFFF 1888 tst r8, r1 1889 bne cbr1_test_pass_dqi_loop_s 1890 b cbr1_next_dll2_parameter 1891 1892/**************************** 1893 Test fail retry loop 1894 ***************************/ 1895cbr1_pattern_fail_retry: 1896 1897/* CBRTest2() start */ 1898cbr1_test_single: 1899 ldr r0, =0x1e6e0070 1900 ldr r1, =0x00000000 1901 str r1, [r0] 1902 ldr r1, =0x00000005 1903 str r1, [r0] 1904 ldr r3, =0x1000 1905 ldr r1, =0x1000 1906cbr1_wait_engine_idle_0: 1907 subs r1, r1, #1 1908 beq cbr1_test_single_end 1909 ldr r2, [r0] 1910 tst r2, r3 @ D[12] = idle bit 1911 beq cbr1_wait_engine_idle_0 1912 1913cbr1_test_single_end: 1914 ldr r0, =0x1e6e0078 @ read fail bit status 1915 ldr r11, [r0] 1916 orr r11, r11, r11, lsr #16 1917 bic r11, r11, #0xFF000000 1918 bic r11, r11, #0x00FF0000 1919 1920 ldr r1, =0xFFFF 1921 cmp r11, r1 1922 beq cbr1_test_fail 1923 1924cbr1_test_burst: 1925 ldr r0, =0x1e6e0070 1926 ldr r2, =0x00000000 1927 str r2, [r0] 1928 ldr r2, =0x00000041 1929 str r2, [r0] 1930 ldr r3, =0x1000 1931 ldr r1, =0x1000 1932cbr1_wait_engine_idle_1: 1933 subs r1, r1, #1 1934 beq cbr1_test_burst_end 1935 ldr r2, [r0] 1936 tst r2, r3 @ D[12] = idle bit 1937 beq cbr1_wait_engine_idle_1 1938 1939cbr1_test_burst_end: 1940 ldr r0, =0x1e6e0078 @ read fail bit status 1941 ldr r2, [r0] 1942 orr r2, r2, r2, lsr #16 1943 bic r2, r2, #0xFF000000 1944 bic r2, r2, #0x00FF0000 1945 orr r11, r11, r2 1946 1947 ldr r2, =0xFFFF 1948 cmp r11, r2 1949 bne cbr1_test_pass 1950/* CBRTest2() end */ 1951 1952cbr1_test_fail: 1953 subs r10, r10, #1 1954 bne cbr1_pattern_fail_retry 1955 mov r9, #0x00 1956 b cbr1_test_pattern_end @ CBRScan2() return(0) 1957 1958cbr1_test_pass: 1959 ldr r1, =0xFFFF @ record the pass bit 1960 eor r11, r11, r1 1961 and r9, r9, r11 @ DQ pass bit 1962 cmp r9, #0x00 1963 beq cbr1_test_pattern_end @ CBRScan2() return(0) 1964 1965 add r5, r5, #0x04 @ increase the test pattern index 1966 b cbr1_next_test_pattern 1967 1968CBR1_END: 1969 mov r5, #0x0 @ init DQ DLL_min sum 1970 mov r6, #0x0 @ init DQ DLL_min valid count 1971 ldr r0, =0x1e72000c 1972 ldr r3, =0x1e720050 1973cbr1_search_dllmin_s: 1974 add r0, r0, #0x04 1975 cmp r0, r3 1976 beq cbr1_search_dllmin_e 1977 ldr r1, [r0] 1978 mov r2, r1, lsr #8 1979 and r2, r2, #0xFF @ get dllmax 1980 and r1, r1, #0xFF @ get dllmin 1981 subs r2, r2, r1 @ dllmax - dllmin 1982 bmi cbr1_search_dllmin_s @ no valid margin found, bypass fine tune 1983 cmp r2, #10 @ (dllmax - dllmin) < 10 1984 blt cbr1_search_dllmin_s @ no enough margin found, bypass fine tune 1985 add r5, r5, r1 1986 add r6, r6, #1 1987 b cbr1_search_dllmin_s 1988 1989cbr1_search_dllmin_e: 1990 cmp r6, #16 1991 bne Calibration_Start_pre @ not all bits valid, retry again 1992 1993 mov r5, r5, lsr #4 1994 ldr r0, =0x1e720000 1995 str r5, [r0] 1996 1997 mov r6, #0x00 @ init DQL CBR value 1998 ldr r0, =0x1e720030 1999 ldr r7, =0x1e72000c 2000cbr1_set_result_dql: 2001 sub r0, r0, #4 2002 cmp r0, r7 2003 beq cbr1_set_result_next 2004 mov r6, r6, lsl #3 2005 ldr r1, [r0] 2006 mov r2, r1, lsr #8 2007 and r2, r2, #0xFF @ get dllmax 2008 and r1, r1, #0xFF @ get dllmin 2009 mov r3, r1 @ dll = dllmin 2010 cmp r5, r3 2011 blt cbr1_set_result_dql_neg 2012 sub r1, r5, r3 2013 mov r2, #19 2014 mul r1, r2, r1 2015 mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 2016 cmp r1, #2 @ dqi_tune max = 2 2017 movgt r1, #2 2018 orr r6, r6, r1 2019 b cbr1_set_result_dql 2020 2021cbr1_set_result_dql_neg: 2022 sub r1, r3, r5 2023 mov r2, #19 2024 mul r1, r2, r1 2025 mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 2026 cmp r1, #2 @ dqi_tune max = -2 2027 movgt r1, #2 2028 mov r2, #8 2029 sub r1, r2, r1 2030 and r1, r1, #7 2031 orr r6, r6, r1 2032 b cbr1_set_result_dql 2033 2034cbr1_set_result_next: 2035 ldr r0, =0x1e6e0080 @ save DQL fine tune result 2036 str r6, [r0] 2037 ldr r0, =0x1e720094 2038 str r6, [r0] 2039 2040 mov r6, #0x00 @ init DQH CBR value 2041 ldr r0, =0x1e720050 2042 ldr r7, =0x1e72002c 2043cbr1_set_result_dqh: 2044 sub r0, r0, #4 2045 cmp r0, r7 2046 beq cbr1_set_result_end 2047 mov r6, r6, lsl #3 2048 ldr r1, [r0] 2049 mov r2, r1, lsr #8 2050 and r2, r2, #0xFF @ get dllmax 2051 and r1, r1, #0xFF @ get dllmin 2052 mov r3, r1 @ dll = dllmin 2053 cmp r5, r3 2054 blt cbr1_set_result_dqh_neg 2055 sub r1, r5, r3 2056 mov r2, #19 2057 mul r1, r2, r1 2058 mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 2059 cmp r1, #3 @ dqi_tune max = 2 2060 movgt r1, #3 2061 subs r1, r1, #1 2062 movmi r1, #7 2063 orr r6, r6, r1 2064 b cbr1_set_result_dqh 2065 2066cbr1_set_result_dqh_neg: 2067 sub r1, r3, r5 2068 mov r2, #19 2069 mul r1, r2, r1 2070 mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 2071 add r1, r1, #1 2072 cmp r1, #2 @ dqi_tune max = -2 2073 movgt r1, #2 2074 mov r2, #8 2075 sub r1, r2, r1 2076 and r1, r1, #7 2077 orr r6, r6, r1 2078 b cbr1_set_result_dqh 2079 2080cbr1_set_result_end: 2081 ldr r0, =0x1e6e0084 @ save DQH fine tune result 2082 str r6, [r0] 2083 ldr r0, =0x1e720098 2084 str r6, [r0] 2085 2086/****************************************************************************** 2087 Search the DLL2 detail margin 2088 *****************************************************************************/ 2089 ldr r0, =0x1e7200a0 2090 mov r1, #0 2091 str r1, [r0] 2092 2093CBR3_START: 2094/* Debug - UART console message */ 2095 ldr r0, =0x1e784000 2096 mov r1, #0x33 @ '3' 2097 str r1, [r0] 2098/* Debug - UART console message */ 2099 2100 mov r6, #0x00 @ init pass count 2101 mov r7, #0x00 @ init DLL2 parameter index 2102 ldr r1, =0x000000ff 2103 ldr r0, =0x1e720008 @ init DQL dllmax,dllmin 2104 str r1, [r0] 2105 ldr r0, =0x1e72000c @ init DQH dllmax,dllmin 2106 str r1, [r0] 2107 2108 ldr r0, =0x1e7200a0 @ CBR3 iteration counter 2109 ldr r1, [r0] 2110 add r1, r1, #1 2111 str r1, [r0] 2112 2113/**************************** 2114 DLL2 delay margin test loop 2115 ***************************/ 2116cbr3_next_dll2_parameter: 2117 ldr r0, =0x1e6e0068 @ load DLL2 parameter 2118 ldr r1, [r0] 2119 bic r1, r1, #0x00FF0000 2120 bic r1, r1, #0xFF000000 2121 orr r1, r1, r7, lsl #16 2122 str r1, [r0] 2123 ldr r2, =0x40404040 @ parameter's max is to 0x40404040 2124 cmp r7, r2 2125 bge CBR3_END 2126 ldr r2, =0x01010101 2127 add r7, r7, r2 2128 2129 ldr r0, =0x1e6e0074 @ set the testing DRAM size = 64KB 2130 ldr r1, =0x0000FFFF 2131 str r1, [r0] 2132 2133/* CBRScan() start */ 2134 mov r9, #0x03 @ init test status 2135 adrl r5, PATTERN_TABLE @ init pattern table index 2136/**************************** 2137 Test pattern iteration loop 2138 ***************************/ 2139cbr3_next_test_pattern: 2140 mov r10, #5 @ set the retry loop of each pattern 2141 ldr r1, [r5] @ load test pattern 2142 ldr r0, =0x1e6e007c 2143 str r1, [r0] 2144 cmp r1, #0x00 @ the last data in pattern is 0x00 2145 bne cbr3_test_single 2146 2147cbr3_test_pattern_end: 2148 cmp r9, #0x00 2149 bne cbr3_test_pass_dql 2150 cmp r6, #10 2151 bge CBR3_END 2152 b cbr3_next_dll2_parameter @ CBRScan() end and test result fail, go to next step 2153 2154cbr3_test_pass_dql: 2155 and r3, r7, #0xFF 2156 sub r3, r3, #0x01 @ we add one after loop check so we need to decrease 1 2157 add r6, r6, #0x01 @ increment pass count 2158 tst r9, #0x01 2159 beq cbr3_test_pass_dqh 2160 2161 ldr r0, =0x1E720008 2162 record_dll2_pass_range 2163 2164cbr3_test_pass_dqh: 2165 tst r9, #0x02 2166 beq cbr3_next_dll2_parameter 2167 ldr r0, =0x1E72000c 2168 record_dll2_pass_range 2169 b cbr3_next_dll2_parameter 2170 2171/**************************** 2172 Test fail retry loop 2173 ***************************/ 2174cbr3_pattern_fail_retry: 2175 2176/* CBRTest() start */ 2177cbr3_test_single: 2178 ldr r0, =0x1e6e0070 2179 ldr r1, =0x00000000 2180 str r1, [r0] 2181 ldr r1, =0x00000005 2182 str r1, [r0] 2183 ldr r3, =0x1000 2184 ldr r8, =0x10000 2185cbr3_wait_engine_idle_0: 2186 subs r8, r8, #1 2187 beq cbr3_test_single_end 2188 ldr r2, [r0] 2189 tst r2, r3 @ D[12] = idle bit 2190 beq cbr3_wait_engine_idle_0 2191 2192cbr3_test_single_end: 2193 ldr r0, =0x1e6e0078 @ read fail bit status 2194 ldr r11, [r0] 2195 orr r11, r11, r11, lsr #16 2196 bic r11, r11, #0xFF000000 2197 bic r11, r11, #0x00FF0000 2198 2199 ldr r1, =0xFF 2200 tst r11, r1 2201 beq cbr3_test_burst 2202 tst r11, r1, lsl #8 2203 bne cbr3_test_fail 2204 2205cbr3_test_burst: 2206 mov r1, #0x00 @ initialize loop index, r1 is loop's index 2207cbr3_test_burst_loop: 2208 ldr r0, =0x1e6e0070 2209 ldr r2, =0x00000000 2210 str r2, [r0] 2211 mov r2, r1, lsl #3 2212 orr r2, r2, #0x41 @ test command = 0x41 | (datagen << 3) 2213 str r2, [r0] 2214 ldr r3, =0x1000 2215 ldr r8, =0x10000 2216cbr3_wait_engine_idle_1: 2217 subs r8, r8, #1 2218 beq cbr3_test_burst_end 2219 ldr r2, [r0] 2220 tst r2, r3 @ D[12] = idle bit 2221 beq cbr3_wait_engine_idle_1 2222 2223cbr3_test_burst_end: 2224 ldr r0, =0x1e6e0078 @ read fail bit status 2225 ldr r2, [r0] 2226 orr r2, r2, r2, lsr #16 2227 bic r2, r2, #0xFF000000 2228 bic r2, r2, #0x00FF0000 2229 orr r11, r11, r2 2230 2231 ldr r2, =0xFF 2232 tst r11, r2 2233 beq cbr3_next_test_burst_mode 2234 tst r11, r2, lsl #8 2235 beq cbr3_next_test_burst_mode 2236/* CBRTest() end */ 2237 2238cbr3_test_fail: 2239 subs r10, r10, #1 2240 bne cbr3_pattern_fail_retry 2241 mov r9, #0x00 2242 b cbr3_test_pattern_end @ CBRScan() return(0) 2243 2244cbr3_next_test_burst_mode: 2245 add r1, r1, #1 @ increase the test mode index 2246 cmp r1, #0x08 @ there are 8 modes 2247 bne cbr3_test_burst_loop 2248 2249 ldr r1, =0xFF @ record the pass byte 2250 tst r11, r1 2251 andne r9, r9, #0x02 @ DQL fail 2252 tst r11, r1, lsl #8 2253 andne r9, r9, #0x01 @ DQH fail 2254 cmp r9, #0x00 2255 beq cbr3_test_pattern_end @ CBRScan() return(0) 2256 2257 add r5, r5, #0x04 @ increase the test pattern index 2258 b cbr3_next_test_pattern 2259 2260CBR3_END: 2261 ldr r0, =0x1e72000c @ check DQH margin 2262 ldr r1, [r0] 2263 mov r2, r1, lsr #8 2264 and r2, r2, #0xFF @ get dllmax 2265 and r1, r1, #0xFF @ get dllmin 2266 subs r5, r2, r1 @ dllmax - dllmin 2267 bmi CBR3_START @ no valid margin found, retry again 2268 cmp r5, #10 @ (dllmax - dllmin) < 10 2269 blt CBR3_START @ no enough margin found, retry again 2270 add r2, r1, r2 @ (dllmin[1] + dllmax[1] + 1) >> 1 2271 add r2, r2, #0x01 2272 mov r1, r2, lsr #1 2273 mov r3, r1, lsl #8 2274 ldr r1, [r0] @ store the dll search result 2275 bic r1, r1, #0xFF000000 2276 bic r1, r1, #0x00FF0000 2277 orr r1, r1, r3, lsl #8 2278 str r1, [r0] 2279 2280 ldr r0, =0x1e720008 @ check DQL margin 2281 ldr r1, [r0] 2282 mov r2, r1, lsr #8 2283 and r2, r2, #0xFF @ get dllmax 2284 and r1, r1, #0xFF @ get dllmin 2285 subs r5, r2, r1 @ dllmax - dllmin 2286 bmi CBR3_START @ no valid margin found, retry again 2287 cmp r5, #10 @ (dllmax - dllmin) < 10 2288 blt CBR3_START @ no enough margin found, retry again 2289 add r2, r1, r2 @ (dllmin[0] + dllmax[0] + 1) >> 1 2290 add r2, r2, #0x01 2291 mov r1, r2, lsr #1 2292 ldr r2, [r0] @ store the dll search result 2293 bic r2, r2, #0xFF000000 2294 bic r2, r2, #0x00FF0000 2295 orr r2, r2, r1, lsl #16 2296 str r2, [r0] 2297 orr r3, r3, r1 2298 2299 ldr r0, =0x1e6e0068 @ save the result dll value 2300 ldr r1, [r0] 2301 bic r1, r1, #0xFF000000 2302 bic r1, r1, #0x00FF0000 2303 orr r1, r1, r3, lsl #16 2304 str r1, [r0] 2305 b CBR4_START 2306 2307.LTORG 2308 2309/****************************************************************************** 2310 Search the DQS input mask margin 2311 *****************************************************************************/ 2312CBR4_START: 2313/* Debug - UART console message */ 2314 ldr r0, =0x1e784000 2315 mov r1, #0x34 @ '4' 2316 str r1, [r0] 2317/* Debug - UART console message */ 2318 2319 ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB 2320 ldr r1, =0x00000FFF 2321 str r1, [r0] 2322 2323 mov r8, #0x00 @ init MCR18[4] 2324 ldr r1, =0x000000ff 2325 ldr r0, =0x1e7200b0 @ init MCR18[4]=0 max,min 2326 str r1, [r0] 2327 ldr r0, =0x1e7200b4 @ init MCR18[4]=1 max,min 2328 str r1, [r0] 2329 2330 ldr r0, =0x1e6e0018 2331 ldr r1, [r0] 2332 bic r1, r1, #0x0000001F 2333 str r1, [r0] 2334 2335 b cbr4_scan_start 2336 2337cbr4_next_maskdly: 2338 add r8, r8, #0x01 2339 and r2, r8, #0x01 2340 ldr r0, =0x1e6e0018 2341 ldr r1, [r0] 2342 bic r1, r1, #0x0000001F 2343 orr r1, r1, r2, lsl #4 2344 str r1, [r0] 2345 cmp r8, #0x02 2346 bge CBR4_END 2347 2348cbr4_scan_start: 2349 mov r6, #0x00 @ init pass count 2350 mov r7, #0x00 @ init mask delay 2351 2352/**************************** 2353 DQS Mask delay margin test loop 2354 ***************************/ 2355cbr4_next_parameter: 2356 cmp r7, #0x10 @ max delay = 0xF 2357 bge cbr4_next_maskdly 2358 ldr r0, =0x1e6e0018 @ load MCR18 parameter 2359 ldr r1, [r0] 2360 bic r1, r1, #0x0000000F 2361 orr r1, r1, r7 2362 str r1, [r0] 2363 add r7, r7, #0x01 2364 2365/* CBRScan3() start */ 2366 adrl r5, PATTERN_TABLE @ init pattern table index 2367/**************************** 2368 Test pattern iteration loop 2369 ***************************/ 2370cbr4_next_test_pattern: 2371 mov r10, #2 @ set the retry loop = 2 of each pattern 2372 ldr r1, [r5] @ load test pattern 2373 ldr r0, =0x1e6e007c 2374 str r1, [r0] 2375 cmp r1, #0x00 @ the last data in pattern is 0x00 2376 bne cbr4_test_burst 2377 2378 and r3, r7, #0xFF 2379 sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 2380 add r6, r6, #0x01 @ increment pass count 2381 2382 ldr r0, =0x1e7200b0 @ record pass window 2383 add r0, r0, r8, lsl #2 2384 record_dll2_pass_range 2385 mov r2, #0x01 2386 add r1, r1, r2, lsl #16 2387 str r1, [r0] 2388 b cbr4_next_parameter 2389 2390cbr4_test_pattern_fail: 2391 cmp r6, #5 @ passcnt >= 5 2392 bge cbr4_next_maskdly 2393 b cbr4_next_parameter 2394 2395/**************************** 2396 Test fail retry loop 2397 ***************************/ 2398cbr4_pattern_fail_retry: 2399 2400/* CBRTest3() start */ 2401cbr4_test_burst: 2402 ldr r0, =0x1e6e0070 2403 ldr r1, =0x00000000 2404 str r1, [r0] 2405 ldr r1, =0x000000C1 2406 str r1, [r0] 2407 ldr r3, =0x3000 2408cbr4_wait_engine_idle_0: 2409 ldr r2, [r0] 2410 tst r2, r3 @ D[12] = idle bit 2411 beq cbr4_wait_engine_idle_0 2412 2413 ldr r2, [r0] @ read fail bit status 2414 mov r1, #0x0 2415 str r1, [r0] 2416 mov r2, r2, lsr #13 @ D[13] = fail bit 2417 cmp r2, #0x00 2418 bne cbr4_test_fail 2419 2420cbr4_test_single: 2421 ldr r0, =0x1e6e0070 2422 ldr r1, =0x00000000 2423 str r1, [r0] 2424 ldr r1, =0x00000085 2425 str r1, [r0] 2426 ldr r3, =0x3000 2427cbr4_wait_engine_idle_1: 2428 ldr r2, [r0] 2429 tst r2, r3 @ D[12] = idle bit 2430 beq cbr4_wait_engine_idle_1 2431 2432 ldr r2, [r0] @ read fail bit status 2433 mov r1, #0x0 2434 str r1, [r0] 2435 mov r2, r2, lsr #13 @ D[13] = fail bit 2436 cmp r2, #0x00 2437 beq cbr4_test_pass 2438 2439/* CBRTest3() end */ 2440 2441cbr4_test_fail: 2442 subs r10, r10, #1 2443 bne cbr4_pattern_fail_retry 2444 b cbr4_test_pattern_fail @ CBRScan3() return(0) 2445 2446cbr4_test_pass: 2447 add r5, r5, #0x04 @ increase the test pattern index 2448 b cbr4_next_test_pattern 2449 2450CBR4_END: 2451 ldr r0, =0x1e7200b0 @ check mask margin 2452 ldr r1, [r0] 2453 add r0, r0, #0x04 2454 ldr r2, [r0] 2455 ands r6, r2, #0xFF @ get min of MCR18[4] = 1 2456 bne cbr4_noset_delay 2457 ands r5, r1, #0xFF @ get min of MCR18[4] = 0 2458 bne cbr4_set_delay 2459 mov r1, r1, lsr #8 @ get max of MCR18[4] = 0 2460 and r1, r1, #0xFF 2461 mov r2, r2, lsr #8 @ get max of MCR18[4] = 1 2462 and r2, r2, #0xFF 2463 sub r1, r1, r5 2464 sub r2, r2, r6 2465 cmp r1, r2 2466 bge cbr4_noset_delay 2467 2468cbr4_set_delay: 2469 ldr r0, =0x1e6e0018 2470 ldr r1, [r0] 2471 orr r1, r1, #0x10 2472 str r1, [r0] 2473 2474cbr4_noset_delay: 2475 ldr r0, =0x1e6e0070 2476 ldr r1, =0x00000000 2477 str r1, [r0] 2478 2479/****************************************************************************** 2480 CBR Finish 2481 *****************************************************************************/ 2482/****************************************************************************** 2483 Check DRAM Size 2484 *****************************************************************************/ 2485 ldr r0, =0x1e6e2070 2486 ldr r1, [r0] 2487 bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2 2488 mov r2, r1, lsr #24 2489 cmp r2, #0x01 2490 beq check_ddr2_size 2491 2492 ldr r0, =0x1e6e0004 2493 ldr r5, [r0] 2494 bic r5, r5, #0x00000003 @ record MCR04 2495 orr r1, r5, #0x3 2496 str r1, [r0] @ set to 4Gbit 2497 ldr r6, =0x003F2217 2498#if defined(CONFIG_DRAM_336) 2499 ldr r6, =0x00361C13 2500#endif 2501 b check_dram_size 2502 2503check_ddr2_size: 2504 ldr r0, =0x1e6e0004 2505 ldr r5, [r0] 2506 bic r5, r5, #0x00000023 @ record MCR04 2507 orr r1, r5, #0x23 2508 str r1, [r0] @ set to 4Gbit 2509 ldr r6, =0x3F2B1B16 2510#if defined(CONFIG_DRAM_336) 2511 ldr r6, =0x3B231612 2512#endif 2513 2514 ldr r0, =0x40000000 2515 ldr r1, =0x1817191A 2516 str r1, [r0] 2517 ldr r0, =0x40002000 2518 ldr r1, =0x73616532 2519 str r1, [r0] 2520 ldr r0, =0x40000000 2521 ldr r1, =0x1817191A 2522 ldr r2, [r0] 2523 cmp r1, r2 2524 bne check_dram_size_end @ == 512Mbit 2525 orr r5, r5, #0x20 @ >= 1Gbit 2526 mov r6, r6, lsr #8 2527 2528check_dram_size: 2529 ldr r0, =0x50100000 2530 ldr r1, =0x41424344 2531 str r1, [r0] 2532 ldr r0, =0x48100000 2533 ldr r1, =0x25262728 2534 str r1, [r0] 2535 ldr r0, =0x40100000 2536 ldr r1, =0x191A1B1C 2537 str r1, [r0] 2538 ldr r0, =0x50100000 2539 ldr r1, =0x41424344 2540 ldr r2, [r0] 2541 cmp r2, r1 @ == 4Gbit 2542 orreq r5, r5, #0x03 2543 moveq r6, r6, lsr #16 2544 beq check_dram_size_end 2545 ldr r0, =0x48100000 2546 ldr r1, =0x25262728 2547 ldr r2, [r0] 2548 cmp r2, r1 @ == 2Gbit 2549 orreq r5, r5, #0x02 2550 moveq r6, r6, lsr #8 2551 beq check_dram_size_end 2552 orr r5, r5, #0x01 @ == 1Gbit 2553 2554check_dram_size_end: 2555 ldr r0, =0x1e6e0004 2556 str r5, [r0] 2557 ldr r0, =0x1e6e0014 2558 ldr r1, [r0] 2559 bic r1, r1, #0x000000FF 2560 and r6, r6, #0xFF 2561 orr r1, r1, r6 2562 str r1, [r0] 2563 2564 ldr r0, =0x1e6e0120 @ VGA Compatible Mode 2565 ldr r1, =0x000050C0 @ 408 MHz 2566#if defined(CONFIG_DRAM_336) 2567 ldr r1, =0x00004DC0 2568#endif 2569 str r1, [r0] 2570 2571/****************************************************************************** 2572 Version Number 2573 *****************************************************************************/ 2574 ldr r0, =0x1e7200a8 2575 ldr r1, =0x20180802 @ released date 2576 str r1, [r0] 2577 2578 add r0, r0, #4 2579 ldr r1, =0x00000065 @ released SDK version 2580 str r1, [r0] 2581 2582/****************************************************************************** 2583 Calibration Code End 2584 ******************************************************************************/ 2585 2586set_scratch: 2587 /*Set Scratch register Bit 6 after ddr initial finished */ 2588 ldr r0, =0x1e6e2040 2589 ldr r1, [r0] 2590 orr r1, r1, #0x41 2591 str r1, [r0] 2592 2593/* Debug - UART console message */ 2594 ldr r0, =0x1e784000 2595 mov r1, #0x44 @ 'D' 2596 str r1, [r0] 2597 mov r1, #0x6F @ 'o' 2598 str r1, [r0] 2599 mov r1, #0x6E @ 'n' 2600 str r1, [r0] 2601 mov r1, #0x65 @ 'e' 2602 str r1, [r0] 2603 mov r1, #0x0D @ '\r' 2604 str r1, [r0] 2605 mov r1, #0x0A @ '\n' 2606 str r1, [r0] 2607/* Debug - UART console message */ 2608 2609/****************************************************************************** 2610 Solve PCIe ASPM issue, only applied to AST2300 series 2611 ******************************************************************************/ 2612 ldr r0, =0x1e6e207c @ Check bounding for AST1150 existence 2613 ldr r1, [r0] 2614 mov r2, r1, lsr #24 2615 cmp r2, #0x01 2616 bne platform_exit @ not match AST2300 2617 bic r1, r1, #0xFFFFFCFF 2618 mov r1, r1, lsr #8 2619 cmp r1, #0x02 2620 beq platform_exit @ match AST1050 2621 2622 ldr r0, =0x1e6e2004 @ Disable I2C controller reset 2623 ldr r1, [r0] 2624 orr r1, r1, #0x04 2625 str r1, [r0] 2626 bic r1, r1, #0x04 2627 str r1, [r0] 2628 2629 ldr r0, =0x1e78a054 @ Check I2C bus state, if busy then quit 2630 ldr r1, [r0] 2631 mov r1, r1, lsr #17 2632 and r1, r1, #0x03 2633 cmp r1, #0x03 2634 bne platform_exit 2635 2636 ldr r0, =0x1e78a040 @ Init I2C1 controller 2637 mov r1, #0x01 2638 orr r1, r1, r1, lsl #16 2639 str r1, [r0] 2640 2641 ldr r0, =0x1e78a044 2642 ldr r1, =0x77776704 2643 str r1, [r0] 2644 2645 mov r1, #0x0 2646 ldr r0, =0x1e78a048 2647 str r1, [r0] 2648 ldr r0, =0x1e78a04c 2649 str r1, [r0] 2650 2651 ldr r0, =0x1e78a050 2652 ldr r1, =0xFFFFFFFF 2653 str r1, [r0] 2654 2655 ldr r0, =0x1e78a200 @ Set AST1150 I2C password 2656 ldr r1, =0x00A88FA8 2657 str r1, [r0] 2658 2659 ldr r0, =0x1e78a05c 2660 ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes 2661 str r1, [r0] 2662 2663 ldr r0, =0x1e78a054 2664 ldr r1, =0x00000063 @ Fire commmand 2665 str r1, [r0] 2666 2667 ldr r0, =0x1e78a050 2668i2c_wait_cmddone_1: 2669 ldr r1, [r0] 2670 tst r1, #0x38 2671 beq i2c_wait_cmddone_1 2672 tst r1, #0x2A @ transmit error 2673 bne platform_exit2 2674 ldr r1, =0xFFFFFFFF 2675 str r1, [r0] 2676 2677 ldr r0, =0x1e78a200 @ Disable ASPM capability 2678 ldr r1, =0x04005DA8 2679 str r1, [r0] 2680 2681 ldr r0, =0x1e78a204 2682 ldr r1, =0x00000024 2683 str r1, [r0] 2684 2685 ldr r0, =0x1e78a05c 2686 ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes 2687 str r1, [r0] 2688 2689 ldr r0, =0x1e78a054 2690 ldr r1, =0x00000063 @ Fire commmand 2691 str r1, [r0] 2692 2693 ldr r0, =0x1e78a050 2694i2c_wait_cmddone_2: 2695 ldr r1, [r0] 2696 tst r1, #0x38 2697 beq i2c_wait_cmddone_2 2698 tst r1, #0x2A @ transmit error 2699 bne platform_exit2 2700 ldr r1, =0xFFFFFFFF 2701 str r1, [r0] 2702 2703platform_exit2: 2704 ldr r0, =0x1e78a040 @ Disable I2C1 controller 2705 mov r1, #0x00 2706 str r1, [r0] 2707 2708 b platform_exit 2709.LTORG 2710 2711platform_exit: 2712#ifdef CONFIG_DRAM_ECC 2713 ldr r0, =0x1e6e0004 2714 ldr r1, [r0] 2715 orr r1, r1, #0x80 2716 str r1, [r0] 2717 2718 ldr r0, =0x1e6e0054 2719 ldr r1, =0x05000000 /* ECC protected memory size, default set at 80M */ 2720 str r1, [r0] 2721 2722 ldr r0, =0x1e6e007C 2723 ldr r1, =0x00000000 2724 str r1, [r0] 2725 ldr r0, =0x1e6e0074 2726 str r1, [r0] 2727 2728 ldr r0, =0x1e6e0070 2729 ldr r1, =0x00000221 2730 str r1, [r0] 2731 2732 ldr r0, =0x1e6e0070 2733 ldr r2, =0x00001000 2734ECC_Init_Flag: 2735 ldr r1, [r0] 2736 tst r1, r2 @ D[12] = 1, Done 2737 beq ECC_Init_Flag 2738 2739 ldr r0, =0x1e6e0070 2740 ldr r1, =0x00000000 2741 str r1, [r0] 2742 2743 ldr r0, =0x1e6e0050 2744 ldr r1, =0x80000000 2745 str r1, [r0] 2746 2747 ldr r0, =0x1e6e0050 2748 ldr r1, =0x00000000 2749 str r1, [r0] 2750 2751 ldr r0, =0x1e6e0070 2752 ldr r1, =0x00000400 2753 str r1, [r0] 2754#endif 2755 ldr r0, =0x1e6e2008 @ Set Video ECLK phase 2756 ldr r1, [r0] 2757 ldr r2, =0xfffffff3 2758 and r1, r1, r2 2759 orr r1, r1, #0x08 2760 str r1, [r0] 2761#if 0 2762 ldr r0, =0x1e6e2004 2763 ldr r1, [r0] 2764 ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue 2765 and r1, r1, r2 2766 str r1, [r0] 2767#endif 2768 ldr r0, =0x1e6e2048 @ Set MAC interface delay timing 2769 ldr r1, =0x2255 2770 str r1, [r0] 2771 2772 ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock 2773 ldr r1, [r0] 2774 mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10 2775 tst r1, #0xC0 2776 movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6 2777 ldr r0, =0x1e6e2008 2778 ldr r1, [r0] 2779 bic r1, r1, #0x00070000 2780 orr r1, r1, r2, lsl #16 2781 str r1, [r0] 2782 2783/* Test - DRAM initial time */ 2784 ldr r0, =0x1e782040 2785 ldr r1, [r0] 2786 ldr r0, =0xFFFFFFFF 2787 sub r1, r0, r1 2788 ldr r0, =0x1e72009c 2789 str r1, [r0] 2790 ldr r0, =0x1e7200a4 2791 str r1, [r0] 2792 ldr r0, =0x1e782030 2793 ldr r1, [r0] 2794 bic r1, r1, #0x0000F000 2795 str r1, [r0] 2796/* Test - DRAM initial time */ 2797 2798/****************************************************************************** 2799 Reset GPIO registers when watchdog reset 2800 ******************************************************************************/ 2801 ldr r0, =0x1e6e207c @ Check Revision ID 2802 ldr r1, [r0] 2803 mov r1, r1, lsr #24 2804 cmp r1, #0x02 2805 bne platform_exit3 @ not match AST2400 2806 2807 ldr r0, =0x1e6e203c @ Check watchdog reset event 2808 ldr r1, [r0] 2809 and r1, r1, #0x06 2810 cmp r1, #0x0 2811 beq platform_exit3 @ no watchdog reset event 2812 2813 ldr r0, =0x1e6e209c @ Check watchdog GPIO selection 2814 ldr r1, [r0] 2815 mov r1, r1, lsr #21 2816 tst r1, #0x01 2817 beq platform_exit3 @ no watchdog reset selection 2818 2819 ldr r1, =0x00000000 @ clear GPIO register reset by PRST_N 2820 ldr r2, =0xFFFFFFFF 2821 ldr r0, =0x1e780008 2822 str r1, [r0] 2823 ldr r0, =0x1e78000c 2824 str r1, [r0] 2825 ldr r0, =0x1e780010 2826 str r1, [r0] 2827 ldr r0, =0x1e780014 2828 str r1, [r0] 2829 ldr r0, =0x1e780018 2830 str r2, [r0] 2831 ldr r0, =0x1e780028 2832 str r1, [r0] 2833 ldr r0, =0x1e78002c 2834 str r1, [r0] 2835 ldr r0, =0x1e780030 2836 str r1, [r0] 2837 ldr r0, =0x1e780034 2838 str r1, [r0] 2839 ldr r0, =0x1e780038 2840 str r2, [r0] 2841 ldr r0, =0x1e780040 2842 str r1, [r0] 2843 ldr r0, =0x1e780044 2844 str r1, [r0] 2845 ldr r0, =0x1e780048 2846 str r1, [r0] 2847 ldr r0, =0x1e78004c 2848 str r1, [r0] 2849 ldr r0, =0x1e780050 2850 str r1, [r0] 2851 ldr r0, =0x1e780054 2852 str r1, [r0] 2853 ldr r0, =0x1e780058 2854 str r1, [r0] 2855 ldr r0, =0x1e780060 2856 str r1, [r0] 2857 ldr r0, =0x1e780064 2858 str r1, [r0] 2859 ldr r0, =0x1e780068 2860 str r1, [r0] 2861 ldr r0, =0x1e78006c 2862 str r1, [r0] 2863 ldr r0, =0x1e780090 2864 str r1, [r0] 2865 ldr r0, =0x1e780094 2866 str r1, [r0] 2867 ldr r0, =0x1e780098 2868 str r1, [r0] 2869 ldr r0, =0x1e78009c 2870 str r1, [r0] 2871 ldr r0, =0x1e7800a0 2872 str r1, [r0] 2873 ldr r0, =0x1e7800a4 2874 str r1, [r0] 2875 ldr r0, =0x1e7800a8 2876 str r2, [r0] 2877 ldr r0, =0x1e7800b0 2878 str r1, [r0] 2879 ldr r0, =0x1e7800b4 2880 str r1, [r0] 2881 ldr r0, =0x1e7800b8 2882 str r1, [r0] 2883 ldr r0, =0x1e7800e0 2884 str r1, [r0] 2885 ldr r0, =0x1e7800e4 2886 str r1, [r0] 2887 ldr r0, =0x1e7800e8 2888 str r1, [r0] 2889 ldr r0, =0x1e7800ec 2890 str r1, [r0] 2891 ldr r0, =0x1e7800f0 2892 str r1, [r0] 2893 ldr r0, =0x1e7800f4 2894 str r1, [r0] 2895 ldr r0, =0x1e7800f8 2896 str r2, [r0] 2897 ldr r0, =0x1e780100 2898 str r1, [r0] 2899 ldr r0, =0x1e780104 2900 str r1, [r0] 2901 ldr r0, =0x1e780108 2902 str r1, [r0] 2903 ldr r0, =0x1e780110 2904 str r1, [r0] 2905 ldr r0, =0x1e780114 2906 str r1, [r0] 2907 ldr r0, =0x1e780118 2908 str r1, [r0] 2909 ldr r0, =0x1e78011c 2910 str r1, [r0] 2911 ldr r0, =0x1e780120 2912 str r1, [r0] 2913 ldr r0, =0x1e780124 2914 str r1, [r0] 2915 ldr r0, =0x1e780128 2916 str r2, [r0] 2917 ldr r0, =0x1e780130 2918 str r1, [r0] 2919 ldr r0, =0x1e780134 2920 str r1, [r0] 2921 ldr r0, =0x1e780138 2922 str r1, [r0] 2923 ldr r0, =0x1e780140 2924 str r1, [r0] 2925 ldr r0, =0x1e780144 2926 str r1, [r0] 2927 ldr r0, =0x1e780148 2928 str r1, [r0] 2929 ldr r0, =0x1e78014c 2930 str r1, [r0] 2931 ldr r0, =0x1e780150 2932 str r1, [r0] 2933 ldr r0, =0x1e780154 2934 str r1, [r0] 2935 ldr r0, =0x1e780158 2936 str r2, [r0] 2937 ldr r0, =0x1e780160 2938 str r1, [r0] 2939 ldr r0, =0x1e780164 2940 str r1, [r0] 2941 ldr r0, =0x1e780168 2942 str r1, [r0] 2943 ldr r0, =0x1e780170 2944 str r1, [r0] 2945 ldr r0, =0x1e780174 2946 str r1, [r0] 2947 ldr r0, =0x1e780178 2948 str r1, [r0] 2949 ldr r0, =0x1e78017c 2950 str r1, [r0] 2951 ldr r0, =0x1e780180 2952 str r1, [r0] 2953 ldr r0, =0x1e780184 2954 str r1, [r0] 2955 ldr r0, =0x1e780188 2956 str r2, [r0] 2957 ldr r0, =0x1e780190 2958 str r1, [r0] 2959 ldr r0, =0x1e780194 2960 str r1, [r0] 2961 ldr r0, =0x1e780198 2962 str r1, [r0] 2963 ldr r0, =0x1e7801d0 2964 str r1, [r0] 2965 ldr r0, =0x1e7801d4 2966 str r1, [r0] 2967 2968 ldr r0, =0x1e780204 @ clear SGPIOM register reset by PRST_N 2969 str r1, [r0] 2970 ldr r0, =0x1e780208 2971 str r1, [r0] 2972 ldr r0, =0x1e78020c 2973 str r1, [r0] 2974 ldr r0, =0x1e780210 2975 str r1, [r0] 2976 ldr r0, =0x1e780214 2977 str r2, [r0] 2978 ldr r0, =0x1e780220 2979 str r1, [r0] 2980 ldr r0, =0x1e780224 2981 str r1, [r0] 2982 ldr r0, =0x1e780228 2983 str r1, [r0] 2984 ldr r0, =0x1e78022c 2985 str r1, [r0] 2986 ldr r0, =0x1e780230 2987 str r2, [r0] 2988 ldr r0, =0x1e78023c 2989 str r1, [r0] 2990 ldr r0, =0x1e780240 2991 str r1, [r0] 2992 ldr r0, =0x1e780244 2993 str r1, [r0] 2994 ldr r0, =0x1e780248 2995 str r1, [r0] 2996 ldr r0, =0x1e78024c 2997 str r2, [r0] 2998 ldr r0, =0x1e780254 2999 ldr r3, =0x01000040 3000 str r3, [r0] 3001 ldr r0, =0x1e780258 3002 str r1, [r0] 3003 ldr r0, =0x1e78025c 3004 str r1, [r0] 3005 ldr r0, =0x1e780260 3006 str r1, [r0] 3007 3008 ldr r0, =0x1e780300 @ clear SGPIOS register reset by PRST_N 3009 str r1, [r0] 3010 ldr r0, =0x1e780304 3011 str r1, [r0] 3012 ldr r0, =0x1e780308 3013 str r1, [r0] 3014 ldr r0, =0x1e78030c 3015 str r1, [r0] 3016 ldr r0, =0x1e780310 3017 str r1, [r0] 3018 ldr r0, =0x1e780314 3019 str r1, [r0] 3020 ldr r0, =0x1e780318 3021 str r2, [r0] 3022 ldr r0, =0x1e78031c 3023 str r2, [r0] 3024 ldr r0, =0x1e780320 3025 str r2, [r0] 3026 3027platform_exit3: 3028 3029/****************************************************************************** 3030 SPI Timing Calibration, not applicable to AST2300 series 3031 ******************************************************************************/ 3032 ldr r0, =0x1e6e207c @ Check Revision ID 3033 ldr r1, [r0] 3034 mov r1, r1, lsr #24 3035 cmp r1, #0x02 3036 blt platform_exit4 @ not match AST2400 or later 3037 3038 ldr r0, =0x1e6e2070 @ Check SPI flash 3039 ldr r1, [r0] 3040 and r1, r1, #0x03 3041 cmp r1, #0x02 3042 bne platform_exit4 3043 3044 mov r2, #0x0 3045 mov r6, #0x0 3046 mov r7, #0x0 3047 init_spi_checksum 3048spi_checksum_wait_0: 3049 ldr r1, [r0] 3050 tst r1, r2 3051 beq spi_checksum_wait_0 3052 ldr r0, =0x1e620090 3053 ldr r5, [r0] @ record golden checksum 3054 ldr r0, =0x1e620080 3055 mov r1, #0x0 3056 str r1, [r0] 3057 3058 ldr r0, =0x1e620010 @ set to fast read mode 3059 ldr r1, =0x000B0041 3060 str r1, [r0] 3061 3062 ldr r6, =0x00F7E6D0 @ Init spiclk loop 3063 mov r8, #0x0 @ Init delay record 3064 3065spi_cbr_next_clkrate: 3066 mov r6, r6, lsr #0x4 3067 cmp r6, #0x0 3068 beq spi_cbr_end 3069 3070 mov r7, #0x0 @ Init delay loop 3071 mov r8, r8, lsl #4 3072 3073spi_cbr_next_delay_s: 3074 mov r2, #0x8 3075 init_spi_checksum 3076spi_checksum_wait_1: 3077 ldr r1, [r0] 3078 tst r1, r2 3079 beq spi_checksum_wait_1 3080 ldr r0, =0x1e620090 3081 ldr r2, [r0] @ read checksum 3082 ldr r0, =0x1e620080 3083 mov r1, #0x0 3084 str r1, [r0] 3085 cmp r2, r5 3086 bne spi_cbr_next_delay_e 3087 3088 mov r2, #0x0 3089 init_spi_checksum 3090spi_checksum_wait_2: 3091 ldr r1, [r0] 3092 tst r1, r2 3093 beq spi_checksum_wait_2 3094 ldr r0, =0x1e620090 3095 ldr r2, [r0] @ read checksum 3096 ldr r0, =0x1e620080 3097 mov r1, #0x0 3098 str r1, [r0] 3099 cmp r2, r5 3100 bne spi_cbr_next_delay_e 3101 3102 orr r8, r8, r7 @ record passed delay 3103 b spi_cbr_next_clkrate 3104 3105spi_cbr_next_delay_e: 3106 add r7, r7, #0x1 3107 cmp r7, #0x6 3108 blt spi_cbr_next_delay_s 3109 b spi_cbr_next_clkrate 3110 3111spi_cbr_end: 3112 ldr r0, =0x1e620094 3113 str r8, [r0] 3114 ldr r0, =0x1e620010 3115 mov r1, #0x0 3116 str r1, [r0] 3117 3118platform_exit4: 3119 3120 ldr r0, =0x1e6e2090 @ set USB2.0 port as Device mode 3121 ldr r1, =0x0000A000 3122 str r1, [r0] 3123 3124 /* back to arch calling code */ 3125 mov pc, lr 3126