1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dmub_psr.h"
27 #include "dc.h"
28 #include "dc_dmub_srv.h"
29 #include "dmub/dmub_srv.h"
30 #include "core_types.h"
31
32 #define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */
33
34 #define MAX_PIPES 6
35
36 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};
37 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};
38
39 /*
40 * Convert dmcub psr state to dmcu psr state.
41 */
convert_psr_state(uint32_t raw_state)42 static enum dc_psr_state convert_psr_state(uint32_t raw_state)
43 {
44 enum dc_psr_state state = PSR_STATE0;
45
46 if (raw_state == 0)
47 state = PSR_STATE0;
48 else if (raw_state == 0x10)
49 state = PSR_STATE1;
50 else if (raw_state == 0x11)
51 state = PSR_STATE1a;
52 else if (raw_state == 0x20)
53 state = PSR_STATE2;
54 else if (raw_state == 0x21)
55 state = PSR_STATE2a;
56 else if (raw_state == 0x22)
57 state = PSR_STATE2b;
58 else if (raw_state == 0x30)
59 state = PSR_STATE3;
60 else if (raw_state == 0x31)
61 state = PSR_STATE3Init;
62 else if (raw_state == 0x40)
63 state = PSR_STATE4;
64 else if (raw_state == 0x41)
65 state = PSR_STATE4a;
66 else if (raw_state == 0x42)
67 state = PSR_STATE4b;
68 else if (raw_state == 0x43)
69 state = PSR_STATE4c;
70 else if (raw_state == 0x44)
71 state = PSR_STATE4d;
72 else if (raw_state == 0x50)
73 state = PSR_STATE5;
74 else if (raw_state == 0x51)
75 state = PSR_STATE5a;
76 else if (raw_state == 0x52)
77 state = PSR_STATE5b;
78 else if (raw_state == 0x53)
79 state = PSR_STATE5c;
80 else if (raw_state == 0x4A)
81 state = PSR_STATE4_FULL_FRAME;
82 else if (raw_state == 0x4B)
83 state = PSR_STATE4a_FULL_FRAME;
84 else if (raw_state == 0x4C)
85 state = PSR_STATE4b_FULL_FRAME;
86 else if (raw_state == 0x4D)
87 state = PSR_STATE4c_FULL_FRAME;
88 else if (raw_state == 0x4E)
89 state = PSR_STATE4_FULL_FRAME_POWERUP;
90 else if (raw_state == 0x4F)
91 state = PSR_STATE4_FULL_FRAME_HW_LOCK;
92 else if (raw_state == 0x60)
93 state = PSR_STATE_HWLOCK_MGR;
94 else if (raw_state == 0x61)
95 state = PSR_STATE_POLLVUPDATE;
96 else
97 state = PSR_STATE_INVALID;
98
99 return state;
100 }
101
102 /*
103 * Get PSR state from firmware.
104 */
dmub_psr_get_state(struct dmub_psr * dmub,enum dc_psr_state * state,uint8_t panel_inst)105 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
106 {
107 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
108 uint32_t raw_state = 0;
109 uint32_t retry_count = 0;
110 enum dmub_status status;
111
112 do {
113 // Send gpint command and wait for ack
114 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
115
116 if (status == DMUB_STATUS_OK) {
117 // GPINT was executed, get response
118 dmub_srv_get_gpint_response(srv, &raw_state);
119 *state = convert_psr_state(raw_state);
120 } else
121 // Return invalid state when GPINT times out
122 *state = PSR_STATE_INVALID;
123
124 } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
125
126 // Assert if max retry hit
127 if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
128 ASSERT(0);
129 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
130 WPP_BIT_FLAG_Firmware_PsrState,
131 "Unable to get PSR state from FW.");
132 } else
133 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
134 WPP_BIT_FLAG_Firmware_PsrState,
135 "Got PSR state from FW. PSR state: %d, Retry count: %d",
136 *state, retry_count);
137 }
138
139 /*
140 * Set PSR version.
141 */
dmub_psr_set_version(struct dmub_psr * dmub,struct dc_stream_state * stream,uint8_t panel_inst)142 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
143 {
144 union dmub_rb_cmd cmd;
145 struct dc_context *dc = dmub->ctx;
146
147 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
148 return false;
149
150 memset(&cmd, 0, sizeof(cmd));
151 cmd.psr_set_version.header.type = DMUB_CMD__PSR;
152 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
153 switch (stream->link->psr_settings.psr_version) {
154 case DC_PSR_VERSION_1:
155 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
156 break;
157 case DC_PSR_VERSION_SU_1:
158 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
159 break;
160 case DC_PSR_VERSION_UNSUPPORTED:
161 default:
162 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
163 break;
164 }
165
166 if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED)
167 return false;
168
169 cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
170 cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
171 cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
172
173 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
174
175 return true;
176 }
177
178 /*
179 * Enable/Disable PSR.
180 */
dmub_psr_enable(struct dmub_psr * dmub,bool enable,bool wait,uint8_t panel_inst)181 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
182 {
183 union dmub_rb_cmd cmd;
184 struct dc_context *dc = dmub->ctx;
185 uint32_t retry_count;
186 enum dc_psr_state state = PSR_STATE0;
187
188 memset(&cmd, 0, sizeof(cmd));
189 cmd.psr_enable.header.type = DMUB_CMD__PSR;
190
191 cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
192 cmd.psr_enable.data.panel_inst = panel_inst;
193
194 if (enable)
195 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
196 else
197 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
198
199 cmd.psr_enable.header.payload_bytes = 0; // Send header only
200
201 dm_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
202
203 /* Below loops 1000 x 500us = 500 ms.
204 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
205 * least a few frames. Should never hit the max retry assert below.
206 */
207 if (wait) {
208 for (retry_count = 0; retry_count <= 1000; retry_count++) {
209 dmub_psr_get_state(dmub, &state, panel_inst);
210
211 if (enable) {
212 if (state != PSR_STATE0)
213 break;
214 } else {
215 if (state == PSR_STATE0)
216 break;
217 }
218
219 /* must *not* be fsleep - this can be called from high irq levels */
220 udelay(500);
221 }
222
223 /* assert if max retry hit */
224 if (retry_count >= 1000)
225 ASSERT(0);
226 }
227 }
228
229 /*
230 * Set PSR level.
231 */
dmub_psr_set_level(struct dmub_psr * dmub,uint16_t psr_level,uint8_t panel_inst)232 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
233 {
234 union dmub_rb_cmd cmd;
235 enum dc_psr_state state = PSR_STATE0;
236 struct dc_context *dc = dmub->ctx;
237
238 dmub_psr_get_state(dmub, &state, panel_inst);
239
240 if (state == PSR_STATE0)
241 return;
242
243 memset(&cmd, 0, sizeof(cmd));
244 cmd.psr_set_level.header.type = DMUB_CMD__PSR;
245 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
246 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
247 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
248 cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
249 cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
250 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
251 }
252
253 /*
254 * Set PSR vtotal requirement for FreeSync PSR.
255 */
dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr * dmub,uint16_t psr_vtotal_idle,uint16_t psr_vtotal_su)256 static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
257 uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
258 {
259 union dmub_rb_cmd cmd;
260 struct dc_context *dc = dmub->ctx;
261
262 memset(&cmd, 0, sizeof(cmd));
263 cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
264 cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
265 cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
266 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
267 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
268
269 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
270 }
271
272 /*
273 * Set PSR power optimization flags.
274 */
dmub_psr_set_power_opt(struct dmub_psr * dmub,unsigned int power_opt,uint8_t panel_inst)275 static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)
276 {
277 union dmub_rb_cmd cmd;
278 struct dc_context *dc = dmub->ctx;
279
280 memset(&cmd, 0, sizeof(cmd));
281 cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR;
282 cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT;
283 cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data);
284 cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
285 cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;
286 cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;
287
288 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
289 }
290
291 /*
292 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
293 */
dmub_psr_copy_settings(struct dmub_psr * dmub,struct dc_link * link,struct psr_context * psr_context,uint8_t panel_inst)294 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
295 struct dc_link *link,
296 struct psr_context *psr_context,
297 uint8_t panel_inst)
298 {
299 union dmub_rb_cmd cmd;
300 struct dc_context *dc = dmub->ctx;
301 struct dmub_cmd_psr_copy_settings_data *copy_settings_data
302 = &cmd.psr_copy_settings.psr_copy_settings_data;
303 struct pipe_ctx *pipe_ctx = NULL;
304 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
305 int i = 0;
306
307 for (i = 0; i < MAX_PIPES; i++) {
308 if (res_ctx->pipe_ctx[i].stream &&
309 res_ctx->pipe_ctx[i].stream->link == link &&
310 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
311 pipe_ctx = &res_ctx->pipe_ctx[i];
312 //TODO: refactor for multi edp support
313 break;
314 }
315 }
316
317 if (!pipe_ctx)
318 return false;
319
320 // First, set the psr version
321 if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
322 return false;
323
324 // Program DP DPHY fast training registers
325 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
326 psr_context->psrExitLinkTrainingRequired);
327
328 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
329 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
330 psr_context->sdpTransmitLineNumDeadline);
331
332 memset(&cmd, 0, sizeof(cmd));
333 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
334 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
335 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
336
337 // Hw insts
338 copy_settings_data->dpphy_inst = psr_context->transmitterId;
339 copy_settings_data->aux_inst = psr_context->channel;
340 copy_settings_data->digfe_inst = psr_context->engineId;
341 copy_settings_data->digbe_inst = psr_context->transmitterId;
342
343 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
344
345 if (pipe_ctx->plane_res.dpp)
346 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
347 else
348 copy_settings_data->dpp_inst = 0;
349 if (pipe_ctx->stream_res.opp)
350 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
351 else
352 copy_settings_data->opp_inst = 0;
353 if (pipe_ctx->stream_res.tg)
354 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
355 else
356 copy_settings_data->otg_inst = 0;
357
358 // Misc
359 copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;
360 copy_settings_data->psr_level = psr_context->psr_level.u32all;
361 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
362 copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
363 copy_settings_data->frame_delay = psr_context->frame_delay;
364 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
365 copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
366 copy_settings_data->debug.u32All = 0;
367 copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
368 copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1;
369 copy_settings_data->debug.bitfields.force_full_frame_update = 0;
370
371 if (psr_context->su_granularity_required == 0)
372 copy_settings_data->su_y_granularity = 0;
373 else
374 copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
375
376 copy_settings_data->line_capture_indication = 0;
377 copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
378 copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
379 copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
380 copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
381 copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
382 copy_settings_data->panel_inst = panel_inst;
383 copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
384
385 /**
386 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
387 * Note that PSRSU+DSC is still under development.
388 */
389 if (copy_settings_data->dsc_enable_status &&
390 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
391 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
392 sizeof(DP_SINK_DEVICE_STR_ID_1)))
393 link->psr_settings.force_ffu_mode = 1;
394 else
395 link->psr_settings.force_ffu_mode = 0;
396 copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
397
398 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
399 !link->dc->debug.disable_fec) &&
400 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
401 !link->panel_config.dsc.disable_dsc_edp &&
402 link->dc->caps.edp_dsc_support)) &&
403 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
404 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
405 sizeof(DP_SINK_DEVICE_STR_ID_1)) ||
406 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
407 sizeof(DP_SINK_DEVICE_STR_ID_2))))
408 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1;
409 else
410 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
411
412 //WA for PSR1 on specific TCON, require frame delay for frame re-lock
413 copy_settings_data->relock_delay_frame_cnt = 0;
414 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
415 copy_settings_data->relock_delay_frame_cnt = 2;
416 copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;
417
418 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
419
420 return true;
421 }
422
423 /*
424 * Send command to PSR to force static ENTER and ignore all state changes until exit
425 */
dmub_psr_force_static(struct dmub_psr * dmub,uint8_t panel_inst)426 static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
427 {
428 union dmub_rb_cmd cmd;
429 struct dc_context *dc = dmub->ctx;
430
431 memset(&cmd, 0, sizeof(cmd));
432
433 cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
434 cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
435 cmd.psr_force_static.header.type = DMUB_CMD__PSR;
436 cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
437 cmd.psr_enable.header.payload_bytes = 0;
438
439 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
440 }
441
442 /*
443 * Get PSR residency from firmware.
444 */
dmub_psr_get_residency(struct dmub_psr * dmub,uint32_t * residency,uint8_t panel_inst)445 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
446 {
447 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
448 uint16_t param = (uint16_t)(panel_inst << 8);
449
450 /* Send gpint command and wait for ack */
451 dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
452
453 dmub_srv_get_gpint_response(srv, residency);
454 }
455
456 static const struct dmub_psr_funcs psr_funcs = {
457 .psr_copy_settings = dmub_psr_copy_settings,
458 .psr_enable = dmub_psr_enable,
459 .psr_get_state = dmub_psr_get_state,
460 .psr_set_level = dmub_psr_set_level,
461 .psr_force_static = dmub_psr_force_static,
462 .psr_get_residency = dmub_psr_get_residency,
463 .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active,
464 .psr_set_power_opt = dmub_psr_set_power_opt,
465 };
466
467 /*
468 * Construct PSR object.
469 */
dmub_psr_construct(struct dmub_psr * psr,struct dc_context * ctx)470 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
471 {
472 psr->ctx = ctx;
473 psr->funcs = &psr_funcs;
474 }
475
476 /*
477 * Allocate and initialize PSR object.
478 */
dmub_psr_create(struct dc_context * ctx)479 struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
480 {
481 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
482
483 if (psr == NULL) {
484 BREAK_TO_DEBUGGER();
485 return NULL;
486 }
487
488 dmub_psr_construct(psr, ctx);
489
490 return psr;
491 }
492
493 /*
494 * Deallocate PSR object.
495 */
dmub_psr_destroy(struct dmub_psr ** dmub)496 void dmub_psr_destroy(struct dmub_psr **dmub)
497 {
498 kfree(*dmub);
499 *dmub = NULL;
500 }
501