1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 */
7
8 #include <common.h>
9 #include <pci.h>
10 #include <asm/processor.h>
11 #include <asm/mmu.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_pci.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <miiphy.h>
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
19 #include <tsec.h>
20 #include <fsl_mdio.h>
21 #include <netdev.h>
22
23 #include "../common/cadmus.h"
24 #include "../common/eeprom.h"
25 #include "../common/via.h"
26
27 void local_bus_init(void);
28
checkboard(void)29 int checkboard (void)
30 {
31 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
32 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
33
34 /* PCI slot in USER bits CSR[6:7] by convention. */
35 uint pci_slot = get_pci_slot ();
36
37 uint cpu_board_rev = get_cpu_board_revision ();
38
39 puts("Board: MPC8548CDS");
40 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
41 get_board_version(), pci_slot);
42 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
43 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
44 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
45 /*
46 * Initialize local bus.
47 */
48 local_bus_init ();
49
50 /*
51 * Hack TSEC 3 and 4 IO voltages.
52 */
53 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
54
55 ecm->eedr = 0xffffffff; /* clear ecm errors */
56 ecm->eeer = 0xffffffff; /* enable ecm errors */
57 return 0;
58 }
59
60 /*
61 * Initialize Local Bus
62 */
63 void
local_bus_init(void)64 local_bus_init(void)
65 {
66 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
67 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
68
69 uint clkdiv;
70 sys_info_t sysinfo;
71
72 get_sys_info(&sysinfo);
73 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
74
75 gur->lbiuiplldcr1 = 0x00078080;
76 if (clkdiv == 16) {
77 gur->lbiuiplldcr0 = 0x7c0f1bf0;
78 } else if (clkdiv == 8) {
79 gur->lbiuiplldcr0 = 0x6c0f1bf0;
80 } else if (clkdiv == 4) {
81 gur->lbiuiplldcr0 = 0x5c0f1bf0;
82 }
83
84 lbc->lcrr |= 0x00030000;
85
86 asm("sync;isync;msync");
87
88 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
89 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
90 }
91
92 /*
93 * Initialize SDRAM memory on the Local Bus.
94 */
lbc_sdram_init(void)95 void lbc_sdram_init(void)
96 {
97 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
98
99 uint idx;
100 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
101 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
102 uint lsdmr_common;
103
104 puts("LBC SDRAM: ");
105 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
106 "\n");
107
108 /*
109 * Setup SDRAM Base and Option Registers
110 */
111 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
112 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
113 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
114 asm("msync");
115
116 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
117 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
118 asm("msync");
119
120 /*
121 * MPC8548 uses "new" 15-16 style addressing.
122 */
123 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
124 lsdmr_common |= LSDMR_BSMA1516;
125
126 /*
127 * Issue PRECHARGE ALL command.
128 */
129 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
130 asm("sync;msync");
131 *sdram_addr = 0xff;
132 ppcDcbf((unsigned long) sdram_addr);
133 udelay(100);
134
135 /*
136 * Issue 8 AUTO REFRESH commands.
137 */
138 for (idx = 0; idx < 8; idx++) {
139 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
140 asm("sync;msync");
141 *sdram_addr = 0xff;
142 ppcDcbf((unsigned long) sdram_addr);
143 udelay(100);
144 }
145
146 /*
147 * Issue 8 MODE-set command.
148 */
149 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
150 asm("sync;msync");
151 *sdram_addr = 0xff;
152 ppcDcbf((unsigned long) sdram_addr);
153 udelay(100);
154
155 /*
156 * Issue NORMAL OP command.
157 */
158 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
159 asm("sync;msync");
160 *sdram_addr = 0xff;
161 ppcDcbf((unsigned long) sdram_addr);
162 udelay(200); /* Overkill. Must wait > 200 bus cycles */
163
164 #endif /* enable SDRAM init */
165 }
166
167 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
168 /* For some reason the Tundra PCI bridge shows up on itself as a
169 * different device. Work around that by refusing to configure it.
170 */
dummy_func(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * tab)171 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
172
173 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
174 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
175 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
176 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
177 mpc85xx_config_via_usbide, {0,0,0}},
178 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
179 mpc85xx_config_via_usb, {0,0,0}},
180 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
181 mpc85xx_config_via_usb2, {0,0,0}},
182 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
183 mpc85xx_config_via_power, {0,0,0}},
184 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
185 mpc85xx_config_via_ac97, {0,0,0}},
186 {},
187 };
188
189 static struct pci_controller pci1_hose;
190 #endif /* CONFIG_PCI */
191
pci_init_board(void)192 void pci_init_board(void)
193 {
194 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
195 struct fsl_pci_info pci_info;
196 u32 devdisr, pordevsr, io_sel;
197 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
198 int first_free_busno = 0;
199 char buf[32];
200
201 devdisr = in_be32(&gur->devdisr);
202 pordevsr = in_be32(&gur->pordevsr);
203 porpllsr = in_be32(&gur->porpllsr);
204 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
205
206 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
207
208 #ifdef CONFIG_PCI1
209 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
210 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
211 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
212 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
213
214 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
215 SET_STD_PCI_INFO(pci_info, 1);
216 set_next_law(pci_info.mem_phys,
217 law_size_bits(pci_info.mem_size), pci_info.law);
218 set_next_law(pci_info.io_phys,
219 law_size_bits(pci_info.io_size), pci_info.law);
220
221 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
222 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
223 (pci_32) ? 32 : 64,
224 strmhz(buf, pci_speed),
225 pci_clk_sel ? "sync" : "async",
226 pci_agent ? "agent" : "host",
227 pci_arb ? "arbiter" : "external-arbiter",
228 pci_info.regs);
229
230 pci1_hose.config_table = pci_mpc85xxcds_config_table;
231 first_free_busno = fsl_pci_init_port(&pci_info,
232 &pci1_hose, first_free_busno);
233
234 #ifdef CONFIG_PCIX_CHECK
235 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
236 /* PCI-X init */
237 if (CONFIG_SYS_CLK_FREQ < 66000000)
238 printf("PCI-X will only work at 66 MHz\n");
239
240 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
241 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
242 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
243 }
244 #endif
245 } else {
246 printf("PCI1: disabled\n");
247 }
248
249 puts("\n");
250 #else
251 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
252 #endif
253
254 #ifdef CONFIG_PCI2
255 {
256 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
257 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
258 if (pci_dual) {
259 printf("PCI2: 32 bit, 66 MHz, %s\n",
260 pci2_clk_sel ? "sync" : "async");
261 } else {
262 printf("PCI2: disabled\n");
263 }
264 }
265 #else
266 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
267 #endif /* CONFIG_PCI2 */
268
269 fsl_pcie_init_board(first_free_busno);
270 }
271
configure_rgmii(void)272 void configure_rgmii(void)
273 {
274 unsigned short temp;
275
276 /* Change the resistors for the PHY */
277 /* This is needed to get the RGMII working for the 1.3+
278 * CDS cards */
279 if (get_board_version() == 0x13) {
280 miiphy_write(DEFAULT_MII_NAME,
281 TSEC1_PHY_ADDR, 29, 18);
282
283 miiphy_read(DEFAULT_MII_NAME,
284 TSEC1_PHY_ADDR, 30, &temp);
285
286 temp = (temp & 0xf03f);
287 temp |= 2 << 9; /* 36 ohm */
288 temp |= 2 << 6; /* 39 ohm */
289
290 miiphy_write(DEFAULT_MII_NAME,
291 TSEC1_PHY_ADDR, 30, temp);
292
293 miiphy_write(DEFAULT_MII_NAME,
294 TSEC1_PHY_ADDR, 29, 3);
295
296 miiphy_write(DEFAULT_MII_NAME,
297 TSEC1_PHY_ADDR, 30, 0x8000);
298 }
299
300 return;
301 }
302
board_eth_init(bd_t * bis)303 int board_eth_init(bd_t *bis)
304 {
305 #ifdef CONFIG_TSEC_ENET
306 struct fsl_pq_mdio_info mdio_info;
307 struct tsec_info_struct tsec_info[4];
308 int num = 0;
309
310 #ifdef CONFIG_TSEC1
311 SET_STD_TSEC_INFO(tsec_info[num], 1);
312 num++;
313 #endif
314 #ifdef CONFIG_TSEC2
315 SET_STD_TSEC_INFO(tsec_info[num], 2);
316 num++;
317 #endif
318 #ifdef CONFIG_TSEC3
319 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
320 if (get_board_version() >= 0x13) {
321 SET_STD_TSEC_INFO(tsec_info[num], 3);
322 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
323 num++;
324 }
325 #endif
326 #ifdef CONFIG_TSEC4
327 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
328 if (get_board_version() >= 0x13) {
329 SET_STD_TSEC_INFO(tsec_info[num], 4);
330 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
331 num++;
332 }
333 #endif
334
335 if (!num) {
336 printf("No TSECs initialized\n");
337
338 return 0;
339 }
340
341 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
342 mdio_info.name = DEFAULT_MII_NAME;
343 fsl_pq_mdio_init(bis, &mdio_info);
344
345 tsec_eth_init(bis, tsec_info, num);
346 configure_rgmii();
347 #endif
348
349 return pci_eth_init(bis);
350 }
351
352 #if defined(CONFIG_OF_BOARD_SETUP)
ft_pci_setup(void * blob,bd_t * bd)353 void ft_pci_setup(void *blob, bd_t *bd)
354 {
355 FT_FSL_PCI_SETUP;
356 }
357 #endif
358