1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 17 #define PWRAP_POLL_DELAY_US 10 18 #define PWRAP_POLL_TIMEOUT_US 10000 19 20 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 21 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 22 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 23 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 24 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 25 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38 26 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 27 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 28 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 29 30 /* macro for wrapper status */ 31 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) 32 #define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007) 33 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) 34 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 35 #define PWRAP_STATE_SYNC_IDLE0 BIT(20) 36 #define PWRAP_STATE_INIT_DONE0 BIT(21) 37 #define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) 38 #define PWRAP_STATE_INIT_DONE1 BIT(15) 39 40 /* macro for WACS FSM */ 41 #define PWRAP_WACS_FSM_IDLE 0x00 42 #define PWRAP_WACS_FSM_REQ 0x02 43 #define PWRAP_WACS_FSM_WFDLE 0x04 44 #define PWRAP_WACS_FSM_WFVLDCLR 0x06 45 #define PWRAP_WACS_INIT_DONE 0x01 46 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01 47 #define PWRAP_WACS_SYNC_BUSY 0x00 48 49 /* macro for device wrapper default value */ 50 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 51 #define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a 52 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 53 54 /* macro for manual command */ 55 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14) 56 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 57 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 58 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 59 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8) 60 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) 61 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8) 62 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) 63 64 /* macro for Watch Dog Timer Source */ 65 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25) 66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20) 67 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6) 68 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff 69 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \ 70 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 71 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 72 73 /* Group of bits used for shown slave capability */ 74 #define PWRAP_SLV_CAP_SPI BIT(0) 75 #define PWRAP_SLV_CAP_DUALIO BIT(1) 76 #define PWRAP_SLV_CAP_SECURITY BIT(2) 77 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) 78 79 /* Group of bits used for shown pwrap capability */ 80 #define PWRAP_CAP_BRIDGE BIT(0) 81 #define PWRAP_CAP_RESET BIT(1) 82 #define PWRAP_CAP_DCM BIT(2) 83 #define PWRAP_CAP_INT1_EN BIT(3) 84 #define PWRAP_CAP_WDT_SRC1 BIT(4) 85 #define PWRAP_CAP_ARB BIT(5) 86 #define PWRAP_CAP_ARB_MT8186 BIT(8) 87 88 /* defines for slave device wrapper registers */ 89 enum dew_regs { 90 PWRAP_DEW_BASE, 91 PWRAP_DEW_DIO_EN, 92 PWRAP_DEW_READ_TEST, 93 PWRAP_DEW_WRITE_TEST, 94 PWRAP_DEW_CRC_EN, 95 PWRAP_DEW_CRC_VAL, 96 PWRAP_DEW_MON_GRP_SEL, 97 PWRAP_DEW_CIPHER_KEY_SEL, 98 PWRAP_DEW_CIPHER_IV_SEL, 99 PWRAP_DEW_CIPHER_RDY, 100 PWRAP_DEW_CIPHER_MODE, 101 PWRAP_DEW_CIPHER_SWRST, 102 103 /* MT6323 only regs */ 104 PWRAP_DEW_CIPHER_EN, 105 PWRAP_DEW_RDDMY_NO, 106 107 /* MT6358 only regs */ 108 PWRAP_SMT_CON1, 109 PWRAP_DRV_CON1, 110 PWRAP_FILTER_CON0, 111 PWRAP_GPIO_PULLEN0_CLR, 112 PWRAP_RG_SPI_CON0, 113 PWRAP_RG_SPI_RECORD0, 114 PWRAP_RG_SPI_CON2, 115 PWRAP_RG_SPI_CON3, 116 PWRAP_RG_SPI_CON4, 117 PWRAP_RG_SPI_CON5, 118 PWRAP_RG_SPI_CON6, 119 PWRAP_RG_SPI_CON7, 120 PWRAP_RG_SPI_CON8, 121 PWRAP_RG_SPI_CON13, 122 PWRAP_SPISLV_KEY, 123 124 /* MT6359 only regs */ 125 PWRAP_DEW_CRC_SWRST, 126 PWRAP_DEW_RG_EN_RECORD, 127 PWRAP_DEW_RECORD_CMD0, 128 PWRAP_DEW_RECORD_CMD1, 129 PWRAP_DEW_RECORD_CMD2, 130 PWRAP_DEW_RECORD_CMD3, 131 PWRAP_DEW_RECORD_CMD4, 132 PWRAP_DEW_RECORD_CMD5, 133 PWRAP_DEW_RECORD_WDATA0, 134 PWRAP_DEW_RECORD_WDATA1, 135 PWRAP_DEW_RECORD_WDATA2, 136 PWRAP_DEW_RECORD_WDATA3, 137 PWRAP_DEW_RECORD_WDATA4, 138 PWRAP_DEW_RECORD_WDATA5, 139 PWRAP_DEW_RG_ADDR_TARGET, 140 PWRAP_DEW_RG_ADDR_MASK, 141 PWRAP_DEW_RG_WDATA_TARGET, 142 PWRAP_DEW_RG_WDATA_MASK, 143 PWRAP_DEW_RG_SPI_RECORD_CLR, 144 PWRAP_DEW_RG_CMD_ALERT_CLR, 145 146 /* MT6397 only regs */ 147 PWRAP_DEW_EVENT_OUT_EN, 148 PWRAP_DEW_EVENT_SRC_EN, 149 PWRAP_DEW_EVENT_SRC, 150 PWRAP_DEW_EVENT_FLAG, 151 PWRAP_DEW_MON_FLAG_SEL, 152 PWRAP_DEW_EVENT_TEST, 153 PWRAP_DEW_CIPHER_LOAD, 154 PWRAP_DEW_CIPHER_START, 155 }; 156 157 static const u32 mt6323_regs[] = { 158 [PWRAP_DEW_BASE] = 0x0000, 159 [PWRAP_DEW_DIO_EN] = 0x018a, 160 [PWRAP_DEW_READ_TEST] = 0x018c, 161 [PWRAP_DEW_WRITE_TEST] = 0x018e, 162 [PWRAP_DEW_CRC_EN] = 0x0192, 163 [PWRAP_DEW_CRC_VAL] = 0x0194, 164 [PWRAP_DEW_MON_GRP_SEL] = 0x0196, 165 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198, 166 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a, 167 [PWRAP_DEW_CIPHER_EN] = 0x019c, 168 [PWRAP_DEW_CIPHER_RDY] = 0x019e, 169 [PWRAP_DEW_CIPHER_MODE] = 0x01a0, 170 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2, 171 [PWRAP_DEW_RDDMY_NO] = 0x01a4, 172 }; 173 174 static const u32 mt6331_regs[] = { 175 [PWRAP_DEW_DIO_EN] = 0x018c, 176 [PWRAP_DEW_READ_TEST] = 0x018e, 177 [PWRAP_DEW_WRITE_TEST] = 0x0190, 178 [PWRAP_DEW_CRC_SWRST] = 0x0192, 179 [PWRAP_DEW_CRC_EN] = 0x0194, 180 [PWRAP_DEW_CRC_VAL] = 0x0196, 181 [PWRAP_DEW_MON_GRP_SEL] = 0x0198, 182 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a, 183 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c, 184 [PWRAP_DEW_CIPHER_EN] = 0x019e, 185 [PWRAP_DEW_CIPHER_RDY] = 0x01a0, 186 [PWRAP_DEW_CIPHER_MODE] = 0x01a2, 187 [PWRAP_DEW_CIPHER_SWRST] = 0x01a4, 188 [PWRAP_DEW_RDDMY_NO] = 0x01a6, 189 }; 190 191 static const u32 mt6332_regs[] = { 192 [PWRAP_DEW_DIO_EN] = 0x80f6, 193 [PWRAP_DEW_READ_TEST] = 0x80f8, 194 [PWRAP_DEW_WRITE_TEST] = 0x80fa, 195 [PWRAP_DEW_CRC_SWRST] = 0x80fc, 196 [PWRAP_DEW_CRC_EN] = 0x80fe, 197 [PWRAP_DEW_CRC_VAL] = 0x8100, 198 [PWRAP_DEW_MON_GRP_SEL] = 0x8102, 199 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104, 200 [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106, 201 [PWRAP_DEW_CIPHER_EN] = 0x8108, 202 [PWRAP_DEW_CIPHER_RDY] = 0x810a, 203 [PWRAP_DEW_CIPHER_MODE] = 0x810c, 204 [PWRAP_DEW_CIPHER_SWRST] = 0x810e, 205 [PWRAP_DEW_RDDMY_NO] = 0x8110, 206 }; 207 208 static const u32 mt6351_regs[] = { 209 [PWRAP_DEW_DIO_EN] = 0x02F2, 210 [PWRAP_DEW_READ_TEST] = 0x02F4, 211 [PWRAP_DEW_WRITE_TEST] = 0x02F6, 212 [PWRAP_DEW_CRC_EN] = 0x02FA, 213 [PWRAP_DEW_CRC_VAL] = 0x02FC, 214 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, 215 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, 216 [PWRAP_DEW_CIPHER_EN] = 0x0304, 217 [PWRAP_DEW_CIPHER_RDY] = 0x0306, 218 [PWRAP_DEW_CIPHER_MODE] = 0x0308, 219 [PWRAP_DEW_CIPHER_SWRST] = 0x030A, 220 [PWRAP_DEW_RDDMY_NO] = 0x030C, 221 }; 222 223 static const u32 mt6357_regs[] = { 224 [PWRAP_DEW_DIO_EN] = 0x040A, 225 [PWRAP_DEW_READ_TEST] = 0x040C, 226 [PWRAP_DEW_WRITE_TEST] = 0x040E, 227 [PWRAP_DEW_CRC_EN] = 0x0412, 228 [PWRAP_DEW_CRC_VAL] = 0x0414, 229 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 230 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, 231 [PWRAP_DEW_CIPHER_EN] = 0x041C, 232 [PWRAP_DEW_CIPHER_RDY] = 0x041E, 233 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 234 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 235 [PWRAP_DEW_RDDMY_NO] = 0x0424, 236 }; 237 238 static const u32 mt6358_regs[] = { 239 [PWRAP_SMT_CON1] = 0x0030, 240 [PWRAP_DRV_CON1] = 0x0038, 241 [PWRAP_FILTER_CON0] = 0x0040, 242 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, 243 [PWRAP_RG_SPI_CON0] = 0x0408, 244 [PWRAP_RG_SPI_RECORD0] = 0x040a, 245 [PWRAP_DEW_DIO_EN] = 0x040c, 246 [PWRAP_DEW_READ_TEST] = 0x040e, 247 [PWRAP_DEW_WRITE_TEST] = 0x0410, 248 [PWRAP_DEW_CRC_EN] = 0x0414, 249 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, 250 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, 251 [PWRAP_DEW_CIPHER_EN] = 0x041e, 252 [PWRAP_DEW_CIPHER_RDY] = 0x0420, 253 [PWRAP_DEW_CIPHER_MODE] = 0x0422, 254 [PWRAP_DEW_CIPHER_SWRST] = 0x0424, 255 [PWRAP_RG_SPI_CON2] = 0x0432, 256 [PWRAP_RG_SPI_CON3] = 0x0434, 257 [PWRAP_RG_SPI_CON4] = 0x0436, 258 [PWRAP_RG_SPI_CON5] = 0x0438, 259 [PWRAP_RG_SPI_CON6] = 0x043a, 260 [PWRAP_RG_SPI_CON7] = 0x043c, 261 [PWRAP_RG_SPI_CON8] = 0x043e, 262 [PWRAP_RG_SPI_CON13] = 0x0448, 263 [PWRAP_SPISLV_KEY] = 0x044a, 264 }; 265 266 static const u32 mt6359_regs[] = { 267 [PWRAP_DEW_RG_EN_RECORD] = 0x040a, 268 [PWRAP_DEW_DIO_EN] = 0x040c, 269 [PWRAP_DEW_READ_TEST] = 0x040e, 270 [PWRAP_DEW_WRITE_TEST] = 0x0410, 271 [PWRAP_DEW_CRC_SWRST] = 0x0412, 272 [PWRAP_DEW_CRC_EN] = 0x0414, 273 [PWRAP_DEW_CRC_VAL] = 0x0416, 274 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 275 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, 276 [PWRAP_DEW_CIPHER_EN] = 0x041c, 277 [PWRAP_DEW_CIPHER_RDY] = 0x041e, 278 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 279 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 280 [PWRAP_DEW_RDDMY_NO] = 0x0424, 281 [PWRAP_DEW_RECORD_CMD0] = 0x0428, 282 [PWRAP_DEW_RECORD_CMD1] = 0x042a, 283 [PWRAP_DEW_RECORD_CMD2] = 0x042c, 284 [PWRAP_DEW_RECORD_CMD3] = 0x042e, 285 [PWRAP_DEW_RECORD_CMD4] = 0x0430, 286 [PWRAP_DEW_RECORD_CMD5] = 0x0432, 287 [PWRAP_DEW_RECORD_WDATA0] = 0x0434, 288 [PWRAP_DEW_RECORD_WDATA1] = 0x0436, 289 [PWRAP_DEW_RECORD_WDATA2] = 0x0438, 290 [PWRAP_DEW_RECORD_WDATA3] = 0x043a, 291 [PWRAP_DEW_RECORD_WDATA4] = 0x043c, 292 [PWRAP_DEW_RECORD_WDATA5] = 0x043e, 293 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, 294 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, 295 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, 296 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, 297 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, 298 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, 299 [PWRAP_SPISLV_KEY] = 0x044a, 300 }; 301 302 static const u32 mt6397_regs[] = { 303 [PWRAP_DEW_BASE] = 0xbc00, 304 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00, 305 [PWRAP_DEW_DIO_EN] = 0xbc02, 306 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04, 307 [PWRAP_DEW_EVENT_SRC] = 0xbc06, 308 [PWRAP_DEW_EVENT_FLAG] = 0xbc08, 309 [PWRAP_DEW_READ_TEST] = 0xbc0a, 310 [PWRAP_DEW_WRITE_TEST] = 0xbc0c, 311 [PWRAP_DEW_CRC_EN] = 0xbc0e, 312 [PWRAP_DEW_CRC_VAL] = 0xbc10, 313 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12, 314 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14, 315 [PWRAP_DEW_EVENT_TEST] = 0xbc16, 316 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18, 317 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a, 318 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c, 319 [PWRAP_DEW_CIPHER_START] = 0xbc1e, 320 [PWRAP_DEW_CIPHER_RDY] = 0xbc20, 321 [PWRAP_DEW_CIPHER_MODE] = 0xbc22, 322 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, 323 }; 324 325 enum pwrap_regs { 326 PWRAP_MUX_SEL, 327 PWRAP_WRAP_EN, 328 PWRAP_DIO_EN, 329 PWRAP_SIDLY, 330 PWRAP_CSHEXT_WRITE, 331 PWRAP_CSHEXT_READ, 332 PWRAP_CSLEXT_START, 333 PWRAP_CSLEXT_END, 334 PWRAP_STAUPD_PRD, 335 PWRAP_STAUPD_GRPEN, 336 PWRAP_STAUPD_MAN_TRIG, 337 PWRAP_STAUPD_STA, 338 PWRAP_WRAP_STA, 339 PWRAP_HARB_INIT, 340 PWRAP_HARB_HPRIO, 341 PWRAP_HIPRIO_ARB_EN, 342 PWRAP_HARB_STA0, 343 PWRAP_HARB_STA1, 344 PWRAP_MAN_EN, 345 PWRAP_MAN_CMD, 346 PWRAP_MAN_RDATA, 347 PWRAP_MAN_VLDCLR, 348 PWRAP_WACS0_EN, 349 PWRAP_INIT_DONE0, 350 PWRAP_WACS0_CMD, 351 PWRAP_WACS0_RDATA, 352 PWRAP_WACS0_VLDCLR, 353 PWRAP_WACS1_EN, 354 PWRAP_INIT_DONE1, 355 PWRAP_WACS1_CMD, 356 PWRAP_WACS1_RDATA, 357 PWRAP_WACS1_VLDCLR, 358 PWRAP_WACS2_EN, 359 PWRAP_INIT_DONE2, 360 PWRAP_WACS2_CMD, 361 PWRAP_WACS2_RDATA, 362 PWRAP_WACS2_VLDCLR, 363 PWRAP_INT_EN, 364 PWRAP_INT_FLG_RAW, 365 PWRAP_INT_FLG, 366 PWRAP_INT_CLR, 367 PWRAP_SIG_ADR, 368 PWRAP_SIG_MODE, 369 PWRAP_SIG_VALUE, 370 PWRAP_SIG_ERRVAL, 371 PWRAP_CRC_EN, 372 PWRAP_TIMER_EN, 373 PWRAP_TIMER_STA, 374 PWRAP_WDT_UNIT, 375 PWRAP_WDT_SRC_EN, 376 PWRAP_WDT_FLG, 377 PWRAP_DEBUG_INT_SEL, 378 PWRAP_CIPHER_KEY_SEL, 379 PWRAP_CIPHER_IV_SEL, 380 PWRAP_CIPHER_RDY, 381 PWRAP_CIPHER_MODE, 382 PWRAP_CIPHER_SWRST, 383 PWRAP_DCM_EN, 384 PWRAP_DCM_DBC_PRD, 385 PWRAP_EINT_STA0_ADR, 386 PWRAP_EINT_STA1_ADR, 387 PWRAP_SWINF_2_WDATA_31_0, 388 PWRAP_SWINF_2_RDATA_31_0, 389 390 /* MT2701 only regs */ 391 PWRAP_ADC_CMD_ADDR, 392 PWRAP_PWRAP_ADC_CMD, 393 PWRAP_ADC_RDY_ADDR, 394 PWRAP_ADC_RDATA_ADDR1, 395 PWRAP_ADC_RDATA_ADDR2, 396 397 /* MT7622 only regs */ 398 PWRAP_STA, 399 PWRAP_CLR, 400 PWRAP_DVFS_ADR8, 401 PWRAP_DVFS_WDATA8, 402 PWRAP_DVFS_ADR9, 403 PWRAP_DVFS_WDATA9, 404 PWRAP_DVFS_ADR10, 405 PWRAP_DVFS_WDATA10, 406 PWRAP_DVFS_ADR11, 407 PWRAP_DVFS_WDATA11, 408 PWRAP_DVFS_ADR12, 409 PWRAP_DVFS_WDATA12, 410 PWRAP_DVFS_ADR13, 411 PWRAP_DVFS_WDATA13, 412 PWRAP_DVFS_ADR14, 413 PWRAP_DVFS_WDATA14, 414 PWRAP_DVFS_ADR15, 415 PWRAP_DVFS_WDATA15, 416 PWRAP_EXT_CK, 417 PWRAP_ADC_RDATA_ADDR, 418 PWRAP_GPS_STA, 419 PWRAP_SW_RST, 420 PWRAP_DVFS_STEP_CTRL0, 421 PWRAP_DVFS_STEP_CTRL1, 422 PWRAP_DVFS_STEP_CTRL2, 423 PWRAP_SPI2_CTRL, 424 425 /* MT8135 only regs */ 426 PWRAP_CSHEXT, 427 PWRAP_EVENT_IN_EN, 428 PWRAP_EVENT_DST_EN, 429 PWRAP_RRARB_INIT, 430 PWRAP_RRARB_EN, 431 PWRAP_RRARB_STA0, 432 PWRAP_RRARB_STA1, 433 PWRAP_EVENT_STA, 434 PWRAP_EVENT_STACLR, 435 PWRAP_CIPHER_LOAD, 436 PWRAP_CIPHER_START, 437 438 /* MT8173 only regs */ 439 PWRAP_RDDMY, 440 PWRAP_SI_CK_CON, 441 PWRAP_DVFS_ADR0, 442 PWRAP_DVFS_WDATA0, 443 PWRAP_DVFS_ADR1, 444 PWRAP_DVFS_WDATA1, 445 PWRAP_DVFS_ADR2, 446 PWRAP_DVFS_WDATA2, 447 PWRAP_DVFS_ADR3, 448 PWRAP_DVFS_WDATA3, 449 PWRAP_DVFS_ADR4, 450 PWRAP_DVFS_WDATA4, 451 PWRAP_DVFS_ADR5, 452 PWRAP_DVFS_WDATA5, 453 PWRAP_DVFS_ADR6, 454 PWRAP_DVFS_WDATA6, 455 PWRAP_DVFS_ADR7, 456 PWRAP_DVFS_WDATA7, 457 PWRAP_SPMINF_STA, 458 PWRAP_CIPHER_EN, 459 460 /* MT8183 only regs */ 461 PWRAP_SI_SAMPLE_CTRL, 462 PWRAP_CSLEXT_WRITE, 463 PWRAP_CSLEXT_READ, 464 PWRAP_EXT_CK_WRITE, 465 PWRAP_STAUPD_CTRL, 466 PWRAP_WACS_P2P_EN, 467 PWRAP_INIT_DONE_P2P, 468 PWRAP_WACS_MD32_EN, 469 PWRAP_INIT_DONE_MD32, 470 PWRAP_INT1_EN, 471 PWRAP_INT1_FLG, 472 PWRAP_INT1_CLR, 473 PWRAP_WDT_SRC_EN_1, 474 PWRAP_INT_GPS_AUXADC_CMD_ADDR, 475 PWRAP_INT_GPS_AUXADC_CMD, 476 PWRAP_INT_GPS_AUXADC_RDATA_ADDR, 477 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR, 478 PWRAP_GPSINF_0_STA, 479 PWRAP_GPSINF_1_STA, 480 481 /* MT8516 only regs */ 482 PWRAP_OP_TYPE, 483 PWRAP_MSB_FIRST, 484 }; 485 486 static int mt2701_regs[] = { 487 [PWRAP_MUX_SEL] = 0x0, 488 [PWRAP_WRAP_EN] = 0x4, 489 [PWRAP_DIO_EN] = 0x8, 490 [PWRAP_SIDLY] = 0xc, 491 [PWRAP_RDDMY] = 0x18, 492 [PWRAP_SI_CK_CON] = 0x1c, 493 [PWRAP_CSHEXT_WRITE] = 0x20, 494 [PWRAP_CSHEXT_READ] = 0x24, 495 [PWRAP_CSLEXT_START] = 0x28, 496 [PWRAP_CSLEXT_END] = 0x2c, 497 [PWRAP_STAUPD_PRD] = 0x30, 498 [PWRAP_STAUPD_GRPEN] = 0x34, 499 [PWRAP_STAUPD_MAN_TRIG] = 0x38, 500 [PWRAP_STAUPD_STA] = 0x3c, 501 [PWRAP_WRAP_STA] = 0x44, 502 [PWRAP_HARB_INIT] = 0x48, 503 [PWRAP_HARB_HPRIO] = 0x4c, 504 [PWRAP_HIPRIO_ARB_EN] = 0x50, 505 [PWRAP_HARB_STA0] = 0x54, 506 [PWRAP_HARB_STA1] = 0x58, 507 [PWRAP_MAN_EN] = 0x5c, 508 [PWRAP_MAN_CMD] = 0x60, 509 [PWRAP_MAN_RDATA] = 0x64, 510 [PWRAP_MAN_VLDCLR] = 0x68, 511 [PWRAP_WACS0_EN] = 0x6c, 512 [PWRAP_INIT_DONE0] = 0x70, 513 [PWRAP_WACS0_CMD] = 0x74, 514 [PWRAP_WACS0_RDATA] = 0x78, 515 [PWRAP_WACS0_VLDCLR] = 0x7c, 516 [PWRAP_WACS1_EN] = 0x80, 517 [PWRAP_INIT_DONE1] = 0x84, 518 [PWRAP_WACS1_CMD] = 0x88, 519 [PWRAP_WACS1_RDATA] = 0x8c, 520 [PWRAP_WACS1_VLDCLR] = 0x90, 521 [PWRAP_WACS2_EN] = 0x94, 522 [PWRAP_INIT_DONE2] = 0x98, 523 [PWRAP_WACS2_CMD] = 0x9c, 524 [PWRAP_WACS2_RDATA] = 0xa0, 525 [PWRAP_WACS2_VLDCLR] = 0xa4, 526 [PWRAP_INT_EN] = 0xa8, 527 [PWRAP_INT_FLG_RAW] = 0xac, 528 [PWRAP_INT_FLG] = 0xb0, 529 [PWRAP_INT_CLR] = 0xb4, 530 [PWRAP_SIG_ADR] = 0xb8, 531 [PWRAP_SIG_MODE] = 0xbc, 532 [PWRAP_SIG_VALUE] = 0xc0, 533 [PWRAP_SIG_ERRVAL] = 0xc4, 534 [PWRAP_CRC_EN] = 0xc8, 535 [PWRAP_TIMER_EN] = 0xcc, 536 [PWRAP_TIMER_STA] = 0xd0, 537 [PWRAP_WDT_UNIT] = 0xd4, 538 [PWRAP_WDT_SRC_EN] = 0xd8, 539 [PWRAP_WDT_FLG] = 0xdc, 540 [PWRAP_DEBUG_INT_SEL] = 0xe0, 541 [PWRAP_DVFS_ADR0] = 0xe4, 542 [PWRAP_DVFS_WDATA0] = 0xe8, 543 [PWRAP_DVFS_ADR1] = 0xec, 544 [PWRAP_DVFS_WDATA1] = 0xf0, 545 [PWRAP_DVFS_ADR2] = 0xf4, 546 [PWRAP_DVFS_WDATA2] = 0xf8, 547 [PWRAP_DVFS_ADR3] = 0xfc, 548 [PWRAP_DVFS_WDATA3] = 0x100, 549 [PWRAP_DVFS_ADR4] = 0x104, 550 [PWRAP_DVFS_WDATA4] = 0x108, 551 [PWRAP_DVFS_ADR5] = 0x10c, 552 [PWRAP_DVFS_WDATA5] = 0x110, 553 [PWRAP_DVFS_ADR6] = 0x114, 554 [PWRAP_DVFS_WDATA6] = 0x118, 555 [PWRAP_DVFS_ADR7] = 0x11c, 556 [PWRAP_DVFS_WDATA7] = 0x120, 557 [PWRAP_CIPHER_KEY_SEL] = 0x124, 558 [PWRAP_CIPHER_IV_SEL] = 0x128, 559 [PWRAP_CIPHER_EN] = 0x12c, 560 [PWRAP_CIPHER_RDY] = 0x130, 561 [PWRAP_CIPHER_MODE] = 0x134, 562 [PWRAP_CIPHER_SWRST] = 0x138, 563 [PWRAP_DCM_EN] = 0x13c, 564 [PWRAP_DCM_DBC_PRD] = 0x140, 565 [PWRAP_ADC_CMD_ADDR] = 0x144, 566 [PWRAP_PWRAP_ADC_CMD] = 0x148, 567 [PWRAP_ADC_RDY_ADDR] = 0x14c, 568 [PWRAP_ADC_RDATA_ADDR1] = 0x150, 569 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 570 }; 571 572 static int mt6765_regs[] = { 573 [PWRAP_MUX_SEL] = 0x0, 574 [PWRAP_WRAP_EN] = 0x4, 575 [PWRAP_DIO_EN] = 0x8, 576 [PWRAP_RDDMY] = 0x20, 577 [PWRAP_CSHEXT_WRITE] = 0x24, 578 [PWRAP_CSHEXT_READ] = 0x28, 579 [PWRAP_CSLEXT_START] = 0x2C, 580 [PWRAP_CSLEXT_END] = 0x30, 581 [PWRAP_STAUPD_PRD] = 0x3C, 582 [PWRAP_HARB_HPRIO] = 0x68, 583 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 584 [PWRAP_MAN_EN] = 0x7C, 585 [PWRAP_MAN_CMD] = 0x80, 586 [PWRAP_WACS0_EN] = 0x8C, 587 [PWRAP_WACS1_EN] = 0x94, 588 [PWRAP_WACS2_EN] = 0x9C, 589 [PWRAP_INIT_DONE2] = 0xA0, 590 [PWRAP_WACS2_CMD] = 0xC20, 591 [PWRAP_WACS2_RDATA] = 0xC24, 592 [PWRAP_WACS2_VLDCLR] = 0xC28, 593 [PWRAP_INT_EN] = 0xB4, 594 [PWRAP_INT_FLG_RAW] = 0xB8, 595 [PWRAP_INT_FLG] = 0xBC, 596 [PWRAP_INT_CLR] = 0xC0, 597 [PWRAP_TIMER_EN] = 0xE8, 598 [PWRAP_WDT_UNIT] = 0xF0, 599 [PWRAP_WDT_SRC_EN] = 0xF4, 600 [PWRAP_DCM_EN] = 0x1DC, 601 [PWRAP_DCM_DBC_PRD] = 0x1E0, 602 }; 603 604 static int mt6779_regs[] = { 605 [PWRAP_MUX_SEL] = 0x0, 606 [PWRAP_WRAP_EN] = 0x4, 607 [PWRAP_DIO_EN] = 0x8, 608 [PWRAP_RDDMY] = 0x20, 609 [PWRAP_CSHEXT_WRITE] = 0x24, 610 [PWRAP_CSHEXT_READ] = 0x28, 611 [PWRAP_CSLEXT_WRITE] = 0x2C, 612 [PWRAP_CSLEXT_READ] = 0x30, 613 [PWRAP_EXT_CK_WRITE] = 0x34, 614 [PWRAP_STAUPD_CTRL] = 0x3C, 615 [PWRAP_STAUPD_GRPEN] = 0x40, 616 [PWRAP_EINT_STA0_ADR] = 0x44, 617 [PWRAP_HARB_HPRIO] = 0x68, 618 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 619 [PWRAP_MAN_EN] = 0x7C, 620 [PWRAP_MAN_CMD] = 0x80, 621 [PWRAP_WACS0_EN] = 0x8C, 622 [PWRAP_INIT_DONE0] = 0x90, 623 [PWRAP_WACS1_EN] = 0x94, 624 [PWRAP_WACS2_EN] = 0x9C, 625 [PWRAP_INIT_DONE1] = 0x98, 626 [PWRAP_INIT_DONE2] = 0xA0, 627 [PWRAP_INT_EN] = 0xBC, 628 [PWRAP_INT_FLG_RAW] = 0xC0, 629 [PWRAP_INT_FLG] = 0xC4, 630 [PWRAP_INT_CLR] = 0xC8, 631 [PWRAP_INT1_EN] = 0xCC, 632 [PWRAP_INT1_FLG] = 0xD4, 633 [PWRAP_INT1_CLR] = 0xD8, 634 [PWRAP_TIMER_EN] = 0xF0, 635 [PWRAP_WDT_UNIT] = 0xF8, 636 [PWRAP_WDT_SRC_EN] = 0xFC, 637 [PWRAP_WDT_SRC_EN_1] = 0x100, 638 [PWRAP_WACS2_CMD] = 0xC20, 639 [PWRAP_WACS2_RDATA] = 0xC24, 640 [PWRAP_WACS2_VLDCLR] = 0xC28, 641 }; 642 643 static int mt6795_regs[] = { 644 [PWRAP_MUX_SEL] = 0x0, 645 [PWRAP_WRAP_EN] = 0x4, 646 [PWRAP_DIO_EN] = 0x8, 647 [PWRAP_SIDLY] = 0xc, 648 [PWRAP_RDDMY] = 0x10, 649 [PWRAP_SI_CK_CON] = 0x14, 650 [PWRAP_CSHEXT_WRITE] = 0x18, 651 [PWRAP_CSHEXT_READ] = 0x1c, 652 [PWRAP_CSLEXT_START] = 0x20, 653 [PWRAP_CSLEXT_END] = 0x24, 654 [PWRAP_STAUPD_PRD] = 0x28, 655 [PWRAP_STAUPD_GRPEN] = 0x2c, 656 [PWRAP_EINT_STA0_ADR] = 0x30, 657 [PWRAP_EINT_STA1_ADR] = 0x34, 658 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 659 [PWRAP_STAUPD_STA] = 0x44, 660 [PWRAP_WRAP_STA] = 0x48, 661 [PWRAP_HARB_INIT] = 0x4c, 662 [PWRAP_HARB_HPRIO] = 0x50, 663 [PWRAP_HIPRIO_ARB_EN] = 0x54, 664 [PWRAP_HARB_STA0] = 0x58, 665 [PWRAP_HARB_STA1] = 0x5c, 666 [PWRAP_MAN_EN] = 0x60, 667 [PWRAP_MAN_CMD] = 0x64, 668 [PWRAP_MAN_RDATA] = 0x68, 669 [PWRAP_MAN_VLDCLR] = 0x6c, 670 [PWRAP_WACS0_EN] = 0x70, 671 [PWRAP_INIT_DONE0] = 0x74, 672 [PWRAP_WACS0_CMD] = 0x78, 673 [PWRAP_WACS0_RDATA] = 0x7c, 674 [PWRAP_WACS0_VLDCLR] = 0x80, 675 [PWRAP_WACS1_EN] = 0x84, 676 [PWRAP_INIT_DONE1] = 0x88, 677 [PWRAP_WACS1_CMD] = 0x8c, 678 [PWRAP_WACS1_RDATA] = 0x90, 679 [PWRAP_WACS1_VLDCLR] = 0x94, 680 [PWRAP_WACS2_EN] = 0x98, 681 [PWRAP_INIT_DONE2] = 0x9c, 682 [PWRAP_WACS2_CMD] = 0xa0, 683 [PWRAP_WACS2_RDATA] = 0xa4, 684 [PWRAP_WACS2_VLDCLR] = 0xa8, 685 [PWRAP_INT_EN] = 0xac, 686 [PWRAP_INT_FLG_RAW] = 0xb0, 687 [PWRAP_INT_FLG] = 0xb4, 688 [PWRAP_INT_CLR] = 0xb8, 689 [PWRAP_SIG_ADR] = 0xbc, 690 [PWRAP_SIG_MODE] = 0xc0, 691 [PWRAP_SIG_VALUE] = 0xc4, 692 [PWRAP_SIG_ERRVAL] = 0xc8, 693 [PWRAP_CRC_EN] = 0xcc, 694 [PWRAP_TIMER_EN] = 0xd0, 695 [PWRAP_TIMER_STA] = 0xd4, 696 [PWRAP_WDT_UNIT] = 0xd8, 697 [PWRAP_WDT_SRC_EN] = 0xdc, 698 [PWRAP_WDT_FLG] = 0xe0, 699 [PWRAP_DEBUG_INT_SEL] = 0xe4, 700 [PWRAP_DVFS_ADR0] = 0xe8, 701 [PWRAP_DVFS_WDATA0] = 0xec, 702 [PWRAP_DVFS_ADR1] = 0xf0, 703 [PWRAP_DVFS_WDATA1] = 0xf4, 704 [PWRAP_DVFS_ADR2] = 0xf8, 705 [PWRAP_DVFS_WDATA2] = 0xfc, 706 [PWRAP_DVFS_ADR3] = 0x100, 707 [PWRAP_DVFS_WDATA3] = 0x104, 708 [PWRAP_DVFS_ADR4] = 0x108, 709 [PWRAP_DVFS_WDATA4] = 0x10c, 710 [PWRAP_DVFS_ADR5] = 0x110, 711 [PWRAP_DVFS_WDATA5] = 0x114, 712 [PWRAP_DVFS_ADR6] = 0x118, 713 [PWRAP_DVFS_WDATA6] = 0x11c, 714 [PWRAP_DVFS_ADR7] = 0x120, 715 [PWRAP_DVFS_WDATA7] = 0x124, 716 [PWRAP_SPMINF_STA] = 0x128, 717 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 718 [PWRAP_CIPHER_IV_SEL] = 0x130, 719 [PWRAP_CIPHER_EN] = 0x134, 720 [PWRAP_CIPHER_RDY] = 0x138, 721 [PWRAP_CIPHER_MODE] = 0x13c, 722 [PWRAP_CIPHER_SWRST] = 0x140, 723 [PWRAP_DCM_EN] = 0x144, 724 [PWRAP_DCM_DBC_PRD] = 0x148, 725 [PWRAP_EXT_CK] = 0x14c, 726 }; 727 728 static int mt6797_regs[] = { 729 [PWRAP_MUX_SEL] = 0x0, 730 [PWRAP_WRAP_EN] = 0x4, 731 [PWRAP_DIO_EN] = 0x8, 732 [PWRAP_SIDLY] = 0xC, 733 [PWRAP_RDDMY] = 0x10, 734 [PWRAP_CSHEXT_WRITE] = 0x18, 735 [PWRAP_CSHEXT_READ] = 0x1C, 736 [PWRAP_CSLEXT_START] = 0x20, 737 [PWRAP_CSLEXT_END] = 0x24, 738 [PWRAP_STAUPD_PRD] = 0x28, 739 [PWRAP_HARB_HPRIO] = 0x50, 740 [PWRAP_HIPRIO_ARB_EN] = 0x54, 741 [PWRAP_MAN_EN] = 0x60, 742 [PWRAP_MAN_CMD] = 0x64, 743 [PWRAP_WACS0_EN] = 0x70, 744 [PWRAP_WACS1_EN] = 0x84, 745 [PWRAP_WACS2_EN] = 0x98, 746 [PWRAP_INIT_DONE2] = 0x9C, 747 [PWRAP_WACS2_CMD] = 0xA0, 748 [PWRAP_WACS2_RDATA] = 0xA4, 749 [PWRAP_WACS2_VLDCLR] = 0xA8, 750 [PWRAP_INT_EN] = 0xC0, 751 [PWRAP_INT_FLG_RAW] = 0xC4, 752 [PWRAP_INT_FLG] = 0xC8, 753 [PWRAP_INT_CLR] = 0xCC, 754 [PWRAP_TIMER_EN] = 0xF4, 755 [PWRAP_WDT_UNIT] = 0xFC, 756 [PWRAP_WDT_SRC_EN] = 0x100, 757 [PWRAP_DCM_EN] = 0x1CC, 758 [PWRAP_DCM_DBC_PRD] = 0x1D4, 759 }; 760 761 static int mt6873_regs[] = { 762 [PWRAP_INIT_DONE2] = 0x0, 763 [PWRAP_TIMER_EN] = 0x3E0, 764 [PWRAP_INT_EN] = 0x448, 765 [PWRAP_WACS2_CMD] = 0xC80, 766 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84, 767 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94, 768 [PWRAP_WACS2_VLDCLR] = 0xCA4, 769 [PWRAP_WACS2_RDATA] = 0xCA8, 770 }; 771 772 static int mt7622_regs[] = { 773 [PWRAP_MUX_SEL] = 0x0, 774 [PWRAP_WRAP_EN] = 0x4, 775 [PWRAP_DIO_EN] = 0x8, 776 [PWRAP_SIDLY] = 0xC, 777 [PWRAP_RDDMY] = 0x10, 778 [PWRAP_SI_CK_CON] = 0x14, 779 [PWRAP_CSHEXT_WRITE] = 0x18, 780 [PWRAP_CSHEXT_READ] = 0x1C, 781 [PWRAP_CSLEXT_START] = 0x20, 782 [PWRAP_CSLEXT_END] = 0x24, 783 [PWRAP_STAUPD_PRD] = 0x28, 784 [PWRAP_STAUPD_GRPEN] = 0x2C, 785 [PWRAP_EINT_STA0_ADR] = 0x30, 786 [PWRAP_EINT_STA1_ADR] = 0x34, 787 [PWRAP_STA] = 0x38, 788 [PWRAP_CLR] = 0x3C, 789 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 790 [PWRAP_STAUPD_STA] = 0x44, 791 [PWRAP_WRAP_STA] = 0x48, 792 [PWRAP_HARB_INIT] = 0x4C, 793 [PWRAP_HARB_HPRIO] = 0x50, 794 [PWRAP_HIPRIO_ARB_EN] = 0x54, 795 [PWRAP_HARB_STA0] = 0x58, 796 [PWRAP_HARB_STA1] = 0x5C, 797 [PWRAP_MAN_EN] = 0x60, 798 [PWRAP_MAN_CMD] = 0x64, 799 [PWRAP_MAN_RDATA] = 0x68, 800 [PWRAP_MAN_VLDCLR] = 0x6C, 801 [PWRAP_WACS0_EN] = 0x70, 802 [PWRAP_INIT_DONE0] = 0x74, 803 [PWRAP_WACS0_CMD] = 0x78, 804 [PWRAP_WACS0_RDATA] = 0x7C, 805 [PWRAP_WACS0_VLDCLR] = 0x80, 806 [PWRAP_WACS1_EN] = 0x84, 807 [PWRAP_INIT_DONE1] = 0x88, 808 [PWRAP_WACS1_CMD] = 0x8C, 809 [PWRAP_WACS1_RDATA] = 0x90, 810 [PWRAP_WACS1_VLDCLR] = 0x94, 811 [PWRAP_WACS2_EN] = 0x98, 812 [PWRAP_INIT_DONE2] = 0x9C, 813 [PWRAP_WACS2_CMD] = 0xA0, 814 [PWRAP_WACS2_RDATA] = 0xA4, 815 [PWRAP_WACS2_VLDCLR] = 0xA8, 816 [PWRAP_INT_EN] = 0xAC, 817 [PWRAP_INT_FLG_RAW] = 0xB0, 818 [PWRAP_INT_FLG] = 0xB4, 819 [PWRAP_INT_CLR] = 0xB8, 820 [PWRAP_SIG_ADR] = 0xBC, 821 [PWRAP_SIG_MODE] = 0xC0, 822 [PWRAP_SIG_VALUE] = 0xC4, 823 [PWRAP_SIG_ERRVAL] = 0xC8, 824 [PWRAP_CRC_EN] = 0xCC, 825 [PWRAP_TIMER_EN] = 0xD0, 826 [PWRAP_TIMER_STA] = 0xD4, 827 [PWRAP_WDT_UNIT] = 0xD8, 828 [PWRAP_WDT_SRC_EN] = 0xDC, 829 [PWRAP_WDT_FLG] = 0xE0, 830 [PWRAP_DEBUG_INT_SEL] = 0xE4, 831 [PWRAP_DVFS_ADR0] = 0xE8, 832 [PWRAP_DVFS_WDATA0] = 0xEC, 833 [PWRAP_DVFS_ADR1] = 0xF0, 834 [PWRAP_DVFS_WDATA1] = 0xF4, 835 [PWRAP_DVFS_ADR2] = 0xF8, 836 [PWRAP_DVFS_WDATA2] = 0xFC, 837 [PWRAP_DVFS_ADR3] = 0x100, 838 [PWRAP_DVFS_WDATA3] = 0x104, 839 [PWRAP_DVFS_ADR4] = 0x108, 840 [PWRAP_DVFS_WDATA4] = 0x10C, 841 [PWRAP_DVFS_ADR5] = 0x110, 842 [PWRAP_DVFS_WDATA5] = 0x114, 843 [PWRAP_DVFS_ADR6] = 0x118, 844 [PWRAP_DVFS_WDATA6] = 0x11C, 845 [PWRAP_DVFS_ADR7] = 0x120, 846 [PWRAP_DVFS_WDATA7] = 0x124, 847 [PWRAP_DVFS_ADR8] = 0x128, 848 [PWRAP_DVFS_WDATA8] = 0x12C, 849 [PWRAP_DVFS_ADR9] = 0x130, 850 [PWRAP_DVFS_WDATA9] = 0x134, 851 [PWRAP_DVFS_ADR10] = 0x138, 852 [PWRAP_DVFS_WDATA10] = 0x13C, 853 [PWRAP_DVFS_ADR11] = 0x140, 854 [PWRAP_DVFS_WDATA11] = 0x144, 855 [PWRAP_DVFS_ADR12] = 0x148, 856 [PWRAP_DVFS_WDATA12] = 0x14C, 857 [PWRAP_DVFS_ADR13] = 0x150, 858 [PWRAP_DVFS_WDATA13] = 0x154, 859 [PWRAP_DVFS_ADR14] = 0x158, 860 [PWRAP_DVFS_WDATA14] = 0x15C, 861 [PWRAP_DVFS_ADR15] = 0x160, 862 [PWRAP_DVFS_WDATA15] = 0x164, 863 [PWRAP_SPMINF_STA] = 0x168, 864 [PWRAP_CIPHER_KEY_SEL] = 0x16C, 865 [PWRAP_CIPHER_IV_SEL] = 0x170, 866 [PWRAP_CIPHER_EN] = 0x174, 867 [PWRAP_CIPHER_RDY] = 0x178, 868 [PWRAP_CIPHER_MODE] = 0x17C, 869 [PWRAP_CIPHER_SWRST] = 0x180, 870 [PWRAP_DCM_EN] = 0x184, 871 [PWRAP_DCM_DBC_PRD] = 0x188, 872 [PWRAP_EXT_CK] = 0x18C, 873 [PWRAP_ADC_CMD_ADDR] = 0x190, 874 [PWRAP_PWRAP_ADC_CMD] = 0x194, 875 [PWRAP_ADC_RDATA_ADDR] = 0x198, 876 [PWRAP_GPS_STA] = 0x19C, 877 [PWRAP_SW_RST] = 0x1A0, 878 [PWRAP_DVFS_STEP_CTRL0] = 0x238, 879 [PWRAP_DVFS_STEP_CTRL1] = 0x23C, 880 [PWRAP_DVFS_STEP_CTRL2] = 0x240, 881 [PWRAP_SPI2_CTRL] = 0x244, 882 }; 883 884 static int mt8135_regs[] = { 885 [PWRAP_MUX_SEL] = 0x0, 886 [PWRAP_WRAP_EN] = 0x4, 887 [PWRAP_DIO_EN] = 0x8, 888 [PWRAP_SIDLY] = 0xc, 889 [PWRAP_CSHEXT] = 0x10, 890 [PWRAP_CSHEXT_WRITE] = 0x14, 891 [PWRAP_CSHEXT_READ] = 0x18, 892 [PWRAP_CSLEXT_START] = 0x1c, 893 [PWRAP_CSLEXT_END] = 0x20, 894 [PWRAP_STAUPD_PRD] = 0x24, 895 [PWRAP_STAUPD_GRPEN] = 0x28, 896 [PWRAP_STAUPD_MAN_TRIG] = 0x2c, 897 [PWRAP_STAUPD_STA] = 0x30, 898 [PWRAP_EVENT_IN_EN] = 0x34, 899 [PWRAP_EVENT_DST_EN] = 0x38, 900 [PWRAP_WRAP_STA] = 0x3c, 901 [PWRAP_RRARB_INIT] = 0x40, 902 [PWRAP_RRARB_EN] = 0x44, 903 [PWRAP_RRARB_STA0] = 0x48, 904 [PWRAP_RRARB_STA1] = 0x4c, 905 [PWRAP_HARB_INIT] = 0x50, 906 [PWRAP_HARB_HPRIO] = 0x54, 907 [PWRAP_HIPRIO_ARB_EN] = 0x58, 908 [PWRAP_HARB_STA0] = 0x5c, 909 [PWRAP_HARB_STA1] = 0x60, 910 [PWRAP_MAN_EN] = 0x64, 911 [PWRAP_MAN_CMD] = 0x68, 912 [PWRAP_MAN_RDATA] = 0x6c, 913 [PWRAP_MAN_VLDCLR] = 0x70, 914 [PWRAP_WACS0_EN] = 0x74, 915 [PWRAP_INIT_DONE0] = 0x78, 916 [PWRAP_WACS0_CMD] = 0x7c, 917 [PWRAP_WACS0_RDATA] = 0x80, 918 [PWRAP_WACS0_VLDCLR] = 0x84, 919 [PWRAP_WACS1_EN] = 0x88, 920 [PWRAP_INIT_DONE1] = 0x8c, 921 [PWRAP_WACS1_CMD] = 0x90, 922 [PWRAP_WACS1_RDATA] = 0x94, 923 [PWRAP_WACS1_VLDCLR] = 0x98, 924 [PWRAP_WACS2_EN] = 0x9c, 925 [PWRAP_INIT_DONE2] = 0xa0, 926 [PWRAP_WACS2_CMD] = 0xa4, 927 [PWRAP_WACS2_RDATA] = 0xa8, 928 [PWRAP_WACS2_VLDCLR] = 0xac, 929 [PWRAP_INT_EN] = 0xb0, 930 [PWRAP_INT_FLG_RAW] = 0xb4, 931 [PWRAP_INT_FLG] = 0xb8, 932 [PWRAP_INT_CLR] = 0xbc, 933 [PWRAP_SIG_ADR] = 0xc0, 934 [PWRAP_SIG_MODE] = 0xc4, 935 [PWRAP_SIG_VALUE] = 0xc8, 936 [PWRAP_SIG_ERRVAL] = 0xcc, 937 [PWRAP_CRC_EN] = 0xd0, 938 [PWRAP_EVENT_STA] = 0xd4, 939 [PWRAP_EVENT_STACLR] = 0xd8, 940 [PWRAP_TIMER_EN] = 0xdc, 941 [PWRAP_TIMER_STA] = 0xe0, 942 [PWRAP_WDT_UNIT] = 0xe4, 943 [PWRAP_WDT_SRC_EN] = 0xe8, 944 [PWRAP_WDT_FLG] = 0xec, 945 [PWRAP_DEBUG_INT_SEL] = 0xf0, 946 [PWRAP_CIPHER_KEY_SEL] = 0x134, 947 [PWRAP_CIPHER_IV_SEL] = 0x138, 948 [PWRAP_CIPHER_LOAD] = 0x13c, 949 [PWRAP_CIPHER_START] = 0x140, 950 [PWRAP_CIPHER_RDY] = 0x144, 951 [PWRAP_CIPHER_MODE] = 0x148, 952 [PWRAP_CIPHER_SWRST] = 0x14c, 953 [PWRAP_DCM_EN] = 0x15c, 954 [PWRAP_DCM_DBC_PRD] = 0x160, 955 }; 956 957 static int mt8173_regs[] = { 958 [PWRAP_MUX_SEL] = 0x0, 959 [PWRAP_WRAP_EN] = 0x4, 960 [PWRAP_DIO_EN] = 0x8, 961 [PWRAP_SIDLY] = 0xc, 962 [PWRAP_RDDMY] = 0x10, 963 [PWRAP_SI_CK_CON] = 0x14, 964 [PWRAP_CSHEXT_WRITE] = 0x18, 965 [PWRAP_CSHEXT_READ] = 0x1c, 966 [PWRAP_CSLEXT_START] = 0x20, 967 [PWRAP_CSLEXT_END] = 0x24, 968 [PWRAP_STAUPD_PRD] = 0x28, 969 [PWRAP_STAUPD_GRPEN] = 0x2c, 970 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 971 [PWRAP_STAUPD_STA] = 0x44, 972 [PWRAP_WRAP_STA] = 0x48, 973 [PWRAP_HARB_INIT] = 0x4c, 974 [PWRAP_HARB_HPRIO] = 0x50, 975 [PWRAP_HIPRIO_ARB_EN] = 0x54, 976 [PWRAP_HARB_STA0] = 0x58, 977 [PWRAP_HARB_STA1] = 0x5c, 978 [PWRAP_MAN_EN] = 0x60, 979 [PWRAP_MAN_CMD] = 0x64, 980 [PWRAP_MAN_RDATA] = 0x68, 981 [PWRAP_MAN_VLDCLR] = 0x6c, 982 [PWRAP_WACS0_EN] = 0x70, 983 [PWRAP_INIT_DONE0] = 0x74, 984 [PWRAP_WACS0_CMD] = 0x78, 985 [PWRAP_WACS0_RDATA] = 0x7c, 986 [PWRAP_WACS0_VLDCLR] = 0x80, 987 [PWRAP_WACS1_EN] = 0x84, 988 [PWRAP_INIT_DONE1] = 0x88, 989 [PWRAP_WACS1_CMD] = 0x8c, 990 [PWRAP_WACS1_RDATA] = 0x90, 991 [PWRAP_WACS1_VLDCLR] = 0x94, 992 [PWRAP_WACS2_EN] = 0x98, 993 [PWRAP_INIT_DONE2] = 0x9c, 994 [PWRAP_WACS2_CMD] = 0xa0, 995 [PWRAP_WACS2_RDATA] = 0xa4, 996 [PWRAP_WACS2_VLDCLR] = 0xa8, 997 [PWRAP_INT_EN] = 0xac, 998 [PWRAP_INT_FLG_RAW] = 0xb0, 999 [PWRAP_INT_FLG] = 0xb4, 1000 [PWRAP_INT_CLR] = 0xb8, 1001 [PWRAP_SIG_ADR] = 0xbc, 1002 [PWRAP_SIG_MODE] = 0xc0, 1003 [PWRAP_SIG_VALUE] = 0xc4, 1004 [PWRAP_SIG_ERRVAL] = 0xc8, 1005 [PWRAP_CRC_EN] = 0xcc, 1006 [PWRAP_TIMER_EN] = 0xd0, 1007 [PWRAP_TIMER_STA] = 0xd4, 1008 [PWRAP_WDT_UNIT] = 0xd8, 1009 [PWRAP_WDT_SRC_EN] = 0xdc, 1010 [PWRAP_WDT_FLG] = 0xe0, 1011 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1012 [PWRAP_DVFS_ADR0] = 0xe8, 1013 [PWRAP_DVFS_WDATA0] = 0xec, 1014 [PWRAP_DVFS_ADR1] = 0xf0, 1015 [PWRAP_DVFS_WDATA1] = 0xf4, 1016 [PWRAP_DVFS_ADR2] = 0xf8, 1017 [PWRAP_DVFS_WDATA2] = 0xfc, 1018 [PWRAP_DVFS_ADR3] = 0x100, 1019 [PWRAP_DVFS_WDATA3] = 0x104, 1020 [PWRAP_DVFS_ADR4] = 0x108, 1021 [PWRAP_DVFS_WDATA4] = 0x10c, 1022 [PWRAP_DVFS_ADR5] = 0x110, 1023 [PWRAP_DVFS_WDATA5] = 0x114, 1024 [PWRAP_DVFS_ADR6] = 0x118, 1025 [PWRAP_DVFS_WDATA6] = 0x11c, 1026 [PWRAP_DVFS_ADR7] = 0x120, 1027 [PWRAP_DVFS_WDATA7] = 0x124, 1028 [PWRAP_SPMINF_STA] = 0x128, 1029 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1030 [PWRAP_CIPHER_IV_SEL] = 0x130, 1031 [PWRAP_CIPHER_EN] = 0x134, 1032 [PWRAP_CIPHER_RDY] = 0x138, 1033 [PWRAP_CIPHER_MODE] = 0x13c, 1034 [PWRAP_CIPHER_SWRST] = 0x140, 1035 [PWRAP_DCM_EN] = 0x144, 1036 [PWRAP_DCM_DBC_PRD] = 0x148, 1037 }; 1038 1039 static int mt8183_regs[] = { 1040 [PWRAP_MUX_SEL] = 0x0, 1041 [PWRAP_WRAP_EN] = 0x4, 1042 [PWRAP_DIO_EN] = 0x8, 1043 [PWRAP_SI_SAMPLE_CTRL] = 0xC, 1044 [PWRAP_RDDMY] = 0x14, 1045 [PWRAP_CSHEXT_WRITE] = 0x18, 1046 [PWRAP_CSHEXT_READ] = 0x1C, 1047 [PWRAP_CSLEXT_WRITE] = 0x20, 1048 [PWRAP_CSLEXT_READ] = 0x24, 1049 [PWRAP_EXT_CK_WRITE] = 0x28, 1050 [PWRAP_STAUPD_CTRL] = 0x30, 1051 [PWRAP_STAUPD_GRPEN] = 0x34, 1052 [PWRAP_EINT_STA0_ADR] = 0x38, 1053 [PWRAP_HARB_HPRIO] = 0x5C, 1054 [PWRAP_HIPRIO_ARB_EN] = 0x60, 1055 [PWRAP_MAN_EN] = 0x70, 1056 [PWRAP_MAN_CMD] = 0x74, 1057 [PWRAP_WACS0_EN] = 0x80, 1058 [PWRAP_INIT_DONE0] = 0x84, 1059 [PWRAP_WACS1_EN] = 0x88, 1060 [PWRAP_INIT_DONE1] = 0x8C, 1061 [PWRAP_WACS2_EN] = 0x90, 1062 [PWRAP_INIT_DONE2] = 0x94, 1063 [PWRAP_WACS_P2P_EN] = 0xA0, 1064 [PWRAP_INIT_DONE_P2P] = 0xA4, 1065 [PWRAP_WACS_MD32_EN] = 0xA8, 1066 [PWRAP_INIT_DONE_MD32] = 0xAC, 1067 [PWRAP_INT_EN] = 0xB0, 1068 [PWRAP_INT_FLG] = 0xB8, 1069 [PWRAP_INT_CLR] = 0xBC, 1070 [PWRAP_INT1_EN] = 0xC0, 1071 [PWRAP_INT1_FLG] = 0xC8, 1072 [PWRAP_INT1_CLR] = 0xCC, 1073 [PWRAP_SIG_ADR] = 0xD0, 1074 [PWRAP_CRC_EN] = 0xE0, 1075 [PWRAP_TIMER_EN] = 0xE4, 1076 [PWRAP_WDT_UNIT] = 0xEC, 1077 [PWRAP_WDT_SRC_EN] = 0xF0, 1078 [PWRAP_WDT_SRC_EN_1] = 0xF4, 1079 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC, 1080 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0, 1081 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4, 1082 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8, 1083 [PWRAP_GPSINF_0_STA] = 0x1EC, 1084 [PWRAP_GPSINF_1_STA] = 0x1F0, 1085 [PWRAP_WACS2_CMD] = 0xC20, 1086 [PWRAP_WACS2_RDATA] = 0xC24, 1087 [PWRAP_WACS2_VLDCLR] = 0xC28, 1088 }; 1089 1090 static int mt8195_regs[] = { 1091 [PWRAP_INIT_DONE2] = 0x0, 1092 [PWRAP_STAUPD_CTRL] = 0x4C, 1093 [PWRAP_TIMER_EN] = 0x3E4, 1094 [PWRAP_INT_EN] = 0x420, 1095 [PWRAP_INT_FLG] = 0x428, 1096 [PWRAP_INT_CLR] = 0x42C, 1097 [PWRAP_INT1_EN] = 0x450, 1098 [PWRAP_INT1_FLG] = 0x458, 1099 [PWRAP_INT1_CLR] = 0x45C, 1100 [PWRAP_WACS2_CMD] = 0x880, 1101 [PWRAP_SWINF_2_WDATA_31_0] = 0x884, 1102 [PWRAP_SWINF_2_RDATA_31_0] = 0x894, 1103 [PWRAP_WACS2_VLDCLR] = 0x8A4, 1104 [PWRAP_WACS2_RDATA] = 0x8A8, 1105 }; 1106 1107 static int mt8365_regs[] = { 1108 [PWRAP_MUX_SEL] = 0x0, 1109 [PWRAP_WRAP_EN] = 0x4, 1110 [PWRAP_DIO_EN] = 0x8, 1111 [PWRAP_CSHEXT_WRITE] = 0x24, 1112 [PWRAP_CSHEXT_READ] = 0x28, 1113 [PWRAP_STAUPD_PRD] = 0x3c, 1114 [PWRAP_STAUPD_GRPEN] = 0x40, 1115 [PWRAP_STAUPD_MAN_TRIG] = 0x58, 1116 [PWRAP_STAUPD_STA] = 0x5c, 1117 [PWRAP_WRAP_STA] = 0x60, 1118 [PWRAP_HARB_INIT] = 0x64, 1119 [PWRAP_HARB_HPRIO] = 0x68, 1120 [PWRAP_HIPRIO_ARB_EN] = 0x6c, 1121 [PWRAP_HARB_STA0] = 0x70, 1122 [PWRAP_HARB_STA1] = 0x74, 1123 [PWRAP_MAN_EN] = 0x7c, 1124 [PWRAP_MAN_CMD] = 0x80, 1125 [PWRAP_MAN_RDATA] = 0x84, 1126 [PWRAP_MAN_VLDCLR] = 0x88, 1127 [PWRAP_WACS0_EN] = 0x8c, 1128 [PWRAP_INIT_DONE0] = 0x90, 1129 [PWRAP_WACS0_CMD] = 0xc00, 1130 [PWRAP_WACS0_RDATA] = 0xc04, 1131 [PWRAP_WACS0_VLDCLR] = 0xc08, 1132 [PWRAP_WACS1_EN] = 0x94, 1133 [PWRAP_INIT_DONE1] = 0x98, 1134 [PWRAP_WACS2_EN] = 0x9c, 1135 [PWRAP_INIT_DONE2] = 0xa0, 1136 [PWRAP_WACS2_CMD] = 0xc20, 1137 [PWRAP_WACS2_RDATA] = 0xc24, 1138 [PWRAP_WACS2_VLDCLR] = 0xc28, 1139 [PWRAP_INT_EN] = 0xb4, 1140 [PWRAP_INT_FLG_RAW] = 0xb8, 1141 [PWRAP_INT_FLG] = 0xbc, 1142 [PWRAP_INT_CLR] = 0xc0, 1143 [PWRAP_SIG_ADR] = 0xd4, 1144 [PWRAP_SIG_MODE] = 0xd8, 1145 [PWRAP_SIG_VALUE] = 0xdc, 1146 [PWRAP_SIG_ERRVAL] = 0xe0, 1147 [PWRAP_CRC_EN] = 0xe4, 1148 [PWRAP_TIMER_EN] = 0xe8, 1149 [PWRAP_TIMER_STA] = 0xec, 1150 [PWRAP_WDT_UNIT] = 0xf0, 1151 [PWRAP_WDT_SRC_EN] = 0xf4, 1152 [PWRAP_WDT_FLG] = 0xfc, 1153 [PWRAP_DEBUG_INT_SEL] = 0x104, 1154 [PWRAP_CIPHER_KEY_SEL] = 0x1c4, 1155 [PWRAP_CIPHER_IV_SEL] = 0x1c8, 1156 [PWRAP_CIPHER_RDY] = 0x1d0, 1157 [PWRAP_CIPHER_MODE] = 0x1d4, 1158 [PWRAP_CIPHER_SWRST] = 0x1d8, 1159 [PWRAP_DCM_EN] = 0x1dc, 1160 [PWRAP_DCM_DBC_PRD] = 0x1e0, 1161 [PWRAP_EINT_STA0_ADR] = 0x44, 1162 [PWRAP_EINT_STA1_ADR] = 0x48, 1163 [PWRAP_INT1_EN] = 0xc4, 1164 [PWRAP_INT1_FLG] = 0xcc, 1165 [PWRAP_INT1_CLR] = 0xd0, 1166 [PWRAP_WDT_SRC_EN_1] = 0xf8, 1167 }; 1168 1169 static int mt8516_regs[] = { 1170 [PWRAP_MUX_SEL] = 0x0, 1171 [PWRAP_WRAP_EN] = 0x4, 1172 [PWRAP_DIO_EN] = 0x8, 1173 [PWRAP_SIDLY] = 0xc, 1174 [PWRAP_RDDMY] = 0x10, 1175 [PWRAP_SI_CK_CON] = 0x14, 1176 [PWRAP_CSHEXT_WRITE] = 0x18, 1177 [PWRAP_CSHEXT_READ] = 0x1c, 1178 [PWRAP_CSLEXT_START] = 0x20, 1179 [PWRAP_CSLEXT_END] = 0x24, 1180 [PWRAP_STAUPD_PRD] = 0x28, 1181 [PWRAP_STAUPD_GRPEN] = 0x2c, 1182 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 1183 [PWRAP_STAUPD_STA] = 0x44, 1184 [PWRAP_WRAP_STA] = 0x48, 1185 [PWRAP_HARB_INIT] = 0x4c, 1186 [PWRAP_HARB_HPRIO] = 0x50, 1187 [PWRAP_HIPRIO_ARB_EN] = 0x54, 1188 [PWRAP_HARB_STA0] = 0x58, 1189 [PWRAP_HARB_STA1] = 0x5c, 1190 [PWRAP_MAN_EN] = 0x60, 1191 [PWRAP_MAN_CMD] = 0x64, 1192 [PWRAP_MAN_RDATA] = 0x68, 1193 [PWRAP_MAN_VLDCLR] = 0x6c, 1194 [PWRAP_WACS0_EN] = 0x70, 1195 [PWRAP_INIT_DONE0] = 0x74, 1196 [PWRAP_WACS0_CMD] = 0x78, 1197 [PWRAP_WACS0_RDATA] = 0x7c, 1198 [PWRAP_WACS0_VLDCLR] = 0x80, 1199 [PWRAP_WACS1_EN] = 0x84, 1200 [PWRAP_INIT_DONE1] = 0x88, 1201 [PWRAP_WACS1_CMD] = 0x8c, 1202 [PWRAP_WACS1_RDATA] = 0x90, 1203 [PWRAP_WACS1_VLDCLR] = 0x94, 1204 [PWRAP_WACS2_EN] = 0x98, 1205 [PWRAP_INIT_DONE2] = 0x9c, 1206 [PWRAP_WACS2_CMD] = 0xa0, 1207 [PWRAP_WACS2_RDATA] = 0xa4, 1208 [PWRAP_WACS2_VLDCLR] = 0xa8, 1209 [PWRAP_INT_EN] = 0xac, 1210 [PWRAP_INT_FLG_RAW] = 0xb0, 1211 [PWRAP_INT_FLG] = 0xb4, 1212 [PWRAP_INT_CLR] = 0xb8, 1213 [PWRAP_SIG_ADR] = 0xbc, 1214 [PWRAP_SIG_MODE] = 0xc0, 1215 [PWRAP_SIG_VALUE] = 0xc4, 1216 [PWRAP_SIG_ERRVAL] = 0xc8, 1217 [PWRAP_CRC_EN] = 0xcc, 1218 [PWRAP_TIMER_EN] = 0xd0, 1219 [PWRAP_TIMER_STA] = 0xd4, 1220 [PWRAP_WDT_UNIT] = 0xd8, 1221 [PWRAP_WDT_SRC_EN] = 0xdc, 1222 [PWRAP_WDT_FLG] = 0xe0, 1223 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1224 [PWRAP_DVFS_ADR0] = 0xe8, 1225 [PWRAP_DVFS_WDATA0] = 0xec, 1226 [PWRAP_DVFS_ADR1] = 0xf0, 1227 [PWRAP_DVFS_WDATA1] = 0xf4, 1228 [PWRAP_DVFS_ADR2] = 0xf8, 1229 [PWRAP_DVFS_WDATA2] = 0xfc, 1230 [PWRAP_DVFS_ADR3] = 0x100, 1231 [PWRAP_DVFS_WDATA3] = 0x104, 1232 [PWRAP_DVFS_ADR4] = 0x108, 1233 [PWRAP_DVFS_WDATA4] = 0x10c, 1234 [PWRAP_DVFS_ADR5] = 0x110, 1235 [PWRAP_DVFS_WDATA5] = 0x114, 1236 [PWRAP_DVFS_ADR6] = 0x118, 1237 [PWRAP_DVFS_WDATA6] = 0x11c, 1238 [PWRAP_DVFS_ADR7] = 0x120, 1239 [PWRAP_DVFS_WDATA7] = 0x124, 1240 [PWRAP_SPMINF_STA] = 0x128, 1241 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1242 [PWRAP_CIPHER_IV_SEL] = 0x130, 1243 [PWRAP_CIPHER_EN] = 0x134, 1244 [PWRAP_CIPHER_RDY] = 0x138, 1245 [PWRAP_CIPHER_MODE] = 0x13c, 1246 [PWRAP_CIPHER_SWRST] = 0x140, 1247 [PWRAP_DCM_EN] = 0x144, 1248 [PWRAP_DCM_DBC_PRD] = 0x148, 1249 [PWRAP_SW_RST] = 0x168, 1250 [PWRAP_OP_TYPE] = 0x16c, 1251 [PWRAP_MSB_FIRST] = 0x170, 1252 }; 1253 1254 static int mt8186_regs[] = { 1255 [PWRAP_MUX_SEL] = 0x0, 1256 [PWRAP_WRAP_EN] = 0x4, 1257 [PWRAP_DIO_EN] = 0x8, 1258 [PWRAP_RDDMY] = 0x20, 1259 [PWRAP_CSHEXT_WRITE] = 0x24, 1260 [PWRAP_CSHEXT_READ] = 0x28, 1261 [PWRAP_CSLEXT_WRITE] = 0x2C, 1262 [PWRAP_CSLEXT_READ] = 0x30, 1263 [PWRAP_EXT_CK_WRITE] = 0x34, 1264 [PWRAP_STAUPD_CTRL] = 0x3C, 1265 [PWRAP_STAUPD_GRPEN] = 0x40, 1266 [PWRAP_EINT_STA0_ADR] = 0x44, 1267 [PWRAP_EINT_STA1_ADR] = 0x48, 1268 [PWRAP_INT_CLR] = 0xC8, 1269 [PWRAP_INT_FLG] = 0xC4, 1270 [PWRAP_MAN_EN] = 0x7C, 1271 [PWRAP_MAN_CMD] = 0x80, 1272 [PWRAP_WACS0_EN] = 0x8C, 1273 [PWRAP_WACS1_EN] = 0x94, 1274 [PWRAP_WACS2_EN] = 0x9C, 1275 [PWRAP_INIT_DONE0] = 0x90, 1276 [PWRAP_INIT_DONE1] = 0x98, 1277 [PWRAP_INIT_DONE2] = 0xA0, 1278 [PWRAP_INT_EN] = 0xBC, 1279 [PWRAP_INT1_EN] = 0xCC, 1280 [PWRAP_INT1_FLG] = 0xD4, 1281 [PWRAP_INT1_CLR] = 0xD8, 1282 [PWRAP_TIMER_EN] = 0xF0, 1283 [PWRAP_WDT_UNIT] = 0xF8, 1284 [PWRAP_WDT_SRC_EN] = 0xFC, 1285 [PWRAP_WDT_SRC_EN_1] = 0x100, 1286 [PWRAP_WDT_FLG] = 0x104, 1287 [PWRAP_SPMINF_STA] = 0x1B4, 1288 [PWRAP_DCM_EN] = 0x1EC, 1289 [PWRAP_DCM_DBC_PRD] = 0x1F0, 1290 [PWRAP_GPSINF_0_STA] = 0x204, 1291 [PWRAP_GPSINF_1_STA] = 0x208, 1292 [PWRAP_WACS0_CMD] = 0xC00, 1293 [PWRAP_WACS0_RDATA] = 0xC04, 1294 [PWRAP_WACS0_VLDCLR] = 0xC08, 1295 [PWRAP_WACS1_CMD] = 0xC10, 1296 [PWRAP_WACS1_RDATA] = 0xC14, 1297 [PWRAP_WACS1_VLDCLR] = 0xC18, 1298 [PWRAP_WACS2_CMD] = 0xC20, 1299 [PWRAP_WACS2_RDATA] = 0xC24, 1300 [PWRAP_WACS2_VLDCLR] = 0xC28, 1301 }; 1302 1303 enum pmic_type { 1304 PMIC_MT6323, 1305 PMIC_MT6331, 1306 PMIC_MT6332, 1307 PMIC_MT6351, 1308 PMIC_MT6357, 1309 PMIC_MT6358, 1310 PMIC_MT6359, 1311 PMIC_MT6380, 1312 PMIC_MT6397, 1313 }; 1314 1315 enum pwrap_type { 1316 PWRAP_MT2701, 1317 PWRAP_MT6765, 1318 PWRAP_MT6779, 1319 PWRAP_MT6795, 1320 PWRAP_MT6797, 1321 PWRAP_MT6873, 1322 PWRAP_MT7622, 1323 PWRAP_MT8135, 1324 PWRAP_MT8173, 1325 PWRAP_MT8183, 1326 PWRAP_MT8186, 1327 PWRAP_MT8195, 1328 PWRAP_MT8365, 1329 PWRAP_MT8516, 1330 }; 1331 1332 struct pmic_wrapper; 1333 1334 struct pwrap_slv_regops { 1335 const struct regmap_config *regmap; 1336 /* 1337 * pwrap operations are highly associated with the PMIC types, 1338 * so the pointers added increases flexibility allowing determination 1339 * which type is used by the detection through device tree. 1340 */ 1341 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); 1342 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); 1343 }; 1344 1345 /** 1346 * struct pwrap_slv_type - PMIC device wrapper definitions 1347 * @dew_regs: Device Wrapper (DeW) register offsets 1348 * @type: PMIC Type (model) 1349 * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device 1350 * @comp_type: Companion PMIC Type (model) 1351 * @regops: Register R/W ops 1352 * @caps: Capability flags for the target device 1353 */ 1354 struct pwrap_slv_type { 1355 const u32 *dew_regs; 1356 enum pmic_type type; 1357 const u32 *comp_dew_regs; 1358 enum pmic_type comp_type; 1359 const struct pwrap_slv_regops *regops; 1360 u32 caps; 1361 }; 1362 1363 struct pmic_wrapper { 1364 struct device *dev; 1365 void __iomem *base; 1366 struct regmap *regmap; 1367 const struct pmic_wrapper_type *master; 1368 const struct pwrap_slv_type *slave; 1369 struct clk *clk_spi; 1370 struct clk *clk_wrap; 1371 struct clk *clk_sys; 1372 struct clk *clk_tmr; 1373 struct reset_control *rstc; 1374 1375 struct reset_control *rstc_bridge; 1376 void __iomem *bridge_base; 1377 }; 1378 1379 struct pmic_wrapper_type { 1380 int *regs; 1381 enum pwrap_type type; 1382 u32 arb_en_all; 1383 u32 int_en_all; 1384 u32 int1_en_all; 1385 u32 spi_w; 1386 u32 wdt_src; 1387 /* Flags indicating the capability for the target pwrap */ 1388 u32 caps; 1389 int (*init_reg_clock)(struct pmic_wrapper *wrp); 1390 int (*init_soc_specific)(struct pmic_wrapper *wrp); 1391 }; 1392 pwrap_readl(struct pmic_wrapper * wrp,enum pwrap_regs reg)1393 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 1394 { 1395 return readl(wrp->base + wrp->master->regs[reg]); 1396 } 1397 pwrap_writel(struct pmic_wrapper * wrp,u32 val,enum pwrap_regs reg)1398 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) 1399 { 1400 writel(val, wrp->base + wrp->master->regs[reg]); 1401 } 1402 pwrap_get_fsm_state(struct pmic_wrapper * wrp)1403 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) 1404 { 1405 u32 val; 1406 1407 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1408 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1409 return PWRAP_GET_WACS_ARB_FSM(val); 1410 else 1411 return PWRAP_GET_WACS_FSM(val); 1412 } 1413 pwrap_is_fsm_idle(struct pmic_wrapper * wrp)1414 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) 1415 { 1416 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; 1417 } 1418 pwrap_is_fsm_vldclr(struct pmic_wrapper * wrp)1419 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) 1420 { 1421 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; 1422 } 1423 1424 /* 1425 * Timeout issue sometimes caused by the last read command 1426 * failed because pmic wrap could not got the FSM_VLDCLR 1427 * in time after finishing WACS2_CMD. It made state machine 1428 * still on FSM_VLDCLR and timeout next time. 1429 * Check the status of FSM and clear the vldclr to recovery the 1430 * error. 1431 */ pwrap_leave_fsm_vldclr(struct pmic_wrapper * wrp)1432 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) 1433 { 1434 if (pwrap_is_fsm_vldclr(wrp)) 1435 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1436 } 1437 pwrap_is_sync_idle(struct pmic_wrapper * wrp)1438 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) 1439 { 1440 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0; 1441 } 1442 pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper * wrp)1443 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) 1444 { 1445 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1446 1447 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && 1448 (val & PWRAP_STATE_SYNC_IDLE0); 1449 } 1450 pwrap_read16(struct pmic_wrapper * wrp,u32 adr,u32 * rdata)1451 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1452 { 1453 bool tmp; 1454 int ret; 1455 u32 val; 1456 1457 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1458 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1459 if (ret) { 1460 pwrap_leave_fsm_vldclr(wrp); 1461 return ret; 1462 } 1463 1464 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1465 val = adr; 1466 else 1467 val = (adr >> 1) << 16; 1468 pwrap_writel(wrp, val, PWRAP_WACS2_CMD); 1469 1470 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1471 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1472 if (ret) 1473 return ret; 1474 1475 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1476 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); 1477 else 1478 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1479 *rdata = PWRAP_GET_WACS_RDATA(val); 1480 1481 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1482 1483 return 0; 1484 } 1485 pwrap_read32(struct pmic_wrapper * wrp,u32 adr,u32 * rdata)1486 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1487 { 1488 bool tmp; 1489 int ret, msb; 1490 1491 *rdata = 0; 1492 for (msb = 0; msb < 2; msb++) { 1493 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1494 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1495 1496 if (ret) { 1497 pwrap_leave_fsm_vldclr(wrp); 1498 return ret; 1499 } 1500 1501 pwrap_writel(wrp, ((msb << 30) | (adr << 16)), 1502 PWRAP_WACS2_CMD); 1503 1504 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1505 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1506 if (ret) 1507 return ret; 1508 1509 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, 1510 PWRAP_WACS2_RDATA)) << (16 * msb)); 1511 1512 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1513 } 1514 1515 return 0; 1516 } 1517 pwrap_read(struct pmic_wrapper * wrp,u32 adr,u32 * rdata)1518 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1519 { 1520 return wrp->slave->regops->pwrap_read(wrp, adr, rdata); 1521 } 1522 pwrap_write16(struct pmic_wrapper * wrp,u32 adr,u32 wdata)1523 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1524 { 1525 bool tmp; 1526 int ret; 1527 1528 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1529 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1530 if (ret) { 1531 pwrap_leave_fsm_vldclr(wrp); 1532 return ret; 1533 } 1534 1535 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { 1536 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); 1537 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); 1538 } else { 1539 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, 1540 PWRAP_WACS2_CMD); 1541 } 1542 1543 return 0; 1544 } 1545 pwrap_write32(struct pmic_wrapper * wrp,u32 adr,u32 wdata)1546 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1547 { 1548 bool tmp; 1549 int ret, msb, rdata; 1550 1551 for (msb = 0; msb < 2; msb++) { 1552 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1553 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1554 if (ret) { 1555 pwrap_leave_fsm_vldclr(wrp); 1556 return ret; 1557 } 1558 1559 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | 1560 ((wdata >> (msb * 16)) & 0xffff), 1561 PWRAP_WACS2_CMD); 1562 1563 /* 1564 * The pwrap_read operation is the requirement of hardware used 1565 * for the synchronization between two successive 16-bit 1566 * pwrap_writel operations composing one 32-bit bus writing. 1567 * Otherwise, we'll find the result fails on the lower 16-bit 1568 * pwrap writing. 1569 */ 1570 if (!msb) 1571 pwrap_read(wrp, adr, &rdata); 1572 } 1573 1574 return 0; 1575 } 1576 pwrap_write(struct pmic_wrapper * wrp,u32 adr,u32 wdata)1577 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1578 { 1579 return wrp->slave->regops->pwrap_write(wrp, adr, wdata); 1580 } 1581 pwrap_regmap_read(void * context,u32 adr,u32 * rdata)1582 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) 1583 { 1584 return pwrap_read(context, adr, rdata); 1585 } 1586 pwrap_regmap_write(void * context,u32 adr,u32 wdata)1587 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) 1588 { 1589 return pwrap_write(context, adr, wdata); 1590 } 1591 pwrap_pmic_read_test(struct pmic_wrapper * wrp,const u32 * dew_regs,u16 read_test_val)1592 static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs, 1593 u16 read_test_val) 1594 { 1595 bool is_success; 1596 u32 rdata; 1597 1598 pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); 1599 is_success = ((rdata & U16_MAX) == read_test_val); 1600 1601 return is_success; 1602 } 1603 pwrap_reset_spislave(struct pmic_wrapper * wrp)1604 static int pwrap_reset_spislave(struct pmic_wrapper *wrp) 1605 { 1606 bool tmp; 1607 int ret, i; 1608 1609 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); 1610 pwrap_writel(wrp, 0, PWRAP_WRAP_EN); 1611 pwrap_writel(wrp, 1, PWRAP_MUX_SEL); 1612 pwrap_writel(wrp, 1, PWRAP_MAN_EN); 1613 pwrap_writel(wrp, 0, PWRAP_DIO_EN); 1614 1615 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, 1616 PWRAP_MAN_CMD); 1617 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1618 PWRAP_MAN_CMD); 1619 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, 1620 PWRAP_MAN_CMD); 1621 1622 for (i = 0; i < 4; i++) 1623 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1624 PWRAP_MAN_CMD); 1625 1626 ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp, 1627 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1628 if (ret) { 1629 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1630 return ret; 1631 } 1632 1633 pwrap_writel(wrp, 0, PWRAP_MAN_EN); 1634 pwrap_writel(wrp, 0, PWRAP_MUX_SEL); 1635 1636 return 0; 1637 } 1638 1639 /* 1640 * pwrap_init_sidly - configure serial input delay 1641 * 1642 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns 1643 * delay. Do a read test with all possible values and chose the best delay. 1644 */ pwrap_init_sidly(struct pmic_wrapper * wrp)1645 static int pwrap_init_sidly(struct pmic_wrapper *wrp) 1646 { 1647 u32 i; 1648 u32 pass = 0; 1649 bool read_ok; 1650 signed char dly[16] = { 1651 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 1652 }; 1653 1654 for (i = 0; i < 4; i++) { 1655 pwrap_writel(wrp, i, PWRAP_SIDLY); 1656 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, 1657 PWRAP_DEW_READ_TEST_VAL); 1658 if (read_ok) { 1659 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); 1660 pass |= 1 << i; 1661 } 1662 } 1663 1664 if (dly[pass] < 0) { 1665 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", 1666 pass); 1667 return -EIO; 1668 } 1669 1670 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); 1671 1672 return 0; 1673 } 1674 pwrap_init_dual_io(struct pmic_wrapper * wrp)1675 static int pwrap_init_dual_io(struct pmic_wrapper *wrp) 1676 { 1677 int ret; 1678 bool read_ok, tmp; 1679 bool comp_read_ok = true; 1680 1681 /* Enable dual IO mode */ 1682 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); 1683 if (wrp->slave->comp_dew_regs) 1684 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); 1685 1686 /* Check IDLE & INIT_DONE in advance */ 1687 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1688 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1689 if (ret) { 1690 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1691 return ret; 1692 } 1693 1694 pwrap_writel(wrp, 1, PWRAP_DIO_EN); 1695 1696 /* Read Test */ 1697 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); 1698 if (wrp->slave->comp_dew_regs) 1699 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, 1700 PWRAP_DEW_COMP_READ_TEST_VAL); 1701 if (!read_ok || !comp_read_ok) { 1702 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", 1703 !read_ok ? "fail" : "success", 1704 wrp->slave->comp_dew_regs && !comp_read_ok ? 1705 ", Companion PMIC fail" : ""); 1706 return -EFAULT; 1707 } 1708 1709 return 0; 1710 } 1711 1712 /* 1713 * pwrap_init_chip_select_ext is used to configure CS extension time for each 1714 * phase during data transactions on the pwrap bus. 1715 */ pwrap_init_chip_select_ext(struct pmic_wrapper * wrp,u8 hext_write,u8 hext_read,u8 lext_start,u8 lext_end)1716 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, 1717 u8 hext_read, u8 lext_start, 1718 u8 lext_end) 1719 { 1720 /* 1721 * After finishing a write and read transaction, extends CS high time 1722 * to be at least xT of BUS CLK as hext_write and hext_read specifies 1723 * respectively. 1724 */ 1725 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); 1726 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); 1727 1728 /* 1729 * Extends CS low time after CSL and before CSH command to be at 1730 * least xT of BUS CLK as lext_start and lext_end specifies 1731 * respectively. 1732 */ 1733 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); 1734 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); 1735 } 1736 pwrap_common_init_reg_clock(struct pmic_wrapper * wrp)1737 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) 1738 { 1739 switch (wrp->master->type) { 1740 case PWRAP_MT6795: 1741 if (wrp->slave->type == PMIC_MT6331) { 1742 const u32 *dew_regs = wrp->slave->dew_regs; 1743 1744 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); 1745 1746 if (wrp->slave->comp_type == PMIC_MT6332) { 1747 dew_regs = wrp->slave->comp_dew_regs; 1748 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); 1749 } 1750 } 1751 pwrap_writel(wrp, 0x88, PWRAP_RDDMY); 1752 pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); 1753 break; 1754 case PWRAP_MT8173: 1755 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); 1756 break; 1757 case PWRAP_MT8135: 1758 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 1759 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); 1760 break; 1761 default: 1762 break; 1763 } 1764 1765 return 0; 1766 } 1767 pwrap_mt2701_init_reg_clock(struct pmic_wrapper * wrp)1768 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp) 1769 { 1770 switch (wrp->slave->type) { 1771 case PMIC_MT6397: 1772 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 1773 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); 1774 break; 1775 1776 case PMIC_MT6323: 1777 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 1778 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 1779 0x8); 1780 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); 1781 break; 1782 default: 1783 break; 1784 } 1785 1786 return 0; 1787 } 1788 pwrap_is_cipher_ready(struct pmic_wrapper * wrp)1789 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) 1790 { 1791 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; 1792 } 1793 __pwrap_is_pmic_cipher_ready(struct pmic_wrapper * wrp,const u32 * dew_regs)1794 static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs) 1795 { 1796 u32 rdata; 1797 int ret; 1798 1799 ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata); 1800 if (ret) 1801 return false; 1802 1803 return rdata == 1; 1804 } 1805 1806 pwrap_is_pmic_cipher_ready(struct pmic_wrapper * wrp)1807 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) 1808 { 1809 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); 1810 1811 if (!ret) 1812 return ret; 1813 1814 /* If there's any companion, wait for it to be ready too */ 1815 if (wrp->slave->comp_dew_regs) 1816 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); 1817 1818 return ret; 1819 } 1820 pwrap_config_cipher(struct pmic_wrapper * wrp,const u32 * dew_regs)1821 static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs) 1822 { 1823 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); 1824 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); 1825 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); 1826 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); 1827 } 1828 pwrap_init_cipher(struct pmic_wrapper * wrp)1829 static int pwrap_init_cipher(struct pmic_wrapper *wrp) 1830 { 1831 int ret; 1832 bool tmp; 1833 u32 rdata = 0; 1834 1835 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST); 1836 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST); 1837 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 1838 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 1839 1840 switch (wrp->master->type) { 1841 case PWRAP_MT8135: 1842 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 1843 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 1844 break; 1845 case PWRAP_MT2701: 1846 case PWRAP_MT6765: 1847 case PWRAP_MT6779: 1848 case PWRAP_MT6795: 1849 case PWRAP_MT6797: 1850 case PWRAP_MT8173: 1851 case PWRAP_MT8186: 1852 case PWRAP_MT8365: 1853 case PWRAP_MT8516: 1854 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1855 break; 1856 case PWRAP_MT7622: 1857 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); 1858 break; 1859 case PWRAP_MT6873: 1860 case PWRAP_MT8183: 1861 case PWRAP_MT8195: 1862 break; 1863 } 1864 1865 /* Config cipher mode @PMIC */ 1866 pwrap_config_cipher(wrp, wrp->slave->dew_regs); 1867 1868 /* If there is any companion PMIC, configure cipher mode there too */ 1869 if (wrp->slave->comp_type > 0) 1870 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); 1871 1872 switch (wrp->slave->type) { 1873 case PMIC_MT6397: 1874 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 1875 0x1); 1876 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 1877 0x1); 1878 break; 1879 case PMIC_MT6323: 1880 case PMIC_MT6351: 1881 case PMIC_MT6357: 1882 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 1883 0x1); 1884 break; 1885 default: 1886 break; 1887 } 1888 1889 /* wait for cipher data ready@AP */ 1890 ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp, 1891 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1892 if (ret) { 1893 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); 1894 return ret; 1895 } 1896 1897 /* wait for cipher data ready@PMIC */ 1898 ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp, 1899 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1900 if (ret) { 1901 dev_err(wrp->dev, 1902 "timeout waiting for cipher data ready@PMIC\n"); 1903 return ret; 1904 } 1905 1906 /* wait for cipher mode idle */ 1907 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); 1908 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1909 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1910 if (ret) { 1911 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); 1912 return ret; 1913 } 1914 1915 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); 1916 1917 /* Write Test */ 1918 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1919 PWRAP_DEW_WRITE_TEST_VAL) || 1920 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1921 &rdata) || 1922 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { 1923 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); 1924 return -EFAULT; 1925 } 1926 1927 return 0; 1928 } 1929 pwrap_init_security(struct pmic_wrapper * wrp)1930 static int pwrap_init_security(struct pmic_wrapper *wrp) 1931 { 1932 u32 crc_val; 1933 int ret; 1934 1935 /* Enable encryption */ 1936 ret = pwrap_init_cipher(wrp); 1937 if (ret) 1938 return ret; 1939 1940 /* Signature checking - using CRC */ 1941 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1942 if (ret == 0 && wrp->slave->comp_dew_regs) 1943 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1944 1945 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); 1946 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); 1947 1948 /* CRC value */ 1949 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; 1950 if (wrp->slave->comp_dew_regs) 1951 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; 1952 1953 pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR); 1954 1955 /* PMIC Wrapper Arbiter priority */ 1956 pwrap_writel(wrp, 1957 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1958 1959 return 0; 1960 } 1961 pwrap_mt8135_init_soc_specific(struct pmic_wrapper * wrp)1962 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) 1963 { 1964 /* enable pwrap events and pwrap bridge in AP side */ 1965 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); 1966 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); 1967 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); 1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); 1969 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); 1970 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); 1971 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); 1972 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); 1973 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); 1974 1975 /* enable PMIC event out and sources */ 1976 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1977 0x1) || 1978 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1979 0xffff)) { 1980 dev_err(wrp->dev, "enable dewrap fail\n"); 1981 return -EFAULT; 1982 } 1983 1984 return 0; 1985 } 1986 pwrap_mt8173_init_soc_specific(struct pmic_wrapper * wrp)1987 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp) 1988 { 1989 /* PMIC_DEWRAP enables */ 1990 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1991 0x1) || 1992 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1993 0xffff)) { 1994 dev_err(wrp->dev, "enable dewrap fail\n"); 1995 return -EFAULT; 1996 } 1997 1998 return 0; 1999 } 2000 pwrap_mt2701_init_soc_specific(struct pmic_wrapper * wrp)2001 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) 2002 { 2003 /* GPS_INTF initialization */ 2004 switch (wrp->slave->type) { 2005 case PMIC_MT6323: 2006 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR); 2007 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD); 2008 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR); 2009 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1); 2010 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2); 2011 break; 2012 default: 2013 break; 2014 } 2015 2016 return 0; 2017 } 2018 pwrap_mt6795_init_soc_specific(struct pmic_wrapper * wrp)2019 static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) 2020 { 2021 pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); 2022 2023 if (wrp->slave->type == PMIC_MT6331) 2024 pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); 2025 2026 if (wrp->slave->comp_type == PMIC_MT6332) 2027 pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); 2028 2029 return 0; 2030 } 2031 pwrap_mt7622_init_soc_specific(struct pmic_wrapper * wrp)2032 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) 2033 { 2034 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); 2035 /* enable 2wire SPI master */ 2036 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); 2037 2038 return 0; 2039 } 2040 pwrap_mt8183_init_soc_specific(struct pmic_wrapper * wrp)2041 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp) 2042 { 2043 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN); 2044 2045 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 2046 pwrap_writel(wrp, 1, PWRAP_CRC_EN); 2047 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR); 2048 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR); 2049 2050 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN); 2051 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN); 2052 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P); 2053 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32); 2054 2055 return 0; 2056 } 2057 pwrap_init(struct pmic_wrapper * wrp)2058 static int pwrap_init(struct pmic_wrapper *wrp) 2059 { 2060 int ret; 2061 2062 if (wrp->rstc) 2063 reset_control_reset(wrp->rstc); 2064 if (wrp->rstc_bridge) 2065 reset_control_reset(wrp->rstc_bridge); 2066 2067 switch (wrp->master->type) { 2068 case PWRAP_MT6795: 2069 fallthrough; 2070 case PWRAP_MT8173: 2071 /* Enable DCM */ 2072 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 2073 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2074 break; 2075 default: 2076 break; 2077 } 2078 2079 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 2080 /* Reset SPI slave */ 2081 ret = pwrap_reset_spislave(wrp); 2082 if (ret) 2083 return ret; 2084 } 2085 2086 pwrap_writel(wrp, 1, PWRAP_WRAP_EN); 2087 2088 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 2089 2090 pwrap_writel(wrp, 1, PWRAP_WACS2_EN); 2091 2092 ret = wrp->master->init_reg_clock(wrp); 2093 if (ret) 2094 return ret; 2095 2096 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 2097 /* Setup serial input delay */ 2098 ret = pwrap_init_sidly(wrp); 2099 if (ret) 2100 return ret; 2101 } 2102 2103 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { 2104 /* Enable dual I/O mode */ 2105 ret = pwrap_init_dual_io(wrp); 2106 if (ret) 2107 return ret; 2108 } 2109 2110 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { 2111 /* Enable security on bus */ 2112 ret = pwrap_init_security(wrp); 2113 if (ret) 2114 return ret; 2115 } 2116 2117 if (wrp->master->type == PWRAP_MT8135) 2118 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 2119 2120 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 2121 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); 2122 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); 2123 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); 2124 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); 2125 2126 if (wrp->master->init_soc_specific) { 2127 ret = wrp->master->init_soc_specific(wrp); 2128 if (ret) 2129 return ret; 2130 } 2131 2132 /* Setup the init done registers */ 2133 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); 2134 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 2135 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 2136 2137 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2138 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 2139 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 2140 } 2141 2142 return 0; 2143 } 2144 pwrap_interrupt(int irqno,void * dev_id)2145 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) 2146 { 2147 u32 rdata; 2148 struct pmic_wrapper *wrp = dev_id; 2149 2150 rdata = pwrap_readl(wrp, PWRAP_INT_FLG); 2151 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); 2152 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR); 2153 2154 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { 2155 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG); 2156 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); 2157 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR); 2158 } 2159 2160 return IRQ_HANDLED; 2161 } 2162 2163 static const struct regmap_config pwrap_regmap_config16 = { 2164 .reg_bits = 16, 2165 .val_bits = 16, 2166 .reg_stride = 2, 2167 .reg_read = pwrap_regmap_read, 2168 .reg_write = pwrap_regmap_write, 2169 .max_register = 0xffff, 2170 }; 2171 2172 static const struct regmap_config pwrap_regmap_config32 = { 2173 .reg_bits = 32, 2174 .val_bits = 32, 2175 .reg_stride = 4, 2176 .reg_read = pwrap_regmap_read, 2177 .reg_write = pwrap_regmap_write, 2178 .max_register = 0xffff, 2179 }; 2180 2181 static const struct pwrap_slv_regops pwrap_regops16 = { 2182 .pwrap_read = pwrap_read16, 2183 .pwrap_write = pwrap_write16, 2184 .regmap = &pwrap_regmap_config16, 2185 }; 2186 2187 static const struct pwrap_slv_regops pwrap_regops32 = { 2188 .pwrap_read = pwrap_read32, 2189 .pwrap_write = pwrap_write32, 2190 .regmap = &pwrap_regmap_config32, 2191 }; 2192 2193 static const struct pwrap_slv_type pmic_mt6323 = { 2194 .dew_regs = mt6323_regs, 2195 .type = PMIC_MT6323, 2196 .regops = &pwrap_regops16, 2197 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2198 PWRAP_SLV_CAP_SECURITY, 2199 }; 2200 2201 static const struct pwrap_slv_type pmic_mt6331 = { 2202 .dew_regs = mt6331_regs, 2203 .type = PMIC_MT6331, 2204 .comp_dew_regs = mt6332_regs, 2205 .comp_type = PMIC_MT6332, 2206 .regops = &pwrap_regops16, 2207 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2208 PWRAP_SLV_CAP_SECURITY, 2209 }; 2210 2211 static const struct pwrap_slv_type pmic_mt6351 = { 2212 .dew_regs = mt6351_regs, 2213 .type = PMIC_MT6351, 2214 .regops = &pwrap_regops16, 2215 .caps = 0, 2216 }; 2217 2218 static const struct pwrap_slv_type pmic_mt6357 = { 2219 .dew_regs = mt6357_regs, 2220 .type = PMIC_MT6357, 2221 .regops = &pwrap_regops16, 2222 .caps = 0, 2223 }; 2224 2225 static const struct pwrap_slv_type pmic_mt6358 = { 2226 .dew_regs = mt6358_regs, 2227 .type = PMIC_MT6358, 2228 .regops = &pwrap_regops16, 2229 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO, 2230 }; 2231 2232 static const struct pwrap_slv_type pmic_mt6359 = { 2233 .dew_regs = mt6359_regs, 2234 .type = PMIC_MT6359, 2235 .regops = &pwrap_regops16, 2236 .caps = PWRAP_SLV_CAP_DUALIO, 2237 }; 2238 2239 static const struct pwrap_slv_type pmic_mt6380 = { 2240 .dew_regs = NULL, 2241 .type = PMIC_MT6380, 2242 .regops = &pwrap_regops32, 2243 .caps = 0, 2244 }; 2245 2246 static const struct pwrap_slv_type pmic_mt6397 = { 2247 .dew_regs = mt6397_regs, 2248 .type = PMIC_MT6397, 2249 .regops = &pwrap_regops16, 2250 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2251 PWRAP_SLV_CAP_SECURITY, 2252 }; 2253 2254 static const struct of_device_id of_slave_match_tbl[] = { 2255 { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, 2256 { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, 2257 { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, 2258 { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, 2259 { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, 2260 { .compatible = "mediatek,mt6359", .data = &pmic_mt6359 }, 2261 2262 /* The MT6380 PMIC only implements a regulator, so we bind it 2263 * directly instead of using a MFD. 2264 */ 2265 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 }, 2266 { .compatible = "mediatek,mt6397", .data = &pmic_mt6397 }, 2267 { /* sentinel */ } 2268 }; 2269 MODULE_DEVICE_TABLE(of, of_slave_match_tbl); 2270 2271 static const struct pmic_wrapper_type pwrap_mt2701 = { 2272 .regs = mt2701_regs, 2273 .type = PWRAP_MT2701, 2274 .arb_en_all = 0x3f, 2275 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2276 .int1_en_all = 0, 2277 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, 2278 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2279 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2280 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2281 .init_soc_specific = pwrap_mt2701_init_soc_specific, 2282 }; 2283 2284 static const struct pmic_wrapper_type pwrap_mt6765 = { 2285 .regs = mt6765_regs, 2286 .type = PWRAP_MT6765, 2287 .arb_en_all = 0x3fd35, 2288 .int_en_all = 0xffffffff, 2289 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2290 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2291 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2292 .init_reg_clock = pwrap_common_init_reg_clock, 2293 .init_soc_specific = NULL, 2294 }; 2295 2296 static const struct pmic_wrapper_type pwrap_mt6779 = { 2297 .regs = mt6779_regs, 2298 .type = PWRAP_MT6779, 2299 .arb_en_all = 0xfbb7f, 2300 .int_en_all = 0xfffffffe, 2301 .int1_en_all = 0, 2302 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2303 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2304 .caps = 0, 2305 .init_reg_clock = pwrap_common_init_reg_clock, 2306 .init_soc_specific = NULL, 2307 }; 2308 2309 static const struct pmic_wrapper_type pwrap_mt6795 = { 2310 .regs = mt6795_regs, 2311 .type = PWRAP_MT6795, 2312 .arb_en_all = 0x3f, 2313 .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)), 2314 .int1_en_all = 0, 2315 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2316 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2317 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2318 .init_reg_clock = pwrap_common_init_reg_clock, 2319 .init_soc_specific = pwrap_mt6795_init_soc_specific, 2320 }; 2321 2322 static const struct pmic_wrapper_type pwrap_mt6797 = { 2323 .regs = mt6797_regs, 2324 .type = PWRAP_MT6797, 2325 .arb_en_all = 0x01fff, 2326 .int_en_all = 0xffffffc6, 2327 .int1_en_all = 0, 2328 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2329 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2330 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2331 .init_reg_clock = pwrap_common_init_reg_clock, 2332 .init_soc_specific = NULL, 2333 }; 2334 2335 static const struct pmic_wrapper_type pwrap_mt6873 = { 2336 .regs = mt6873_regs, 2337 .type = PWRAP_MT6873, 2338 .arb_en_all = 0x777f, 2339 .int_en_all = BIT(4) | BIT(5), 2340 .int1_en_all = 0, 2341 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2342 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2343 .caps = PWRAP_CAP_ARB, 2344 .init_reg_clock = pwrap_common_init_reg_clock, 2345 .init_soc_specific = NULL, 2346 }; 2347 2348 static const struct pmic_wrapper_type pwrap_mt7622 = { 2349 .regs = mt7622_regs, 2350 .type = PWRAP_MT7622, 2351 .arb_en_all = 0xff, 2352 .int_en_all = ~(u32)BIT(31), 2353 .int1_en_all = 0, 2354 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2355 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2356 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2357 .init_reg_clock = pwrap_common_init_reg_clock, 2358 .init_soc_specific = pwrap_mt7622_init_soc_specific, 2359 }; 2360 2361 static const struct pmic_wrapper_type pwrap_mt8135 = { 2362 .regs = mt8135_regs, 2363 .type = PWRAP_MT8135, 2364 .arb_en_all = 0x1ff, 2365 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2366 .int1_en_all = 0, 2367 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2368 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2369 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2370 .init_reg_clock = pwrap_common_init_reg_clock, 2371 .init_soc_specific = pwrap_mt8135_init_soc_specific, 2372 }; 2373 2374 static const struct pmic_wrapper_type pwrap_mt8173 = { 2375 .regs = mt8173_regs, 2376 .type = PWRAP_MT8173, 2377 .arb_en_all = 0x3f, 2378 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2379 .int1_en_all = 0, 2380 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2381 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2382 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2383 .init_reg_clock = pwrap_common_init_reg_clock, 2384 .init_soc_specific = pwrap_mt8173_init_soc_specific, 2385 }; 2386 2387 static const struct pmic_wrapper_type pwrap_mt8183 = { 2388 .regs = mt8183_regs, 2389 .type = PWRAP_MT8183, 2390 .arb_en_all = 0x3fa75, 2391 .int_en_all = 0xffffffff, 2392 .int1_en_all = 0xeef7ffff, 2393 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2394 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2395 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2396 .init_reg_clock = pwrap_common_init_reg_clock, 2397 .init_soc_specific = pwrap_mt8183_init_soc_specific, 2398 }; 2399 2400 static struct pmic_wrapper_type pwrap_mt8195 = { 2401 .regs = mt8195_regs, 2402 .type = PWRAP_MT8195, 2403 .arb_en_all = 0x777f, /* NEED CONFIRM */ 2404 .int_en_all = 0x180000, /* NEED CONFIRM */ 2405 .int1_en_all = 0, 2406 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2407 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2408 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, 2409 .init_reg_clock = pwrap_common_init_reg_clock, 2410 .init_soc_specific = NULL, 2411 }; 2412 2413 static const struct pmic_wrapper_type pwrap_mt8365 = { 2414 .regs = mt8365_regs, 2415 .type = PWRAP_MT8365, 2416 .arb_en_all = 0x3ffff, 2417 .int_en_all = 0x7f1fffff, 2418 .int1_en_all = 0x0, 2419 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2420 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2421 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2422 .init_reg_clock = pwrap_common_init_reg_clock, 2423 .init_soc_specific = NULL, 2424 }; 2425 2426 static struct pmic_wrapper_type pwrap_mt8516 = { 2427 .regs = mt8516_regs, 2428 .type = PWRAP_MT8516, 2429 .arb_en_all = 0xff, 2430 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2431 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2432 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2433 .caps = PWRAP_CAP_DCM, 2434 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2435 .init_soc_specific = NULL, 2436 }; 2437 2438 static struct pmic_wrapper_type pwrap_mt8186 = { 2439 .regs = mt8186_regs, 2440 .type = PWRAP_MT8186, 2441 .arb_en_all = 0xfb27f, 2442 .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ 2443 .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */ 2444 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2445 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2446 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, 2447 .init_reg_clock = pwrap_common_init_reg_clock, 2448 .init_soc_specific = NULL, 2449 }; 2450 2451 static const struct of_device_id of_pwrap_match_tbl[] = { 2452 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, 2453 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, 2454 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, 2455 { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, 2456 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, 2457 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, 2458 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, 2459 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 }, 2460 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 }, 2461 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 }, 2462 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 }, 2463 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 }, 2464 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 }, 2465 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 }, 2466 { /* sentinel */ } 2467 }; 2468 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); 2469 pwrap_probe(struct platform_device * pdev)2470 static int pwrap_probe(struct platform_device *pdev) 2471 { 2472 int ret, irq; 2473 u32 mask_done; 2474 struct pmic_wrapper *wrp; 2475 struct device_node *np = pdev->dev.of_node; 2476 const struct of_device_id *of_slave_id = NULL; 2477 2478 if (np->child) 2479 of_slave_id = of_match_node(of_slave_match_tbl, np->child); 2480 2481 if (!of_slave_id) { 2482 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); 2483 return -EINVAL; 2484 } 2485 2486 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); 2487 if (!wrp) 2488 return -ENOMEM; 2489 2490 platform_set_drvdata(pdev, wrp); 2491 2492 wrp->master = of_device_get_match_data(&pdev->dev); 2493 wrp->slave = of_slave_id->data; 2494 wrp->dev = &pdev->dev; 2495 2496 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap"); 2497 if (IS_ERR(wrp->base)) 2498 return PTR_ERR(wrp->base); 2499 2500 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { 2501 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); 2502 if (IS_ERR(wrp->rstc)) { 2503 ret = PTR_ERR(wrp->rstc); 2504 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); 2505 return ret; 2506 } 2507 } 2508 2509 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2510 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge"); 2511 if (IS_ERR(wrp->bridge_base)) 2512 return PTR_ERR(wrp->bridge_base); 2513 2514 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, 2515 "pwrap-bridge"); 2516 if (IS_ERR(wrp->rstc_bridge)) { 2517 ret = PTR_ERR(wrp->rstc_bridge); 2518 dev_dbg(wrp->dev, 2519 "cannot get pwrap-bridge reset: %d\n", ret); 2520 return ret; 2521 } 2522 } 2523 2524 wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); 2525 if (IS_ERR(wrp->clk_spi)) { 2526 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2527 PTR_ERR(wrp->clk_spi)); 2528 return PTR_ERR(wrp->clk_spi); 2529 } 2530 2531 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); 2532 if (IS_ERR(wrp->clk_wrap)) { 2533 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2534 PTR_ERR(wrp->clk_wrap)); 2535 return PTR_ERR(wrp->clk_wrap); 2536 } 2537 2538 wrp->clk_sys = devm_clk_get_optional(wrp->dev, "sys"); 2539 if (IS_ERR(wrp->clk_sys)) { 2540 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys), 2541 "failed to get clock: %pe\n", 2542 wrp->clk_sys); 2543 } 2544 2545 wrp->clk_tmr = devm_clk_get_optional(wrp->dev, "tmr"); 2546 if (IS_ERR(wrp->clk_tmr)) { 2547 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr), 2548 "failed to get clock: %pe\n", 2549 wrp->clk_tmr); 2550 } 2551 2552 ret = clk_prepare_enable(wrp->clk_spi); 2553 if (ret) 2554 return ret; 2555 2556 ret = clk_prepare_enable(wrp->clk_wrap); 2557 if (ret) 2558 goto err_out1; 2559 2560 ret = clk_prepare_enable(wrp->clk_sys); 2561 if (ret) 2562 goto err_out2; 2563 2564 ret = clk_prepare_enable(wrp->clk_tmr); 2565 if (ret) 2566 goto err_out3; 2567 2568 /* Enable internal dynamic clock */ 2569 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { 2570 pwrap_writel(wrp, 1, PWRAP_DCM_EN); 2571 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2572 } 2573 2574 /* 2575 * The PMIC could already be initialized by the bootloader. 2576 * Skip initialization here in this case. 2577 */ 2578 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { 2579 ret = pwrap_init(wrp); 2580 if (ret) { 2581 dev_dbg(wrp->dev, "init failed with %d\n", ret); 2582 goto err_out4; 2583 } 2584 } 2585 2586 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2587 mask_done = PWRAP_STATE_INIT_DONE1; 2588 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) 2589 mask_done = PWRAP_STATE_INIT_DONE0_MT8186; 2590 else 2591 mask_done = PWRAP_STATE_INIT_DONE0; 2592 2593 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { 2594 dev_dbg(wrp->dev, "initialization isn't finished\n"); 2595 ret = -ENODEV; 2596 goto err_out4; 2597 } 2598 2599 /* Initialize watchdog, may not be done by the bootloader */ 2600 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2601 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); 2602 2603 /* 2604 * Since STAUPD was not used on mt8173 platform, 2605 * so STAUPD of WDT_SRC which should be turned off 2606 */ 2607 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); 2608 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) 2609 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); 2610 2611 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2612 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); 2613 else 2614 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); 2615 2616 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); 2617 /* 2618 * We add INT1 interrupt to handle starvation and request exception 2619 * If we support it, we should enable it here. 2620 */ 2621 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) 2622 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); 2623 2624 irq = platform_get_irq(pdev, 0); 2625 if (irq < 0) { 2626 ret = irq; 2627 goto err_out2; 2628 } 2629 2630 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, 2631 IRQF_TRIGGER_HIGH, 2632 "mt-pmic-pwrap", wrp); 2633 if (ret) 2634 goto err_out4; 2635 2636 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap); 2637 if (IS_ERR(wrp->regmap)) { 2638 ret = PTR_ERR(wrp->regmap); 2639 goto err_out2; 2640 } 2641 2642 ret = of_platform_populate(np, NULL, NULL, wrp->dev); 2643 if (ret) { 2644 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", 2645 np); 2646 goto err_out4; 2647 } 2648 2649 return 0; 2650 2651 err_out4: 2652 clk_disable_unprepare(wrp->clk_tmr); 2653 err_out3: 2654 clk_disable_unprepare(wrp->clk_sys); 2655 err_out2: 2656 clk_disable_unprepare(wrp->clk_wrap); 2657 err_out1: 2658 clk_disable_unprepare(wrp->clk_spi); 2659 2660 return ret; 2661 } 2662 2663 static struct platform_driver pwrap_drv = { 2664 .driver = { 2665 .name = "mt-pmic-pwrap", 2666 .of_match_table = of_pwrap_match_tbl, 2667 }, 2668 .probe = pwrap_probe, 2669 }; 2670 2671 module_platform_driver(pwrap_drv); 2672 2673 MODULE_AUTHOR("Flora Fu, MediaTek"); 2674 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver"); 2675 MODULE_LICENSE("GPL v2"); 2676