xref: /openbmc/linux/drivers/clk/qcom/gcc-msm8960.c (revision c4dc24da)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16 
17 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
19 
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "clk-hfpll.h"
26 #include "reset.h"
27 
28 static struct clk_pll pll3 = {
29 	.l_reg = 0x3164,
30 	.m_reg = 0x3168,
31 	.n_reg = 0x316c,
32 	.config_reg = 0x3174,
33 	.mode_reg = 0x3160,
34 	.status_reg = 0x3178,
35 	.status_bit = 16,
36 	.clkr.hw.init = &(struct clk_init_data){
37 		.name = "pll3",
38 		.parent_data = &(const struct clk_parent_data){
39 			.fw_name = "pxo", .name = "pxo_board",
40 		},
41 		.num_parents = 1,
42 		.ops = &clk_pll_ops,
43 	},
44 };
45 
46 static struct clk_regmap pll4_vote = {
47 	.enable_reg = 0x34c0,
48 	.enable_mask = BIT(4),
49 	.hw.init = &(struct clk_init_data){
50 		.name = "pll4_vote",
51 		.parent_data = &(const struct clk_parent_data){
52 			.fw_name = "pll4", .name = "pll4",
53 		},
54 		.num_parents = 1,
55 		.ops = &clk_pll_vote_ops,
56 	},
57 };
58 
59 static struct clk_pll pll8 = {
60 	.l_reg = 0x3144,
61 	.m_reg = 0x3148,
62 	.n_reg = 0x314c,
63 	.config_reg = 0x3154,
64 	.mode_reg = 0x3140,
65 	.status_reg = 0x3158,
66 	.status_bit = 16,
67 	.clkr.hw.init = &(struct clk_init_data){
68 		.name = "pll8",
69 		.parent_data = &(const struct clk_parent_data){
70 			.fw_name = "pxo", .name = "pxo_board",
71 		},
72 		.num_parents = 1,
73 		.ops = &clk_pll_ops,
74 	},
75 };
76 
77 static struct clk_regmap pll8_vote = {
78 	.enable_reg = 0x34c0,
79 	.enable_mask = BIT(8),
80 	.hw.init = &(struct clk_init_data){
81 		.name = "pll8_vote",
82 		.parent_hws = (const struct clk_hw*[]){
83 			&pll8.clkr.hw
84 		},
85 		.num_parents = 1,
86 		.ops = &clk_pll_vote_ops,
87 	},
88 };
89 
90 static struct hfpll_data hfpll0_data = {
91 	.mode_reg = 0x3200,
92 	.l_reg = 0x3208,
93 	.m_reg = 0x320c,
94 	.n_reg = 0x3210,
95 	.config_reg = 0x3204,
96 	.status_reg = 0x321c,
97 	.config_val = 0x7845c665,
98 	.droop_reg = 0x3214,
99 	.droop_val = 0x0108c000,
100 	.min_rate = 600000000UL,
101 	.max_rate = 1800000000UL,
102 };
103 
104 static struct clk_hfpll hfpll0 = {
105 	.d = &hfpll0_data,
106 	.clkr.hw.init = &(struct clk_init_data){
107 		.parent_data = &(const struct clk_parent_data){
108 			.fw_name = "pxo", .name = "pxo_board",
109 		},
110 		.num_parents = 1,
111 		.name = "hfpll0",
112 		.ops = &clk_ops_hfpll,
113 		.flags = CLK_IGNORE_UNUSED,
114 	},
115 	.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
116 };
117 
118 static struct hfpll_data hfpll1_8064_data = {
119 	.mode_reg = 0x3240,
120 	.l_reg = 0x3248,
121 	.m_reg = 0x324c,
122 	.n_reg = 0x3250,
123 	.config_reg = 0x3244,
124 	.status_reg = 0x325c,
125 	.config_val = 0x7845c665,
126 	.droop_reg = 0x3254,
127 	.droop_val = 0x0108c000,
128 	.min_rate = 600000000UL,
129 	.max_rate = 1800000000UL,
130 };
131 
132 static struct hfpll_data hfpll1_data = {
133 	.mode_reg = 0x3300,
134 	.l_reg = 0x3308,
135 	.m_reg = 0x330c,
136 	.n_reg = 0x3310,
137 	.config_reg = 0x3304,
138 	.status_reg = 0x331c,
139 	.config_val = 0x7845c665,
140 	.droop_reg = 0x3314,
141 	.droop_val = 0x0108c000,
142 	.min_rate = 600000000UL,
143 	.max_rate = 1800000000UL,
144 };
145 
146 static struct clk_hfpll hfpll1 = {
147 	.d = &hfpll1_data,
148 	.clkr.hw.init = &(struct clk_init_data){
149 		.parent_data = &(const struct clk_parent_data){
150 			.fw_name = "pxo", .name = "pxo_board",
151 		},
152 		.num_parents = 1,
153 		.name = "hfpll1",
154 		.ops = &clk_ops_hfpll,
155 		.flags = CLK_IGNORE_UNUSED,
156 	},
157 	.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
158 };
159 
160 static struct hfpll_data hfpll2_data = {
161 	.mode_reg = 0x3280,
162 	.l_reg = 0x3288,
163 	.m_reg = 0x328c,
164 	.n_reg = 0x3290,
165 	.config_reg = 0x3284,
166 	.status_reg = 0x329c,
167 	.config_val = 0x7845c665,
168 	.droop_reg = 0x3294,
169 	.droop_val = 0x0108c000,
170 	.min_rate = 600000000UL,
171 	.max_rate = 1800000000UL,
172 };
173 
174 static struct clk_hfpll hfpll2 = {
175 	.d = &hfpll2_data,
176 	.clkr.hw.init = &(struct clk_init_data){
177 		.parent_data = &(const struct clk_parent_data){
178 			.fw_name = "pxo", .name = "pxo_board",
179 		},
180 		.num_parents = 1,
181 		.name = "hfpll2",
182 		.ops = &clk_ops_hfpll,
183 		.flags = CLK_IGNORE_UNUSED,
184 	},
185 	.lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
186 };
187 
188 static struct hfpll_data hfpll3_data = {
189 	.mode_reg = 0x32c0,
190 	.l_reg = 0x32c8,
191 	.m_reg = 0x32cc,
192 	.n_reg = 0x32d0,
193 	.config_reg = 0x32c4,
194 	.status_reg = 0x32dc,
195 	.config_val = 0x7845c665,
196 	.droop_reg = 0x32d4,
197 	.droop_val = 0x0108c000,
198 	.min_rate = 600000000UL,
199 	.max_rate = 1800000000UL,
200 };
201 
202 static struct clk_hfpll hfpll3 = {
203 	.d = &hfpll3_data,
204 	.clkr.hw.init = &(struct clk_init_data){
205 		.parent_data = &(const struct clk_parent_data){
206 			.fw_name = "pxo", .name = "pxo_board",
207 		},
208 		.num_parents = 1,
209 		.name = "hfpll3",
210 		.ops = &clk_ops_hfpll,
211 		.flags = CLK_IGNORE_UNUSED,
212 	},
213 	.lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
214 };
215 
216 static struct hfpll_data hfpll_l2_8064_data = {
217 	.mode_reg = 0x3300,
218 	.l_reg = 0x3308,
219 	.m_reg = 0x330c,
220 	.n_reg = 0x3310,
221 	.config_reg = 0x3304,
222 	.status_reg = 0x331c,
223 	.config_val = 0x7845c665,
224 	.droop_reg = 0x3314,
225 	.droop_val = 0x0108c000,
226 	.min_rate = 600000000UL,
227 	.max_rate = 1800000000UL,
228 };
229 
230 static struct hfpll_data hfpll_l2_data = {
231 	.mode_reg = 0x3400,
232 	.l_reg = 0x3408,
233 	.m_reg = 0x340c,
234 	.n_reg = 0x3410,
235 	.config_reg = 0x3404,
236 	.status_reg = 0x341c,
237 	.config_val = 0x7845c665,
238 	.droop_reg = 0x3414,
239 	.droop_val = 0x0108c000,
240 	.min_rate = 600000000UL,
241 	.max_rate = 1800000000UL,
242 };
243 
244 static struct clk_hfpll hfpll_l2 = {
245 	.d = &hfpll_l2_data,
246 	.clkr.hw.init = &(struct clk_init_data){
247 		.parent_data = &(const struct clk_parent_data){
248 			.fw_name = "pxo", .name = "pxo_board",
249 		},
250 		.num_parents = 1,
251 		.name = "hfpll_l2",
252 		.ops = &clk_ops_hfpll,
253 		.flags = CLK_IGNORE_UNUSED,
254 	},
255 	.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
256 };
257 
258 static struct clk_pll pll14 = {
259 	.l_reg = 0x31c4,
260 	.m_reg = 0x31c8,
261 	.n_reg = 0x31cc,
262 	.config_reg = 0x31d4,
263 	.mode_reg = 0x31c0,
264 	.status_reg = 0x31d8,
265 	.status_bit = 16,
266 	.clkr.hw.init = &(struct clk_init_data){
267 		.name = "pll14",
268 		.parent_data = &(const struct clk_parent_data){
269 			.fw_name = "pxo", .name = "pxo_board",
270 		},
271 		.num_parents = 1,
272 		.ops = &clk_pll_ops,
273 	},
274 };
275 
276 static struct clk_regmap pll14_vote = {
277 	.enable_reg = 0x34c0,
278 	.enable_mask = BIT(14),
279 	.hw.init = &(struct clk_init_data){
280 		.name = "pll14_vote",
281 		.parent_hws = (const struct clk_hw*[]){
282 			&pll14.clkr.hw
283 		},
284 		.num_parents = 1,
285 		.ops = &clk_pll_vote_ops,
286 	},
287 };
288 
289 enum {
290 	P_PXO,
291 	P_PLL8,
292 	P_PLL3,
293 	P_CXO,
294 };
295 
296 static const struct parent_map gcc_pxo_pll8_map[] = {
297 	{ P_PXO, 0 },
298 	{ P_PLL8, 3 }
299 };
300 
301 static const struct clk_parent_data gcc_pxo_pll8[] = {
302 	{ .fw_name = "pxo", .name = "pxo_board" },
303 	{ .hw = &pll8_vote.hw },
304 };
305 
306 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
307 	{ P_PXO, 0 },
308 	{ P_PLL8, 3 },
309 	{ P_CXO, 5 }
310 };
311 
312 static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
313 	{ .fw_name = "pxo", .name = "pxo_board" },
314 	{ .hw = &pll8_vote.hw },
315 	{ .fw_name = "cxo", .name = "cxo_board" },
316 };
317 
318 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
319 	{ P_PXO, 0 },
320 	{ P_PLL8, 3 },
321 	{ P_PLL3, 6 }
322 };
323 
324 static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
325 	{ .fw_name = "pxo", .name = "pxo_board" },
326 	{ .hw = &pll8_vote.hw },
327 	{ .hw = &pll3.clkr.hw },
328 };
329 
330 static struct freq_tbl clk_tbl_gsbi_uart[] = {
331 	{  1843200, P_PLL8, 2,  6, 625 },
332 	{  3686400, P_PLL8, 2, 12, 625 },
333 	{  7372800, P_PLL8, 2, 24, 625 },
334 	{ 14745600, P_PLL8, 2, 48, 625 },
335 	{ 16000000, P_PLL8, 4,  1,   6 },
336 	{ 24000000, P_PLL8, 4,  1,   4 },
337 	{ 32000000, P_PLL8, 4,  1,   3 },
338 	{ 40000000, P_PLL8, 1,  5,  48 },
339 	{ 46400000, P_PLL8, 1, 29, 240 },
340 	{ 48000000, P_PLL8, 4,  1,   2 },
341 	{ 51200000, P_PLL8, 1,  2,  15 },
342 	{ 56000000, P_PLL8, 1,  7,  48 },
343 	{ 58982400, P_PLL8, 1, 96, 625 },
344 	{ 64000000, P_PLL8, 2,  1,   3 },
345 	{ }
346 };
347 
348 static struct clk_rcg gsbi1_uart_src = {
349 	.ns_reg = 0x29d4,
350 	.md_reg = 0x29d0,
351 	.mn = {
352 		.mnctr_en_bit = 8,
353 		.mnctr_reset_bit = 7,
354 		.mnctr_mode_shift = 5,
355 		.n_val_shift = 16,
356 		.m_val_shift = 16,
357 		.width = 16,
358 	},
359 	.p = {
360 		.pre_div_shift = 3,
361 		.pre_div_width = 2,
362 	},
363 	.s = {
364 		.src_sel_shift = 0,
365 		.parent_map = gcc_pxo_pll8_map,
366 	},
367 	.freq_tbl = clk_tbl_gsbi_uart,
368 	.clkr = {
369 		.enable_reg = 0x29d4,
370 		.enable_mask = BIT(11),
371 		.hw.init = &(struct clk_init_data){
372 			.name = "gsbi1_uart_src",
373 			.parent_data = gcc_pxo_pll8,
374 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
375 			.ops = &clk_rcg_ops,
376 			.flags = CLK_SET_PARENT_GATE,
377 		},
378 	},
379 };
380 
381 static struct clk_branch gsbi1_uart_clk = {
382 	.halt_reg = 0x2fcc,
383 	.halt_bit = 10,
384 	.clkr = {
385 		.enable_reg = 0x29d4,
386 		.enable_mask = BIT(9),
387 		.hw.init = &(struct clk_init_data){
388 			.name = "gsbi1_uart_clk",
389 			.parent_hws = (const struct clk_hw*[]){
390 				&gsbi1_uart_src.clkr.hw
391 			},
392 			.num_parents = 1,
393 			.ops = &clk_branch_ops,
394 			.flags = CLK_SET_RATE_PARENT,
395 		},
396 	},
397 };
398 
399 static struct clk_rcg gsbi2_uart_src = {
400 	.ns_reg = 0x29f4,
401 	.md_reg = 0x29f0,
402 	.mn = {
403 		.mnctr_en_bit = 8,
404 		.mnctr_reset_bit = 7,
405 		.mnctr_mode_shift = 5,
406 		.n_val_shift = 16,
407 		.m_val_shift = 16,
408 		.width = 16,
409 	},
410 	.p = {
411 		.pre_div_shift = 3,
412 		.pre_div_width = 2,
413 	},
414 	.s = {
415 		.src_sel_shift = 0,
416 		.parent_map = gcc_pxo_pll8_map,
417 	},
418 	.freq_tbl = clk_tbl_gsbi_uart,
419 	.clkr = {
420 		.enable_reg = 0x29f4,
421 		.enable_mask = BIT(11),
422 		.hw.init = &(struct clk_init_data){
423 			.name = "gsbi2_uart_src",
424 			.parent_data = gcc_pxo_pll8,
425 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
426 			.ops = &clk_rcg_ops,
427 			.flags = CLK_SET_PARENT_GATE,
428 		},
429 	},
430 };
431 
432 static struct clk_branch gsbi2_uart_clk = {
433 	.halt_reg = 0x2fcc,
434 	.halt_bit = 6,
435 	.clkr = {
436 		.enable_reg = 0x29f4,
437 		.enable_mask = BIT(9),
438 		.hw.init = &(struct clk_init_data){
439 			.name = "gsbi2_uart_clk",
440 			.parent_hws = (const struct clk_hw*[]){
441 				&gsbi2_uart_src.clkr.hw
442 			},
443 			.num_parents = 1,
444 			.ops = &clk_branch_ops,
445 			.flags = CLK_SET_RATE_PARENT,
446 		},
447 	},
448 };
449 
450 static struct clk_rcg gsbi3_uart_src = {
451 	.ns_reg = 0x2a14,
452 	.md_reg = 0x2a10,
453 	.mn = {
454 		.mnctr_en_bit = 8,
455 		.mnctr_reset_bit = 7,
456 		.mnctr_mode_shift = 5,
457 		.n_val_shift = 16,
458 		.m_val_shift = 16,
459 		.width = 16,
460 	},
461 	.p = {
462 		.pre_div_shift = 3,
463 		.pre_div_width = 2,
464 	},
465 	.s = {
466 		.src_sel_shift = 0,
467 		.parent_map = gcc_pxo_pll8_map,
468 	},
469 	.freq_tbl = clk_tbl_gsbi_uart,
470 	.clkr = {
471 		.enable_reg = 0x2a14,
472 		.enable_mask = BIT(11),
473 		.hw.init = &(struct clk_init_data){
474 			.name = "gsbi3_uart_src",
475 			.parent_data = gcc_pxo_pll8,
476 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
477 			.ops = &clk_rcg_ops,
478 			.flags = CLK_SET_PARENT_GATE,
479 		},
480 	},
481 };
482 
483 static struct clk_branch gsbi3_uart_clk = {
484 	.halt_reg = 0x2fcc,
485 	.halt_bit = 2,
486 	.clkr = {
487 		.enable_reg = 0x2a14,
488 		.enable_mask = BIT(9),
489 		.hw.init = &(struct clk_init_data){
490 			.name = "gsbi3_uart_clk",
491 			.parent_hws = (const struct clk_hw*[]){
492 				&gsbi3_uart_src.clkr.hw
493 			},
494 			.num_parents = 1,
495 			.ops = &clk_branch_ops,
496 			.flags = CLK_SET_RATE_PARENT,
497 		},
498 	},
499 };
500 
501 static struct clk_rcg gsbi4_uart_src = {
502 	.ns_reg = 0x2a34,
503 	.md_reg = 0x2a30,
504 	.mn = {
505 		.mnctr_en_bit = 8,
506 		.mnctr_reset_bit = 7,
507 		.mnctr_mode_shift = 5,
508 		.n_val_shift = 16,
509 		.m_val_shift = 16,
510 		.width = 16,
511 	},
512 	.p = {
513 		.pre_div_shift = 3,
514 		.pre_div_width = 2,
515 	},
516 	.s = {
517 		.src_sel_shift = 0,
518 		.parent_map = gcc_pxo_pll8_map,
519 	},
520 	.freq_tbl = clk_tbl_gsbi_uart,
521 	.clkr = {
522 		.enable_reg = 0x2a34,
523 		.enable_mask = BIT(11),
524 		.hw.init = &(struct clk_init_data){
525 			.name = "gsbi4_uart_src",
526 			.parent_data = gcc_pxo_pll8,
527 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
528 			.ops = &clk_rcg_ops,
529 			.flags = CLK_SET_PARENT_GATE,
530 		},
531 	},
532 };
533 
534 static struct clk_branch gsbi4_uart_clk = {
535 	.halt_reg = 0x2fd0,
536 	.halt_bit = 26,
537 	.clkr = {
538 		.enable_reg = 0x2a34,
539 		.enable_mask = BIT(9),
540 		.hw.init = &(struct clk_init_data){
541 			.name = "gsbi4_uart_clk",
542 			.parent_hws = (const struct clk_hw*[]){
543 				&gsbi4_uart_src.clkr.hw
544 			},
545 			.num_parents = 1,
546 			.ops = &clk_branch_ops,
547 			.flags = CLK_SET_RATE_PARENT,
548 		},
549 	},
550 };
551 
552 static struct clk_rcg gsbi5_uart_src = {
553 	.ns_reg = 0x2a54,
554 	.md_reg = 0x2a50,
555 	.mn = {
556 		.mnctr_en_bit = 8,
557 		.mnctr_reset_bit = 7,
558 		.mnctr_mode_shift = 5,
559 		.n_val_shift = 16,
560 		.m_val_shift = 16,
561 		.width = 16,
562 	},
563 	.p = {
564 		.pre_div_shift = 3,
565 		.pre_div_width = 2,
566 	},
567 	.s = {
568 		.src_sel_shift = 0,
569 		.parent_map = gcc_pxo_pll8_map,
570 	},
571 	.freq_tbl = clk_tbl_gsbi_uart,
572 	.clkr = {
573 		.enable_reg = 0x2a54,
574 		.enable_mask = BIT(11),
575 		.hw.init = &(struct clk_init_data){
576 			.name = "gsbi5_uart_src",
577 			.parent_data = gcc_pxo_pll8,
578 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
579 			.ops = &clk_rcg_ops,
580 			.flags = CLK_SET_PARENT_GATE,
581 		},
582 	},
583 };
584 
585 static struct clk_branch gsbi5_uart_clk = {
586 	.halt_reg = 0x2fd0,
587 	.halt_bit = 22,
588 	.clkr = {
589 		.enable_reg = 0x2a54,
590 		.enable_mask = BIT(9),
591 		.hw.init = &(struct clk_init_data){
592 			.name = "gsbi5_uart_clk",
593 			.parent_hws = (const struct clk_hw*[]){
594 				&gsbi5_uart_src.clkr.hw
595 			},
596 			.num_parents = 1,
597 			.ops = &clk_branch_ops,
598 			.flags = CLK_SET_RATE_PARENT,
599 		},
600 	},
601 };
602 
603 static struct clk_rcg gsbi6_uart_src = {
604 	.ns_reg = 0x2a74,
605 	.md_reg = 0x2a70,
606 	.mn = {
607 		.mnctr_en_bit = 8,
608 		.mnctr_reset_bit = 7,
609 		.mnctr_mode_shift = 5,
610 		.n_val_shift = 16,
611 		.m_val_shift = 16,
612 		.width = 16,
613 	},
614 	.p = {
615 		.pre_div_shift = 3,
616 		.pre_div_width = 2,
617 	},
618 	.s = {
619 		.src_sel_shift = 0,
620 		.parent_map = gcc_pxo_pll8_map,
621 	},
622 	.freq_tbl = clk_tbl_gsbi_uart,
623 	.clkr = {
624 		.enable_reg = 0x2a74,
625 		.enable_mask = BIT(11),
626 		.hw.init = &(struct clk_init_data){
627 			.name = "gsbi6_uart_src",
628 			.parent_data = gcc_pxo_pll8,
629 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
630 			.ops = &clk_rcg_ops,
631 			.flags = CLK_SET_PARENT_GATE,
632 		},
633 	},
634 };
635 
636 static struct clk_branch gsbi6_uart_clk = {
637 	.halt_reg = 0x2fd0,
638 	.halt_bit = 18,
639 	.clkr = {
640 		.enable_reg = 0x2a74,
641 		.enable_mask = BIT(9),
642 		.hw.init = &(struct clk_init_data){
643 			.name = "gsbi6_uart_clk",
644 			.parent_hws = (const struct clk_hw*[]){
645 				&gsbi6_uart_src.clkr.hw
646 			},
647 			.num_parents = 1,
648 			.ops = &clk_branch_ops,
649 			.flags = CLK_SET_RATE_PARENT,
650 		},
651 	},
652 };
653 
654 static struct clk_rcg gsbi7_uart_src = {
655 	.ns_reg = 0x2a94,
656 	.md_reg = 0x2a90,
657 	.mn = {
658 		.mnctr_en_bit = 8,
659 		.mnctr_reset_bit = 7,
660 		.mnctr_mode_shift = 5,
661 		.n_val_shift = 16,
662 		.m_val_shift = 16,
663 		.width = 16,
664 	},
665 	.p = {
666 		.pre_div_shift = 3,
667 		.pre_div_width = 2,
668 	},
669 	.s = {
670 		.src_sel_shift = 0,
671 		.parent_map = gcc_pxo_pll8_map,
672 	},
673 	.freq_tbl = clk_tbl_gsbi_uart,
674 	.clkr = {
675 		.enable_reg = 0x2a94,
676 		.enable_mask = BIT(11),
677 		.hw.init = &(struct clk_init_data){
678 			.name = "gsbi7_uart_src",
679 			.parent_data = gcc_pxo_pll8,
680 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
681 			.ops = &clk_rcg_ops,
682 			.flags = CLK_SET_PARENT_GATE,
683 		},
684 	},
685 };
686 
687 static struct clk_branch gsbi7_uart_clk = {
688 	.halt_reg = 0x2fd0,
689 	.halt_bit = 14,
690 	.clkr = {
691 		.enable_reg = 0x2a94,
692 		.enable_mask = BIT(9),
693 		.hw.init = &(struct clk_init_data){
694 			.name = "gsbi7_uart_clk",
695 			.parent_hws = (const struct clk_hw*[]){
696 				&gsbi7_uart_src.clkr.hw
697 			},
698 			.num_parents = 1,
699 			.ops = &clk_branch_ops,
700 			.flags = CLK_SET_RATE_PARENT,
701 		},
702 	},
703 };
704 
705 static struct clk_rcg gsbi8_uart_src = {
706 	.ns_reg = 0x2ab4,
707 	.md_reg = 0x2ab0,
708 	.mn = {
709 		.mnctr_en_bit = 8,
710 		.mnctr_reset_bit = 7,
711 		.mnctr_mode_shift = 5,
712 		.n_val_shift = 16,
713 		.m_val_shift = 16,
714 		.width = 16,
715 	},
716 	.p = {
717 		.pre_div_shift = 3,
718 		.pre_div_width = 2,
719 	},
720 	.s = {
721 		.src_sel_shift = 0,
722 		.parent_map = gcc_pxo_pll8_map,
723 	},
724 	.freq_tbl = clk_tbl_gsbi_uart,
725 	.clkr = {
726 		.enable_reg = 0x2ab4,
727 		.enable_mask = BIT(11),
728 		.hw.init = &(struct clk_init_data){
729 			.name = "gsbi8_uart_src",
730 			.parent_data = gcc_pxo_pll8,
731 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
732 			.ops = &clk_rcg_ops,
733 			.flags = CLK_SET_PARENT_GATE,
734 		},
735 	},
736 };
737 
738 static struct clk_branch gsbi8_uart_clk = {
739 	.halt_reg = 0x2fd0,
740 	.halt_bit = 10,
741 	.clkr = {
742 		.enable_reg = 0x2ab4,
743 		.enable_mask = BIT(9),
744 		.hw.init = &(struct clk_init_data){
745 			.name = "gsbi8_uart_clk",
746 			.parent_hws = (const struct clk_hw*[]){
747 				&gsbi8_uart_src.clkr.hw
748 			},
749 			.num_parents = 1,
750 			.ops = &clk_branch_ops,
751 			.flags = CLK_SET_RATE_PARENT,
752 		},
753 	},
754 };
755 
756 static struct clk_rcg gsbi9_uart_src = {
757 	.ns_reg = 0x2ad4,
758 	.md_reg = 0x2ad0,
759 	.mn = {
760 		.mnctr_en_bit = 8,
761 		.mnctr_reset_bit = 7,
762 		.mnctr_mode_shift = 5,
763 		.n_val_shift = 16,
764 		.m_val_shift = 16,
765 		.width = 16,
766 	},
767 	.p = {
768 		.pre_div_shift = 3,
769 		.pre_div_width = 2,
770 	},
771 	.s = {
772 		.src_sel_shift = 0,
773 		.parent_map = gcc_pxo_pll8_map,
774 	},
775 	.freq_tbl = clk_tbl_gsbi_uart,
776 	.clkr = {
777 		.enable_reg = 0x2ad4,
778 		.enable_mask = BIT(11),
779 		.hw.init = &(struct clk_init_data){
780 			.name = "gsbi9_uart_src",
781 			.parent_data = gcc_pxo_pll8,
782 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
783 			.ops = &clk_rcg_ops,
784 			.flags = CLK_SET_PARENT_GATE,
785 		},
786 	},
787 };
788 
789 static struct clk_branch gsbi9_uart_clk = {
790 	.halt_reg = 0x2fd0,
791 	.halt_bit = 6,
792 	.clkr = {
793 		.enable_reg = 0x2ad4,
794 		.enable_mask = BIT(9),
795 		.hw.init = &(struct clk_init_data){
796 			.name = "gsbi9_uart_clk",
797 			.parent_hws = (const struct clk_hw*[]){
798 				&gsbi9_uart_src.clkr.hw
799 			},
800 			.num_parents = 1,
801 			.ops = &clk_branch_ops,
802 			.flags = CLK_SET_RATE_PARENT,
803 		},
804 	},
805 };
806 
807 static struct clk_rcg gsbi10_uart_src = {
808 	.ns_reg = 0x2af4,
809 	.md_reg = 0x2af0,
810 	.mn = {
811 		.mnctr_en_bit = 8,
812 		.mnctr_reset_bit = 7,
813 		.mnctr_mode_shift = 5,
814 		.n_val_shift = 16,
815 		.m_val_shift = 16,
816 		.width = 16,
817 	},
818 	.p = {
819 		.pre_div_shift = 3,
820 		.pre_div_width = 2,
821 	},
822 	.s = {
823 		.src_sel_shift = 0,
824 		.parent_map = gcc_pxo_pll8_map,
825 	},
826 	.freq_tbl = clk_tbl_gsbi_uart,
827 	.clkr = {
828 		.enable_reg = 0x2af4,
829 		.enable_mask = BIT(11),
830 		.hw.init = &(struct clk_init_data){
831 			.name = "gsbi10_uart_src",
832 			.parent_data = gcc_pxo_pll8,
833 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
834 			.ops = &clk_rcg_ops,
835 			.flags = CLK_SET_PARENT_GATE,
836 		},
837 	},
838 };
839 
840 static struct clk_branch gsbi10_uart_clk = {
841 	.halt_reg = 0x2fd0,
842 	.halt_bit = 2,
843 	.clkr = {
844 		.enable_reg = 0x2af4,
845 		.enable_mask = BIT(9),
846 		.hw.init = &(struct clk_init_data){
847 			.name = "gsbi10_uart_clk",
848 			.parent_hws = (const struct clk_hw*[]){
849 				&gsbi10_uart_src.clkr.hw
850 			},
851 			.num_parents = 1,
852 			.ops = &clk_branch_ops,
853 			.flags = CLK_SET_RATE_PARENT,
854 		},
855 	},
856 };
857 
858 static struct clk_rcg gsbi11_uart_src = {
859 	.ns_reg = 0x2b14,
860 	.md_reg = 0x2b10,
861 	.mn = {
862 		.mnctr_en_bit = 8,
863 		.mnctr_reset_bit = 7,
864 		.mnctr_mode_shift = 5,
865 		.n_val_shift = 16,
866 		.m_val_shift = 16,
867 		.width = 16,
868 	},
869 	.p = {
870 		.pre_div_shift = 3,
871 		.pre_div_width = 2,
872 	},
873 	.s = {
874 		.src_sel_shift = 0,
875 		.parent_map = gcc_pxo_pll8_map,
876 	},
877 	.freq_tbl = clk_tbl_gsbi_uart,
878 	.clkr = {
879 		.enable_reg = 0x2b14,
880 		.enable_mask = BIT(11),
881 		.hw.init = &(struct clk_init_data){
882 			.name = "gsbi11_uart_src",
883 			.parent_data = gcc_pxo_pll8,
884 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
885 			.ops = &clk_rcg_ops,
886 			.flags = CLK_SET_PARENT_GATE,
887 		},
888 	},
889 };
890 
891 static struct clk_branch gsbi11_uart_clk = {
892 	.halt_reg = 0x2fd4,
893 	.halt_bit = 17,
894 	.clkr = {
895 		.enable_reg = 0x2b14,
896 		.enable_mask = BIT(9),
897 		.hw.init = &(struct clk_init_data){
898 			.name = "gsbi11_uart_clk",
899 			.parent_hws = (const struct clk_hw*[]){
900 				&gsbi11_uart_src.clkr.hw
901 			},
902 			.num_parents = 1,
903 			.ops = &clk_branch_ops,
904 			.flags = CLK_SET_RATE_PARENT,
905 		},
906 	},
907 };
908 
909 static struct clk_rcg gsbi12_uart_src = {
910 	.ns_reg = 0x2b34,
911 	.md_reg = 0x2b30,
912 	.mn = {
913 		.mnctr_en_bit = 8,
914 		.mnctr_reset_bit = 7,
915 		.mnctr_mode_shift = 5,
916 		.n_val_shift = 16,
917 		.m_val_shift = 16,
918 		.width = 16,
919 	},
920 	.p = {
921 		.pre_div_shift = 3,
922 		.pre_div_width = 2,
923 	},
924 	.s = {
925 		.src_sel_shift = 0,
926 		.parent_map = gcc_pxo_pll8_map,
927 	},
928 	.freq_tbl = clk_tbl_gsbi_uart,
929 	.clkr = {
930 		.enable_reg = 0x2b34,
931 		.enable_mask = BIT(11),
932 		.hw.init = &(struct clk_init_data){
933 			.name = "gsbi12_uart_src",
934 			.parent_data = gcc_pxo_pll8,
935 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
936 			.ops = &clk_rcg_ops,
937 			.flags = CLK_SET_PARENT_GATE,
938 		},
939 	},
940 };
941 
942 static struct clk_branch gsbi12_uart_clk = {
943 	.halt_reg = 0x2fd4,
944 	.halt_bit = 13,
945 	.clkr = {
946 		.enable_reg = 0x2b34,
947 		.enable_mask = BIT(9),
948 		.hw.init = &(struct clk_init_data){
949 			.name = "gsbi12_uart_clk",
950 			.parent_hws = (const struct clk_hw*[]){
951 				&gsbi12_uart_src.clkr.hw
952 			},
953 			.num_parents = 1,
954 			.ops = &clk_branch_ops,
955 			.flags = CLK_SET_RATE_PARENT,
956 		},
957 	},
958 };
959 
960 static struct freq_tbl clk_tbl_gsbi_qup[] = {
961 	{  1100000, P_PXO,  1, 2, 49 },
962 	{  5400000, P_PXO,  1, 1,  5 },
963 	{ 10800000, P_PXO,  1, 2,  5 },
964 	{ 15060000, P_PLL8, 1, 2, 51 },
965 	{ 24000000, P_PLL8, 4, 1,  4 },
966 	{ 25600000, P_PLL8, 1, 1, 15 },
967 	{ 27000000, P_PXO,  1, 0,  0 },
968 	{ 48000000, P_PLL8, 4, 1,  2 },
969 	{ 51200000, P_PLL8, 1, 2, 15 },
970 	{ }
971 };
972 
973 static struct clk_rcg gsbi1_qup_src = {
974 	.ns_reg = 0x29cc,
975 	.md_reg = 0x29c8,
976 	.mn = {
977 		.mnctr_en_bit = 8,
978 		.mnctr_reset_bit = 7,
979 		.mnctr_mode_shift = 5,
980 		.n_val_shift = 16,
981 		.m_val_shift = 16,
982 		.width = 8,
983 	},
984 	.p = {
985 		.pre_div_shift = 3,
986 		.pre_div_width = 2,
987 	},
988 	.s = {
989 		.src_sel_shift = 0,
990 		.parent_map = gcc_pxo_pll8_map,
991 	},
992 	.freq_tbl = clk_tbl_gsbi_qup,
993 	.clkr = {
994 		.enable_reg = 0x29cc,
995 		.enable_mask = BIT(11),
996 		.hw.init = &(struct clk_init_data){
997 			.name = "gsbi1_qup_src",
998 			.parent_data = gcc_pxo_pll8,
999 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1000 			.ops = &clk_rcg_ops,
1001 			.flags = CLK_SET_PARENT_GATE,
1002 		},
1003 	},
1004 };
1005 
1006 static struct clk_branch gsbi1_qup_clk = {
1007 	.halt_reg = 0x2fcc,
1008 	.halt_bit = 9,
1009 	.clkr = {
1010 		.enable_reg = 0x29cc,
1011 		.enable_mask = BIT(9),
1012 		.hw.init = &(struct clk_init_data){
1013 			.name = "gsbi1_qup_clk",
1014 			.parent_hws = (const struct clk_hw*[]){
1015 				&gsbi1_qup_src.clkr.hw
1016 			},
1017 			.num_parents = 1,
1018 			.ops = &clk_branch_ops,
1019 			.flags = CLK_SET_RATE_PARENT,
1020 		},
1021 	},
1022 };
1023 
1024 static struct clk_rcg gsbi2_qup_src = {
1025 	.ns_reg = 0x29ec,
1026 	.md_reg = 0x29e8,
1027 	.mn = {
1028 		.mnctr_en_bit = 8,
1029 		.mnctr_reset_bit = 7,
1030 		.mnctr_mode_shift = 5,
1031 		.n_val_shift = 16,
1032 		.m_val_shift = 16,
1033 		.width = 8,
1034 	},
1035 	.p = {
1036 		.pre_div_shift = 3,
1037 		.pre_div_width = 2,
1038 	},
1039 	.s = {
1040 		.src_sel_shift = 0,
1041 		.parent_map = gcc_pxo_pll8_map,
1042 	},
1043 	.freq_tbl = clk_tbl_gsbi_qup,
1044 	.clkr = {
1045 		.enable_reg = 0x29ec,
1046 		.enable_mask = BIT(11),
1047 		.hw.init = &(struct clk_init_data){
1048 			.name = "gsbi2_qup_src",
1049 			.parent_data = gcc_pxo_pll8,
1050 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1051 			.ops = &clk_rcg_ops,
1052 			.flags = CLK_SET_PARENT_GATE,
1053 		},
1054 	},
1055 };
1056 
1057 static struct clk_branch gsbi2_qup_clk = {
1058 	.halt_reg = 0x2fcc,
1059 	.halt_bit = 4,
1060 	.clkr = {
1061 		.enable_reg = 0x29ec,
1062 		.enable_mask = BIT(9),
1063 		.hw.init = &(struct clk_init_data){
1064 			.name = "gsbi2_qup_clk",
1065 			.parent_hws = (const struct clk_hw*[]){
1066 				&gsbi2_qup_src.clkr.hw
1067 			},
1068 			.num_parents = 1,
1069 			.ops = &clk_branch_ops,
1070 			.flags = CLK_SET_RATE_PARENT,
1071 		},
1072 	},
1073 };
1074 
1075 static struct clk_rcg gsbi3_qup_src = {
1076 	.ns_reg = 0x2a0c,
1077 	.md_reg = 0x2a08,
1078 	.mn = {
1079 		.mnctr_en_bit = 8,
1080 		.mnctr_reset_bit = 7,
1081 		.mnctr_mode_shift = 5,
1082 		.n_val_shift = 16,
1083 		.m_val_shift = 16,
1084 		.width = 8,
1085 	},
1086 	.p = {
1087 		.pre_div_shift = 3,
1088 		.pre_div_width = 2,
1089 	},
1090 	.s = {
1091 		.src_sel_shift = 0,
1092 		.parent_map = gcc_pxo_pll8_map,
1093 	},
1094 	.freq_tbl = clk_tbl_gsbi_qup,
1095 	.clkr = {
1096 		.enable_reg = 0x2a0c,
1097 		.enable_mask = BIT(11),
1098 		.hw.init = &(struct clk_init_data){
1099 			.name = "gsbi3_qup_src",
1100 			.parent_data = gcc_pxo_pll8,
1101 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1102 			.ops = &clk_rcg_ops,
1103 			.flags = CLK_SET_PARENT_GATE,
1104 		},
1105 	},
1106 };
1107 
1108 static struct clk_branch gsbi3_qup_clk = {
1109 	.halt_reg = 0x2fcc,
1110 	.halt_bit = 0,
1111 	.clkr = {
1112 		.enable_reg = 0x2a0c,
1113 		.enable_mask = BIT(9),
1114 		.hw.init = &(struct clk_init_data){
1115 			.name = "gsbi3_qup_clk",
1116 			.parent_hws = (const struct clk_hw*[]){
1117 				&gsbi3_qup_src.clkr.hw
1118 			},
1119 			.num_parents = 1,
1120 			.ops = &clk_branch_ops,
1121 			.flags = CLK_SET_RATE_PARENT,
1122 		},
1123 	},
1124 };
1125 
1126 static struct clk_rcg gsbi4_qup_src = {
1127 	.ns_reg = 0x2a2c,
1128 	.md_reg = 0x2a28,
1129 	.mn = {
1130 		.mnctr_en_bit = 8,
1131 		.mnctr_reset_bit = 7,
1132 		.mnctr_mode_shift = 5,
1133 		.n_val_shift = 16,
1134 		.m_val_shift = 16,
1135 		.width = 8,
1136 	},
1137 	.p = {
1138 		.pre_div_shift = 3,
1139 		.pre_div_width = 2,
1140 	},
1141 	.s = {
1142 		.src_sel_shift = 0,
1143 		.parent_map = gcc_pxo_pll8_map,
1144 	},
1145 	.freq_tbl = clk_tbl_gsbi_qup,
1146 	.clkr = {
1147 		.enable_reg = 0x2a2c,
1148 		.enable_mask = BIT(11),
1149 		.hw.init = &(struct clk_init_data){
1150 			.name = "gsbi4_qup_src",
1151 			.parent_data = gcc_pxo_pll8,
1152 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1153 			.ops = &clk_rcg_ops,
1154 			.flags = CLK_SET_PARENT_GATE,
1155 		},
1156 	},
1157 };
1158 
1159 static struct clk_branch gsbi4_qup_clk = {
1160 	.halt_reg = 0x2fd0,
1161 	.halt_bit = 24,
1162 	.clkr = {
1163 		.enable_reg = 0x2a2c,
1164 		.enable_mask = BIT(9),
1165 		.hw.init = &(struct clk_init_data){
1166 			.name = "gsbi4_qup_clk",
1167 			.parent_hws = (const struct clk_hw*[]){
1168 				&gsbi4_qup_src.clkr.hw
1169 			},
1170 			.num_parents = 1,
1171 			.ops = &clk_branch_ops,
1172 			.flags = CLK_SET_RATE_PARENT,
1173 		},
1174 	},
1175 };
1176 
1177 static struct clk_rcg gsbi5_qup_src = {
1178 	.ns_reg = 0x2a4c,
1179 	.md_reg = 0x2a48,
1180 	.mn = {
1181 		.mnctr_en_bit = 8,
1182 		.mnctr_reset_bit = 7,
1183 		.mnctr_mode_shift = 5,
1184 		.n_val_shift = 16,
1185 		.m_val_shift = 16,
1186 		.width = 8,
1187 	},
1188 	.p = {
1189 		.pre_div_shift = 3,
1190 		.pre_div_width = 2,
1191 	},
1192 	.s = {
1193 		.src_sel_shift = 0,
1194 		.parent_map = gcc_pxo_pll8_map,
1195 	},
1196 	.freq_tbl = clk_tbl_gsbi_qup,
1197 	.clkr = {
1198 		.enable_reg = 0x2a4c,
1199 		.enable_mask = BIT(11),
1200 		.hw.init = &(struct clk_init_data){
1201 			.name = "gsbi5_qup_src",
1202 			.parent_data = gcc_pxo_pll8,
1203 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1204 			.ops = &clk_rcg_ops,
1205 			.flags = CLK_SET_PARENT_GATE,
1206 		},
1207 	},
1208 };
1209 
1210 static struct clk_branch gsbi5_qup_clk = {
1211 	.halt_reg = 0x2fd0,
1212 	.halt_bit = 20,
1213 	.clkr = {
1214 		.enable_reg = 0x2a4c,
1215 		.enable_mask = BIT(9),
1216 		.hw.init = &(struct clk_init_data){
1217 			.name = "gsbi5_qup_clk",
1218 			.parent_hws = (const struct clk_hw*[]){
1219 				&gsbi5_qup_src.clkr.hw
1220 			},
1221 			.num_parents = 1,
1222 			.ops = &clk_branch_ops,
1223 			.flags = CLK_SET_RATE_PARENT,
1224 		},
1225 	},
1226 };
1227 
1228 static struct clk_rcg gsbi6_qup_src = {
1229 	.ns_reg = 0x2a6c,
1230 	.md_reg = 0x2a68,
1231 	.mn = {
1232 		.mnctr_en_bit = 8,
1233 		.mnctr_reset_bit = 7,
1234 		.mnctr_mode_shift = 5,
1235 		.n_val_shift = 16,
1236 		.m_val_shift = 16,
1237 		.width = 8,
1238 	},
1239 	.p = {
1240 		.pre_div_shift = 3,
1241 		.pre_div_width = 2,
1242 	},
1243 	.s = {
1244 		.src_sel_shift = 0,
1245 		.parent_map = gcc_pxo_pll8_map,
1246 	},
1247 	.freq_tbl = clk_tbl_gsbi_qup,
1248 	.clkr = {
1249 		.enable_reg = 0x2a6c,
1250 		.enable_mask = BIT(11),
1251 		.hw.init = &(struct clk_init_data){
1252 			.name = "gsbi6_qup_src",
1253 			.parent_data = gcc_pxo_pll8,
1254 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1255 			.ops = &clk_rcg_ops,
1256 			.flags = CLK_SET_PARENT_GATE,
1257 		},
1258 	},
1259 };
1260 
1261 static struct clk_branch gsbi6_qup_clk = {
1262 	.halt_reg = 0x2fd0,
1263 	.halt_bit = 16,
1264 	.clkr = {
1265 		.enable_reg = 0x2a6c,
1266 		.enable_mask = BIT(9),
1267 		.hw.init = &(struct clk_init_data){
1268 			.name = "gsbi6_qup_clk",
1269 			.parent_hws = (const struct clk_hw*[]){
1270 				&gsbi6_qup_src.clkr.hw
1271 			},
1272 			.num_parents = 1,
1273 			.ops = &clk_branch_ops,
1274 			.flags = CLK_SET_RATE_PARENT,
1275 		},
1276 	},
1277 };
1278 
1279 static struct clk_rcg gsbi7_qup_src = {
1280 	.ns_reg = 0x2a8c,
1281 	.md_reg = 0x2a88,
1282 	.mn = {
1283 		.mnctr_en_bit = 8,
1284 		.mnctr_reset_bit = 7,
1285 		.mnctr_mode_shift = 5,
1286 		.n_val_shift = 16,
1287 		.m_val_shift = 16,
1288 		.width = 8,
1289 	},
1290 	.p = {
1291 		.pre_div_shift = 3,
1292 		.pre_div_width = 2,
1293 	},
1294 	.s = {
1295 		.src_sel_shift = 0,
1296 		.parent_map = gcc_pxo_pll8_map,
1297 	},
1298 	.freq_tbl = clk_tbl_gsbi_qup,
1299 	.clkr = {
1300 		.enable_reg = 0x2a8c,
1301 		.enable_mask = BIT(11),
1302 		.hw.init = &(struct clk_init_data){
1303 			.name = "gsbi7_qup_src",
1304 			.parent_data = gcc_pxo_pll8,
1305 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1306 			.ops = &clk_rcg_ops,
1307 			.flags = CLK_SET_PARENT_GATE,
1308 		},
1309 	},
1310 };
1311 
1312 static struct clk_branch gsbi7_qup_clk = {
1313 	.halt_reg = 0x2fd0,
1314 	.halt_bit = 12,
1315 	.clkr = {
1316 		.enable_reg = 0x2a8c,
1317 		.enable_mask = BIT(9),
1318 		.hw.init = &(struct clk_init_data){
1319 			.name = "gsbi7_qup_clk",
1320 			.parent_hws = (const struct clk_hw*[]){
1321 				&gsbi7_qup_src.clkr.hw
1322 			},
1323 			.num_parents = 1,
1324 			.ops = &clk_branch_ops,
1325 			.flags = CLK_SET_RATE_PARENT,
1326 		},
1327 	},
1328 };
1329 
1330 static struct clk_rcg gsbi8_qup_src = {
1331 	.ns_reg = 0x2aac,
1332 	.md_reg = 0x2aa8,
1333 	.mn = {
1334 		.mnctr_en_bit = 8,
1335 		.mnctr_reset_bit = 7,
1336 		.mnctr_mode_shift = 5,
1337 		.n_val_shift = 16,
1338 		.m_val_shift = 16,
1339 		.width = 8,
1340 	},
1341 	.p = {
1342 		.pre_div_shift = 3,
1343 		.pre_div_width = 2,
1344 	},
1345 	.s = {
1346 		.src_sel_shift = 0,
1347 		.parent_map = gcc_pxo_pll8_map,
1348 	},
1349 	.freq_tbl = clk_tbl_gsbi_qup,
1350 	.clkr = {
1351 		.enable_reg = 0x2aac,
1352 		.enable_mask = BIT(11),
1353 		.hw.init = &(struct clk_init_data){
1354 			.name = "gsbi8_qup_src",
1355 			.parent_data = gcc_pxo_pll8,
1356 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1357 			.ops = &clk_rcg_ops,
1358 			.flags = CLK_SET_PARENT_GATE,
1359 		},
1360 	},
1361 };
1362 
1363 static struct clk_branch gsbi8_qup_clk = {
1364 	.halt_reg = 0x2fd0,
1365 	.halt_bit = 8,
1366 	.clkr = {
1367 		.enable_reg = 0x2aac,
1368 		.enable_mask = BIT(9),
1369 		.hw.init = &(struct clk_init_data){
1370 			.name = "gsbi8_qup_clk",
1371 			.parent_hws = (const struct clk_hw*[]){
1372 				&gsbi8_qup_src.clkr.hw
1373 			},
1374 			.num_parents = 1,
1375 			.ops = &clk_branch_ops,
1376 			.flags = CLK_SET_RATE_PARENT,
1377 		},
1378 	},
1379 };
1380 
1381 static struct clk_rcg gsbi9_qup_src = {
1382 	.ns_reg = 0x2acc,
1383 	.md_reg = 0x2ac8,
1384 	.mn = {
1385 		.mnctr_en_bit = 8,
1386 		.mnctr_reset_bit = 7,
1387 		.mnctr_mode_shift = 5,
1388 		.n_val_shift = 16,
1389 		.m_val_shift = 16,
1390 		.width = 8,
1391 	},
1392 	.p = {
1393 		.pre_div_shift = 3,
1394 		.pre_div_width = 2,
1395 	},
1396 	.s = {
1397 		.src_sel_shift = 0,
1398 		.parent_map = gcc_pxo_pll8_map,
1399 	},
1400 	.freq_tbl = clk_tbl_gsbi_qup,
1401 	.clkr = {
1402 		.enable_reg = 0x2acc,
1403 		.enable_mask = BIT(11),
1404 		.hw.init = &(struct clk_init_data){
1405 			.name = "gsbi9_qup_src",
1406 			.parent_data = gcc_pxo_pll8,
1407 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1408 			.ops = &clk_rcg_ops,
1409 			.flags = CLK_SET_PARENT_GATE,
1410 		},
1411 	},
1412 };
1413 
1414 static struct clk_branch gsbi9_qup_clk = {
1415 	.halt_reg = 0x2fd0,
1416 	.halt_bit = 4,
1417 	.clkr = {
1418 		.enable_reg = 0x2acc,
1419 		.enable_mask = BIT(9),
1420 		.hw.init = &(struct clk_init_data){
1421 			.name = "gsbi9_qup_clk",
1422 			.parent_hws = (const struct clk_hw*[]){
1423 				&gsbi9_qup_src.clkr.hw
1424 			},
1425 			.num_parents = 1,
1426 			.ops = &clk_branch_ops,
1427 			.flags = CLK_SET_RATE_PARENT,
1428 		},
1429 	},
1430 };
1431 
1432 static struct clk_rcg gsbi10_qup_src = {
1433 	.ns_reg = 0x2aec,
1434 	.md_reg = 0x2ae8,
1435 	.mn = {
1436 		.mnctr_en_bit = 8,
1437 		.mnctr_reset_bit = 7,
1438 		.mnctr_mode_shift = 5,
1439 		.n_val_shift = 16,
1440 		.m_val_shift = 16,
1441 		.width = 8,
1442 	},
1443 	.p = {
1444 		.pre_div_shift = 3,
1445 		.pre_div_width = 2,
1446 	},
1447 	.s = {
1448 		.src_sel_shift = 0,
1449 		.parent_map = gcc_pxo_pll8_map,
1450 	},
1451 	.freq_tbl = clk_tbl_gsbi_qup,
1452 	.clkr = {
1453 		.enable_reg = 0x2aec,
1454 		.enable_mask = BIT(11),
1455 		.hw.init = &(struct clk_init_data){
1456 			.name = "gsbi10_qup_src",
1457 			.parent_data = gcc_pxo_pll8,
1458 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1459 			.ops = &clk_rcg_ops,
1460 			.flags = CLK_SET_PARENT_GATE,
1461 		},
1462 	},
1463 };
1464 
1465 static struct clk_branch gsbi10_qup_clk = {
1466 	.halt_reg = 0x2fd0,
1467 	.halt_bit = 0,
1468 	.clkr = {
1469 		.enable_reg = 0x2aec,
1470 		.enable_mask = BIT(9),
1471 		.hw.init = &(struct clk_init_data){
1472 			.name = "gsbi10_qup_clk",
1473 			.parent_hws = (const struct clk_hw*[]){
1474 				&gsbi10_qup_src.clkr.hw
1475 			},
1476 			.num_parents = 1,
1477 			.ops = &clk_branch_ops,
1478 			.flags = CLK_SET_RATE_PARENT,
1479 		},
1480 	},
1481 };
1482 
1483 static struct clk_rcg gsbi11_qup_src = {
1484 	.ns_reg = 0x2b0c,
1485 	.md_reg = 0x2b08,
1486 	.mn = {
1487 		.mnctr_en_bit = 8,
1488 		.mnctr_reset_bit = 7,
1489 		.mnctr_mode_shift = 5,
1490 		.n_val_shift = 16,
1491 		.m_val_shift = 16,
1492 		.width = 8,
1493 	},
1494 	.p = {
1495 		.pre_div_shift = 3,
1496 		.pre_div_width = 2,
1497 	},
1498 	.s = {
1499 		.src_sel_shift = 0,
1500 		.parent_map = gcc_pxo_pll8_map,
1501 	},
1502 	.freq_tbl = clk_tbl_gsbi_qup,
1503 	.clkr = {
1504 		.enable_reg = 0x2b0c,
1505 		.enable_mask = BIT(11),
1506 		.hw.init = &(struct clk_init_data){
1507 			.name = "gsbi11_qup_src",
1508 			.parent_data = gcc_pxo_pll8,
1509 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1510 			.ops = &clk_rcg_ops,
1511 			.flags = CLK_SET_PARENT_GATE,
1512 		},
1513 	},
1514 };
1515 
1516 static struct clk_branch gsbi11_qup_clk = {
1517 	.halt_reg = 0x2fd4,
1518 	.halt_bit = 15,
1519 	.clkr = {
1520 		.enable_reg = 0x2b0c,
1521 		.enable_mask = BIT(9),
1522 		.hw.init = &(struct clk_init_data){
1523 			.name = "gsbi11_qup_clk",
1524 			.parent_hws = (const struct clk_hw*[]){
1525 				&gsbi11_qup_src.clkr.hw
1526 			},
1527 			.num_parents = 1,
1528 			.ops = &clk_branch_ops,
1529 			.flags = CLK_SET_RATE_PARENT,
1530 		},
1531 	},
1532 };
1533 
1534 static struct clk_rcg gsbi12_qup_src = {
1535 	.ns_reg = 0x2b2c,
1536 	.md_reg = 0x2b28,
1537 	.mn = {
1538 		.mnctr_en_bit = 8,
1539 		.mnctr_reset_bit = 7,
1540 		.mnctr_mode_shift = 5,
1541 		.n_val_shift = 16,
1542 		.m_val_shift = 16,
1543 		.width = 8,
1544 	},
1545 	.p = {
1546 		.pre_div_shift = 3,
1547 		.pre_div_width = 2,
1548 	},
1549 	.s = {
1550 		.src_sel_shift = 0,
1551 		.parent_map = gcc_pxo_pll8_map,
1552 	},
1553 	.freq_tbl = clk_tbl_gsbi_qup,
1554 	.clkr = {
1555 		.enable_reg = 0x2b2c,
1556 		.enable_mask = BIT(11),
1557 		.hw.init = &(struct clk_init_data){
1558 			.name = "gsbi12_qup_src",
1559 			.parent_data = gcc_pxo_pll8,
1560 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1561 			.ops = &clk_rcg_ops,
1562 			.flags = CLK_SET_PARENT_GATE,
1563 		},
1564 	},
1565 };
1566 
1567 static struct clk_branch gsbi12_qup_clk = {
1568 	.halt_reg = 0x2fd4,
1569 	.halt_bit = 11,
1570 	.clkr = {
1571 		.enable_reg = 0x2b2c,
1572 		.enable_mask = BIT(9),
1573 		.hw.init = &(struct clk_init_data){
1574 			.name = "gsbi12_qup_clk",
1575 			.parent_hws = (const struct clk_hw*[]){
1576 				&gsbi12_qup_src.clkr.hw
1577 			},
1578 			.num_parents = 1,
1579 			.ops = &clk_branch_ops,
1580 			.flags = CLK_SET_RATE_PARENT,
1581 		},
1582 	},
1583 };
1584 
1585 static const struct freq_tbl clk_tbl_gp[] = {
1586 	{ 9600000, P_CXO,  2, 0, 0 },
1587 	{ 13500000, P_PXO,  2, 0, 0 },
1588 	{ 19200000, P_CXO,  1, 0, 0 },
1589 	{ 27000000, P_PXO,  1, 0, 0 },
1590 	{ 64000000, P_PLL8, 2, 1, 3 },
1591 	{ 76800000, P_PLL8, 1, 1, 5 },
1592 	{ 96000000, P_PLL8, 4, 0, 0 },
1593 	{ 128000000, P_PLL8, 3, 0, 0 },
1594 	{ 192000000, P_PLL8, 2, 0, 0 },
1595 	{ }
1596 };
1597 
1598 static struct clk_rcg gp0_src = {
1599 	.ns_reg = 0x2d24,
1600 	.md_reg = 0x2d00,
1601 	.mn = {
1602 		.mnctr_en_bit = 8,
1603 		.mnctr_reset_bit = 7,
1604 		.mnctr_mode_shift = 5,
1605 		.n_val_shift = 16,
1606 		.m_val_shift = 16,
1607 		.width = 8,
1608 	},
1609 	.p = {
1610 		.pre_div_shift = 3,
1611 		.pre_div_width = 2,
1612 	},
1613 	.s = {
1614 		.src_sel_shift = 0,
1615 		.parent_map = gcc_pxo_pll8_cxo_map,
1616 	},
1617 	.freq_tbl = clk_tbl_gp,
1618 	.clkr = {
1619 		.enable_reg = 0x2d24,
1620 		.enable_mask = BIT(11),
1621 		.hw.init = &(struct clk_init_data){
1622 			.name = "gp0_src",
1623 			.parent_data = gcc_pxo_pll8_cxo,
1624 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1625 			.ops = &clk_rcg_ops,
1626 			.flags = CLK_SET_PARENT_GATE,
1627 		},
1628 	}
1629 };
1630 
1631 static struct clk_branch gp0_clk = {
1632 	.halt_reg = 0x2fd8,
1633 	.halt_bit = 7,
1634 	.clkr = {
1635 		.enable_reg = 0x2d24,
1636 		.enable_mask = BIT(9),
1637 		.hw.init = &(struct clk_init_data){
1638 			.name = "gp0_clk",
1639 			.parent_hws = (const struct clk_hw*[]){
1640 				&gp0_src.clkr.hw
1641 			},
1642 			.num_parents = 1,
1643 			.ops = &clk_branch_ops,
1644 			.flags = CLK_SET_RATE_PARENT,
1645 		},
1646 	},
1647 };
1648 
1649 static struct clk_rcg gp1_src = {
1650 	.ns_reg = 0x2d44,
1651 	.md_reg = 0x2d40,
1652 	.mn = {
1653 		.mnctr_en_bit = 8,
1654 		.mnctr_reset_bit = 7,
1655 		.mnctr_mode_shift = 5,
1656 		.n_val_shift = 16,
1657 		.m_val_shift = 16,
1658 		.width = 8,
1659 	},
1660 	.p = {
1661 		.pre_div_shift = 3,
1662 		.pre_div_width = 2,
1663 	},
1664 	.s = {
1665 		.src_sel_shift = 0,
1666 		.parent_map = gcc_pxo_pll8_cxo_map,
1667 	},
1668 	.freq_tbl = clk_tbl_gp,
1669 	.clkr = {
1670 		.enable_reg = 0x2d44,
1671 		.enable_mask = BIT(11),
1672 		.hw.init = &(struct clk_init_data){
1673 			.name = "gp1_src",
1674 			.parent_data = gcc_pxo_pll8_cxo,
1675 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1676 			.ops = &clk_rcg_ops,
1677 			.flags = CLK_SET_RATE_GATE,
1678 		},
1679 	}
1680 };
1681 
1682 static struct clk_branch gp1_clk = {
1683 	.halt_reg = 0x2fd8,
1684 	.halt_bit = 6,
1685 	.clkr = {
1686 		.enable_reg = 0x2d44,
1687 		.enable_mask = BIT(9),
1688 		.hw.init = &(struct clk_init_data){
1689 			.name = "gp1_clk",
1690 			.parent_hws = (const struct clk_hw*[]){
1691 				&gp1_src.clkr.hw
1692 			},
1693 			.num_parents = 1,
1694 			.ops = &clk_branch_ops,
1695 			.flags = CLK_SET_RATE_PARENT,
1696 		},
1697 	},
1698 };
1699 
1700 static struct clk_rcg gp2_src = {
1701 	.ns_reg = 0x2d64,
1702 	.md_reg = 0x2d60,
1703 	.mn = {
1704 		.mnctr_en_bit = 8,
1705 		.mnctr_reset_bit = 7,
1706 		.mnctr_mode_shift = 5,
1707 		.n_val_shift = 16,
1708 		.m_val_shift = 16,
1709 		.width = 8,
1710 	},
1711 	.p = {
1712 		.pre_div_shift = 3,
1713 		.pre_div_width = 2,
1714 	},
1715 	.s = {
1716 		.src_sel_shift = 0,
1717 		.parent_map = gcc_pxo_pll8_cxo_map,
1718 	},
1719 	.freq_tbl = clk_tbl_gp,
1720 	.clkr = {
1721 		.enable_reg = 0x2d64,
1722 		.enable_mask = BIT(11),
1723 		.hw.init = &(struct clk_init_data){
1724 			.name = "gp2_src",
1725 			.parent_data = gcc_pxo_pll8_cxo,
1726 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1727 			.ops = &clk_rcg_ops,
1728 			.flags = CLK_SET_RATE_GATE,
1729 		},
1730 	}
1731 };
1732 
1733 static struct clk_branch gp2_clk = {
1734 	.halt_reg = 0x2fd8,
1735 	.halt_bit = 5,
1736 	.clkr = {
1737 		.enable_reg = 0x2d64,
1738 		.enable_mask = BIT(9),
1739 		.hw.init = &(struct clk_init_data){
1740 			.name = "gp2_clk",
1741 			.parent_hws = (const struct clk_hw*[]){
1742 				&gp2_src.clkr.hw
1743 			},
1744 			.num_parents = 1,
1745 			.ops = &clk_branch_ops,
1746 			.flags = CLK_SET_RATE_PARENT,
1747 		},
1748 	},
1749 };
1750 
1751 static struct clk_branch pmem_clk = {
1752 	.hwcg_reg = 0x25a0,
1753 	.hwcg_bit = 6,
1754 	.halt_reg = 0x2fc8,
1755 	.halt_bit = 20,
1756 	.clkr = {
1757 		.enable_reg = 0x25a0,
1758 		.enable_mask = BIT(4),
1759 		.hw.init = &(struct clk_init_data){
1760 			.name = "pmem_clk",
1761 			.ops = &clk_branch_ops,
1762 		},
1763 	},
1764 };
1765 
1766 static struct clk_rcg prng_src = {
1767 	.ns_reg = 0x2e80,
1768 	.p = {
1769 		.pre_div_shift = 3,
1770 		.pre_div_width = 4,
1771 	},
1772 	.s = {
1773 		.src_sel_shift = 0,
1774 		.parent_map = gcc_pxo_pll8_map,
1775 	},
1776 	.clkr = {
1777 		.hw.init = &(struct clk_init_data){
1778 			.name = "prng_src",
1779 			.parent_data = gcc_pxo_pll8,
1780 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1781 			.ops = &clk_rcg_ops,
1782 		},
1783 	},
1784 };
1785 
1786 static struct clk_branch prng_clk = {
1787 	.halt_reg = 0x2fd8,
1788 	.halt_check = BRANCH_HALT_VOTED,
1789 	.halt_bit = 10,
1790 	.clkr = {
1791 		.enable_reg = 0x3080,
1792 		.enable_mask = BIT(10),
1793 		.hw.init = &(struct clk_init_data){
1794 			.name = "prng_clk",
1795 			.parent_hws = (const struct clk_hw*[]){
1796 				&prng_src.clkr.hw
1797 			},
1798 			.num_parents = 1,
1799 			.ops = &clk_branch_ops,
1800 		},
1801 	},
1802 };
1803 
1804 static const struct freq_tbl clk_tbl_sdc[] = {
1805 	{    144000, P_PXO,   3, 2, 125 },
1806 	{    400000, P_PLL8,  4, 1, 240 },
1807 	{  16000000, P_PLL8,  4, 1,   6 },
1808 	{  17070000, P_PLL8,  1, 2,  45 },
1809 	{  20210000, P_PLL8,  1, 1,  19 },
1810 	{  24000000, P_PLL8,  4, 1,   4 },
1811 	{  48000000, P_PLL8,  4, 1,   2 },
1812 	{  64000000, P_PLL8,  3, 1,   2 },
1813 	{  96000000, P_PLL8,  4, 0,   0 },
1814 	{ 192000000, P_PLL8,  2, 0,   0 },
1815 	{ }
1816 };
1817 
1818 static struct clk_rcg sdc1_src = {
1819 	.ns_reg = 0x282c,
1820 	.md_reg = 0x2828,
1821 	.mn = {
1822 		.mnctr_en_bit = 8,
1823 		.mnctr_reset_bit = 7,
1824 		.mnctr_mode_shift = 5,
1825 		.n_val_shift = 16,
1826 		.m_val_shift = 16,
1827 		.width = 8,
1828 	},
1829 	.p = {
1830 		.pre_div_shift = 3,
1831 		.pre_div_width = 2,
1832 	},
1833 	.s = {
1834 		.src_sel_shift = 0,
1835 		.parent_map = gcc_pxo_pll8_map,
1836 	},
1837 	.freq_tbl = clk_tbl_sdc,
1838 	.clkr = {
1839 		.enable_reg = 0x282c,
1840 		.enable_mask = BIT(11),
1841 		.hw.init = &(struct clk_init_data){
1842 			.name = "sdc1_src",
1843 			.parent_data = gcc_pxo_pll8,
1844 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1845 			.ops = &clk_rcg_ops,
1846 		},
1847 	}
1848 };
1849 
1850 static struct clk_branch sdc1_clk = {
1851 	.halt_reg = 0x2fc8,
1852 	.halt_bit = 6,
1853 	.clkr = {
1854 		.enable_reg = 0x282c,
1855 		.enable_mask = BIT(9),
1856 		.hw.init = &(struct clk_init_data){
1857 			.name = "sdc1_clk",
1858 			.parent_hws = (const struct clk_hw*[]){
1859 				&sdc1_src.clkr.hw
1860 			},
1861 			.num_parents = 1,
1862 			.ops = &clk_branch_ops,
1863 			.flags = CLK_SET_RATE_PARENT,
1864 		},
1865 	},
1866 };
1867 
1868 static struct clk_rcg sdc2_src = {
1869 	.ns_reg = 0x284c,
1870 	.md_reg = 0x2848,
1871 	.mn = {
1872 		.mnctr_en_bit = 8,
1873 		.mnctr_reset_bit = 7,
1874 		.mnctr_mode_shift = 5,
1875 		.n_val_shift = 16,
1876 		.m_val_shift = 16,
1877 		.width = 8,
1878 	},
1879 	.p = {
1880 		.pre_div_shift = 3,
1881 		.pre_div_width = 2,
1882 	},
1883 	.s = {
1884 		.src_sel_shift = 0,
1885 		.parent_map = gcc_pxo_pll8_map,
1886 	},
1887 	.freq_tbl = clk_tbl_sdc,
1888 	.clkr = {
1889 		.enable_reg = 0x284c,
1890 		.enable_mask = BIT(11),
1891 		.hw.init = &(struct clk_init_data){
1892 			.name = "sdc2_src",
1893 			.parent_data = gcc_pxo_pll8,
1894 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1895 			.ops = &clk_rcg_ops,
1896 		},
1897 	}
1898 };
1899 
1900 static struct clk_branch sdc2_clk = {
1901 	.halt_reg = 0x2fc8,
1902 	.halt_bit = 5,
1903 	.clkr = {
1904 		.enable_reg = 0x284c,
1905 		.enable_mask = BIT(9),
1906 		.hw.init = &(struct clk_init_data){
1907 			.name = "sdc2_clk",
1908 			.parent_hws = (const struct clk_hw*[]){
1909 				&sdc2_src.clkr.hw
1910 			},
1911 			.num_parents = 1,
1912 			.ops = &clk_branch_ops,
1913 			.flags = CLK_SET_RATE_PARENT,
1914 		},
1915 	},
1916 };
1917 
1918 static struct clk_rcg sdc3_src = {
1919 	.ns_reg = 0x286c,
1920 	.md_reg = 0x2868,
1921 	.mn = {
1922 		.mnctr_en_bit = 8,
1923 		.mnctr_reset_bit = 7,
1924 		.mnctr_mode_shift = 5,
1925 		.n_val_shift = 16,
1926 		.m_val_shift = 16,
1927 		.width = 8,
1928 	},
1929 	.p = {
1930 		.pre_div_shift = 3,
1931 		.pre_div_width = 2,
1932 	},
1933 	.s = {
1934 		.src_sel_shift = 0,
1935 		.parent_map = gcc_pxo_pll8_map,
1936 	},
1937 	.freq_tbl = clk_tbl_sdc,
1938 	.clkr = {
1939 		.enable_reg = 0x286c,
1940 		.enable_mask = BIT(11),
1941 		.hw.init = &(struct clk_init_data){
1942 			.name = "sdc3_src",
1943 			.parent_data = gcc_pxo_pll8,
1944 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1945 			.ops = &clk_rcg_ops,
1946 		},
1947 	}
1948 };
1949 
1950 static struct clk_branch sdc3_clk = {
1951 	.halt_reg = 0x2fc8,
1952 	.halt_bit = 4,
1953 	.clkr = {
1954 		.enable_reg = 0x286c,
1955 		.enable_mask = BIT(9),
1956 		.hw.init = &(struct clk_init_data){
1957 			.name = "sdc3_clk",
1958 			.parent_hws = (const struct clk_hw*[]){
1959 				&sdc3_src.clkr.hw
1960 			},
1961 			.num_parents = 1,
1962 			.ops = &clk_branch_ops,
1963 			.flags = CLK_SET_RATE_PARENT,
1964 		},
1965 	},
1966 };
1967 
1968 static struct clk_rcg sdc4_src = {
1969 	.ns_reg = 0x288c,
1970 	.md_reg = 0x2888,
1971 	.mn = {
1972 		.mnctr_en_bit = 8,
1973 		.mnctr_reset_bit = 7,
1974 		.mnctr_mode_shift = 5,
1975 		.n_val_shift = 16,
1976 		.m_val_shift = 16,
1977 		.width = 8,
1978 	},
1979 	.p = {
1980 		.pre_div_shift = 3,
1981 		.pre_div_width = 2,
1982 	},
1983 	.s = {
1984 		.src_sel_shift = 0,
1985 		.parent_map = gcc_pxo_pll8_map,
1986 	},
1987 	.freq_tbl = clk_tbl_sdc,
1988 	.clkr = {
1989 		.enable_reg = 0x288c,
1990 		.enable_mask = BIT(11),
1991 		.hw.init = &(struct clk_init_data){
1992 			.name = "sdc4_src",
1993 			.parent_data = gcc_pxo_pll8,
1994 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1995 			.ops = &clk_rcg_ops,
1996 		},
1997 	}
1998 };
1999 
2000 static struct clk_branch sdc4_clk = {
2001 	.halt_reg = 0x2fc8,
2002 	.halt_bit = 3,
2003 	.clkr = {
2004 		.enable_reg = 0x288c,
2005 		.enable_mask = BIT(9),
2006 		.hw.init = &(struct clk_init_data){
2007 			.name = "sdc4_clk",
2008 			.parent_hws = (const struct clk_hw*[]){
2009 				&sdc4_src.clkr.hw
2010 			},
2011 			.num_parents = 1,
2012 			.ops = &clk_branch_ops,
2013 			.flags = CLK_SET_RATE_PARENT,
2014 		},
2015 	},
2016 };
2017 
2018 static struct clk_rcg sdc5_src = {
2019 	.ns_reg = 0x28ac,
2020 	.md_reg = 0x28a8,
2021 	.mn = {
2022 		.mnctr_en_bit = 8,
2023 		.mnctr_reset_bit = 7,
2024 		.mnctr_mode_shift = 5,
2025 		.n_val_shift = 16,
2026 		.m_val_shift = 16,
2027 		.width = 8,
2028 	},
2029 	.p = {
2030 		.pre_div_shift = 3,
2031 		.pre_div_width = 2,
2032 	},
2033 	.s = {
2034 		.src_sel_shift = 0,
2035 		.parent_map = gcc_pxo_pll8_map,
2036 	},
2037 	.freq_tbl = clk_tbl_sdc,
2038 	.clkr = {
2039 		.enable_reg = 0x28ac,
2040 		.enable_mask = BIT(11),
2041 		.hw.init = &(struct clk_init_data){
2042 			.name = "sdc5_src",
2043 			.parent_data = gcc_pxo_pll8,
2044 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2045 			.ops = &clk_rcg_ops,
2046 		},
2047 	}
2048 };
2049 
2050 static struct clk_branch sdc5_clk = {
2051 	.halt_reg = 0x2fc8,
2052 	.halt_bit = 2,
2053 	.clkr = {
2054 		.enable_reg = 0x28ac,
2055 		.enable_mask = BIT(9),
2056 		.hw.init = &(struct clk_init_data){
2057 			.name = "sdc5_clk",
2058 			.parent_hws = (const struct clk_hw*[]){
2059 				&sdc5_src.clkr.hw
2060 			},
2061 			.num_parents = 1,
2062 			.ops = &clk_branch_ops,
2063 			.flags = CLK_SET_RATE_PARENT,
2064 		},
2065 	},
2066 };
2067 
2068 static const struct freq_tbl clk_tbl_tsif_ref[] = {
2069 	{ 105000, P_PXO,  1, 1, 256 },
2070 	{ }
2071 };
2072 
2073 static struct clk_rcg tsif_ref_src = {
2074 	.ns_reg = 0x2710,
2075 	.md_reg = 0x270c,
2076 	.mn = {
2077 		.mnctr_en_bit = 8,
2078 		.mnctr_reset_bit = 7,
2079 		.mnctr_mode_shift = 5,
2080 		.n_val_shift = 16,
2081 		.m_val_shift = 16,
2082 		.width = 16,
2083 	},
2084 	.p = {
2085 		.pre_div_shift = 3,
2086 		.pre_div_width = 2,
2087 	},
2088 	.s = {
2089 		.src_sel_shift = 0,
2090 		.parent_map = gcc_pxo_pll8_map,
2091 	},
2092 	.freq_tbl = clk_tbl_tsif_ref,
2093 	.clkr = {
2094 		.enable_reg = 0x2710,
2095 		.enable_mask = BIT(11),
2096 		.hw.init = &(struct clk_init_data){
2097 			.name = "tsif_ref_src",
2098 			.parent_data = gcc_pxo_pll8,
2099 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2100 			.ops = &clk_rcg_ops,
2101 			.flags = CLK_SET_RATE_GATE,
2102 		},
2103 	}
2104 };
2105 
2106 static struct clk_branch tsif_ref_clk = {
2107 	.halt_reg = 0x2fd4,
2108 	.halt_bit = 5,
2109 	.clkr = {
2110 		.enable_reg = 0x2710,
2111 		.enable_mask = BIT(9),
2112 		.hw.init = &(struct clk_init_data){
2113 			.name = "tsif_ref_clk",
2114 			.parent_hws = (const struct clk_hw*[]){
2115 				&tsif_ref_src.clkr.hw
2116 			},
2117 			.num_parents = 1,
2118 			.ops = &clk_branch_ops,
2119 			.flags = CLK_SET_RATE_PARENT,
2120 		},
2121 	},
2122 };
2123 
2124 static const struct freq_tbl clk_tbl_usb[] = {
2125 	{ 60000000, P_PLL8, 1, 5, 32 },
2126 	{ }
2127 };
2128 
2129 static struct clk_rcg usb_hs1_xcvr_src = {
2130 	.ns_reg = 0x290c,
2131 	.md_reg = 0x2908,
2132 	.mn = {
2133 		.mnctr_en_bit = 8,
2134 		.mnctr_reset_bit = 7,
2135 		.mnctr_mode_shift = 5,
2136 		.n_val_shift = 16,
2137 		.m_val_shift = 16,
2138 		.width = 8,
2139 	},
2140 	.p = {
2141 		.pre_div_shift = 3,
2142 		.pre_div_width = 2,
2143 	},
2144 	.s = {
2145 		.src_sel_shift = 0,
2146 		.parent_map = gcc_pxo_pll8_map,
2147 	},
2148 	.freq_tbl = clk_tbl_usb,
2149 	.clkr = {
2150 		.enable_reg = 0x290c,
2151 		.enable_mask = BIT(11),
2152 		.hw.init = &(struct clk_init_data){
2153 			.name = "usb_hs1_xcvr_src",
2154 			.parent_data = gcc_pxo_pll8,
2155 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2156 			.ops = &clk_rcg_ops,
2157 			.flags = CLK_SET_RATE_GATE,
2158 		},
2159 	}
2160 };
2161 
2162 static struct clk_branch usb_hs1_xcvr_clk = {
2163 	.halt_reg = 0x2fc8,
2164 	.halt_bit = 0,
2165 	.clkr = {
2166 		.enable_reg = 0x290c,
2167 		.enable_mask = BIT(9),
2168 		.hw.init = &(struct clk_init_data){
2169 			.name = "usb_hs1_xcvr_clk",
2170 			.parent_hws = (const struct clk_hw*[]){
2171 				&usb_hs1_xcvr_src.clkr.hw
2172 			},
2173 			.num_parents = 1,
2174 			.ops = &clk_branch_ops,
2175 			.flags = CLK_SET_RATE_PARENT,
2176 		},
2177 	},
2178 };
2179 
2180 static struct clk_rcg usb_hs3_xcvr_src = {
2181 	.ns_reg = 0x370c,
2182 	.md_reg = 0x3708,
2183 	.mn = {
2184 		.mnctr_en_bit = 8,
2185 		.mnctr_reset_bit = 7,
2186 		.mnctr_mode_shift = 5,
2187 		.n_val_shift = 16,
2188 		.m_val_shift = 16,
2189 		.width = 8,
2190 	},
2191 	.p = {
2192 		.pre_div_shift = 3,
2193 		.pre_div_width = 2,
2194 	},
2195 	.s = {
2196 		.src_sel_shift = 0,
2197 		.parent_map = gcc_pxo_pll8_map,
2198 	},
2199 	.freq_tbl = clk_tbl_usb,
2200 	.clkr = {
2201 		.enable_reg = 0x370c,
2202 		.enable_mask = BIT(11),
2203 		.hw.init = &(struct clk_init_data){
2204 			.name = "usb_hs3_xcvr_src",
2205 			.parent_data = gcc_pxo_pll8,
2206 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2207 			.ops = &clk_rcg_ops,
2208 			.flags = CLK_SET_RATE_GATE,
2209 		},
2210 	}
2211 };
2212 
2213 static struct clk_branch usb_hs3_xcvr_clk = {
2214 	.halt_reg = 0x2fc8,
2215 	.halt_bit = 30,
2216 	.clkr = {
2217 		.enable_reg = 0x370c,
2218 		.enable_mask = BIT(9),
2219 		.hw.init = &(struct clk_init_data){
2220 			.name = "usb_hs3_xcvr_clk",
2221 			.parent_hws = (const struct clk_hw*[]){
2222 				&usb_hs3_xcvr_src.clkr.hw
2223 			},
2224 			.num_parents = 1,
2225 			.ops = &clk_branch_ops,
2226 			.flags = CLK_SET_RATE_PARENT,
2227 		},
2228 	},
2229 };
2230 
2231 static struct clk_rcg usb_hs4_xcvr_src = {
2232 	.ns_reg = 0x372c,
2233 	.md_reg = 0x3728,
2234 	.mn = {
2235 		.mnctr_en_bit = 8,
2236 		.mnctr_reset_bit = 7,
2237 		.mnctr_mode_shift = 5,
2238 		.n_val_shift = 16,
2239 		.m_val_shift = 16,
2240 		.width = 8,
2241 	},
2242 	.p = {
2243 		.pre_div_shift = 3,
2244 		.pre_div_width = 2,
2245 	},
2246 	.s = {
2247 		.src_sel_shift = 0,
2248 		.parent_map = gcc_pxo_pll8_map,
2249 	},
2250 	.freq_tbl = clk_tbl_usb,
2251 	.clkr = {
2252 		.enable_reg = 0x372c,
2253 		.enable_mask = BIT(11),
2254 		.hw.init = &(struct clk_init_data){
2255 			.name = "usb_hs4_xcvr_src",
2256 			.parent_data = gcc_pxo_pll8,
2257 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2258 			.ops = &clk_rcg_ops,
2259 			.flags = CLK_SET_RATE_GATE,
2260 		},
2261 	}
2262 };
2263 
2264 static struct clk_branch usb_hs4_xcvr_clk = {
2265 	.halt_reg = 0x2fc8,
2266 	.halt_bit = 2,
2267 	.clkr = {
2268 		.enable_reg = 0x372c,
2269 		.enable_mask = BIT(9),
2270 		.hw.init = &(struct clk_init_data){
2271 			.name = "usb_hs4_xcvr_clk",
2272 			.parent_hws = (const struct clk_hw*[]){
2273 				&usb_hs4_xcvr_src.clkr.hw
2274 			},
2275 			.num_parents = 1,
2276 			.ops = &clk_branch_ops,
2277 			.flags = CLK_SET_RATE_PARENT,
2278 		},
2279 	},
2280 };
2281 
2282 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2283 	.ns_reg = 0x2928,
2284 	.md_reg = 0x2924,
2285 	.mn = {
2286 		.mnctr_en_bit = 8,
2287 		.mnctr_reset_bit = 7,
2288 		.mnctr_mode_shift = 5,
2289 		.n_val_shift = 16,
2290 		.m_val_shift = 16,
2291 		.width = 8,
2292 	},
2293 	.p = {
2294 		.pre_div_shift = 3,
2295 		.pre_div_width = 2,
2296 	},
2297 	.s = {
2298 		.src_sel_shift = 0,
2299 		.parent_map = gcc_pxo_pll8_map,
2300 	},
2301 	.freq_tbl = clk_tbl_usb,
2302 	.clkr = {
2303 		.enable_reg = 0x2928,
2304 		.enable_mask = BIT(11),
2305 		.hw.init = &(struct clk_init_data){
2306 			.name = "usb_hsic_xcvr_fs_src",
2307 			.parent_data = gcc_pxo_pll8,
2308 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2309 			.ops = &clk_rcg_ops,
2310 			.flags = CLK_SET_RATE_GATE,
2311 		},
2312 	}
2313 };
2314 
2315 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2316 	.halt_reg = 0x2fc8,
2317 	.halt_bit = 2,
2318 	.clkr = {
2319 		.enable_reg = 0x2928,
2320 		.enable_mask = BIT(9),
2321 		.hw.init = &(struct clk_init_data){
2322 			.name = "usb_hsic_xcvr_fs_clk",
2323 			.parent_hws = (const struct clk_hw*[]){
2324 				&usb_hsic_xcvr_fs_src.clkr.hw,
2325 			},
2326 			.num_parents = 1,
2327 			.ops = &clk_branch_ops,
2328 			.flags = CLK_SET_RATE_PARENT,
2329 		},
2330 	},
2331 };
2332 
2333 static struct clk_branch usb_hsic_system_clk = {
2334 	.halt_reg = 0x2fcc,
2335 	.halt_bit = 24,
2336 	.clkr = {
2337 		.enable_reg = 0x292c,
2338 		.enable_mask = BIT(4),
2339 		.hw.init = &(struct clk_init_data){
2340 			.parent_hws = (const struct clk_hw*[]){
2341 				&usb_hsic_xcvr_fs_src.clkr.hw,
2342 			},
2343 			.num_parents = 1,
2344 			.name = "usb_hsic_system_clk",
2345 			.ops = &clk_branch_ops,
2346 			.flags = CLK_SET_RATE_PARENT,
2347 		},
2348 	},
2349 };
2350 
2351 static struct clk_branch usb_hsic_hsic_clk = {
2352 	.halt_reg = 0x2fcc,
2353 	.halt_bit = 19,
2354 	.clkr = {
2355 		.enable_reg = 0x2b44,
2356 		.enable_mask = BIT(0),
2357 		.hw.init = &(struct clk_init_data){
2358 			.parent_hws = (const struct clk_hw*[]){
2359 				&pll14_vote.hw
2360 			},
2361 			.num_parents = 1,
2362 			.name = "usb_hsic_hsic_clk",
2363 			.ops = &clk_branch_ops,
2364 		},
2365 	},
2366 };
2367 
2368 static struct clk_branch usb_hsic_hsio_cal_clk = {
2369 	.halt_reg = 0x2fcc,
2370 	.halt_bit = 23,
2371 	.clkr = {
2372 		.enable_reg = 0x2b48,
2373 		.enable_mask = BIT(0),
2374 		.hw.init = &(struct clk_init_data){
2375 			.name = "usb_hsic_hsio_cal_clk",
2376 			.ops = &clk_branch_ops,
2377 		},
2378 	},
2379 };
2380 
2381 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2382 	.ns_reg = 0x2968,
2383 	.md_reg = 0x2964,
2384 	.mn = {
2385 		.mnctr_en_bit = 8,
2386 		.mnctr_reset_bit = 7,
2387 		.mnctr_mode_shift = 5,
2388 		.n_val_shift = 16,
2389 		.m_val_shift = 16,
2390 		.width = 8,
2391 	},
2392 	.p = {
2393 		.pre_div_shift = 3,
2394 		.pre_div_width = 2,
2395 	},
2396 	.s = {
2397 		.src_sel_shift = 0,
2398 		.parent_map = gcc_pxo_pll8_map,
2399 	},
2400 	.freq_tbl = clk_tbl_usb,
2401 	.clkr = {
2402 		.enable_reg = 0x2968,
2403 		.enable_mask = BIT(11),
2404 		.hw.init = &(struct clk_init_data){
2405 			.name = "usb_fs1_xcvr_fs_src",
2406 			.parent_data = gcc_pxo_pll8,
2407 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2408 			.ops = &clk_rcg_ops,
2409 			.flags = CLK_SET_RATE_GATE,
2410 		},
2411 	}
2412 };
2413 
2414 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2415 	.halt_reg = 0x2fcc,
2416 	.halt_bit = 15,
2417 	.clkr = {
2418 		.enable_reg = 0x2968,
2419 		.enable_mask = BIT(9),
2420 		.hw.init = &(struct clk_init_data){
2421 			.name = "usb_fs1_xcvr_fs_clk",
2422 			.parent_hws = (const struct clk_hw*[]){
2423 				&usb_fs1_xcvr_fs_src.clkr.hw,
2424 			},
2425 			.num_parents = 1,
2426 			.ops = &clk_branch_ops,
2427 			.flags = CLK_SET_RATE_PARENT,
2428 		},
2429 	},
2430 };
2431 
2432 static struct clk_branch usb_fs1_system_clk = {
2433 	.halt_reg = 0x2fcc,
2434 	.halt_bit = 16,
2435 	.clkr = {
2436 		.enable_reg = 0x296c,
2437 		.enable_mask = BIT(4),
2438 		.hw.init = &(struct clk_init_data){
2439 			.parent_hws = (const struct clk_hw*[]){
2440 				&usb_fs1_xcvr_fs_src.clkr.hw,
2441 			},
2442 			.num_parents = 1,
2443 			.name = "usb_fs1_system_clk",
2444 			.ops = &clk_branch_ops,
2445 			.flags = CLK_SET_RATE_PARENT,
2446 		},
2447 	},
2448 };
2449 
2450 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2451 	.ns_reg = 0x2988,
2452 	.md_reg = 0x2984,
2453 	.mn = {
2454 		.mnctr_en_bit = 8,
2455 		.mnctr_reset_bit = 7,
2456 		.mnctr_mode_shift = 5,
2457 		.n_val_shift = 16,
2458 		.m_val_shift = 16,
2459 		.width = 8,
2460 	},
2461 	.p = {
2462 		.pre_div_shift = 3,
2463 		.pre_div_width = 2,
2464 	},
2465 	.s = {
2466 		.src_sel_shift = 0,
2467 		.parent_map = gcc_pxo_pll8_map,
2468 	},
2469 	.freq_tbl = clk_tbl_usb,
2470 	.clkr = {
2471 		.enable_reg = 0x2988,
2472 		.enable_mask = BIT(11),
2473 		.hw.init = &(struct clk_init_data){
2474 			.name = "usb_fs2_xcvr_fs_src",
2475 			.parent_data = gcc_pxo_pll8,
2476 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2477 			.ops = &clk_rcg_ops,
2478 			.flags = CLK_SET_RATE_GATE,
2479 		},
2480 	}
2481 };
2482 
2483 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2484 	.halt_reg = 0x2fcc,
2485 	.halt_bit = 12,
2486 	.clkr = {
2487 		.enable_reg = 0x2988,
2488 		.enable_mask = BIT(9),
2489 		.hw.init = &(struct clk_init_data){
2490 			.name = "usb_fs2_xcvr_fs_clk",
2491 			.parent_hws = (const struct clk_hw*[]){
2492 				&usb_fs2_xcvr_fs_src.clkr.hw,
2493 			},
2494 			.num_parents = 1,
2495 			.ops = &clk_branch_ops,
2496 			.flags = CLK_SET_RATE_PARENT,
2497 		},
2498 	},
2499 };
2500 
2501 static struct clk_branch usb_fs2_system_clk = {
2502 	.halt_reg = 0x2fcc,
2503 	.halt_bit = 13,
2504 	.clkr = {
2505 		.enable_reg = 0x298c,
2506 		.enable_mask = BIT(4),
2507 		.hw.init = &(struct clk_init_data){
2508 			.name = "usb_fs2_system_clk",
2509 			.parent_hws = (const struct clk_hw*[]){
2510 				&usb_fs2_xcvr_fs_src.clkr.hw,
2511 			},
2512 			.num_parents = 1,
2513 			.ops = &clk_branch_ops,
2514 			.flags = CLK_SET_RATE_PARENT,
2515 		},
2516 	},
2517 };
2518 
2519 static struct clk_branch ce1_core_clk = {
2520 	.hwcg_reg = 0x2724,
2521 	.hwcg_bit = 6,
2522 	.halt_reg = 0x2fd4,
2523 	.halt_bit = 27,
2524 	.clkr = {
2525 		.enable_reg = 0x2724,
2526 		.enable_mask = BIT(4),
2527 		.hw.init = &(struct clk_init_data){
2528 			.name = "ce1_core_clk",
2529 			.ops = &clk_branch_ops,
2530 		},
2531 	},
2532 };
2533 
2534 static struct clk_branch ce1_h_clk = {
2535 	.halt_reg = 0x2fd4,
2536 	.halt_bit = 1,
2537 	.clkr = {
2538 		.enable_reg = 0x2720,
2539 		.enable_mask = BIT(4),
2540 		.hw.init = &(struct clk_init_data){
2541 			.name = "ce1_h_clk",
2542 			.ops = &clk_branch_ops,
2543 		},
2544 	},
2545 };
2546 
2547 static struct clk_branch dma_bam_h_clk = {
2548 	.hwcg_reg = 0x25c0,
2549 	.hwcg_bit = 6,
2550 	.halt_reg = 0x2fc8,
2551 	.halt_bit = 12,
2552 	.clkr = {
2553 		.enable_reg = 0x25c0,
2554 		.enable_mask = BIT(4),
2555 		.hw.init = &(struct clk_init_data){
2556 			.name = "dma_bam_h_clk",
2557 			.ops = &clk_branch_ops,
2558 		},
2559 	},
2560 };
2561 
2562 static struct clk_branch gsbi1_h_clk = {
2563 	.hwcg_reg = 0x29c0,
2564 	.hwcg_bit = 6,
2565 	.halt_reg = 0x2fcc,
2566 	.halt_bit = 11,
2567 	.clkr = {
2568 		.enable_reg = 0x29c0,
2569 		.enable_mask = BIT(4),
2570 		.hw.init = &(struct clk_init_data){
2571 			.name = "gsbi1_h_clk",
2572 			.ops = &clk_branch_ops,
2573 		},
2574 	},
2575 };
2576 
2577 static struct clk_branch gsbi2_h_clk = {
2578 	.hwcg_reg = 0x29e0,
2579 	.hwcg_bit = 6,
2580 	.halt_reg = 0x2fcc,
2581 	.halt_bit = 7,
2582 	.clkr = {
2583 		.enable_reg = 0x29e0,
2584 		.enable_mask = BIT(4),
2585 		.hw.init = &(struct clk_init_data){
2586 			.name = "gsbi2_h_clk",
2587 			.ops = &clk_branch_ops,
2588 		},
2589 	},
2590 };
2591 
2592 static struct clk_branch gsbi3_h_clk = {
2593 	.hwcg_reg = 0x2a00,
2594 	.hwcg_bit = 6,
2595 	.halt_reg = 0x2fcc,
2596 	.halt_bit = 3,
2597 	.clkr = {
2598 		.enable_reg = 0x2a00,
2599 		.enable_mask = BIT(4),
2600 		.hw.init = &(struct clk_init_data){
2601 			.name = "gsbi3_h_clk",
2602 			.ops = &clk_branch_ops,
2603 		},
2604 	},
2605 };
2606 
2607 static struct clk_branch gsbi4_h_clk = {
2608 	.hwcg_reg = 0x2a20,
2609 	.hwcg_bit = 6,
2610 	.halt_reg = 0x2fd0,
2611 	.halt_bit = 27,
2612 	.clkr = {
2613 		.enable_reg = 0x2a20,
2614 		.enable_mask = BIT(4),
2615 		.hw.init = &(struct clk_init_data){
2616 			.name = "gsbi4_h_clk",
2617 			.ops = &clk_branch_ops,
2618 		},
2619 	},
2620 };
2621 
2622 static struct clk_branch gsbi5_h_clk = {
2623 	.hwcg_reg = 0x2a40,
2624 	.hwcg_bit = 6,
2625 	.halt_reg = 0x2fd0,
2626 	.halt_bit = 23,
2627 	.clkr = {
2628 		.enable_reg = 0x2a40,
2629 		.enable_mask = BIT(4),
2630 		.hw.init = &(struct clk_init_data){
2631 			.name = "gsbi5_h_clk",
2632 			.ops = &clk_branch_ops,
2633 		},
2634 	},
2635 };
2636 
2637 static struct clk_branch gsbi6_h_clk = {
2638 	.hwcg_reg = 0x2a60,
2639 	.hwcg_bit = 6,
2640 	.halt_reg = 0x2fd0,
2641 	.halt_bit = 19,
2642 	.clkr = {
2643 		.enable_reg = 0x2a60,
2644 		.enable_mask = BIT(4),
2645 		.hw.init = &(struct clk_init_data){
2646 			.name = "gsbi6_h_clk",
2647 			.ops = &clk_branch_ops,
2648 		},
2649 	},
2650 };
2651 
2652 static struct clk_branch gsbi7_h_clk = {
2653 	.hwcg_reg = 0x2a80,
2654 	.hwcg_bit = 6,
2655 	.halt_reg = 0x2fd0,
2656 	.halt_bit = 15,
2657 	.clkr = {
2658 		.enable_reg = 0x2a80,
2659 		.enable_mask = BIT(4),
2660 		.hw.init = &(struct clk_init_data){
2661 			.name = "gsbi7_h_clk",
2662 			.ops = &clk_branch_ops,
2663 		},
2664 	},
2665 };
2666 
2667 static struct clk_branch gsbi8_h_clk = {
2668 	.hwcg_reg = 0x2aa0,
2669 	.hwcg_bit = 6,
2670 	.halt_reg = 0x2fd0,
2671 	.halt_bit = 11,
2672 	.clkr = {
2673 		.enable_reg = 0x2aa0,
2674 		.enable_mask = BIT(4),
2675 		.hw.init = &(struct clk_init_data){
2676 			.name = "gsbi8_h_clk",
2677 			.ops = &clk_branch_ops,
2678 		},
2679 	},
2680 };
2681 
2682 static struct clk_branch gsbi9_h_clk = {
2683 	.hwcg_reg = 0x2ac0,
2684 	.hwcg_bit = 6,
2685 	.halt_reg = 0x2fd0,
2686 	.halt_bit = 7,
2687 	.clkr = {
2688 		.enable_reg = 0x2ac0,
2689 		.enable_mask = BIT(4),
2690 		.hw.init = &(struct clk_init_data){
2691 			.name = "gsbi9_h_clk",
2692 			.ops = &clk_branch_ops,
2693 		},
2694 	},
2695 };
2696 
2697 static struct clk_branch gsbi10_h_clk = {
2698 	.hwcg_reg = 0x2ae0,
2699 	.hwcg_bit = 6,
2700 	.halt_reg = 0x2fd0,
2701 	.halt_bit = 3,
2702 	.clkr = {
2703 		.enable_reg = 0x2ae0,
2704 		.enable_mask = BIT(4),
2705 		.hw.init = &(struct clk_init_data){
2706 			.name = "gsbi10_h_clk",
2707 			.ops = &clk_branch_ops,
2708 		},
2709 	},
2710 };
2711 
2712 static struct clk_branch gsbi11_h_clk = {
2713 	.hwcg_reg = 0x2b00,
2714 	.hwcg_bit = 6,
2715 	.halt_reg = 0x2fd4,
2716 	.halt_bit = 18,
2717 	.clkr = {
2718 		.enable_reg = 0x2b00,
2719 		.enable_mask = BIT(4),
2720 		.hw.init = &(struct clk_init_data){
2721 			.name = "gsbi11_h_clk",
2722 			.ops = &clk_branch_ops,
2723 		},
2724 	},
2725 };
2726 
2727 static struct clk_branch gsbi12_h_clk = {
2728 	.hwcg_reg = 0x2b20,
2729 	.hwcg_bit = 6,
2730 	.halt_reg = 0x2fd4,
2731 	.halt_bit = 14,
2732 	.clkr = {
2733 		.enable_reg = 0x2b20,
2734 		.enable_mask = BIT(4),
2735 		.hw.init = &(struct clk_init_data){
2736 			.name = "gsbi12_h_clk",
2737 			.ops = &clk_branch_ops,
2738 		},
2739 	},
2740 };
2741 
2742 static struct clk_branch tsif_h_clk = {
2743 	.hwcg_reg = 0x2700,
2744 	.hwcg_bit = 6,
2745 	.halt_reg = 0x2fd4,
2746 	.halt_bit = 7,
2747 	.clkr = {
2748 		.enable_reg = 0x2700,
2749 		.enable_mask = BIT(4),
2750 		.hw.init = &(struct clk_init_data){
2751 			.name = "tsif_h_clk",
2752 			.ops = &clk_branch_ops,
2753 		},
2754 	},
2755 };
2756 
2757 static struct clk_branch usb_fs1_h_clk = {
2758 	.halt_reg = 0x2fcc,
2759 	.halt_bit = 17,
2760 	.clkr = {
2761 		.enable_reg = 0x2960,
2762 		.enable_mask = BIT(4),
2763 		.hw.init = &(struct clk_init_data){
2764 			.name = "usb_fs1_h_clk",
2765 			.ops = &clk_branch_ops,
2766 		},
2767 	},
2768 };
2769 
2770 static struct clk_branch usb_fs2_h_clk = {
2771 	.halt_reg = 0x2fcc,
2772 	.halt_bit = 14,
2773 	.clkr = {
2774 		.enable_reg = 0x2980,
2775 		.enable_mask = BIT(4),
2776 		.hw.init = &(struct clk_init_data){
2777 			.name = "usb_fs2_h_clk",
2778 			.ops = &clk_branch_ops,
2779 		},
2780 	},
2781 };
2782 
2783 static struct clk_branch usb_hs1_h_clk = {
2784 	.hwcg_reg = 0x2900,
2785 	.hwcg_bit = 6,
2786 	.halt_reg = 0x2fc8,
2787 	.halt_bit = 1,
2788 	.clkr = {
2789 		.enable_reg = 0x2900,
2790 		.enable_mask = BIT(4),
2791 		.hw.init = &(struct clk_init_data){
2792 			.name = "usb_hs1_h_clk",
2793 			.ops = &clk_branch_ops,
2794 		},
2795 	},
2796 };
2797 
2798 static struct clk_branch usb_hs3_h_clk = {
2799 	.halt_reg = 0x2fc8,
2800 	.halt_bit = 31,
2801 	.clkr = {
2802 		.enable_reg = 0x3700,
2803 		.enable_mask = BIT(4),
2804 		.hw.init = &(struct clk_init_data){
2805 			.name = "usb_hs3_h_clk",
2806 			.ops = &clk_branch_ops,
2807 		},
2808 	},
2809 };
2810 
2811 static struct clk_branch usb_hs4_h_clk = {
2812 	.halt_reg = 0x2fc8,
2813 	.halt_bit = 7,
2814 	.clkr = {
2815 		.enable_reg = 0x3720,
2816 		.enable_mask = BIT(4),
2817 		.hw.init = &(struct clk_init_data){
2818 			.name = "usb_hs4_h_clk",
2819 			.ops = &clk_branch_ops,
2820 		},
2821 	},
2822 };
2823 
2824 static struct clk_branch usb_hsic_h_clk = {
2825 	.halt_reg = 0x2fcc,
2826 	.halt_bit = 28,
2827 	.clkr = {
2828 		.enable_reg = 0x2920,
2829 		.enable_mask = BIT(4),
2830 		.hw.init = &(struct clk_init_data){
2831 			.name = "usb_hsic_h_clk",
2832 			.ops = &clk_branch_ops,
2833 		},
2834 	},
2835 };
2836 
2837 static struct clk_branch sdc1_h_clk = {
2838 	.hwcg_reg = 0x2820,
2839 	.hwcg_bit = 6,
2840 	.halt_reg = 0x2fc8,
2841 	.halt_bit = 11,
2842 	.clkr = {
2843 		.enable_reg = 0x2820,
2844 		.enable_mask = BIT(4),
2845 		.hw.init = &(struct clk_init_data){
2846 			.name = "sdc1_h_clk",
2847 			.ops = &clk_branch_ops,
2848 		},
2849 	},
2850 };
2851 
2852 static struct clk_branch sdc2_h_clk = {
2853 	.hwcg_reg = 0x2840,
2854 	.hwcg_bit = 6,
2855 	.halt_reg = 0x2fc8,
2856 	.halt_bit = 10,
2857 	.clkr = {
2858 		.enable_reg = 0x2840,
2859 		.enable_mask = BIT(4),
2860 		.hw.init = &(struct clk_init_data){
2861 			.name = "sdc2_h_clk",
2862 			.ops = &clk_branch_ops,
2863 		},
2864 	},
2865 };
2866 
2867 static struct clk_branch sdc3_h_clk = {
2868 	.hwcg_reg = 0x2860,
2869 	.hwcg_bit = 6,
2870 	.halt_reg = 0x2fc8,
2871 	.halt_bit = 9,
2872 	.clkr = {
2873 		.enable_reg = 0x2860,
2874 		.enable_mask = BIT(4),
2875 		.hw.init = &(struct clk_init_data){
2876 			.name = "sdc3_h_clk",
2877 			.ops = &clk_branch_ops,
2878 		},
2879 	},
2880 };
2881 
2882 static struct clk_branch sdc4_h_clk = {
2883 	.hwcg_reg = 0x2880,
2884 	.hwcg_bit = 6,
2885 	.halt_reg = 0x2fc8,
2886 	.halt_bit = 8,
2887 	.clkr = {
2888 		.enable_reg = 0x2880,
2889 		.enable_mask = BIT(4),
2890 		.hw.init = &(struct clk_init_data){
2891 			.name = "sdc4_h_clk",
2892 			.ops = &clk_branch_ops,
2893 		},
2894 	},
2895 };
2896 
2897 static struct clk_branch sdc5_h_clk = {
2898 	.hwcg_reg = 0x28a0,
2899 	.hwcg_bit = 6,
2900 	.halt_reg = 0x2fc8,
2901 	.halt_bit = 7,
2902 	.clkr = {
2903 		.enable_reg = 0x28a0,
2904 		.enable_mask = BIT(4),
2905 		.hw.init = &(struct clk_init_data){
2906 			.name = "sdc5_h_clk",
2907 			.ops = &clk_branch_ops,
2908 		},
2909 	},
2910 };
2911 
2912 static struct clk_branch adm0_clk = {
2913 	.halt_reg = 0x2fdc,
2914 	.halt_check = BRANCH_HALT_VOTED,
2915 	.halt_bit = 14,
2916 	.clkr = {
2917 		.enable_reg = 0x3080,
2918 		.enable_mask = BIT(2),
2919 		.hw.init = &(struct clk_init_data){
2920 			.name = "adm0_clk",
2921 			.ops = &clk_branch_ops,
2922 		},
2923 	},
2924 };
2925 
2926 static struct clk_branch adm0_pbus_clk = {
2927 	.hwcg_reg = 0x2208,
2928 	.hwcg_bit = 6,
2929 	.halt_reg = 0x2fdc,
2930 	.halt_check = BRANCH_HALT_VOTED,
2931 	.halt_bit = 13,
2932 	.clkr = {
2933 		.enable_reg = 0x3080,
2934 		.enable_mask = BIT(3),
2935 		.hw.init = &(struct clk_init_data){
2936 			.name = "adm0_pbus_clk",
2937 			.ops = &clk_branch_ops,
2938 		},
2939 	},
2940 };
2941 
2942 static struct freq_tbl clk_tbl_ce3[] = {
2943 	{ 48000000, P_PLL8, 8 },
2944 	{ 100000000, P_PLL3, 12 },
2945 	{ 120000000, P_PLL3, 10 },
2946 	{ }
2947 };
2948 
2949 static struct clk_rcg ce3_src = {
2950 	.ns_reg = 0x36c0,
2951 	.p = {
2952 		.pre_div_shift = 3,
2953 		.pre_div_width = 4,
2954 	},
2955 	.s = {
2956 		.src_sel_shift = 0,
2957 		.parent_map = gcc_pxo_pll8_pll3_map,
2958 	},
2959 	.freq_tbl = clk_tbl_ce3,
2960 	.clkr = {
2961 		.enable_reg = 0x36c0,
2962 		.enable_mask = BIT(7),
2963 		.hw.init = &(struct clk_init_data){
2964 			.name = "ce3_src",
2965 			.parent_data = gcc_pxo_pll8_pll3,
2966 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
2967 			.ops = &clk_rcg_ops,
2968 			.flags = CLK_SET_RATE_GATE,
2969 		},
2970 	},
2971 };
2972 
2973 static struct clk_branch ce3_core_clk = {
2974 	.halt_reg = 0x2fdc,
2975 	.halt_bit = 5,
2976 	.clkr = {
2977 		.enable_reg = 0x36cc,
2978 		.enable_mask = BIT(4),
2979 		.hw.init = &(struct clk_init_data){
2980 			.name = "ce3_core_clk",
2981 			.parent_hws = (const struct clk_hw*[]){
2982 				&ce3_src.clkr.hw
2983 			},
2984 			.num_parents = 1,
2985 			.ops = &clk_branch_ops,
2986 			.flags = CLK_SET_RATE_PARENT,
2987 		},
2988 	},
2989 };
2990 
2991 static struct clk_branch ce3_h_clk = {
2992 	.halt_reg = 0x2fc4,
2993 	.halt_bit = 16,
2994 	.clkr = {
2995 		.enable_reg = 0x36c4,
2996 		.enable_mask = BIT(4),
2997 		.hw.init = &(struct clk_init_data){
2998 			.name = "ce3_h_clk",
2999 			.parent_hws = (const struct clk_hw*[]){
3000 				&ce3_src.clkr.hw
3001 			},
3002 			.num_parents = 1,
3003 			.ops = &clk_branch_ops,
3004 			.flags = CLK_SET_RATE_PARENT,
3005 		},
3006 	},
3007 };
3008 
3009 static const struct freq_tbl clk_tbl_sata_ref[] = {
3010 	{ 48000000, P_PLL8, 8, 0, 0 },
3011 	{ 100000000, P_PLL3, 12, 0, 0 },
3012 	{ }
3013 };
3014 
3015 static struct clk_rcg sata_clk_src = {
3016 	.ns_reg = 0x2c08,
3017 	.p = {
3018 		.pre_div_shift = 3,
3019 		.pre_div_width = 4,
3020 	},
3021 	.s = {
3022 		.src_sel_shift = 0,
3023 		.parent_map = gcc_pxo_pll8_pll3_map,
3024 	},
3025 	.freq_tbl = clk_tbl_sata_ref,
3026 	.clkr = {
3027 		.enable_reg = 0x2c08,
3028 		.enable_mask = BIT(7),
3029 		.hw.init = &(struct clk_init_data){
3030 			.name = "sata_clk_src",
3031 			.parent_data = gcc_pxo_pll8_pll3,
3032 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
3033 			.ops = &clk_rcg_ops,
3034 			.flags = CLK_SET_RATE_GATE,
3035 		},
3036 	},
3037 };
3038 
3039 static struct clk_branch sata_rxoob_clk = {
3040 	.halt_reg = 0x2fdc,
3041 	.halt_bit = 26,
3042 	.clkr = {
3043 		.enable_reg = 0x2c0c,
3044 		.enable_mask = BIT(4),
3045 		.hw.init = &(struct clk_init_data){
3046 			.name = "sata_rxoob_clk",
3047 			.parent_hws = (const struct clk_hw*[]){
3048 				&sata_clk_src.clkr.hw,
3049 			},
3050 			.num_parents = 1,
3051 			.ops = &clk_branch_ops,
3052 			.flags = CLK_SET_RATE_PARENT,
3053 		},
3054 	},
3055 };
3056 
3057 static struct clk_branch sata_pmalive_clk = {
3058 	.halt_reg = 0x2fdc,
3059 	.halt_bit = 25,
3060 	.clkr = {
3061 		.enable_reg = 0x2c10,
3062 		.enable_mask = BIT(4),
3063 		.hw.init = &(struct clk_init_data){
3064 			.name = "sata_pmalive_clk",
3065 			.parent_hws = (const struct clk_hw*[]){
3066 				&sata_clk_src.clkr.hw,
3067 			},
3068 			.num_parents = 1,
3069 			.ops = &clk_branch_ops,
3070 			.flags = CLK_SET_RATE_PARENT,
3071 		},
3072 	},
3073 };
3074 
3075 static struct clk_branch sata_phy_ref_clk = {
3076 	.halt_reg = 0x2fdc,
3077 	.halt_bit = 24,
3078 	.clkr = {
3079 		.enable_reg = 0x2c14,
3080 		.enable_mask = BIT(4),
3081 		.hw.init = &(struct clk_init_data){
3082 			.name = "sata_phy_ref_clk",
3083 			.parent_data = &(const struct clk_parent_data){
3084 				.fw_name = "pxo", .name = "pxo_board",
3085 			},
3086 			.num_parents = 1,
3087 			.ops = &clk_branch_ops,
3088 		},
3089 	},
3090 };
3091 
3092 static struct clk_branch sata_a_clk = {
3093 	.halt_reg = 0x2fc0,
3094 	.halt_bit = 12,
3095 	.clkr = {
3096 		.enable_reg = 0x2c20,
3097 		.enable_mask = BIT(4),
3098 		.hw.init = &(struct clk_init_data){
3099 			.name = "sata_a_clk",
3100 			.ops = &clk_branch_ops,
3101 		},
3102 	},
3103 };
3104 
3105 static struct clk_branch sata_h_clk = {
3106 	.halt_reg = 0x2fdc,
3107 	.halt_bit = 27,
3108 	.clkr = {
3109 		.enable_reg = 0x2c00,
3110 		.enable_mask = BIT(4),
3111 		.hw.init = &(struct clk_init_data){
3112 			.name = "sata_h_clk",
3113 			.ops = &clk_branch_ops,
3114 		},
3115 	},
3116 };
3117 
3118 static struct clk_branch sfab_sata_s_h_clk = {
3119 	.halt_reg = 0x2fc4,
3120 	.halt_bit = 14,
3121 	.clkr = {
3122 		.enable_reg = 0x2480,
3123 		.enable_mask = BIT(4),
3124 		.hw.init = &(struct clk_init_data){
3125 			.name = "sfab_sata_s_h_clk",
3126 			.ops = &clk_branch_ops,
3127 		},
3128 	},
3129 };
3130 
3131 static struct clk_branch sata_phy_cfg_clk = {
3132 	.halt_reg = 0x2fcc,
3133 	.halt_bit = 12,
3134 	.clkr = {
3135 		.enable_reg = 0x2c40,
3136 		.enable_mask = BIT(4),
3137 		.hw.init = &(struct clk_init_data){
3138 			.name = "sata_phy_cfg_clk",
3139 			.ops = &clk_branch_ops,
3140 		},
3141 	},
3142 };
3143 
3144 static struct clk_branch pcie_phy_ref_clk = {
3145 	.halt_reg = 0x2fdc,
3146 	.halt_bit = 29,
3147 	.clkr = {
3148 		.enable_reg = 0x22d0,
3149 		.enable_mask = BIT(4),
3150 		.hw.init = &(struct clk_init_data){
3151 			.name = "pcie_phy_ref_clk",
3152 			.ops = &clk_branch_ops,
3153 		},
3154 	},
3155 };
3156 
3157 static struct clk_branch pcie_h_clk = {
3158 	.halt_reg = 0x2fd4,
3159 	.halt_bit = 8,
3160 	.clkr = {
3161 		.enable_reg = 0x22cc,
3162 		.enable_mask = BIT(4),
3163 		.hw.init = &(struct clk_init_data){
3164 			.name = "pcie_h_clk",
3165 			.ops = &clk_branch_ops,
3166 		},
3167 	},
3168 };
3169 
3170 static struct clk_branch pcie_a_clk = {
3171 	.halt_reg = 0x2fc0,
3172 	.halt_bit = 13,
3173 	.clkr = {
3174 		.enable_reg = 0x22c0,
3175 		.enable_mask = BIT(4),
3176 		.hw.init = &(struct clk_init_data){
3177 			.name = "pcie_a_clk",
3178 			.ops = &clk_branch_ops,
3179 		},
3180 	},
3181 };
3182 
3183 static struct clk_branch pmic_arb0_h_clk = {
3184 	.halt_reg = 0x2fd8,
3185 	.halt_check = BRANCH_HALT_VOTED,
3186 	.halt_bit = 22,
3187 	.clkr = {
3188 		.enable_reg = 0x3080,
3189 		.enable_mask = BIT(8),
3190 		.hw.init = &(struct clk_init_data){
3191 			.name = "pmic_arb0_h_clk",
3192 			.ops = &clk_branch_ops,
3193 		},
3194 	},
3195 };
3196 
3197 static struct clk_branch pmic_arb1_h_clk = {
3198 	.halt_reg = 0x2fd8,
3199 	.halt_check = BRANCH_HALT_VOTED,
3200 	.halt_bit = 21,
3201 	.clkr = {
3202 		.enable_reg = 0x3080,
3203 		.enable_mask = BIT(9),
3204 		.hw.init = &(struct clk_init_data){
3205 			.name = "pmic_arb1_h_clk",
3206 			.ops = &clk_branch_ops,
3207 		},
3208 	},
3209 };
3210 
3211 static struct clk_branch pmic_ssbi2_clk = {
3212 	.halt_reg = 0x2fd8,
3213 	.halt_check = BRANCH_HALT_VOTED,
3214 	.halt_bit = 23,
3215 	.clkr = {
3216 		.enable_reg = 0x3080,
3217 		.enable_mask = BIT(7),
3218 		.hw.init = &(struct clk_init_data){
3219 			.name = "pmic_ssbi2_clk",
3220 			.ops = &clk_branch_ops,
3221 		},
3222 	},
3223 };
3224 
3225 static struct clk_branch rpm_msg_ram_h_clk = {
3226 	.hwcg_reg = 0x27e0,
3227 	.hwcg_bit = 6,
3228 	.halt_reg = 0x2fd8,
3229 	.halt_check = BRANCH_HALT_VOTED,
3230 	.halt_bit = 12,
3231 	.clkr = {
3232 		.enable_reg = 0x3080,
3233 		.enable_mask = BIT(6),
3234 		.hw.init = &(struct clk_init_data){
3235 			.name = "rpm_msg_ram_h_clk",
3236 			.ops = &clk_branch_ops,
3237 		},
3238 	},
3239 };
3240 
3241 static struct clk_regmap *gcc_msm8960_clks[] = {
3242 	[PLL3] = &pll3.clkr,
3243 	[PLL4_VOTE] = &pll4_vote,
3244 	[PLL8] = &pll8.clkr,
3245 	[PLL8_VOTE] = &pll8_vote,
3246 	[PLL14] = &pll14.clkr,
3247 	[PLL14_VOTE] = &pll14_vote,
3248 	[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3249 	[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3250 	[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3251 	[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3252 	[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3253 	[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3254 	[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3255 	[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3256 	[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3257 	[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3258 	[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3259 	[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3260 	[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3261 	[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3262 	[GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3263 	[GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3264 	[GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3265 	[GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3266 	[GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3267 	[GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3268 	[GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3269 	[GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3270 	[GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3271 	[GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3272 	[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3273 	[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3274 	[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3275 	[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3276 	[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3277 	[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3278 	[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3279 	[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3280 	[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3281 	[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3282 	[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3283 	[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3284 	[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3285 	[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3286 	[GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3287 	[GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3288 	[GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3289 	[GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3290 	[GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3291 	[GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3292 	[GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3293 	[GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3294 	[GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3295 	[GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3296 	[GP0_SRC] = &gp0_src.clkr,
3297 	[GP0_CLK] = &gp0_clk.clkr,
3298 	[GP1_SRC] = &gp1_src.clkr,
3299 	[GP1_CLK] = &gp1_clk.clkr,
3300 	[GP2_SRC] = &gp2_src.clkr,
3301 	[GP2_CLK] = &gp2_clk.clkr,
3302 	[PMEM_A_CLK] = &pmem_clk.clkr,
3303 	[PRNG_SRC] = &prng_src.clkr,
3304 	[PRNG_CLK] = &prng_clk.clkr,
3305 	[SDC1_SRC] = &sdc1_src.clkr,
3306 	[SDC1_CLK] = &sdc1_clk.clkr,
3307 	[SDC2_SRC] = &sdc2_src.clkr,
3308 	[SDC2_CLK] = &sdc2_clk.clkr,
3309 	[SDC3_SRC] = &sdc3_src.clkr,
3310 	[SDC3_CLK] = &sdc3_clk.clkr,
3311 	[SDC4_SRC] = &sdc4_src.clkr,
3312 	[SDC4_CLK] = &sdc4_clk.clkr,
3313 	[SDC5_SRC] = &sdc5_src.clkr,
3314 	[SDC5_CLK] = &sdc5_clk.clkr,
3315 	[TSIF_REF_SRC] = &tsif_ref_src.clkr,
3316 	[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3317 	[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3318 	[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3319 	[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3320 	[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3321 	[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3322 	[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3323 	[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3324 	[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3325 	[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3326 	[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3327 	[USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3328 	[USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3329 	[USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3330 	[CE1_CORE_CLK] = &ce1_core_clk.clkr,
3331 	[CE1_H_CLK] = &ce1_h_clk.clkr,
3332 	[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3333 	[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3334 	[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3335 	[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3336 	[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3337 	[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3338 	[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3339 	[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3340 	[GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3341 	[GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3342 	[GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3343 	[GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3344 	[GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3345 	[TSIF_H_CLK] = &tsif_h_clk.clkr,
3346 	[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3347 	[USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3348 	[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3349 	[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3350 	[SDC1_H_CLK] = &sdc1_h_clk.clkr,
3351 	[SDC2_H_CLK] = &sdc2_h_clk.clkr,
3352 	[SDC3_H_CLK] = &sdc3_h_clk.clkr,
3353 	[SDC4_H_CLK] = &sdc4_h_clk.clkr,
3354 	[SDC5_H_CLK] = &sdc5_h_clk.clkr,
3355 	[ADM0_CLK] = &adm0_clk.clkr,
3356 	[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3357 	[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3358 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3359 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3360 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3361 	[PLL9] = &hfpll0.clkr,
3362 	[PLL10] = &hfpll1.clkr,
3363 	[PLL12] = &hfpll_l2.clkr,
3364 };
3365 
3366 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3367 	[SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3368 	[SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3369 	[QDSS_STM_RESET] = { 0x2060, 6 },
3370 	[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3371 	[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3372 	[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3373 	[AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3374 	[AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3375 	[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3376 	[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3377 	[SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3378 	[ADM0_C2_RESET] = { 0x220c, 4},
3379 	[ADM0_C1_RESET] = { 0x220c, 3},
3380 	[ADM0_C0_RESET] = { 0x220c, 2},
3381 	[ADM0_PBUS_RESET] = { 0x220c, 1 },
3382 	[ADM0_RESET] = { 0x220c },
3383 	[QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3384 	[QDSS_POR_RESET] = { 0x2260, 4 },
3385 	[QDSS_TSCTR_RESET] = { 0x2260, 3 },
3386 	[QDSS_HRESET_RESET] = { 0x2260, 2 },
3387 	[QDSS_AXI_RESET] = { 0x2260, 1 },
3388 	[QDSS_DBG_RESET] = { 0x2260 },
3389 	[PCIE_A_RESET] = { 0x22c0, 7 },
3390 	[PCIE_AUX_RESET] = { 0x22c8, 7 },
3391 	[PCIE_H_RESET] = { 0x22d0, 7 },
3392 	[SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3393 	[SFAB_PCIE_S_RESET] = { 0x22d4 },
3394 	[SFAB_MSS_M_RESET] = { 0x2340, 7 },
3395 	[SFAB_USB3_M_RESET] = { 0x2360, 7 },
3396 	[SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3397 	[SFAB_LPASS_RESET] = { 0x23a0, 7 },
3398 	[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3399 	[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3400 	[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3401 	[SFAB_SATA_S_RESET] = { 0x2480, 7 },
3402 	[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3403 	[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3404 	[DFAB_SWAY0_RESET] = { 0x2540, 7 },
3405 	[DFAB_SWAY1_RESET] = { 0x2544, 7 },
3406 	[DFAB_ARB0_RESET] = { 0x2560, 7 },
3407 	[DFAB_ARB1_RESET] = { 0x2564, 7 },
3408 	[PPSS_PROC_RESET] = { 0x2594, 1 },
3409 	[PPSS_RESET] = { 0x2594},
3410 	[DMA_BAM_RESET] = { 0x25c0, 7 },
3411 	[SPS_TIC_H_RESET] = { 0x2600, 7 },
3412 	[SLIMBUS_H_RESET] = { 0x2620, 7 },
3413 	[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3414 	[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3415 	[TSIF_H_RESET] = { 0x2700, 7 },
3416 	[CE1_H_RESET] = { 0x2720, 7 },
3417 	[CE1_CORE_RESET] = { 0x2724, 7 },
3418 	[CE1_SLEEP_RESET] = { 0x2728, 7 },
3419 	[CE2_H_RESET] = { 0x2740, 7 },
3420 	[CE2_CORE_RESET] = { 0x2744, 7 },
3421 	[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3422 	[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3423 	[RPM_PROC_RESET] = { 0x27c0, 7 },
3424 	[PMIC_SSBI2_RESET] = { 0x280c, 12 },
3425 	[SDC1_RESET] = { 0x2830 },
3426 	[SDC2_RESET] = { 0x2850 },
3427 	[SDC3_RESET] = { 0x2870 },
3428 	[SDC4_RESET] = { 0x2890 },
3429 	[SDC5_RESET] = { 0x28b0 },
3430 	[DFAB_A2_RESET] = { 0x28c0, 7 },
3431 	[USB_HS1_RESET] = { 0x2910 },
3432 	[USB_HSIC_RESET] = { 0x2934 },
3433 	[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3434 	[USB_FS1_RESET] = { 0x2974 },
3435 	[USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3436 	[USB_FS2_RESET] = { 0x2994 },
3437 	[GSBI1_RESET] = { 0x29dc },
3438 	[GSBI2_RESET] = { 0x29fc },
3439 	[GSBI3_RESET] = { 0x2a1c },
3440 	[GSBI4_RESET] = { 0x2a3c },
3441 	[GSBI5_RESET] = { 0x2a5c },
3442 	[GSBI6_RESET] = { 0x2a7c },
3443 	[GSBI7_RESET] = { 0x2a9c },
3444 	[GSBI8_RESET] = { 0x2abc },
3445 	[GSBI9_RESET] = { 0x2adc },
3446 	[GSBI10_RESET] = { 0x2afc },
3447 	[GSBI11_RESET] = { 0x2b1c },
3448 	[GSBI12_RESET] = { 0x2b3c },
3449 	[SPDM_RESET] = { 0x2b6c },
3450 	[TLMM_H_RESET] = { 0x2ba0, 7 },
3451 	[SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3452 	[MSS_SLP_RESET] = { 0x2c60, 7 },
3453 	[MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3454 	[MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3455 	[MSS_RESET] = { 0x2c64 },
3456 	[SATA_H_RESET] = { 0x2c80, 7 },
3457 	[SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3458 	[SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3459 	[SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3460 	[TSSC_RESET] = { 0x2ca0, 7 },
3461 	[PDM_RESET] = { 0x2cc0, 12 },
3462 	[MPM_H_RESET] = { 0x2da0, 7 },
3463 	[MPM_RESET] = { 0x2da4 },
3464 	[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3465 	[PRNG_RESET] = { 0x2e80, 12 },
3466 	[RIVA_RESET] = { 0x35e0 },
3467 };
3468 
3469 static struct clk_regmap *gcc_apq8064_clks[] = {
3470 	[PLL3] = &pll3.clkr,
3471 	[PLL4_VOTE] = &pll4_vote,
3472 	[PLL8] = &pll8.clkr,
3473 	[PLL8_VOTE] = &pll8_vote,
3474 	[PLL14] = &pll14.clkr,
3475 	[PLL14_VOTE] = &pll14_vote,
3476 	[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3477 	[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3478 	[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3479 	[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3480 	[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3481 	[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3482 	[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3483 	[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3484 	[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3485 	[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3486 	[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3487 	[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3488 	[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3489 	[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3490 	[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3491 	[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3492 	[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3493 	[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3494 	[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3495 	[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3496 	[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3497 	[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3498 	[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3499 	[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3500 	[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3501 	[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3502 	[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3503 	[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3504 	[GP0_SRC] = &gp0_src.clkr,
3505 	[GP0_CLK] = &gp0_clk.clkr,
3506 	[GP1_SRC] = &gp1_src.clkr,
3507 	[GP1_CLK] = &gp1_clk.clkr,
3508 	[GP2_SRC] = &gp2_src.clkr,
3509 	[GP2_CLK] = &gp2_clk.clkr,
3510 	[PMEM_A_CLK] = &pmem_clk.clkr,
3511 	[PRNG_SRC] = &prng_src.clkr,
3512 	[PRNG_CLK] = &prng_clk.clkr,
3513 	[SDC1_SRC] = &sdc1_src.clkr,
3514 	[SDC1_CLK] = &sdc1_clk.clkr,
3515 	[SDC2_SRC] = &sdc2_src.clkr,
3516 	[SDC2_CLK] = &sdc2_clk.clkr,
3517 	[SDC3_SRC] = &sdc3_src.clkr,
3518 	[SDC3_CLK] = &sdc3_clk.clkr,
3519 	[SDC4_SRC] = &sdc4_src.clkr,
3520 	[SDC4_CLK] = &sdc4_clk.clkr,
3521 	[TSIF_REF_SRC] = &tsif_ref_src.clkr,
3522 	[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3523 	[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3524 	[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3525 	[USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3526 	[USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3527 	[USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3528 	[USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3529 	[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3530 	[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3531 	[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3532 	[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3533 	[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3534 	[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3535 	[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3536 	[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3537 	[SATA_H_CLK] = &sata_h_clk.clkr,
3538 	[SATA_CLK_SRC] = &sata_clk_src.clkr,
3539 	[SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3540 	[SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3541 	[SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3542 	[SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3543 	[SATA_A_CLK] = &sata_a_clk.clkr,
3544 	[SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3545 	[CE3_SRC] = &ce3_src.clkr,
3546 	[CE3_CORE_CLK] = &ce3_core_clk.clkr,
3547 	[CE3_H_CLK] = &ce3_h_clk.clkr,
3548 	[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3549 	[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3550 	[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3551 	[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3552 	[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3553 	[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3554 	[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3555 	[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3556 	[TSIF_H_CLK] = &tsif_h_clk.clkr,
3557 	[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3558 	[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3559 	[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3560 	[USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3561 	[USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3562 	[SDC1_H_CLK] = &sdc1_h_clk.clkr,
3563 	[SDC2_H_CLK] = &sdc2_h_clk.clkr,
3564 	[SDC3_H_CLK] = &sdc3_h_clk.clkr,
3565 	[SDC4_H_CLK] = &sdc4_h_clk.clkr,
3566 	[ADM0_CLK] = &adm0_clk.clkr,
3567 	[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3568 	[PCIE_A_CLK] = &pcie_a_clk.clkr,
3569 	[PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3570 	[PCIE_H_CLK] = &pcie_h_clk.clkr,
3571 	[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3572 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3573 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3574 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3575 	[PLL9] = &hfpll0.clkr,
3576 	[PLL10] = &hfpll1.clkr,
3577 	[PLL12] = &hfpll_l2.clkr,
3578 	[PLL16] = &hfpll2.clkr,
3579 	[PLL17] = &hfpll3.clkr,
3580 };
3581 
3582 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3583 	[QDSS_STM_RESET] = { 0x2060, 6 },
3584 	[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3585 	[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3586 	[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3587 	[AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3588 	[AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3589 	[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3590 	[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3591 	[SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3592 	[ADM0_C2_RESET] = { 0x220c, 4},
3593 	[ADM0_C1_RESET] = { 0x220c, 3},
3594 	[ADM0_C0_RESET] = { 0x220c, 2},
3595 	[ADM0_PBUS_RESET] = { 0x220c, 1 },
3596 	[ADM0_RESET] = { 0x220c },
3597 	[QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3598 	[QDSS_POR_RESET] = { 0x2260, 4 },
3599 	[QDSS_TSCTR_RESET] = { 0x2260, 3 },
3600 	[QDSS_HRESET_RESET] = { 0x2260, 2 },
3601 	[QDSS_AXI_RESET] = { 0x2260, 1 },
3602 	[QDSS_DBG_RESET] = { 0x2260 },
3603 	[SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3604 	[SFAB_PCIE_S_RESET] = { 0x22d8 },
3605 	[PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3606 	[PCIE_PHY_RESET] = { 0x22dc, 5 },
3607 	[PCIE_PCI_RESET] = { 0x22dc, 4 },
3608 	[PCIE_POR_RESET] = { 0x22dc, 3 },
3609 	[PCIE_HCLK_RESET] = { 0x22dc, 2 },
3610 	[PCIE_ACLK_RESET] = { 0x22dc },
3611 	[SFAB_USB3_M_RESET] = { 0x2360, 7 },
3612 	[SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3613 	[SFAB_LPASS_RESET] = { 0x23a0, 7 },
3614 	[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3615 	[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3616 	[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3617 	[SFAB_SATA_S_RESET] = { 0x2480, 7 },
3618 	[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3619 	[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3620 	[DFAB_SWAY0_RESET] = { 0x2540, 7 },
3621 	[DFAB_SWAY1_RESET] = { 0x2544, 7 },
3622 	[DFAB_ARB0_RESET] = { 0x2560, 7 },
3623 	[DFAB_ARB1_RESET] = { 0x2564, 7 },
3624 	[PPSS_PROC_RESET] = { 0x2594, 1 },
3625 	[PPSS_RESET] = { 0x2594},
3626 	[DMA_BAM_RESET] = { 0x25c0, 7 },
3627 	[SPS_TIC_H_RESET] = { 0x2600, 7 },
3628 	[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3629 	[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3630 	[TSIF_H_RESET] = { 0x2700, 7 },
3631 	[CE1_H_RESET] = { 0x2720, 7 },
3632 	[CE1_CORE_RESET] = { 0x2724, 7 },
3633 	[CE1_SLEEP_RESET] = { 0x2728, 7 },
3634 	[CE2_H_RESET] = { 0x2740, 7 },
3635 	[CE2_CORE_RESET] = { 0x2744, 7 },
3636 	[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3637 	[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3638 	[RPM_PROC_RESET] = { 0x27c0, 7 },
3639 	[PMIC_SSBI2_RESET] = { 0x280c, 12 },
3640 	[SDC1_RESET] = { 0x2830 },
3641 	[SDC2_RESET] = { 0x2850 },
3642 	[SDC3_RESET] = { 0x2870 },
3643 	[SDC4_RESET] = { 0x2890 },
3644 	[USB_HS1_RESET] = { 0x2910 },
3645 	[USB_HSIC_RESET] = { 0x2934 },
3646 	[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3647 	[USB_FS1_RESET] = { 0x2974 },
3648 	[GSBI1_RESET] = { 0x29dc },
3649 	[GSBI2_RESET] = { 0x29fc },
3650 	[GSBI3_RESET] = { 0x2a1c },
3651 	[GSBI4_RESET] = { 0x2a3c },
3652 	[GSBI5_RESET] = { 0x2a5c },
3653 	[GSBI6_RESET] = { 0x2a7c },
3654 	[GSBI7_RESET] = { 0x2a9c },
3655 	[SPDM_RESET] = { 0x2b6c },
3656 	[TLMM_H_RESET] = { 0x2ba0, 7 },
3657 	[SATA_SFAB_M_RESET] = { 0x2c18 },
3658 	[SATA_RESET] = { 0x2c1c },
3659 	[GSS_SLP_RESET] = { 0x2c60, 7 },
3660 	[GSS_RESET] = { 0x2c64 },
3661 	[TSSC_RESET] = { 0x2ca0, 7 },
3662 	[PDM_RESET] = { 0x2cc0, 12 },
3663 	[MPM_H_RESET] = { 0x2da0, 7 },
3664 	[MPM_RESET] = { 0x2da4 },
3665 	[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3666 	[PRNG_RESET] = { 0x2e80, 12 },
3667 	[RIVA_RESET] = { 0x35e0 },
3668 	[CE3_H_RESET] = { 0x36c4, 7 },
3669 	[SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3670 	[SFAB_CE3_S_RESET] = { 0x36c8 },
3671 	[CE3_RESET] = { 0x36cc, 7 },
3672 	[CE3_SLEEP_RESET] = { 0x36d0, 7 },
3673 	[USB_HS3_RESET] = { 0x3710 },
3674 	[USB_HS4_RESET] = { 0x3730 },
3675 };
3676 
3677 static const struct regmap_config gcc_msm8960_regmap_config = {
3678 	.reg_bits	= 32,
3679 	.reg_stride	= 4,
3680 	.val_bits	= 32,
3681 	.max_register	= 0x3660,
3682 	.fast_io	= true,
3683 };
3684 
3685 static const struct regmap_config gcc_apq8064_regmap_config = {
3686 	.reg_bits	= 32,
3687 	.reg_stride	= 4,
3688 	.val_bits	= 32,
3689 	.max_register	= 0x3880,
3690 	.fast_io	= true,
3691 };
3692 
3693 static const struct qcom_cc_desc gcc_msm8960_desc = {
3694 	.config = &gcc_msm8960_regmap_config,
3695 	.clks = gcc_msm8960_clks,
3696 	.num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3697 	.resets = gcc_msm8960_resets,
3698 	.num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3699 };
3700 
3701 static const struct qcom_cc_desc gcc_apq8064_desc = {
3702 	.config = &gcc_apq8064_regmap_config,
3703 	.clks = gcc_apq8064_clks,
3704 	.num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3705 	.resets = gcc_apq8064_resets,
3706 	.num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3707 };
3708 
3709 static const struct of_device_id gcc_msm8960_match_table[] = {
3710 	{ .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3711 	{ .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3712 	{ }
3713 };
3714 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3715 
gcc_msm8960_probe(struct platform_device * pdev)3716 static int gcc_msm8960_probe(struct platform_device *pdev)
3717 {
3718 	struct device *dev = &pdev->dev;
3719 	const struct of_device_id *match;
3720 	struct platform_device *tsens;
3721 	int ret;
3722 
3723 	match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3724 	if (!match)
3725 		return -EINVAL;
3726 
3727 	ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3728 	if (ret)
3729 		return ret;
3730 
3731 	ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3732 	if (ret)
3733 		return ret;
3734 
3735 	ret = qcom_cc_probe(pdev, match->data);
3736 	if (ret)
3737 		return ret;
3738 
3739 	if (match->data == &gcc_apq8064_desc) {
3740 		hfpll1.d = &hfpll1_8064_data;
3741 		hfpll_l2.d = &hfpll_l2_8064_data;
3742 	}
3743 
3744 	if (of_get_available_child_count(pdev->dev.of_node) != 0)
3745 		return devm_of_platform_populate(&pdev->dev);
3746 
3747 	tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3748 					      NULL, 0);
3749 	if (IS_ERR(tsens))
3750 		return PTR_ERR(tsens);
3751 
3752 	platform_set_drvdata(pdev, tsens);
3753 
3754 	return 0;
3755 }
3756 
gcc_msm8960_remove(struct platform_device * pdev)3757 static void gcc_msm8960_remove(struct platform_device *pdev)
3758 {
3759 	struct platform_device *tsens = platform_get_drvdata(pdev);
3760 
3761 	if (tsens)
3762 		platform_device_unregister(tsens);
3763 }
3764 
3765 static struct platform_driver gcc_msm8960_driver = {
3766 	.probe		= gcc_msm8960_probe,
3767 	.remove_new	= gcc_msm8960_remove,
3768 	.driver		= {
3769 		.name	= "gcc-msm8960",
3770 		.of_match_table = gcc_msm8960_match_table,
3771 	},
3772 };
3773 
gcc_msm8960_init(void)3774 static int __init gcc_msm8960_init(void)
3775 {
3776 	return platform_driver_register(&gcc_msm8960_driver);
3777 }
3778 core_initcall(gcc_msm8960_init);
3779 
gcc_msm8960_exit(void)3780 static void __exit gcc_msm8960_exit(void)
3781 {
3782 	platform_driver_unregister(&gcc_msm8960_driver);
3783 }
3784 module_exit(gcc_msm8960_exit);
3785 
3786 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3787 MODULE_LICENSE("GPL v2");
3788 MODULE_ALIAS("platform:gcc-msm8960");
3789