xref: /openbmc/linux/drivers/clk/imx/clk-pllv3.c (revision 64ea30d1)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2012 Freescale Semiconductor, Inc.
4  * Copyright 2012 Linaro Ltd.
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/slab.h>
13 #include <linux/jiffies.h>
14 #include <linux/err.h>
15 #include "clk.h"
16 
17 #define PLL_NUM_OFFSET		0x10
18 #define PLL_DENOM_OFFSET	0x20
19 #define PLL_IMX7_NUM_OFFSET	0x20
20 #define PLL_IMX7_DENOM_OFFSET	0x30
21 
22 #define PLL_VF610_NUM_OFFSET	0x20
23 #define PLL_VF610_DENOM_OFFSET	0x30
24 
25 #define BM_PLL_POWER		(0x1 << 12)
26 #define BM_PLL_LOCK		(0x1 << 31)
27 #define IMX7_ENET_PLL_POWER	(0x1 << 5)
28 #define IMX7_DDR_PLL_POWER	(0x1 << 20)
29 
30 #define PLL_LOCK_TIMEOUT	10000
31 
32 /**
33  * struct clk_pllv3 - IMX PLL clock version 3
34  * @hw:		clock source
35  * @base:	 base address of PLL registers
36  * @power_bit:	 pll power bit mask
37  * @powerup_set: set power_bit to power up the PLL
38  * @div_mask:	 mask of divider bits
39  * @div_shift:	 shift of divider bits
40  * @ref_clock:	reference clock rate
41  * @num_offset:	num register offset
42  * @denom_offset: denom register offset
43  *
44  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
45  * is actually a multiplier, and always sits at bit 0.
46  */
47 struct clk_pllv3 {
48 	struct clk_hw	hw;
49 	void __iomem	*base;
50 	u32		power_bit;
51 	bool		powerup_set;
52 	u32		div_mask;
53 	u32		div_shift;
54 	unsigned long	ref_clock;
55 	u32		num_offset;
56 	u32		denom_offset;
57 };
58 
59 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
60 
clk_pllv3_wait_lock(struct clk_pllv3 * pll)61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
62 {
63 	u32 val = readl_relaxed(pll->base) & pll->power_bit;
64 
65 	/* No need to wait for lock when pll is not powered up */
66 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
67 		return 0;
68 
69 	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
70 					  500, PLL_LOCK_TIMEOUT);
71 }
72 
clk_pllv3_prepare(struct clk_hw * hw)73 static int clk_pllv3_prepare(struct clk_hw *hw)
74 {
75 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
76 	u32 val;
77 
78 	val = readl_relaxed(pll->base);
79 	if (pll->powerup_set)
80 		val |= pll->power_bit;
81 	else
82 		val &= ~pll->power_bit;
83 	writel_relaxed(val, pll->base);
84 
85 	return clk_pllv3_wait_lock(pll);
86 }
87 
clk_pllv3_unprepare(struct clk_hw * hw)88 static void clk_pllv3_unprepare(struct clk_hw *hw)
89 {
90 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
91 	u32 val;
92 
93 	val = readl_relaxed(pll->base);
94 	if (pll->powerup_set)
95 		val &= ~pll->power_bit;
96 	else
97 		val |= pll->power_bit;
98 	writel_relaxed(val, pll->base);
99 }
100 
clk_pllv3_is_prepared(struct clk_hw * hw)101 static int clk_pllv3_is_prepared(struct clk_hw *hw)
102 {
103 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
104 
105 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
106 		return 1;
107 
108 	return 0;
109 }
110 
clk_pllv3_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)111 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
112 					   unsigned long parent_rate)
113 {
114 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
115 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
116 
117 	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
118 }
119 
clk_pllv3_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)120 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
121 				 unsigned long *prate)
122 {
123 	unsigned long parent_rate = *prate;
124 
125 	return (rate >= parent_rate * 22) ? parent_rate * 22 :
126 					    parent_rate * 20;
127 }
128 
clk_pllv3_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)129 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
130 		unsigned long parent_rate)
131 {
132 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
133 	u32 val, div;
134 
135 	if (rate == parent_rate * 22)
136 		div = 1;
137 	else if (rate == parent_rate * 20)
138 		div = 0;
139 	else
140 		return -EINVAL;
141 
142 	val = readl_relaxed(pll->base);
143 	val &= ~(pll->div_mask << pll->div_shift);
144 	val |= (div << pll->div_shift);
145 	writel_relaxed(val, pll->base);
146 
147 	return clk_pllv3_wait_lock(pll);
148 }
149 
150 static const struct clk_ops clk_pllv3_ops = {
151 	.prepare	= clk_pllv3_prepare,
152 	.unprepare	= clk_pllv3_unprepare,
153 	.is_prepared	= clk_pllv3_is_prepared,
154 	.recalc_rate	= clk_pllv3_recalc_rate,
155 	.round_rate	= clk_pllv3_round_rate,
156 	.set_rate	= clk_pllv3_set_rate,
157 };
158 
clk_pllv3_sys_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)159 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
160 					       unsigned long parent_rate)
161 {
162 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
163 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
164 
165 	return parent_rate * div / 2;
166 }
167 
clk_pllv3_sys_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)168 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
169 				     unsigned long *prate)
170 {
171 	unsigned long parent_rate = *prate;
172 	unsigned long min_rate = parent_rate * 54 / 2;
173 	unsigned long max_rate = parent_rate * 108 / 2;
174 	u32 div;
175 
176 	if (rate > max_rate)
177 		rate = max_rate;
178 	else if (rate < min_rate)
179 		rate = min_rate;
180 	div = rate * 2 / parent_rate;
181 
182 	return parent_rate * div / 2;
183 }
184 
clk_pllv3_sys_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)185 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
186 		unsigned long parent_rate)
187 {
188 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
189 	unsigned long min_rate = parent_rate * 54 / 2;
190 	unsigned long max_rate = parent_rate * 108 / 2;
191 	u32 val, div;
192 
193 	if (rate < min_rate || rate > max_rate)
194 		return -EINVAL;
195 
196 	div = rate * 2 / parent_rate;
197 	val = readl_relaxed(pll->base);
198 	val &= ~pll->div_mask;
199 	val |= div;
200 	writel_relaxed(val, pll->base);
201 
202 	return clk_pllv3_wait_lock(pll);
203 }
204 
205 static const struct clk_ops clk_pllv3_sys_ops = {
206 	.prepare	= clk_pllv3_prepare,
207 	.unprepare	= clk_pllv3_unprepare,
208 	.is_prepared	= clk_pllv3_is_prepared,
209 	.recalc_rate	= clk_pllv3_sys_recalc_rate,
210 	.round_rate	= clk_pllv3_sys_round_rate,
211 	.set_rate	= clk_pllv3_sys_set_rate,
212 };
213 
clk_pllv3_av_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)214 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
215 					      unsigned long parent_rate)
216 {
217 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
218 	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
219 	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
220 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 	u64 temp64 = (u64)parent_rate;
222 
223 	temp64 *= mfn;
224 	do_div(temp64, mfd);
225 
226 	return parent_rate * div + (unsigned long)temp64;
227 }
228 
clk_pllv3_av_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)229 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
230 				    unsigned long *prate)
231 {
232 	unsigned long parent_rate = *prate;
233 	unsigned long min_rate = parent_rate * 27;
234 	unsigned long max_rate = parent_rate * 54;
235 	u32 div;
236 	u32 mfn, mfd = 1000000;
237 	u32 max_mfd = 0x3FFFFFFF;
238 	u64 temp64;
239 
240 	if (rate > max_rate)
241 		rate = max_rate;
242 	else if (rate < min_rate)
243 		rate = min_rate;
244 
245 	if (parent_rate <= max_mfd)
246 		mfd = parent_rate;
247 
248 	div = rate / parent_rate;
249 	temp64 = (u64) (rate - div * parent_rate);
250 	temp64 *= mfd;
251 	temp64 = div64_ul(temp64, parent_rate);
252 	mfn = temp64;
253 
254 	temp64 = (u64)parent_rate;
255 	temp64 *= mfn;
256 	do_div(temp64, mfd);
257 
258 	return parent_rate * div + (unsigned long)temp64;
259 }
260 
clk_pllv3_av_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)261 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
262 		unsigned long parent_rate)
263 {
264 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
265 	unsigned long min_rate = parent_rate * 27;
266 	unsigned long max_rate = parent_rate * 54;
267 	u32 val, div;
268 	u32 mfn, mfd = 1000000;
269 	u32 max_mfd = 0x3FFFFFFF;
270 	u64 temp64;
271 
272 	if (rate < min_rate || rate > max_rate)
273 		return -EINVAL;
274 
275 	if (parent_rate <= max_mfd)
276 		mfd = parent_rate;
277 
278 	div = rate / parent_rate;
279 	temp64 = (u64) (rate - div * parent_rate);
280 	temp64 *= mfd;
281 	temp64 = div64_ul(temp64, parent_rate);
282 	mfn = temp64;
283 
284 	val = readl_relaxed(pll->base);
285 	val &= ~pll->div_mask;
286 	val |= div;
287 	writel_relaxed(val, pll->base);
288 	writel_relaxed(mfn, pll->base + pll->num_offset);
289 	writel_relaxed(mfd, pll->base + pll->denom_offset);
290 
291 	return clk_pllv3_wait_lock(pll);
292 }
293 
294 static const struct clk_ops clk_pllv3_av_ops = {
295 	.prepare	= clk_pllv3_prepare,
296 	.unprepare	= clk_pllv3_unprepare,
297 	.is_prepared	= clk_pllv3_is_prepared,
298 	.recalc_rate	= clk_pllv3_av_recalc_rate,
299 	.round_rate	= clk_pllv3_av_round_rate,
300 	.set_rate	= clk_pllv3_av_set_rate,
301 };
302 
303 struct clk_pllv3_vf610_mf {
304 	u32 mfi;	/* integer part, can be 20 or 22 */
305 	u32 mfn;	/* numerator, 30-bit value */
306 	u32 mfd;	/* denominator, 30-bit value, must be less than mfn */
307 };
308 
clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,struct clk_pllv3_vf610_mf mf)309 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
310 		struct clk_pllv3_vf610_mf mf)
311 {
312 	u64 temp64;
313 
314 	temp64 = parent_rate;
315 	temp64 *= mf.mfn;
316 	do_div(temp64, mf.mfd);
317 
318 	return (parent_rate * mf.mfi) + temp64;
319 }
320 
clk_pllv3_vf610_rate_to_mf(unsigned long parent_rate,unsigned long rate)321 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
322 		unsigned long parent_rate, unsigned long rate)
323 {
324 	struct clk_pllv3_vf610_mf mf;
325 	u64 temp64;
326 
327 	mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
328 	mf.mfd = 0x3fffffff;	/* use max supported value for best accuracy */
329 
330 	if (rate <= parent_rate * mf.mfi)
331 		mf.mfn = 0;
332 	else if (rate >= parent_rate * (mf.mfi + 1))
333 		mf.mfn = mf.mfd - 1;
334 	else {
335 		/* rate = parent_rate * (mfi + mfn/mfd) */
336 		temp64 = rate - parent_rate * mf.mfi;
337 		temp64 *= mf.mfd;
338 		temp64 = div64_ul(temp64, parent_rate);
339 		mf.mfn = temp64;
340 	}
341 
342 	return mf;
343 }
344 
clk_pllv3_vf610_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)345 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
346 					      unsigned long parent_rate)
347 {
348 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
349 	struct clk_pllv3_vf610_mf mf;
350 
351 	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
352 	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
353 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
354 
355 	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
356 }
357 
clk_pllv3_vf610_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)358 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
359 				    unsigned long *prate)
360 {
361 	struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
362 
363 	return clk_pllv3_vf610_mf_to_rate(*prate, mf);
364 }
365 
clk_pllv3_vf610_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)366 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
367 		unsigned long parent_rate)
368 {
369 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
370 	struct clk_pllv3_vf610_mf mf =
371 			clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
372 	u32 val;
373 
374 	val = readl_relaxed(pll->base);
375 	if (mf.mfi == 20)
376 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */
377 	else
378 		val |= pll->div_mask;	/* set bit for mfi=22 */
379 	writel_relaxed(val, pll->base);
380 
381 	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
382 	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
383 
384 	return clk_pllv3_wait_lock(pll);
385 }
386 
387 static const struct clk_ops clk_pllv3_vf610_ops = {
388 	.prepare	= clk_pllv3_prepare,
389 	.unprepare	= clk_pllv3_unprepare,
390 	.is_prepared	= clk_pllv3_is_prepared,
391 	.recalc_rate	= clk_pllv3_vf610_recalc_rate,
392 	.round_rate	= clk_pllv3_vf610_round_rate,
393 	.set_rate	= clk_pllv3_vf610_set_rate,
394 };
395 
clk_pllv3_enet_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)396 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
397 						unsigned long parent_rate)
398 {
399 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
400 
401 	return pll->ref_clock;
402 }
403 
404 static const struct clk_ops clk_pllv3_enet_ops = {
405 	.prepare	= clk_pllv3_prepare,
406 	.unprepare	= clk_pllv3_unprepare,
407 	.is_prepared	= clk_pllv3_is_prepared,
408 	.recalc_rate	= clk_pllv3_enet_recalc_rate,
409 };
410 
imx_clk_hw_pllv3(enum imx_pllv3_type type,const char * name,const char * parent_name,void __iomem * base,u32 div_mask)411 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
412 			  const char *parent_name, void __iomem *base,
413 			  u32 div_mask)
414 {
415 	struct clk_pllv3 *pll;
416 	const struct clk_ops *ops;
417 	struct clk_hw *hw;
418 	struct clk_init_data init;
419 	int ret;
420 
421 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
422 	if (!pll)
423 		return ERR_PTR(-ENOMEM);
424 
425 	pll->power_bit = BM_PLL_POWER;
426 	pll->num_offset = PLL_NUM_OFFSET;
427 	pll->denom_offset = PLL_DENOM_OFFSET;
428 
429 	switch (type) {
430 	case IMX_PLLV3_SYS:
431 		ops = &clk_pllv3_sys_ops;
432 		break;
433 	case IMX_PLLV3_SYS_VF610:
434 		ops = &clk_pllv3_vf610_ops;
435 		pll->num_offset = PLL_VF610_NUM_OFFSET;
436 		pll->denom_offset = PLL_VF610_DENOM_OFFSET;
437 		break;
438 	case IMX_PLLV3_USB_VF610:
439 		pll->div_shift = 1;
440 		fallthrough;
441 	case IMX_PLLV3_USB:
442 		ops = &clk_pllv3_ops;
443 		pll->powerup_set = true;
444 		break;
445 	case IMX_PLLV3_AV_IMX7:
446 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
447 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
448 		fallthrough;
449 	case IMX_PLLV3_AV:
450 		ops = &clk_pllv3_av_ops;
451 		break;
452 	case IMX_PLLV3_ENET_IMX7:
453 		pll->power_bit = IMX7_ENET_PLL_POWER;
454 		pll->ref_clock = 1000000000;
455 		ops = &clk_pllv3_enet_ops;
456 		break;
457 	case IMX_PLLV3_ENET:
458 		pll->ref_clock = 500000000;
459 		ops = &clk_pllv3_enet_ops;
460 		break;
461 	case IMX_PLLV3_DDR_IMX7:
462 		pll->power_bit = IMX7_DDR_PLL_POWER;
463 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
464 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
465 		ops = &clk_pllv3_av_ops;
466 		break;
467 	default:
468 		ops = &clk_pllv3_ops;
469 	}
470 	pll->base = base;
471 	pll->div_mask = div_mask;
472 
473 	init.name = name;
474 	init.ops = ops;
475 	init.flags = 0;
476 	init.parent_names = &parent_name;
477 	init.num_parents = 1;
478 
479 	pll->hw.init = &init;
480 	hw = &pll->hw;
481 
482 	ret = clk_hw_register(NULL, hw);
483 	if (ret) {
484 		kfree(pll);
485 		return ERR_PTR(ret);
486 	}
487 
488 	return hw;
489 }
490 EXPORT_SYMBOL_GPL(imx_clk_hw_pllv3);
491