1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63
64 extern const struct net_device_ops mlx5e_netdev_ops;
65 struct page_pool;
66
67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
68 #define MLX5E_METADATA_ETHER_LEN 8
69
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
71
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
74
75 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
88
89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
95
96 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
97 * These are theoretical maximums, which can be further restricted by
98 * capabilities. These values are used for static resource allocations and
99 * sanity checks.
100 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
101 * size actually used at runtime, but it's not a problem when calculating static
102 * array sizes.
103 */
104 #define MLX5_UMR_MAX_FLEX_SPACE \
105 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
106 MLX5_UMR_FLEX_ALIGNMENT))
107 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
108 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
109
110 #define MLX5E_MAX_RQ_NUM_MTTS \
111 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
112 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
113 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
114
115 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
116 #define MLX5E_LOG_MAX_RX_WQE_BULK \
117 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
118
119 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
120 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
121 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
122
123 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
124 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
125 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
126
127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
128
129 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
130 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
131
132 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
135 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
138 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
140
141 #define MLX5E_MIN_NUM_CHANNELS 0x1
142 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
143 #define MLX5E_TX_CQ_POLL_BUDGET 128
144 #define MLX5E_TX_XSK_POLL_BUDGET 64
145 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
146
147 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\
148 (sizeof(struct mlx5e_umr_wqe) +\
149 (sizeof(struct mlx5_klm) * (sgl_len)))
150
151 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \
152 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB))
153
154 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\
155 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS))
156
157 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\
158 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm))
159
160 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
161 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT)
162
163 #define MLX5E_MAX_KLM_PER_WQE(mdev) \
164 MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev))
165
166 #define mlx5e_state_dereference(priv, p) \
167 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
168
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)169 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
170 {
171 if (mlx5_lag_is_lacp_owner(mdev))
172 return 1;
173
174 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
175 }
176
mlx5_min_rx_wqes(int wq_type,u32 wq_size)177 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
178 {
179 switch (wq_type) {
180 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
181 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
182 wq_size / 2);
183 default:
184 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
185 wq_size / 2);
186 }
187 }
188
189 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)190 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
191 {
192 return is_kdump_kernel() ?
193 MLX5E_MIN_NUM_CHANNELS :
194 min_t(int, mlx5_comp_vectors_max(mdev), MLX5E_MAX_NUM_CHANNELS);
195 }
196
197 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
198 * bytes units. Driver hardens the limitation to 1KB (16
199 * WQEBBs), unless firmware capability is stricter.
200 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)201 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
202 {
203 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
204
205 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
206 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
207 }
208
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)209 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
210 {
211 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
212 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
213 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
214 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
215 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
216 * cache-aligned.
217 */
218 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
219
220 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
221 #if L1_CACHE_BYTES >= 128
222 wqebbs = ALIGN_DOWN(wqebbs, 2);
223 #endif
224 return wqebbs;
225 }
226
227 struct mlx5e_tx_wqe {
228 struct mlx5_wqe_ctrl_seg ctrl;
229 struct mlx5_wqe_eth_seg eth;
230 struct mlx5_wqe_data_seg data[];
231 };
232
233 struct mlx5e_rx_wqe_ll {
234 struct mlx5_wqe_srq_next_seg next;
235 struct mlx5_wqe_data_seg data[];
236 };
237
238 struct mlx5e_rx_wqe_cyc {
239 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
240 };
241
242 struct mlx5e_umr_wqe {
243 struct mlx5_wqe_ctrl_seg ctrl;
244 struct mlx5_wqe_umr_ctrl_seg uctrl;
245 struct mlx5_mkey_seg mkc;
246 union {
247 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
248 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
249 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
250 };
251 };
252
253 enum mlx5e_priv_flag {
254 MLX5E_PFLAG_RX_CQE_BASED_MODER,
255 MLX5E_PFLAG_TX_CQE_BASED_MODER,
256 MLX5E_PFLAG_RX_CQE_COMPRESS,
257 MLX5E_PFLAG_RX_STRIDING_RQ,
258 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
259 MLX5E_PFLAG_XDP_TX_MPWQE,
260 MLX5E_PFLAG_SKB_TX_MPWQE,
261 MLX5E_PFLAG_TX_PORT_TS,
262 MLX5E_NUM_PFLAGS, /* Keep last */
263 };
264
265 #define MLX5E_SET_PFLAG(params, pflag, enable) \
266 do { \
267 if (enable) \
268 (params)->pflags |= BIT(pflag); \
269 else \
270 (params)->pflags &= ~(BIT(pflag)); \
271 } while (0)
272
273 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
274
275 enum packet_merge {
276 MLX5E_PACKET_MERGE_NONE,
277 MLX5E_PACKET_MERGE_LRO,
278 MLX5E_PACKET_MERGE_SHAMPO,
279 };
280
281 struct mlx5e_packet_merge_param {
282 enum packet_merge type;
283 u32 timeout;
284 struct {
285 u8 match_criteria_type;
286 u8 alignment_granularity;
287 } shampo;
288 };
289
290 struct mlx5e_params {
291 u8 log_sq_size;
292 u8 rq_wq_type;
293 u8 log_rq_mtu_frames;
294 u16 num_channels;
295 struct {
296 u16 mode;
297 u8 num_tc;
298 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
299 struct {
300 u64 max_rate[TC_MAX_QUEUE];
301 u32 hw_id[TC_MAX_QUEUE];
302 } channel;
303 } mqprio;
304 bool rx_cqe_compress_def;
305 struct dim_cq_moder rx_cq_moderation;
306 struct dim_cq_moder tx_cq_moderation;
307 struct mlx5e_packet_merge_param packet_merge;
308 u8 tx_min_inline_mode;
309 bool vlan_strip_disable;
310 bool scatter_fcs_en;
311 bool rx_dim_enabled;
312 bool tx_dim_enabled;
313 u32 pflags;
314 struct bpf_prog *xdp_prog;
315 struct mlx5e_xsk *xsk;
316 unsigned int sw_mtu;
317 int hard_mtu;
318 bool ptp_rx;
319 __be32 terminate_lkey_be;
320 };
321
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)322 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
323 {
324 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
325 params->mqprio.num_tc : 1;
326 }
327
328 /* Keep this enum consistent with the corresponding strings array
329 * declared in en/reporter_rx.c
330 */
331 enum {
332 MLX5E_RQ_STATE_ENABLED = 0,
333 MLX5E_RQ_STATE_RECOVERING,
334 MLX5E_RQ_STATE_DIM,
335 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
336 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
337 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
338 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
339 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
340 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
341 MLX5E_NUM_RQ_STATES, /* Must be kept last */
342 };
343
344 struct mlx5e_cq {
345 /* data path - accessed per cqe */
346 struct mlx5_cqwq wq;
347
348 /* data path - accessed per napi poll */
349 u16 event_ctr;
350 struct napi_struct *napi;
351 struct mlx5_core_cq mcq;
352 struct mlx5e_ch_stats *ch_stats;
353
354 /* control */
355 struct net_device *netdev;
356 struct mlx5_core_dev *mdev;
357 struct mlx5e_priv *priv;
358 struct mlx5_wq_ctrl wq_ctrl;
359 } ____cacheline_aligned_in_smp;
360
361 struct mlx5e_cq_decomp {
362 /* cqe decompression */
363 struct mlx5_cqe64 title;
364 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
365 u8 mini_arr_idx;
366 u16 left;
367 u16 wqe_counter;
368 bool last_cqe_title;
369 } ____cacheline_aligned_in_smp;
370
371 enum mlx5e_dma_map_type {
372 MLX5E_DMA_MAP_SINGLE,
373 MLX5E_DMA_MAP_PAGE
374 };
375
376 struct mlx5e_sq_dma {
377 dma_addr_t addr;
378 u32 size;
379 enum mlx5e_dma_map_type type;
380 };
381
382 /* Keep this enum consistent with with the corresponding strings array
383 * declared in en/reporter_tx.c
384 */
385 enum {
386 MLX5E_SQ_STATE_ENABLED = 0,
387 MLX5E_SQ_STATE_MPWQE,
388 MLX5E_SQ_STATE_RECOVERING,
389 MLX5E_SQ_STATE_IPSEC,
390 MLX5E_SQ_STATE_DIM,
391 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
392 MLX5E_SQ_STATE_PENDING_XSK_TX,
393 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
394 MLX5E_SQ_STATE_XDP_MULTIBUF,
395 MLX5E_NUM_SQ_STATES, /* Must be kept last */
396 };
397
398 struct mlx5e_tx_mpwqe {
399 /* Current MPWQE session */
400 struct mlx5e_tx_wqe *wqe;
401 u32 bytes_count;
402 u8 ds_count;
403 u8 pkt_count;
404 u8 inline_on;
405 };
406
407 struct mlx5e_skb_fifo {
408 struct sk_buff **fifo;
409 u16 *pc;
410 u16 *cc;
411 u16 mask;
412 };
413
414 struct mlx5e_ptpsq;
415
416 struct mlx5e_txqsq {
417 /* data path */
418
419 /* dirtied @completion */
420 u16 cc;
421 u16 skb_fifo_cc;
422 u32 dma_fifo_cc;
423 struct dim dim; /* Adaptive Moderation */
424
425 /* dirtied @xmit */
426 u16 pc ____cacheline_aligned_in_smp;
427 u16 skb_fifo_pc;
428 u32 dma_fifo_pc;
429 struct mlx5e_tx_mpwqe mpwqe;
430
431 struct mlx5e_cq cq;
432
433 /* read only */
434 struct mlx5_wq_cyc wq;
435 u32 dma_fifo_mask;
436 struct mlx5e_sq_stats *stats;
437 struct {
438 struct mlx5e_sq_dma *dma_fifo;
439 struct mlx5e_skb_fifo skb_fifo;
440 struct mlx5e_tx_wqe_info *wqe_info;
441 } db;
442 void __iomem *uar_map;
443 struct netdev_queue *txq;
444 u32 sqn;
445 u16 stop_room;
446 u8 max_sq_mpw_wqebbs;
447 u8 min_inline_mode;
448 struct device *pdev;
449 __be32 mkey_be;
450 unsigned long state;
451 unsigned int hw_mtu;
452 struct mlx5_clock *clock;
453 struct net_device *netdev;
454 struct mlx5_core_dev *mdev;
455 struct mlx5e_channel *channel;
456 struct mlx5e_priv *priv;
457
458 /* control path */
459 struct mlx5_wq_ctrl wq_ctrl;
460 int ch_ix;
461 int txq_ix;
462 u32 rate_limit;
463 struct work_struct recover_work;
464 struct mlx5e_ptpsq *ptpsq;
465 cqe_ts_to_ns ptp_cyc2time;
466 } ____cacheline_aligned_in_smp;
467
468 struct mlx5e_xdp_info_fifo {
469 union mlx5e_xdp_info *xi;
470 u32 *cc;
471 u32 *pc;
472 u32 mask;
473 };
474
475 struct mlx5e_xdpsq;
476 struct mlx5e_xmit_data;
477 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
478 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
479 struct mlx5e_xmit_data *,
480 int);
481
482 struct mlx5e_xdpsq {
483 /* data path */
484
485 /* dirtied @completion */
486 u32 xdpi_fifo_cc;
487 u16 cc;
488
489 /* dirtied @xmit */
490 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
491 u16 pc;
492 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
493 struct mlx5e_tx_mpwqe mpwqe;
494
495 struct mlx5e_cq cq;
496
497 /* read only */
498 struct xsk_buff_pool *xsk_pool;
499 struct mlx5_wq_cyc wq;
500 struct mlx5e_xdpsq_stats *stats;
501 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
502 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
503 struct {
504 struct mlx5e_xdp_wqe_info *wqe_info;
505 struct mlx5e_xdp_info_fifo xdpi_fifo;
506 } db;
507 void __iomem *uar_map;
508 u32 sqn;
509 struct device *pdev;
510 __be32 mkey_be;
511 u16 stop_room;
512 u8 max_sq_mpw_wqebbs;
513 u8 min_inline_mode;
514 unsigned long state;
515 unsigned int hw_mtu;
516
517 /* control path */
518 struct mlx5_wq_ctrl wq_ctrl;
519 struct mlx5e_channel *channel;
520 } ____cacheline_aligned_in_smp;
521
522 struct mlx5e_ktls_resync_resp;
523
524 struct mlx5e_icosq {
525 /* data path */
526 u16 cc;
527 u16 pc;
528
529 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
530 struct mlx5e_cq cq;
531
532 /* write@xmit, read@completion */
533 struct {
534 struct mlx5e_icosq_wqe_info *wqe_info;
535 } db;
536
537 /* read only */
538 struct mlx5_wq_cyc wq;
539 void __iomem *uar_map;
540 u32 sqn;
541 u16 reserved_room;
542 unsigned long state;
543 struct mlx5e_ktls_resync_resp *ktls_resync;
544
545 /* control path */
546 struct mlx5_wq_ctrl wq_ctrl;
547 struct mlx5e_channel *channel;
548
549 struct work_struct recover_work;
550 } ____cacheline_aligned_in_smp;
551
552 struct mlx5e_frag_page {
553 struct page *page;
554 u16 frags;
555 };
556
557 enum mlx5e_wqe_frag_flag {
558 MLX5E_WQE_FRAG_LAST_IN_PAGE,
559 MLX5E_WQE_FRAG_SKIP_RELEASE,
560 };
561
562 struct mlx5e_wqe_frag_info {
563 union {
564 struct mlx5e_frag_page *frag_page;
565 struct xdp_buff **xskp;
566 };
567 u32 offset;
568 u8 flags;
569 };
570
571 union mlx5e_alloc_units {
572 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
573 DECLARE_FLEX_ARRAY(struct page *, pages);
574 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
575 };
576
577 struct mlx5e_mpw_info {
578 u16 consumed_strides;
579 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
580 struct mlx5e_frag_page linear_page;
581 union mlx5e_alloc_units alloc_units;
582 };
583
584 #define MLX5E_MAX_RX_FRAGS 4
585
586 struct mlx5e_rq;
587 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
588 typedef struct sk_buff *
589 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
590 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
591 u32 head_offset, u32 page_idx);
592 typedef struct sk_buff *
593 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
594 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
595 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
596 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
597 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
598
599 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
600 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
601
602 enum mlx5e_rq_flag {
603 MLX5E_RQ_FLAG_XDP_XMIT,
604 MLX5E_RQ_FLAG_XDP_REDIRECT,
605 };
606
607 struct mlx5e_rq_frag_info {
608 int frag_size;
609 int frag_stride;
610 };
611
612 struct mlx5e_rq_frags_info {
613 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
614 u8 num_frags;
615 u8 log_num_frags;
616 u16 wqe_bulk;
617 u16 refill_unit;
618 u8 wqe_index_mask;
619 };
620
621 struct mlx5e_dma_info {
622 dma_addr_t addr;
623 union {
624 struct mlx5e_frag_page *frag_page;
625 struct page *page;
626 };
627 };
628
629 struct mlx5e_shampo_hd {
630 u32 mkey;
631 struct mlx5e_dma_info *info;
632 struct mlx5e_frag_page *pages;
633 u16 curr_page_index;
634 u16 hd_per_wq;
635 u16 hd_per_wqe;
636 unsigned long *bitmap;
637 u16 pi;
638 u16 ci;
639 __be32 key;
640 u64 last_addr;
641 };
642
643 struct mlx5e_hw_gro_data {
644 struct sk_buff *skb;
645 struct flow_keys fk;
646 int second_ip_id;
647 };
648
649 enum mlx5e_mpwrq_umr_mode {
650 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
651 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
652 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
653 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
654 };
655
656 struct mlx5e_rq {
657 /* data path */
658 union {
659 struct {
660 struct mlx5_wq_cyc wq;
661 struct mlx5e_wqe_frag_info *frags;
662 union mlx5e_alloc_units *alloc_units;
663 struct mlx5e_rq_frags_info info;
664 mlx5e_fp_skb_from_cqe skb_from_cqe;
665 } wqe;
666 struct {
667 struct mlx5_wq_ll wq;
668 struct mlx5e_umr_wqe umr_wqe;
669 struct mlx5e_mpw_info *info;
670 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
671 __be32 umr_mkey_be;
672 u16 num_strides;
673 u16 actual_wq_head;
674 u8 log_stride_sz;
675 u8 umr_in_progress;
676 u8 umr_last_bulk;
677 u8 umr_completed;
678 u8 min_wqe_bulk;
679 u8 page_shift;
680 u8 pages_per_wqe;
681 u8 umr_wqebbs;
682 u8 mtts_per_wqe;
683 u8 umr_mode;
684 struct mlx5e_shampo_hd *shampo;
685 } mpwqe;
686 };
687 struct {
688 u16 headroom;
689 u32 frame0_sz;
690 u8 map_dir; /* dma map direction */
691 } buff;
692
693 struct device *pdev;
694 struct net_device *netdev;
695 struct mlx5e_rq_stats *stats;
696 struct mlx5e_cq cq;
697 struct mlx5e_cq_decomp cqd;
698 struct hwtstamp_config *tstamp;
699 struct mlx5_clock *clock;
700 struct mlx5e_icosq *icosq;
701 struct mlx5e_priv *priv;
702
703 struct mlx5e_hw_gro_data *hw_gro_data;
704
705 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
706 mlx5e_fp_post_rx_wqes post_wqes;
707 mlx5e_fp_dealloc_wqe dealloc_wqe;
708
709 unsigned long state;
710 int ix;
711 unsigned int hw_mtu;
712
713 struct dim dim; /* Dynamic Interrupt Moderation */
714
715 /* XDP */
716 struct bpf_prog __rcu *xdp_prog;
717 struct mlx5e_xdpsq *xdpsq;
718 DECLARE_BITMAP(flags, 8);
719 struct page_pool *page_pool;
720
721 /* AF_XDP zero-copy */
722 struct xsk_buff_pool *xsk_pool;
723
724 struct work_struct recover_work;
725
726 /* control */
727 struct mlx5_wq_ctrl wq_ctrl;
728 __be32 mkey_be;
729 u8 wq_type;
730 u32 rqn;
731 struct mlx5_core_dev *mdev;
732 struct mlx5e_channel *channel;
733 struct mlx5e_dma_info wqe_overflow;
734
735 /* XDP read-mostly */
736 struct xdp_rxq_info xdp_rxq;
737 cqe_ts_to_ns ptp_cyc2time;
738 } ____cacheline_aligned_in_smp;
739
740 enum mlx5e_channel_state {
741 MLX5E_CHANNEL_STATE_XSK,
742 MLX5E_CHANNEL_NUM_STATES
743 };
744
745 struct mlx5e_channel {
746 /* data path */
747 struct mlx5e_rq rq;
748 struct mlx5e_xdpsq rq_xdpsq;
749 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
750 struct mlx5e_icosq icosq; /* internal control operations */
751 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
752 bool xdp;
753 struct napi_struct napi;
754 struct device *pdev;
755 struct net_device *netdev;
756 __be32 mkey_be;
757 u16 qos_sqs_size;
758 u8 num_tc;
759 u8 lag_port;
760
761 /* XDP_REDIRECT */
762 struct mlx5e_xdpsq xdpsq;
763
764 /* AF_XDP zero-copy */
765 struct mlx5e_rq xskrq;
766 struct mlx5e_xdpsq xsksq;
767
768 /* Async ICOSQ */
769 struct mlx5e_icosq async_icosq;
770 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
771 spinlock_t async_icosq_lock;
772
773 /* data path - accessed per napi poll */
774 const struct cpumask *aff_mask;
775 struct mlx5e_ch_stats *stats;
776
777 /* control */
778 struct mlx5e_priv *priv;
779 struct mlx5_core_dev *mdev;
780 struct hwtstamp_config *tstamp;
781 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
782 int ix;
783 int cpu;
784 /* Sync between icosq recovery and XSK enable/disable. */
785 struct mutex icosq_recovery_lock;
786 };
787
788 struct mlx5e_ptp;
789
790 struct mlx5e_channels {
791 struct mlx5e_channel **c;
792 struct mlx5e_ptp *ptp;
793 unsigned int num;
794 struct mlx5e_params params;
795 };
796
797 struct mlx5e_channel_stats {
798 struct mlx5e_ch_stats ch;
799 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
800 struct mlx5e_rq_stats rq;
801 struct mlx5e_rq_stats xskrq;
802 struct mlx5e_xdpsq_stats rq_xdpsq;
803 struct mlx5e_xdpsq_stats xdpsq;
804 struct mlx5e_xdpsq_stats xsksq;
805 } ____cacheline_aligned_in_smp;
806
807 struct mlx5e_ptp_stats {
808 struct mlx5e_ch_stats ch;
809 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
810 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
811 struct mlx5e_rq_stats rq;
812 } ____cacheline_aligned_in_smp;
813
814 enum {
815 MLX5E_STATE_OPENED,
816 MLX5E_STATE_DESTROYING,
817 MLX5E_STATE_XDP_TX_ENABLED,
818 MLX5E_STATE_XDP_ACTIVE,
819 MLX5E_STATE_CHANNELS_ACTIVE,
820 };
821
822 struct mlx5e_modify_sq_param {
823 int curr_state;
824 int next_state;
825 int rl_update;
826 int rl_index;
827 bool qos_update;
828 u16 qos_queue_group_id;
829 };
830
831 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
832 struct mlx5e_hv_vhca_stats_agent {
833 struct mlx5_hv_vhca_agent *agent;
834 struct delayed_work work;
835 u16 delay;
836 void *buf;
837 };
838 #endif
839
840 struct mlx5e_xsk {
841 /* XSK buffer pools are stored separately from channels,
842 * because we don't want to lose them when channels are
843 * recreated. The kernel also stores buffer pool, but it doesn't
844 * distinguish between zero-copy and non-zero-copy UMEMs, so
845 * rely on our mechanism.
846 */
847 struct xsk_buff_pool **pools;
848 u16 refcnt;
849 bool ever_used;
850 };
851
852 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
853 * initialized, and used where we can't allocate them because that functions
854 * must not fail. Use with care and make sure the same variable is not used
855 * simultaneously by multiple users.
856 */
857 struct mlx5e_scratchpad {
858 cpumask_var_t cpumask;
859 };
860
861 struct mlx5e_trap;
862 struct mlx5e_htb;
863
864 struct mlx5e_priv {
865 /* priv data path fields - start */
866 struct mlx5e_selq selq;
867 struct mlx5e_txqsq **txq2sq;
868 #ifdef CONFIG_MLX5_CORE_EN_DCB
869 struct mlx5e_dcbx_dp dcbx_dp;
870 #endif
871 /* priv data path fields - end */
872
873 unsigned long state;
874 struct mutex state_lock; /* Protects Interface state */
875 struct mlx5e_rq drop_rq;
876
877 struct mlx5e_channels channels;
878 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
879 struct mlx5e_rx_res *rx_res;
880 u32 *tx_rates;
881
882 struct mlx5e_flow_steering *fs;
883
884 struct workqueue_struct *wq;
885 struct work_struct update_carrier_work;
886 struct work_struct set_rx_mode_work;
887 struct work_struct tx_timeout_work;
888 struct work_struct update_stats_work;
889 struct work_struct monitor_counters_work;
890 struct mlx5_nb monitor_counters_nb;
891
892 struct mlx5_core_dev *mdev;
893 struct net_device *netdev;
894 struct mlx5e_trap *en_trap;
895 struct mlx5e_stats stats;
896 struct mlx5e_channel_stats **channel_stats;
897 struct mlx5e_channel_stats trap_stats;
898 struct mlx5e_ptp_stats ptp_stats;
899 struct mlx5e_sq_stats **htb_qos_sq_stats;
900 u16 htb_max_qos_sqs;
901 u16 stats_nch;
902 u16 max_nch;
903 u8 max_opened_tc;
904 bool tx_ptp_opened;
905 bool rx_ptp_opened;
906 struct hwtstamp_config tstamp;
907 u16 q_counter;
908 u16 drop_rq_q_counter;
909 struct notifier_block events_nb;
910 struct notifier_block blocking_events_nb;
911
912 struct udp_tunnel_nic_info nic_info;
913 #ifdef CONFIG_MLX5_CORE_EN_DCB
914 struct mlx5e_dcbx dcbx;
915 #endif
916
917 const struct mlx5e_profile *profile;
918 void *ppriv;
919 #ifdef CONFIG_MLX5_MACSEC
920 struct mlx5e_macsec *macsec;
921 #endif
922 #ifdef CONFIG_MLX5_EN_IPSEC
923 struct mlx5e_ipsec *ipsec;
924 #endif
925 #ifdef CONFIG_MLX5_EN_TLS
926 struct mlx5e_tls *tls;
927 #endif
928 struct devlink_health_reporter *tx_reporter;
929 struct devlink_health_reporter *rx_reporter;
930 struct mlx5e_xsk xsk;
931 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
932 struct mlx5e_hv_vhca_stats_agent stats_agent;
933 #endif
934 struct mlx5e_scratchpad scratchpad;
935 struct mlx5e_htb *htb;
936 struct mlx5e_mqprio_rl *mqprio_rl;
937 struct dentry *dfs_root;
938 };
939
940 struct mlx5e_dev {
941 struct mlx5e_priv *priv;
942 struct devlink_port dl_port;
943 };
944
945 struct mlx5e_rx_handlers {
946 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
947 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
948 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
949 };
950
951 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
952
953 enum mlx5e_profile_feature {
954 MLX5E_PROFILE_FEATURE_PTP_RX,
955 MLX5E_PROFILE_FEATURE_PTP_TX,
956 MLX5E_PROFILE_FEATURE_QOS_HTB,
957 MLX5E_PROFILE_FEATURE_FS_VLAN,
958 MLX5E_PROFILE_FEATURE_FS_TC,
959 };
960
961 struct mlx5e_profile {
962 int (*init)(struct mlx5_core_dev *mdev,
963 struct net_device *netdev);
964 void (*cleanup)(struct mlx5e_priv *priv);
965 int (*init_rx)(struct mlx5e_priv *priv);
966 void (*cleanup_rx)(struct mlx5e_priv *priv);
967 int (*init_tx)(struct mlx5e_priv *priv);
968 void (*cleanup_tx)(struct mlx5e_priv *priv);
969 void (*enable)(struct mlx5e_priv *priv);
970 void (*disable)(struct mlx5e_priv *priv);
971 int (*update_rx)(struct mlx5e_priv *priv);
972 void (*update_stats)(struct mlx5e_priv *priv);
973 void (*update_carrier)(struct mlx5e_priv *priv);
974 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
975 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
976 mlx5e_stats_grp_t *stats_grps;
977 const struct mlx5e_rx_handlers *rx_handlers;
978 int max_tc;
979 u32 features;
980 };
981
982 #define mlx5e_profile_feature_cap(profile, feature) \
983 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
984
985 void mlx5e_build_ptys2ethtool_map(void);
986
987 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
988 enum mlx5e_mpwrq_umr_mode umr_mode);
989
990 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close);
991 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
992 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
993
994 int mlx5e_self_test_num(struct mlx5e_priv *priv);
995 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
996 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
997 u64 *buf);
998 void mlx5e_set_rx_mode_work(struct work_struct *work);
999
1000 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1001 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1002 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1003
1004 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1005 u16 vid);
1006 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1007 u16 vid);
1008 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1009
1010 struct mlx5e_xsk_param;
1011
1012 struct mlx5e_rq_param;
1013 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1014 struct mlx5e_xsk_param *xsk, int node,
1015 struct mlx5e_rq *rq);
1016 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1017 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1018 void mlx5e_close_rq(struct mlx5e_rq *rq);
1019 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
1020 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1021
1022 struct mlx5e_sq_param;
1023 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1024 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1025 struct mlx5e_xdpsq *sq, bool is_redirect);
1026 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1027
1028 struct mlx5e_create_cq_param {
1029 struct napi_struct *napi;
1030 struct mlx5e_ch_stats *ch_stats;
1031 int node;
1032 int ix;
1033 };
1034
1035 struct mlx5e_cq_param;
1036 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1037 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1038 struct mlx5e_cq *cq);
1039 void mlx5e_close_cq(struct mlx5e_cq *cq);
1040
1041 int mlx5e_open_locked(struct net_device *netdev);
1042 int mlx5e_close_locked(struct net_device *netdev);
1043
1044 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1045 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1046
1047 int mlx5e_open_channels(struct mlx5e_priv *priv,
1048 struct mlx5e_channels *chs);
1049 void mlx5e_close_channels(struct mlx5e_channels *chs);
1050
1051 /* Function pointer to be used to modify HW or kernel settings while
1052 * switching channels
1053 */
1054 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1055 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1056 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1057 { \
1058 return fn(priv); \
1059 }
1060 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1061 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1062 struct mlx5e_params *new_params,
1063 mlx5e_fp_preactivate preactivate,
1064 void *context, bool reset);
1065 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1066 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1067 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1068 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1069 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1070
1071 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1072 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1073 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1074 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1075 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1076
1077 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1078 struct mlx5e_modify_sq_param *p);
1079 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1080 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1081 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1082 struct mlx5e_sq_stats *sq_stats);
1083 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1084 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1085 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1086 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1088 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1089 struct mlx5e_create_sq_param;
1090 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1091 struct mlx5e_sq_param *param,
1092 struct mlx5e_create_sq_param *csp,
1093 u16 qos_queue_group_id,
1094 u32 *sqn);
1095 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1096 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1097
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1098 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1099 {
1100 return MLX5_CAP_ETH(mdev, swp) &&
1101 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1102 }
1103
1104 extern const struct ethtool_ops mlx5e_ethtool_ops;
1105
1106 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1107 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1108 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1109 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1110 bool enable_mc_lb);
1111 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1112
1113 /* common netdev helpers */
1114 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1115 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1116 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1117 struct mlx5e_rq *drop_rq);
1118 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1119
1120 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1121 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1122
1123 int mlx5e_create_tises(struct mlx5e_priv *priv);
1124 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1125 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1126 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1127 int mlx5e_close(struct net_device *netdev);
1128 int mlx5e_open(struct net_device *netdev);
1129
1130 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1131
1132 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1133 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1134 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1135 mlx5e_fp_preactivate preactivate);
1136 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1137
1138 /* ethtool helpers */
1139 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1140 struct ethtool_drvinfo *drvinfo);
1141 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1142 uint32_t stringset, uint8_t *data);
1143 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1144 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1145 struct ethtool_stats *stats, u64 *data);
1146 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1147 struct ethtool_ringparam *param,
1148 struct kernel_ethtool_ringparam *kernel_param);
1149 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1150 struct ethtool_ringparam *param);
1151 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1152 struct ethtool_channels *ch);
1153 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1154 struct ethtool_channels *ch);
1155 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1156 struct ethtool_coalesce *coal,
1157 struct kernel_ethtool_coalesce *kernel_coal);
1158 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1159 struct ethtool_coalesce *coal,
1160 struct kernel_ethtool_coalesce *kernel_coal,
1161 struct netlink_ext_ack *extack);
1162 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1163 struct ethtool_link_ksettings *link_ksettings);
1164 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1165 const struct ethtool_link_ksettings *link_ksettings);
1166 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1167 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1168 const u8 hfunc);
1169 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1170 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1171 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1172 struct ethtool_ts_info *info);
1173 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1174 struct ethtool_flash *flash);
1175 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1176 struct ethtool_pauseparam *pauseparam);
1177 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1178 struct ethtool_pauseparam *pauseparam);
1179
1180 /* mlx5e generic netdev management API */
1181 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1182 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1183 {
1184 return !is_kdump_kernel() &&
1185 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1186 }
1187
1188 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1189 int mlx5e_priv_init(struct mlx5e_priv *priv,
1190 const struct mlx5e_profile *profile,
1191 struct net_device *netdev,
1192 struct mlx5_core_dev *mdev);
1193 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1194 struct net_device *
1195 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1196 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1197 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1198 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1199 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1200 const struct mlx5e_profile *new_profile, void *new_ppriv);
1201 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1202 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1203 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1204 void mlx5e_rx_dim_work(struct work_struct *work);
1205 void mlx5e_tx_dim_work(struct work_struct *work);
1206
1207 void mlx5e_set_xdp_feature(struct net_device *netdev);
1208 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1209 struct net_device *netdev,
1210 netdev_features_t features);
1211 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1212 #ifdef CONFIG_MLX5_ESWITCH
1213 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1214 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1215 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1216 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1217 #endif
1218 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1219 #endif /* __MLX5_EN_H__ */
1220