1 /*
2 * linux/drivers/video/amba-clcd.c
3 *
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 *
11 * ARM PrimeCell PL110 Color LCD Controller
12 */
13 #include <linux/amba/bus.h>
14 #include <linux/amba/clcd.h>
15 #include <linux/backlight.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/mm.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_graph.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <video/display_timing.h>
30 #include <video/of_display_timing.h>
31 #include <video/videomode.h>
32
33 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
34
35 /* This is limited to 16 characters when displayed by X startup */
36 static const char *clcd_name = "CLCD FB";
37
clcdfb_set_start(struct clcd_fb * fb)38 static inline void clcdfb_set_start(struct clcd_fb *fb)
39 {
40 unsigned long ustart = fb->fb.fix.smem_start;
41 unsigned long lstart;
42
43 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
44 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
45
46 writel(ustart, fb->regs + CLCD_UBAS);
47 writel(lstart, fb->regs + CLCD_LBAS);
48 }
49
clcdfb_disable(struct clcd_fb * fb)50 static void clcdfb_disable(struct clcd_fb *fb)
51 {
52 u32 val;
53
54 if (fb->board->disable)
55 fb->board->disable(fb);
56
57 if (fb->panel->backlight) {
58 fb->panel->backlight->props.power = FB_BLANK_POWERDOWN;
59 backlight_update_status(fb->panel->backlight);
60 }
61
62 val = readl(fb->regs + fb->off_cntl);
63 if (val & CNTL_LCDPWR) {
64 val &= ~CNTL_LCDPWR;
65 writel(val, fb->regs + fb->off_cntl);
66
67 msleep(20);
68 }
69 if (val & CNTL_LCDEN) {
70 val &= ~CNTL_LCDEN;
71 writel(val, fb->regs + fb->off_cntl);
72 }
73
74 /*
75 * Disable CLCD clock source.
76 */
77 if (fb->clk_enabled) {
78 fb->clk_enabled = false;
79 clk_disable(fb->clk);
80 }
81 }
82
clcdfb_enable(struct clcd_fb * fb,u32 cntl)83 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
84 {
85 /*
86 * Enable the CLCD clock source.
87 */
88 if (!fb->clk_enabled) {
89 fb->clk_enabled = true;
90 clk_enable(fb->clk);
91 }
92
93 /*
94 * Bring up by first enabling..
95 */
96 cntl |= CNTL_LCDEN;
97 writel(cntl, fb->regs + fb->off_cntl);
98
99 msleep(20);
100
101 /*
102 * and now apply power.
103 */
104 cntl |= CNTL_LCDPWR;
105 writel(cntl, fb->regs + fb->off_cntl);
106
107 /*
108 * Turn on backlight
109 */
110 if (fb->panel->backlight) {
111 fb->panel->backlight->props.power = FB_BLANK_UNBLANK;
112 backlight_update_status(fb->panel->backlight);
113 }
114
115 /*
116 * finally, enable the interface.
117 */
118 if (fb->board->enable)
119 fb->board->enable(fb);
120 }
121
122 static int
clcdfb_set_bitfields(struct clcd_fb * fb,struct fb_var_screeninfo * var)123 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
124 {
125 u32 caps;
126 int ret = 0;
127
128 if (fb->panel->caps && fb->board->caps)
129 caps = fb->panel->caps & fb->board->caps;
130 else {
131 /* Old way of specifying what can be used */
132 caps = fb->panel->cntl & CNTL_BGR ?
133 CLCD_CAP_BGR : CLCD_CAP_RGB;
134 /* But mask out 444 modes as they weren't supported */
135 caps &= ~CLCD_CAP_444;
136 }
137
138 /* Only TFT panels can do RGB888/BGR888 */
139 if (!(fb->panel->cntl & CNTL_LCDTFT))
140 caps &= ~CLCD_CAP_888;
141
142 memset(&var->transp, 0, sizeof(var->transp));
143
144 var->red.msb_right = 0;
145 var->green.msb_right = 0;
146 var->blue.msb_right = 0;
147
148 switch (var->bits_per_pixel) {
149 case 1:
150 case 2:
151 case 4:
152 case 8:
153 /* If we can't do 5551, reject */
154 caps &= CLCD_CAP_5551;
155 if (!caps) {
156 ret = -EINVAL;
157 break;
158 }
159
160 var->red.length = var->bits_per_pixel;
161 var->red.offset = 0;
162 var->green.length = var->bits_per_pixel;
163 var->green.offset = 0;
164 var->blue.length = var->bits_per_pixel;
165 var->blue.offset = 0;
166 break;
167
168 case 16:
169 /* If we can't do 444, 5551 or 565, reject */
170 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
171 ret = -EINVAL;
172 break;
173 }
174
175 /*
176 * Green length can be 4, 5 or 6 depending whether
177 * we're operating in 444, 5551 or 565 mode.
178 */
179 if (var->green.length == 4 && caps & CLCD_CAP_444)
180 caps &= CLCD_CAP_444;
181 if (var->green.length == 5 && caps & CLCD_CAP_5551)
182 caps &= CLCD_CAP_5551;
183 else if (var->green.length == 6 && caps & CLCD_CAP_565)
184 caps &= CLCD_CAP_565;
185 else {
186 /*
187 * PL110 officially only supports RGB555,
188 * but may be wired up to allow RGB565.
189 */
190 if (caps & CLCD_CAP_565) {
191 var->green.length = 6;
192 caps &= CLCD_CAP_565;
193 } else if (caps & CLCD_CAP_5551) {
194 var->green.length = 5;
195 caps &= CLCD_CAP_5551;
196 } else {
197 var->green.length = 4;
198 caps &= CLCD_CAP_444;
199 }
200 }
201
202 if (var->green.length >= 5) {
203 var->red.length = 5;
204 var->blue.length = 5;
205 } else {
206 var->red.length = 4;
207 var->blue.length = 4;
208 }
209 break;
210 case 32:
211 /* If we can't do 888, reject */
212 caps &= CLCD_CAP_888;
213 if (!caps) {
214 ret = -EINVAL;
215 break;
216 }
217
218 var->red.length = 8;
219 var->green.length = 8;
220 var->blue.length = 8;
221 break;
222 default:
223 ret = -EINVAL;
224 break;
225 }
226
227 /*
228 * >= 16bpp displays have separate colour component bitfields
229 * encoded in the pixel data. Calculate their position from
230 * the bitfield length defined above.
231 */
232 if (ret == 0 && var->bits_per_pixel >= 16) {
233 bool bgr, rgb;
234
235 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
236 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
237
238 if (!bgr && !rgb)
239 /*
240 * The requested format was not possible, try just
241 * our capabilities. One of BGR or RGB must be
242 * supported.
243 */
244 bgr = caps & CLCD_CAP_BGR;
245
246 if (bgr) {
247 var->blue.offset = 0;
248 var->green.offset = var->blue.offset + var->blue.length;
249 var->red.offset = var->green.offset + var->green.length;
250 } else {
251 var->red.offset = 0;
252 var->green.offset = var->red.offset + var->red.length;
253 var->blue.offset = var->green.offset + var->green.length;
254 }
255 }
256
257 return ret;
258 }
259
clcdfb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)260 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
261 {
262 struct clcd_fb *fb = to_clcd(info);
263 int ret = -EINVAL;
264
265 if (fb->board->check)
266 ret = fb->board->check(fb, var);
267
268 if (ret == 0 &&
269 var->xres_virtual * var->bits_per_pixel / 8 *
270 var->yres_virtual > fb->fb.fix.smem_len)
271 ret = -EINVAL;
272
273 if (ret == 0)
274 ret = clcdfb_set_bitfields(fb, var);
275
276 return ret;
277 }
278
clcdfb_set_par(struct fb_info * info)279 static int clcdfb_set_par(struct fb_info *info)
280 {
281 struct clcd_fb *fb = to_clcd(info);
282 struct clcd_regs regs;
283
284 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
285 fb->fb.var.bits_per_pixel / 8;
286
287 if (fb->fb.var.bits_per_pixel <= 8)
288 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
289 else
290 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
291
292 fb->board->decode(fb, ®s);
293
294 clcdfb_disable(fb);
295
296 writel(regs.tim0, fb->regs + CLCD_TIM0);
297 writel(regs.tim1, fb->regs + CLCD_TIM1);
298 writel(regs.tim2, fb->regs + CLCD_TIM2);
299 writel(regs.tim3, fb->regs + CLCD_TIM3);
300
301 clcdfb_set_start(fb);
302
303 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
304
305 fb->clcd_cntl = regs.cntl;
306
307 clcdfb_enable(fb, regs.cntl);
308
309 #ifdef DEBUG
310 printk(KERN_INFO
311 "CLCD: Registers set to\n"
312 " %08x %08x %08x %08x\n"
313 " %08x %08x %08x %08x\n",
314 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
315 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
316 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
317 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
318 #endif
319
320 return 0;
321 }
322
convert_bitfield(int val,struct fb_bitfield * bf)323 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
324 {
325 unsigned int mask = (1 << bf->length) - 1;
326
327 return (val >> (16 - bf->length) & mask) << bf->offset;
328 }
329
330 /*
331 * Set a single color register. The values supplied have a 16 bit
332 * magnitude. Return != 0 for invalid regno.
333 */
334 static int
clcdfb_setcolreg(unsigned int regno,unsigned int red,unsigned int green,unsigned int blue,unsigned int transp,struct fb_info * info)335 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
336 unsigned int blue, unsigned int transp, struct fb_info *info)
337 {
338 struct clcd_fb *fb = to_clcd(info);
339
340 if (regno < 16)
341 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
342 convert_bitfield(blue, &fb->fb.var.blue) |
343 convert_bitfield(green, &fb->fb.var.green) |
344 convert_bitfield(red, &fb->fb.var.red);
345
346 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
347 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
348 u32 val, mask, newval;
349
350 newval = (red >> 11) & 0x001f;
351 newval |= (green >> 6) & 0x03e0;
352 newval |= (blue >> 1) & 0x7c00;
353
354 /*
355 * 3.2.11: if we're configured for big endian
356 * byte order, the palette entries are swapped.
357 */
358 if (fb->clcd_cntl & CNTL_BEBO)
359 regno ^= 1;
360
361 if (regno & 1) {
362 newval <<= 16;
363 mask = 0x0000ffff;
364 } else {
365 mask = 0xffff0000;
366 }
367
368 val = readl(fb->regs + hw_reg) & mask;
369 writel(val | newval, fb->regs + hw_reg);
370 }
371
372 return regno > 255;
373 }
374
375 /*
376 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
377 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
378 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
379 * to e.g. a video mode which doesn't support it. Implements VESA suspend
380 * and powerdown modes on hardware that supports disabling hsync/vsync:
381 * blank_mode == 2: suspend vsync
382 * blank_mode == 3: suspend hsync
383 * blank_mode == 4: powerdown
384 */
clcdfb_blank(int blank_mode,struct fb_info * info)385 static int clcdfb_blank(int blank_mode, struct fb_info *info)
386 {
387 struct clcd_fb *fb = to_clcd(info);
388
389 if (blank_mode != 0) {
390 clcdfb_disable(fb);
391 } else {
392 clcdfb_enable(fb, fb->clcd_cntl);
393 }
394 return 0;
395 }
396
clcdfb_mmap(struct fb_info * info,struct vm_area_struct * vma)397 static int clcdfb_mmap(struct fb_info *info,
398 struct vm_area_struct *vma)
399 {
400 struct clcd_fb *fb = to_clcd(info);
401 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
402 int ret = -EINVAL;
403
404 len = info->fix.smem_len;
405
406 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
407 fb->board->mmap)
408 ret = fb->board->mmap(fb, vma);
409
410 return ret;
411 }
412
413 static const struct fb_ops clcdfb_ops = {
414 .owner = THIS_MODULE,
415 .fb_check_var = clcdfb_check_var,
416 .fb_set_par = clcdfb_set_par,
417 .fb_setcolreg = clcdfb_setcolreg,
418 .fb_blank = clcdfb_blank,
419 .fb_fillrect = cfb_fillrect,
420 .fb_copyarea = cfb_copyarea,
421 .fb_imageblit = cfb_imageblit,
422 .fb_mmap = clcdfb_mmap,
423 };
424
clcdfb_register(struct clcd_fb * fb)425 static int clcdfb_register(struct clcd_fb *fb)
426 {
427 int ret;
428
429 /*
430 * ARM PL111 always has IENB at 0x1c; it's only PL110
431 * which is reversed on some platforms.
432 */
433 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
434 fb->off_ienb = CLCD_PL111_IENB;
435 fb->off_cntl = CLCD_PL111_CNTL;
436 } else {
437 fb->off_ienb = CLCD_PL110_IENB;
438 fb->off_cntl = CLCD_PL110_CNTL;
439 }
440
441 fb->clk = clk_get(&fb->dev->dev, NULL);
442 if (IS_ERR(fb->clk)) {
443 ret = PTR_ERR(fb->clk);
444 goto out;
445 }
446
447 ret = clk_prepare(fb->clk);
448 if (ret)
449 goto free_clk;
450
451 fb->fb.device = &fb->dev->dev;
452
453 fb->fb.fix.mmio_start = fb->dev->res.start;
454 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
455
456 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
457 if (!fb->regs) {
458 printk(KERN_ERR "CLCD: unable to remap registers\n");
459 ret = -ENOMEM;
460 goto clk_unprep;
461 }
462
463 fb->fb.fbops = &clcdfb_ops;
464 fb->fb.pseudo_palette = fb->cmap;
465
466 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
467 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
468 fb->fb.fix.type_aux = 0;
469 fb->fb.fix.xpanstep = 0;
470 fb->fb.fix.ypanstep = 0;
471 fb->fb.fix.ywrapstep = 0;
472 fb->fb.fix.accel = FB_ACCEL_NONE;
473
474 fb->fb.var.xres = fb->panel->mode.xres;
475 fb->fb.var.yres = fb->panel->mode.yres;
476 fb->fb.var.xres_virtual = fb->panel->mode.xres;
477 fb->fb.var.yres_virtual = fb->panel->mode.yres;
478 fb->fb.var.bits_per_pixel = fb->panel->bpp;
479 fb->fb.var.grayscale = fb->panel->grayscale;
480 fb->fb.var.pixclock = fb->panel->mode.pixclock;
481 fb->fb.var.left_margin = fb->panel->mode.left_margin;
482 fb->fb.var.right_margin = fb->panel->mode.right_margin;
483 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
484 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
485 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
486 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
487 fb->fb.var.sync = fb->panel->mode.sync;
488 fb->fb.var.vmode = fb->panel->mode.vmode;
489 fb->fb.var.activate = FB_ACTIVATE_NOW;
490 fb->fb.var.nonstd = 0;
491 fb->fb.var.height = fb->panel->height;
492 fb->fb.var.width = fb->panel->width;
493 fb->fb.var.accel_flags = 0;
494
495 fb->fb.monspecs.hfmin = 0;
496 fb->fb.monspecs.hfmax = 100000;
497 fb->fb.monspecs.vfmin = 0;
498 fb->fb.monspecs.vfmax = 400;
499 fb->fb.monspecs.dclkmin = 1000000;
500 fb->fb.monspecs.dclkmax = 100000000;
501
502 /*
503 * Make sure that the bitfields are set appropriately.
504 */
505 clcdfb_set_bitfields(fb, &fb->fb.var);
506
507 /*
508 * Allocate colourmap.
509 */
510 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
511 if (ret)
512 goto unmap;
513
514 /*
515 * Ensure interrupts are disabled.
516 */
517 writel(0, fb->regs + fb->off_ienb);
518
519 fb_set_var(&fb->fb, &fb->fb.var);
520
521 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
522 fb->board->name, fb->panel->mode.name);
523
524 ret = register_framebuffer(&fb->fb);
525 if (ret == 0)
526 goto out;
527
528 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
529
530 fb_dealloc_cmap(&fb->fb.cmap);
531 unmap:
532 iounmap(fb->regs);
533 clk_unprep:
534 clk_unprepare(fb->clk);
535 free_clk:
536 clk_put(fb->clk);
537 out:
538 return ret;
539 }
540
541 #ifdef CONFIG_OF
clcdfb_of_get_dpi_panel_mode(struct device_node * node,struct clcd_panel * clcd_panel)542 static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
543 struct clcd_panel *clcd_panel)
544 {
545 int err;
546 struct display_timing timing;
547 struct videomode video;
548
549 err = of_get_display_timing(node, "panel-timing", &timing);
550 if (err) {
551 pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
552 return err;
553 }
554
555 videomode_from_timing(&timing, &video);
556
557 err = fb_videomode_from_videomode(&video, &clcd_panel->mode);
558 if (err)
559 return err;
560
561 /* Set up some inversion flags */
562 if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
563 clcd_panel->tim2 |= TIM2_IPC;
564 else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE))
565 /*
566 * To preserve backwards compatibility, the IPC (inverted
567 * pixel clock) flag needs to be set on any display that
568 * doesn't explicitly specify that the pixel clock is
569 * active on the negative or positive edge.
570 */
571 clcd_panel->tim2 |= TIM2_IPC;
572
573 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
574 clcd_panel->tim2 |= TIM2_IHS;
575
576 if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
577 clcd_panel->tim2 |= TIM2_IVS;
578
579 if (timing.flags & DISPLAY_FLAGS_DE_LOW)
580 clcd_panel->tim2 |= TIM2_IOE;
581
582 return 0;
583 }
584
clcdfb_snprintf_mode(char * buf,int size,struct fb_videomode * mode)585 static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
586 {
587 return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
588 mode->refresh);
589 }
590
clcdfb_of_get_backlight(struct device * dev,struct clcd_panel * clcd_panel)591 static int clcdfb_of_get_backlight(struct device *dev,
592 struct clcd_panel *clcd_panel)
593 {
594 struct backlight_device *backlight;
595
596 /* Look up the optional backlight device */
597 backlight = devm_of_find_backlight(dev);
598 if (IS_ERR(backlight))
599 return PTR_ERR(backlight);
600
601 clcd_panel->backlight = backlight;
602 return 0;
603 }
604
clcdfb_of_get_mode(struct device * dev,struct device_node * panel,struct clcd_panel * clcd_panel)605 static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel,
606 struct clcd_panel *clcd_panel)
607 {
608 int err;
609 struct fb_videomode *mode;
610 char *name;
611 int len;
612
613 /* Only directly connected DPI panels supported for now */
614 if (of_device_is_compatible(panel, "panel-dpi"))
615 err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel);
616 else
617 err = -ENOENT;
618 if (err)
619 return err;
620 mode = &clcd_panel->mode;
621
622 len = clcdfb_snprintf_mode(NULL, 0, mode);
623 name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
624 if (!name)
625 return -ENOMEM;
626
627 clcdfb_snprintf_mode(name, len + 1, mode);
628 mode->name = name;
629
630 return 0;
631 }
632
clcdfb_of_init_tft_panel(struct clcd_fb * fb,u32 r0,u32 g0,u32 b0)633 static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
634 {
635 static struct {
636 unsigned int part;
637 u32 r0, g0, b0;
638 u32 caps;
639 } panels[] = {
640 { 0x110, 1, 7, 13, CLCD_CAP_5551 },
641 { 0x110, 0, 8, 16, CLCD_CAP_888 },
642 { 0x110, 16, 8, 0, CLCD_CAP_888 },
643 { 0x111, 4, 14, 20, CLCD_CAP_444 },
644 { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
645 { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
646 CLCD_CAP_565 },
647 { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
648 CLCD_CAP_565 | CLCD_CAP_888 },
649 };
650 int i;
651
652 /* Bypass pixel clock divider */
653 fb->panel->tim2 |= TIM2_BCD;
654
655 /* TFT display, vert. comp. interrupt at the start of the back porch */
656 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
657
658 fb->panel->caps = 0;
659
660 /* Match the setup with known variants */
661 for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
662 if (amba_part(fb->dev) != panels[i].part)
663 continue;
664 if (g0 != panels[i].g0)
665 continue;
666 if (r0 == panels[i].r0 && b0 == panels[i].b0)
667 fb->panel->caps = panels[i].caps;
668 }
669
670 /*
671 * If we actually physically connected the R lines to B and
672 * vice versa
673 */
674 if (r0 != 0 && b0 == 0)
675 fb->panel->bgr_connection = true;
676
677 return fb->panel->caps ? 0 : -EINVAL;
678 }
679
clcdfb_of_init_display(struct clcd_fb * fb)680 static int clcdfb_of_init_display(struct clcd_fb *fb)
681 {
682 struct device_node *endpoint, *panel;
683 int err;
684 unsigned int bpp;
685 u32 max_bandwidth;
686 u32 tft_r0b0g0[3];
687
688 fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
689 if (!fb->panel)
690 return -ENOMEM;
691
692 /*
693 * Fetch the panel endpoint.
694 */
695 endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
696 if (!endpoint)
697 return -ENODEV;
698
699 panel = of_graph_get_remote_port_parent(endpoint);
700 if (!panel) {
701 err = -ENODEV;
702 goto out_endpoint_put;
703 }
704
705 err = clcdfb_of_get_backlight(&fb->dev->dev, fb->panel);
706 if (err)
707 goto out_panel_put;
708
709 err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel);
710 if (err)
711 goto out_panel_put;
712
713 err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
714 &max_bandwidth);
715 if (!err) {
716 /*
717 * max_bandwidth is in bytes per second and pixclock in
718 * pico-seconds, so the maximum allowed bits per pixel is
719 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
720 * Rearrange this calculation to avoid overflow and then ensure
721 * result is a valid format.
722 */
723 bpp = max_bandwidth / (1000 / 8)
724 / PICOS2KHZ(fb->panel->mode.pixclock);
725 bpp = rounddown_pow_of_two(bpp);
726 if (bpp > 32)
727 bpp = 32;
728 } else
729 bpp = 32;
730 fb->panel->bpp = bpp;
731
732 #ifdef CONFIG_CPU_BIG_ENDIAN
733 fb->panel->cntl |= CNTL_BEBO;
734 #endif
735 fb->panel->width = -1;
736 fb->panel->height = -1;
737
738 if (of_property_read_u32_array(endpoint,
739 "arm,pl11x,tft-r0g0b0-pads",
740 tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0) {
741 err = -ENOENT;
742 goto out_panel_put;
743 }
744
745 of_node_put(panel);
746 of_node_put(endpoint);
747
748 return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
749 tft_r0b0g0[1], tft_r0b0g0[2]);
750 out_panel_put:
751 of_node_put(panel);
752 out_endpoint_put:
753 of_node_put(endpoint);
754 return err;
755 }
756
clcdfb_of_vram_setup(struct clcd_fb * fb)757 static int clcdfb_of_vram_setup(struct clcd_fb *fb)
758 {
759 int err;
760 struct device_node *memory;
761 u64 size;
762
763 err = clcdfb_of_init_display(fb);
764 if (err)
765 return err;
766
767 memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
768 if (!memory)
769 return -ENODEV;
770
771 fb->fb.screen_base = of_iomap(memory, 0);
772 if (!fb->fb.screen_base) {
773 of_node_put(memory);
774 return -ENOMEM;
775 }
776
777 fb->fb.fix.smem_start = of_translate_address(memory,
778 of_get_address(memory, 0, &size, NULL));
779 fb->fb.fix.smem_len = size;
780 of_node_put(memory);
781
782 return 0;
783 }
784
clcdfb_of_vram_mmap(struct clcd_fb * fb,struct vm_area_struct * vma)785 static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
786 {
787 unsigned long off, user_size, kernel_size;
788
789
790 off = vma->vm_pgoff << PAGE_SHIFT;
791 user_size = vma->vm_end - vma->vm_start;
792 kernel_size = fb->fb.fix.smem_len;
793
794 if (off >= kernel_size || user_size > (kernel_size - off))
795 return -ENXIO;
796
797 return remap_pfn_range(vma, vma->vm_start,
798 __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
799 user_size,
800 pgprot_writecombine(vma->vm_page_prot));
801 }
802
clcdfb_of_vram_remove(struct clcd_fb * fb)803 static void clcdfb_of_vram_remove(struct clcd_fb *fb)
804 {
805 iounmap(fb->fb.screen_base);
806 }
807
clcdfb_of_dma_setup(struct clcd_fb * fb)808 static int clcdfb_of_dma_setup(struct clcd_fb *fb)
809 {
810 unsigned long framesize;
811 dma_addr_t dma;
812 int err;
813
814 err = clcdfb_of_init_display(fb);
815 if (err)
816 return err;
817
818 framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres *
819 fb->panel->bpp / 8);
820 fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
821 &dma, GFP_KERNEL);
822 if (!fb->fb.screen_base)
823 return -ENOMEM;
824
825 fb->fb.fix.smem_start = dma;
826 fb->fb.fix.smem_len = framesize;
827
828 return 0;
829 }
830
clcdfb_of_dma_mmap(struct clcd_fb * fb,struct vm_area_struct * vma)831 static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
832 {
833 return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
834 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
835 }
836
clcdfb_of_dma_remove(struct clcd_fb * fb)837 static void clcdfb_of_dma_remove(struct clcd_fb *fb)
838 {
839 dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
840 fb->fb.screen_base, fb->fb.fix.smem_start);
841 }
842
clcdfb_of_get_board(struct amba_device * dev)843 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
844 {
845 struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
846 GFP_KERNEL);
847 struct device_node *node = dev->dev.of_node;
848
849 if (!board)
850 return NULL;
851
852 board->name = of_node_full_name(node);
853 board->caps = CLCD_CAP_ALL;
854 board->check = clcdfb_check;
855 board->decode = clcdfb_decode;
856 if (of_property_present(node, "memory-region")) {
857 board->setup = clcdfb_of_vram_setup;
858 board->mmap = clcdfb_of_vram_mmap;
859 board->remove = clcdfb_of_vram_remove;
860 } else {
861 board->setup = clcdfb_of_dma_setup;
862 board->mmap = clcdfb_of_dma_mmap;
863 board->remove = clcdfb_of_dma_remove;
864 }
865
866 return board;
867 }
868 #else
clcdfb_of_get_board(struct amba_device * dev)869 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
870 {
871 return NULL;
872 }
873 #endif
874
clcdfb_probe(struct amba_device * dev,const struct amba_id * id)875 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
876 {
877 struct clcd_board *board = dev_get_platdata(&dev->dev);
878 struct clcd_fb *fb;
879 int ret;
880
881 if (!board)
882 board = clcdfb_of_get_board(dev);
883
884 if (!board)
885 return -EINVAL;
886
887 ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
888 if (ret)
889 goto out;
890
891 ret = amba_request_regions(dev, NULL);
892 if (ret) {
893 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
894 goto out;
895 }
896
897 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
898 if (!fb) {
899 ret = -ENOMEM;
900 goto free_region;
901 }
902
903 fb->dev = dev;
904 fb->board = board;
905
906 dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n",
907 amba_part(dev), amba_manf(dev), amba_rev(dev),
908 (unsigned long long)dev->res.start);
909
910 ret = fb->board->setup(fb);
911 if (ret)
912 goto free_fb;
913
914 ret = clcdfb_register(fb);
915 if (ret == 0) {
916 amba_set_drvdata(dev, fb);
917 goto out;
918 }
919
920 fb->board->remove(fb);
921 free_fb:
922 kfree(fb);
923 free_region:
924 amba_release_regions(dev);
925 out:
926 return ret;
927 }
928
clcdfb_remove(struct amba_device * dev)929 static void clcdfb_remove(struct amba_device *dev)
930 {
931 struct clcd_fb *fb = amba_get_drvdata(dev);
932
933 clcdfb_disable(fb);
934 unregister_framebuffer(&fb->fb);
935 if (fb->fb.cmap.len)
936 fb_dealloc_cmap(&fb->fb.cmap);
937 iounmap(fb->regs);
938 clk_unprepare(fb->clk);
939 clk_put(fb->clk);
940
941 fb->board->remove(fb);
942
943 kfree(fb);
944
945 amba_release_regions(dev);
946 }
947
948 static const struct amba_id clcdfb_id_table[] = {
949 {
950 .id = 0x00041110,
951 .mask = 0x000ffffe,
952 },
953 { 0, 0 },
954 };
955
956 MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
957
958 static struct amba_driver clcd_driver = {
959 .drv = {
960 .name = "clcd-pl11x",
961 },
962 .probe = clcdfb_probe,
963 .remove = clcdfb_remove,
964 .id_table = clcdfb_id_table,
965 };
966
amba_clcdfb_init(void)967 static int __init amba_clcdfb_init(void)
968 {
969 if (fb_get_options("ambafb", NULL))
970 return -ENODEV;
971
972 return amba_driver_register(&clcd_driver);
973 }
974
975 module_init(amba_clcdfb_init);
976
amba_clcdfb_exit(void)977 static void __exit amba_clcdfb_exit(void)
978 {
979 amba_driver_unregister(&clcd_driver);
980 }
981
982 module_exit(amba_clcdfb_exit);
983
984 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
985 MODULE_LICENSE("GPL");
986