xref: /openbmc/linux/drivers/usb/chipidea/core.c (revision 84a13b97)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * core.c - ChipIdea USB IP core family device controller
4  *
5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6  * Copyright (C) 2020 NXP
7  *
8  * Author: David Lopo
9  *	   Peter Chen <peter.chen@nxp.com>
10  *
11  * Main Features:
12  * - Four transfers are supported, usbtest is passed
13  * - USB Certification for gadget: CH9 and Mass Storage are passed
14  * - Low power mode
15  * - USB wakeup
16  */
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
36 #include <linux/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
39 
40 #include "ci.h"
41 #include "udc.h"
42 #include "bits.h"
43 #include "host.h"
44 #include "otg.h"
45 #include "otg_fsm.h"
46 
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 	[CAP_CAPLENGTH]		= 0x00U,
50 	[CAP_HCCPARAMS]		= 0x08U,
51 	[CAP_DCCPARAMS]		= 0x24U,
52 	[CAP_TESTMODE]		= 0x38U,
53 	[OP_USBCMD]		= 0x00U,
54 	[OP_USBSTS]		= 0x04U,
55 	[OP_USBINTR]		= 0x08U,
56 	[OP_FRINDEX]		= 0x0CU,
57 	[OP_DEVICEADDR]		= 0x14U,
58 	[OP_ENDPTLISTADDR]	= 0x18U,
59 	[OP_TTCTRL]		= 0x1CU,
60 	[OP_BURSTSIZE]		= 0x20U,
61 	[OP_ULPI_VIEWPORT]	= 0x30U,
62 	[OP_PORTSC]		= 0x44U,
63 	[OP_DEVLC]		= 0x84U,
64 	[OP_OTGSC]		= 0x64U,
65 	[OP_USBMODE]		= 0x68U,
66 	[OP_ENDPTSETUPSTAT]	= 0x6CU,
67 	[OP_ENDPTPRIME]		= 0x70U,
68 	[OP_ENDPTFLUSH]		= 0x74U,
69 	[OP_ENDPTSTAT]		= 0x78U,
70 	[OP_ENDPTCOMPLETE]	= 0x7CU,
71 	[OP_ENDPTCTRL]		= 0x80U,
72 };
73 
74 static const u8 ci_regs_lpm[] = {
75 	[CAP_CAPLENGTH]		= 0x00U,
76 	[CAP_HCCPARAMS]		= 0x08U,
77 	[CAP_DCCPARAMS]		= 0x24U,
78 	[CAP_TESTMODE]		= 0xFCU,
79 	[OP_USBCMD]		= 0x00U,
80 	[OP_USBSTS]		= 0x04U,
81 	[OP_USBINTR]		= 0x08U,
82 	[OP_FRINDEX]		= 0x0CU,
83 	[OP_DEVICEADDR]		= 0x14U,
84 	[OP_ENDPTLISTADDR]	= 0x18U,
85 	[OP_TTCTRL]		= 0x1CU,
86 	[OP_BURSTSIZE]		= 0x20U,
87 	[OP_ULPI_VIEWPORT]	= 0x30U,
88 	[OP_PORTSC]		= 0x44U,
89 	[OP_DEVLC]		= 0x84U,
90 	[OP_OTGSC]		= 0xC4U,
91 	[OP_USBMODE]		= 0xC8U,
92 	[OP_ENDPTSETUPSTAT]	= 0xD8U,
93 	[OP_ENDPTPRIME]		= 0xDCU,
94 	[OP_ENDPTFLUSH]		= 0xE0U,
95 	[OP_ENDPTSTAT]		= 0xE4U,
96 	[OP_ENDPTCOMPLETE]	= 0xE8U,
97 	[OP_ENDPTCTRL]		= 0xECU,
98 };
99 
hw_alloc_regmap(struct ci_hdrc * ci,bool is_lpm)100 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
101 {
102 	int i;
103 
104 	for (i = 0; i < OP_ENDPTCTRL; i++)
105 		ci->hw_bank.regmap[i] =
106 			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
107 			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
108 
109 	for (; i <= OP_LAST; i++)
110 		ci->hw_bank.regmap[i] = ci->hw_bank.op +
111 			4 * (i - OP_ENDPTCTRL) +
112 			(is_lpm
113 			 ? ci_regs_lpm[OP_ENDPTCTRL]
114 			 : ci_regs_nolpm[OP_ENDPTCTRL]);
115 
116 }
117 
ci_get_revision(struct ci_hdrc * ci)118 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
119 {
120 	int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
121 	enum ci_revision rev = CI_REVISION_UNKNOWN;
122 
123 	if (ver == 0x2) {
124 		rev = hw_read_id_reg(ci, ID_ID, REVISION)
125 			>> __ffs(REVISION);
126 		rev += CI_REVISION_20;
127 	} else if (ver == 0x0) {
128 		rev = CI_REVISION_1X;
129 	}
130 
131 	return rev;
132 }
133 
134 /**
135  * hw_read_intr_enable: returns interrupt enable register
136  *
137  * @ci: the controller
138  *
139  * This function returns register data
140  */
hw_read_intr_enable(struct ci_hdrc * ci)141 u32 hw_read_intr_enable(struct ci_hdrc *ci)
142 {
143 	return hw_read(ci, OP_USBINTR, ~0);
144 }
145 
146 /**
147  * hw_read_intr_status: returns interrupt status register
148  *
149  * @ci: the controller
150  *
151  * This function returns register data
152  */
hw_read_intr_status(struct ci_hdrc * ci)153 u32 hw_read_intr_status(struct ci_hdrc *ci)
154 {
155 	return hw_read(ci, OP_USBSTS, ~0);
156 }
157 
158 /**
159  * hw_port_test_set: writes port test mode (execute without interruption)
160  * @ci: the controller
161  * @mode: new value
162  *
163  * This function returns an error code
164  */
hw_port_test_set(struct ci_hdrc * ci,u8 mode)165 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
166 {
167 	const u8 TEST_MODE_MAX = 7;
168 
169 	if (mode > TEST_MODE_MAX)
170 		return -EINVAL;
171 
172 	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
173 	return 0;
174 }
175 
176 /**
177  * hw_port_test_get: reads port test mode value
178  *
179  * @ci: the controller
180  *
181  * This function returns port test mode value
182  */
hw_port_test_get(struct ci_hdrc * ci)183 u8 hw_port_test_get(struct ci_hdrc *ci)
184 {
185 	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
186 }
187 
hw_wait_phy_stable(void)188 static void hw_wait_phy_stable(void)
189 {
190 	/*
191 	 * The phy needs some delay to output the stable status from low
192 	 * power mode. And for OTGSC, the status inputs are debounced
193 	 * using a 1 ms time constant, so, delay 2ms for controller to get
194 	 * the stable status, like vbus and id when the phy leaves low power.
195 	 */
196 	usleep_range(2000, 2500);
197 }
198 
199 /* The PHY enters/leaves low power mode */
ci_hdrc_enter_lpm_common(struct ci_hdrc * ci,bool enable)200 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
201 {
202 	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
203 	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
204 
205 	if (enable && !lpm)
206 		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
207 				PORTSC_PHCD(ci->hw_bank.lpm));
208 	else if (!enable && lpm)
209 		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
210 				0);
211 }
212 
ci_hdrc_enter_lpm(struct ci_hdrc * ci,bool enable)213 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
214 {
215 	return ci->platdata->enter_lpm(ci, enable);
216 }
217 
hw_device_init(struct ci_hdrc * ci,void __iomem * base)218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
219 {
220 	u32 reg;
221 
222 	/* bank is a module variable */
223 	ci->hw_bank.abs = base;
224 
225 	ci->hw_bank.cap = ci->hw_bank.abs;
226 	ci->hw_bank.cap += ci->platdata->capoffset;
227 	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
228 
229 	hw_alloc_regmap(ci, false);
230 	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
231 		__ffs(HCCPARAMS_LEN);
232 	ci->hw_bank.lpm  = reg;
233 	if (reg)
234 		hw_alloc_regmap(ci, !!reg);
235 	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236 	ci->hw_bank.size += OP_LAST;
237 	ci->hw_bank.size /= sizeof(u32);
238 
239 	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
240 		__ffs(DCCPARAMS_DEN);
241 	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
242 
243 	if (ci->hw_ep_max > ENDPT_MAX)
244 		return -ENODEV;
245 
246 	ci_hdrc_enter_lpm(ci, false);
247 
248 	/* Disable all interrupts bits */
249 	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
250 
251 	/* Clear all interrupts status bits*/
252 	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
253 
254 	ci->rev = ci_get_revision(ci);
255 
256 	dev_dbg(ci->dev,
257 		"revision: %d, lpm: %d; cap: %px op: %px\n",
258 		ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
259 
260 	/* setup lock mode ? */
261 
262 	/* ENDPTSETUPSTAT is '0' by default */
263 
264 	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
265 
266 	return 0;
267 }
268 
hw_phymode_configure(struct ci_hdrc * ci)269 void hw_phymode_configure(struct ci_hdrc *ci)
270 {
271 	u32 portsc, lpm, sts = 0;
272 
273 	switch (ci->platdata->phy_mode) {
274 	case USBPHY_INTERFACE_MODE_UTMI:
275 		portsc = PORTSC_PTS(PTS_UTMI);
276 		lpm = DEVLC_PTS(PTS_UTMI);
277 		break;
278 	case USBPHY_INTERFACE_MODE_UTMIW:
279 		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
280 		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
281 		break;
282 	case USBPHY_INTERFACE_MODE_ULPI:
283 		portsc = PORTSC_PTS(PTS_ULPI);
284 		lpm = DEVLC_PTS(PTS_ULPI);
285 		break;
286 	case USBPHY_INTERFACE_MODE_SERIAL:
287 		portsc = PORTSC_PTS(PTS_SERIAL);
288 		lpm = DEVLC_PTS(PTS_SERIAL);
289 		sts = 1;
290 		break;
291 	case USBPHY_INTERFACE_MODE_HSIC:
292 		portsc = PORTSC_PTS(PTS_HSIC);
293 		lpm = DEVLC_PTS(PTS_HSIC);
294 		break;
295 	default:
296 		return;
297 	}
298 
299 	if (ci->hw_bank.lpm) {
300 		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
301 		if (sts)
302 			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
303 	} else {
304 		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
305 		if (sts)
306 			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
307 	}
308 }
309 EXPORT_SYMBOL_GPL(hw_phymode_configure);
310 
311 /**
312  * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
313  * interfaces
314  * @ci: the controller
315  *
316  * This function returns an error code if the phy failed to init
317  */
_ci_usb_phy_init(struct ci_hdrc * ci)318 static int _ci_usb_phy_init(struct ci_hdrc *ci)
319 {
320 	int ret;
321 
322 	if (ci->phy) {
323 		ret = phy_init(ci->phy);
324 		if (ret)
325 			return ret;
326 
327 		ret = phy_power_on(ci->phy);
328 		if (ret) {
329 			phy_exit(ci->phy);
330 			return ret;
331 		}
332 	} else {
333 		ret = usb_phy_init(ci->usb_phy);
334 	}
335 
336 	return ret;
337 }
338 
339 /**
340  * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
341  * interfaces
342  * @ci: the controller
343  */
ci_usb_phy_exit(struct ci_hdrc * ci)344 static void ci_usb_phy_exit(struct ci_hdrc *ci)
345 {
346 	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
347 		return;
348 
349 	if (ci->phy) {
350 		phy_power_off(ci->phy);
351 		phy_exit(ci->phy);
352 	} else {
353 		usb_phy_shutdown(ci->usb_phy);
354 	}
355 }
356 
357 /**
358  * ci_usb_phy_init: initialize phy according to different phy type
359  * @ci: the controller
360  *
361  * This function returns an error code if usb_phy_init has failed
362  */
ci_usb_phy_init(struct ci_hdrc * ci)363 static int ci_usb_phy_init(struct ci_hdrc *ci)
364 {
365 	int ret;
366 
367 	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
368 		return 0;
369 
370 	switch (ci->platdata->phy_mode) {
371 	case USBPHY_INTERFACE_MODE_UTMI:
372 	case USBPHY_INTERFACE_MODE_UTMIW:
373 	case USBPHY_INTERFACE_MODE_HSIC:
374 		ret = _ci_usb_phy_init(ci);
375 		if (!ret)
376 			hw_wait_phy_stable();
377 		else
378 			return ret;
379 		hw_phymode_configure(ci);
380 		break;
381 	case USBPHY_INTERFACE_MODE_ULPI:
382 	case USBPHY_INTERFACE_MODE_SERIAL:
383 		hw_phymode_configure(ci);
384 		ret = _ci_usb_phy_init(ci);
385 		if (ret)
386 			return ret;
387 		break;
388 	default:
389 		ret = _ci_usb_phy_init(ci);
390 		if (!ret)
391 			hw_wait_phy_stable();
392 	}
393 
394 	return ret;
395 }
396 
397 
398 /**
399  * ci_platform_configure: do controller configure
400  * @ci: the controller
401  *
402  */
ci_platform_configure(struct ci_hdrc * ci)403 void ci_platform_configure(struct ci_hdrc *ci)
404 {
405 	bool is_device_mode, is_host_mode;
406 
407 	is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
408 	is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
409 
410 	if (is_device_mode) {
411 		phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
412 
413 		if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
414 			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
415 				 USBMODE_CI_SDIS);
416 	}
417 
418 	if (is_host_mode) {
419 		phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
420 
421 		if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
422 			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
423 				 USBMODE_CI_SDIS);
424 	}
425 
426 	if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
427 		if (ci->hw_bank.lpm)
428 			hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
429 		else
430 			hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
431 	}
432 
433 	if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
434 		hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
435 
436 	hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
437 
438 	if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
439 		hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
440 			ci->platdata->ahb_burst_config);
441 
442 	/* override burst size, take effect only when ahb_burst_config is 0 */
443 	if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
444 		if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
445 			hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
446 			ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
447 
448 		if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
449 			hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
450 				ci->platdata->rx_burst_size);
451 	}
452 }
453 
454 /**
455  * hw_controller_reset: do controller reset
456  * @ci: the controller
457   *
458  * This function returns an error code
459  */
hw_controller_reset(struct ci_hdrc * ci)460 static int hw_controller_reset(struct ci_hdrc *ci)
461 {
462 	int count = 0;
463 
464 	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
465 	while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
466 		udelay(10);
467 		if (count++ > 1000)
468 			return -ETIMEDOUT;
469 	}
470 
471 	return 0;
472 }
473 
474 /**
475  * hw_device_reset: resets chip (execute without interruption)
476  * @ci: the controller
477  *
478  * This function returns an error code
479  */
hw_device_reset(struct ci_hdrc * ci)480 int hw_device_reset(struct ci_hdrc *ci)
481 {
482 	int ret;
483 
484 	/* should flush & stop before reset */
485 	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
486 	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
487 
488 	ret = hw_controller_reset(ci);
489 	if (ret) {
490 		dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
491 		return ret;
492 	}
493 
494 	if (ci->platdata->notify_event) {
495 		ret = ci->platdata->notify_event(ci,
496 			CI_HDRC_CONTROLLER_RESET_EVENT);
497 		if (ret)
498 			return ret;
499 	}
500 
501 	/* USBMODE should be configured step by step */
502 	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
503 	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
504 	/* HW >= 2.3 */
505 	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
506 
507 	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
508 		dev_err(ci->dev, "cannot enter in %s device mode\n",
509 			ci_role(ci)->name);
510 		dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
511 		return -ENODEV;
512 	}
513 
514 	ci_platform_configure(ci);
515 
516 	return 0;
517 }
518 
ci_irq_handler(int irq,void * data)519 static irqreturn_t ci_irq_handler(int irq, void *data)
520 {
521 	struct ci_hdrc *ci = data;
522 	irqreturn_t ret = IRQ_NONE;
523 	u32 otgsc = 0;
524 
525 	if (ci->in_lpm) {
526 		/*
527 		 * If we already have a wakeup irq pending there,
528 		 * let's just return to wait resume finished firstly.
529 		 */
530 		if (ci->wakeup_int)
531 			return IRQ_HANDLED;
532 
533 		disable_irq_nosync(irq);
534 		ci->wakeup_int = true;
535 		pm_runtime_get(ci->dev);
536 		return IRQ_HANDLED;
537 	}
538 
539 	if (ci->is_otg) {
540 		otgsc = hw_read_otgsc(ci, ~0);
541 		if (ci_otg_is_fsm_mode(ci)) {
542 			ret = ci_otg_fsm_irq(ci);
543 			if (ret == IRQ_HANDLED)
544 				return ret;
545 		}
546 	}
547 
548 	/*
549 	 * Handle id change interrupt, it indicates device/host function
550 	 * switch.
551 	 */
552 	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
553 		ci->id_event = true;
554 		/* Clear ID change irq status */
555 		hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
556 		ci_otg_queue_work(ci);
557 		return IRQ_HANDLED;
558 	}
559 
560 	/*
561 	 * Handle vbus change interrupt, it indicates device connection
562 	 * and disconnection events.
563 	 */
564 	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
565 		ci->b_sess_valid_event = true;
566 		/* Clear BSV irq */
567 		hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
568 		ci_otg_queue_work(ci);
569 		return IRQ_HANDLED;
570 	}
571 
572 	/* Handle device/host interrupt */
573 	if (ci->role != CI_ROLE_END)
574 		ret = ci_role(ci)->irq(ci);
575 
576 	return ret;
577 }
578 
ci_irq(struct ci_hdrc * ci)579 static void ci_irq(struct ci_hdrc *ci)
580 {
581 	unsigned long flags;
582 
583 	local_irq_save(flags);
584 	ci_irq_handler(ci->irq, ci);
585 	local_irq_restore(flags);
586 }
587 
ci_cable_notifier(struct notifier_block * nb,unsigned long event,void * ptr)588 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
589 			     void *ptr)
590 {
591 	struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
592 	struct ci_hdrc *ci = cbl->ci;
593 
594 	cbl->connected = event;
595 	cbl->changed = true;
596 
597 	ci_irq(ci);
598 	return NOTIFY_DONE;
599 }
600 
ci_usb_role_switch_get(struct usb_role_switch * sw)601 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
602 {
603 	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
604 	enum usb_role role;
605 	unsigned long flags;
606 
607 	spin_lock_irqsave(&ci->lock, flags);
608 	role = ci_role_to_usb_role(ci);
609 	spin_unlock_irqrestore(&ci->lock, flags);
610 
611 	return role;
612 }
613 
ci_usb_role_switch_set(struct usb_role_switch * sw,enum usb_role role)614 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
615 				  enum usb_role role)
616 {
617 	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
618 	struct ci_hdrc_cable *cable;
619 
620 	if (role == USB_ROLE_HOST) {
621 		cable = &ci->platdata->id_extcon;
622 		cable->changed = true;
623 		cable->connected = true;
624 		cable = &ci->platdata->vbus_extcon;
625 		cable->changed = true;
626 		cable->connected = false;
627 	} else if (role == USB_ROLE_DEVICE) {
628 		cable = &ci->platdata->id_extcon;
629 		cable->changed = true;
630 		cable->connected = false;
631 		cable = &ci->platdata->vbus_extcon;
632 		cable->changed = true;
633 		cable->connected = true;
634 	} else {
635 		cable = &ci->platdata->id_extcon;
636 		cable->changed = true;
637 		cable->connected = false;
638 		cable = &ci->platdata->vbus_extcon;
639 		cable->changed = true;
640 		cable->connected = false;
641 	}
642 
643 	ci_irq(ci);
644 	return 0;
645 }
646 
ci_get_role(struct ci_hdrc * ci)647 static enum ci_role ci_get_role(struct ci_hdrc *ci)
648 {
649 	enum ci_role role;
650 
651 	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
652 		if (ci->is_otg) {
653 			role = ci_otg_role(ci);
654 			hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
655 		} else {
656 			/*
657 			 * If the controller is not OTG capable, but support
658 			 * role switch, the defalt role is gadget, and the
659 			 * user can switch it through debugfs.
660 			 */
661 			role = CI_ROLE_GADGET;
662 		}
663 	} else {
664 		role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST
665 					: CI_ROLE_GADGET;
666 	}
667 
668 	return role;
669 }
670 
671 static struct usb_role_switch_desc ci_role_switch = {
672 	.set = ci_usb_role_switch_set,
673 	.get = ci_usb_role_switch_get,
674 	.allow_userspace_control = true,
675 };
676 
ci_get_platdata(struct device * dev,struct ci_hdrc_platform_data * platdata)677 static int ci_get_platdata(struct device *dev,
678 		struct ci_hdrc_platform_data *platdata)
679 {
680 	struct extcon_dev *ext_vbus, *ext_id;
681 	struct ci_hdrc_cable *cable;
682 	int ret;
683 
684 	if (!platdata->phy_mode)
685 		platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
686 
687 	if (!platdata->dr_mode)
688 		platdata->dr_mode = usb_get_dr_mode(dev);
689 
690 	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
691 		platdata->dr_mode = USB_DR_MODE_OTG;
692 
693 	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
694 		/* Get the vbus regulator */
695 		platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
696 		if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
697 			return -EPROBE_DEFER;
698 		} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
699 			/* no vbus regulator is needed */
700 			platdata->reg_vbus = NULL;
701 		} else if (IS_ERR(platdata->reg_vbus)) {
702 			dev_err(dev, "Getting regulator error: %ld\n",
703 				PTR_ERR(platdata->reg_vbus));
704 			return PTR_ERR(platdata->reg_vbus);
705 		}
706 		/* Get TPL support */
707 		if (!platdata->tpl_support)
708 			platdata->tpl_support =
709 				of_usb_host_tpl_support(dev->of_node);
710 	}
711 
712 	if (platdata->dr_mode == USB_DR_MODE_OTG) {
713 		/* We can support HNP and SRP of OTG 2.0 */
714 		platdata->ci_otg_caps.otg_rev = 0x0200;
715 		platdata->ci_otg_caps.hnp_support = true;
716 		platdata->ci_otg_caps.srp_support = true;
717 
718 		/* Update otg capabilities by DT properties */
719 		ret = of_usb_update_otg_caps(dev->of_node,
720 					&platdata->ci_otg_caps);
721 		if (ret)
722 			return ret;
723 	}
724 
725 	if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
726 		platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
727 
728 	of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
729 				     &platdata->phy_clkgate_delay_us);
730 
731 	platdata->itc_setting = 1;
732 
733 	of_property_read_u32(dev->of_node, "itc-setting",
734 					&platdata->itc_setting);
735 
736 	ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
737 				&platdata->ahb_burst_config);
738 	if (!ret) {
739 		platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
740 	} else if (ret != -EINVAL) {
741 		dev_err(dev, "failed to get ahb-burst-config\n");
742 		return ret;
743 	}
744 
745 	ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
746 				&platdata->tx_burst_size);
747 	if (!ret) {
748 		platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
749 	} else if (ret != -EINVAL) {
750 		dev_err(dev, "failed to get tx-burst-size-dword\n");
751 		return ret;
752 	}
753 
754 	ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
755 				&platdata->rx_burst_size);
756 	if (!ret) {
757 		platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
758 	} else if (ret != -EINVAL) {
759 		dev_err(dev, "failed to get rx-burst-size-dword\n");
760 		return ret;
761 	}
762 
763 	if (of_property_read_bool(dev->of_node, "non-zero-ttctrl-ttha"))
764 		platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
765 
766 	ext_id = ERR_PTR(-ENODEV);
767 	ext_vbus = ERR_PTR(-ENODEV);
768 	if (of_property_read_bool(dev->of_node, "extcon")) {
769 		/* Each one of them is not mandatory */
770 		ext_vbus = extcon_get_edev_by_phandle(dev, 0);
771 		if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
772 			return PTR_ERR(ext_vbus);
773 
774 		ext_id = extcon_get_edev_by_phandle(dev, 1);
775 		if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
776 			return PTR_ERR(ext_id);
777 	}
778 
779 	cable = &platdata->vbus_extcon;
780 	cable->nb.notifier_call = ci_cable_notifier;
781 	cable->edev = ext_vbus;
782 
783 	if (!IS_ERR(ext_vbus)) {
784 		ret = extcon_get_state(cable->edev, EXTCON_USB);
785 		if (ret)
786 			cable->connected = true;
787 		else
788 			cable->connected = false;
789 	}
790 
791 	cable = &platdata->id_extcon;
792 	cable->nb.notifier_call = ci_cable_notifier;
793 	cable->edev = ext_id;
794 
795 	if (!IS_ERR(ext_id)) {
796 		ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
797 		if (ret)
798 			cable->connected = true;
799 		else
800 			cable->connected = false;
801 	}
802 
803 	if (device_property_read_bool(dev, "usb-role-switch"))
804 		ci_role_switch.fwnode = dev->fwnode;
805 
806 	platdata->pctl = devm_pinctrl_get(dev);
807 	if (!IS_ERR(platdata->pctl)) {
808 		struct pinctrl_state *p;
809 
810 		p = pinctrl_lookup_state(platdata->pctl, "default");
811 		if (!IS_ERR(p))
812 			platdata->pins_default = p;
813 
814 		p = pinctrl_lookup_state(platdata->pctl, "host");
815 		if (!IS_ERR(p))
816 			platdata->pins_host = p;
817 
818 		p = pinctrl_lookup_state(platdata->pctl, "device");
819 		if (!IS_ERR(p))
820 			platdata->pins_device = p;
821 	}
822 
823 	if (!platdata->enter_lpm)
824 		platdata->enter_lpm = ci_hdrc_enter_lpm_common;
825 
826 	return 0;
827 }
828 
ci_extcon_register(struct ci_hdrc * ci)829 static int ci_extcon_register(struct ci_hdrc *ci)
830 {
831 	struct ci_hdrc_cable *id, *vbus;
832 	int ret;
833 
834 	id = &ci->platdata->id_extcon;
835 	id->ci = ci;
836 	if (!IS_ERR_OR_NULL(id->edev)) {
837 		ret = devm_extcon_register_notifier(ci->dev, id->edev,
838 						EXTCON_USB_HOST, &id->nb);
839 		if (ret < 0) {
840 			dev_err(ci->dev, "register ID failed\n");
841 			return ret;
842 		}
843 	}
844 
845 	vbus = &ci->platdata->vbus_extcon;
846 	vbus->ci = ci;
847 	if (!IS_ERR_OR_NULL(vbus->edev)) {
848 		ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
849 						EXTCON_USB, &vbus->nb);
850 		if (ret < 0) {
851 			dev_err(ci->dev, "register VBUS failed\n");
852 			return ret;
853 		}
854 	}
855 
856 	return 0;
857 }
858 
ci_power_lost_work(struct work_struct * work)859 static void ci_power_lost_work(struct work_struct *work)
860 {
861 	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, power_lost_work);
862 	enum ci_role role;
863 
864 	disable_irq_nosync(ci->irq);
865 	pm_runtime_get_sync(ci->dev);
866 	if (!ci_otg_is_fsm_mode(ci)) {
867 		role = ci_get_role(ci);
868 
869 		if (ci->role != role) {
870 			ci_handle_id_switch(ci);
871 		} else if (role == CI_ROLE_GADGET) {
872 			if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV))
873 				usb_gadget_vbus_connect(&ci->gadget);
874 		}
875 	}
876 	pm_runtime_put_sync(ci->dev);
877 	enable_irq(ci->irq);
878 }
879 
880 static DEFINE_IDA(ci_ida);
881 
ci_hdrc_add_device(struct device * dev,struct resource * res,int nres,struct ci_hdrc_platform_data * platdata)882 struct platform_device *ci_hdrc_add_device(struct device *dev,
883 			struct resource *res, int nres,
884 			struct ci_hdrc_platform_data *platdata)
885 {
886 	struct platform_device *pdev;
887 	int id, ret;
888 
889 	ret = ci_get_platdata(dev, platdata);
890 	if (ret)
891 		return ERR_PTR(ret);
892 
893 	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
894 	if (id < 0)
895 		return ERR_PTR(id);
896 
897 	pdev = platform_device_alloc("ci_hdrc", id);
898 	if (!pdev) {
899 		ret = -ENOMEM;
900 		goto put_id;
901 	}
902 
903 	pdev->dev.parent = dev;
904 	device_set_of_node_from_dev(&pdev->dev, dev);
905 
906 	ret = platform_device_add_resources(pdev, res, nres);
907 	if (ret)
908 		goto err;
909 
910 	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
911 	if (ret)
912 		goto err;
913 
914 	ret = platform_device_add(pdev);
915 	if (ret)
916 		goto err;
917 
918 	return pdev;
919 
920 err:
921 	platform_device_put(pdev);
922 put_id:
923 	ida_simple_remove(&ci_ida, id);
924 	return ERR_PTR(ret);
925 }
926 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
927 
ci_hdrc_remove_device(struct platform_device * pdev)928 void ci_hdrc_remove_device(struct platform_device *pdev)
929 {
930 	int id = pdev->id;
931 	platform_device_unregister(pdev);
932 	ida_simple_remove(&ci_ida, id);
933 }
934 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
935 
936 /**
937  * ci_hdrc_query_available_role: get runtime available operation mode
938  *
939  * The glue layer can get current operation mode (host/peripheral/otg)
940  * This function should be called after ci core device has created.
941  *
942  * @pdev: the platform device of ci core.
943  *
944  * Return runtime usb_dr_mode.
945  */
ci_hdrc_query_available_role(struct platform_device * pdev)946 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
947 {
948 	struct ci_hdrc *ci = platform_get_drvdata(pdev);
949 
950 	if (!ci)
951 		return USB_DR_MODE_UNKNOWN;
952 	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
953 		return USB_DR_MODE_OTG;
954 	else if (ci->roles[CI_ROLE_HOST])
955 		return USB_DR_MODE_HOST;
956 	else if (ci->roles[CI_ROLE_GADGET])
957 		return USB_DR_MODE_PERIPHERAL;
958 	else
959 		return USB_DR_MODE_UNKNOWN;
960 }
961 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
962 
ci_role_destroy(struct ci_hdrc * ci)963 static inline void ci_role_destroy(struct ci_hdrc *ci)
964 {
965 	ci_hdrc_gadget_destroy(ci);
966 	ci_hdrc_host_destroy(ci);
967 	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
968 		ci_hdrc_otg_destroy(ci);
969 }
970 
ci_get_otg_capable(struct ci_hdrc * ci)971 static void ci_get_otg_capable(struct ci_hdrc *ci)
972 {
973 	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
974 		ci->is_otg = false;
975 	else
976 		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
977 				DCCPARAMS_DC | DCCPARAMS_HC)
978 					== (DCCPARAMS_DC | DCCPARAMS_HC));
979 	if (ci->is_otg) {
980 		dev_dbg(ci->dev, "It is OTG capable controller\n");
981 		/* Disable and clear all OTG irq */
982 		hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
983 							OTGSC_INT_STATUS_BITS);
984 	}
985 }
986 
role_show(struct device * dev,struct device_attribute * attr,char * buf)987 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
988 			  char *buf)
989 {
990 	struct ci_hdrc *ci = dev_get_drvdata(dev);
991 
992 	if (ci->role != CI_ROLE_END)
993 		return sprintf(buf, "%s\n", ci_role(ci)->name);
994 
995 	return 0;
996 }
997 
role_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)998 static ssize_t role_store(struct device *dev,
999 		struct device_attribute *attr, const char *buf, size_t n)
1000 {
1001 	struct ci_hdrc *ci = dev_get_drvdata(dev);
1002 	enum ci_role role;
1003 	int ret;
1004 
1005 	if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
1006 		dev_warn(dev, "Current configuration is not dual-role, quit\n");
1007 		return -EPERM;
1008 	}
1009 
1010 	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
1011 		if (!strncmp(buf, ci->roles[role]->name,
1012 			     strlen(ci->roles[role]->name)))
1013 			break;
1014 
1015 	if (role == CI_ROLE_END)
1016 		return -EINVAL;
1017 
1018 	mutex_lock(&ci->mutex);
1019 
1020 	if (role == ci->role) {
1021 		mutex_unlock(&ci->mutex);
1022 		return n;
1023 	}
1024 
1025 	pm_runtime_get_sync(dev);
1026 	disable_irq(ci->irq);
1027 	ci_role_stop(ci);
1028 	ret = ci_role_start(ci, role);
1029 	if (!ret && ci->role == CI_ROLE_GADGET)
1030 		ci_handle_vbus_change(ci);
1031 	enable_irq(ci->irq);
1032 	pm_runtime_put_sync(dev);
1033 	mutex_unlock(&ci->mutex);
1034 
1035 	return (ret == 0) ? n : ret;
1036 }
1037 static DEVICE_ATTR_RW(role);
1038 
1039 static struct attribute *ci_attrs[] = {
1040 	&dev_attr_role.attr,
1041 	NULL,
1042 };
1043 ATTRIBUTE_GROUPS(ci);
1044 
ci_hdrc_probe(struct platform_device * pdev)1045 static int ci_hdrc_probe(struct platform_device *pdev)
1046 {
1047 	struct device	*dev = &pdev->dev;
1048 	struct ci_hdrc	*ci;
1049 	struct resource	*res;
1050 	void __iomem	*base;
1051 	int		ret;
1052 	enum usb_dr_mode dr_mode;
1053 
1054 	if (!dev_get_platdata(dev)) {
1055 		dev_err(dev, "platform data missing\n");
1056 		return -ENODEV;
1057 	}
1058 
1059 	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1060 	if (IS_ERR(base))
1061 		return PTR_ERR(base);
1062 
1063 	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1064 	if (!ci)
1065 		return -ENOMEM;
1066 
1067 	spin_lock_init(&ci->lock);
1068 	mutex_init(&ci->mutex);
1069 	INIT_WORK(&ci->power_lost_work, ci_power_lost_work);
1070 
1071 	ci->dev = dev;
1072 	ci->platdata = dev_get_platdata(dev);
1073 	ci->imx28_write_fix = !!(ci->platdata->flags &
1074 		CI_HDRC_IMX28_WRITE_FIX);
1075 	ci->supports_runtime_pm = !!(ci->platdata->flags &
1076 		CI_HDRC_SUPPORTS_RUNTIME_PM);
1077 	ci->has_portsc_pec_bug = !!(ci->platdata->flags &
1078 		CI_HDRC_HAS_PORTSC_PEC_MISSED);
1079 	platform_set_drvdata(pdev, ci);
1080 
1081 	ret = hw_device_init(ci, base);
1082 	if (ret < 0) {
1083 		dev_err(dev, "can't initialize hardware\n");
1084 		return -ENODEV;
1085 	}
1086 
1087 	ret = ci_ulpi_init(ci);
1088 	if (ret)
1089 		return ret;
1090 
1091 	if (ci->platdata->phy) {
1092 		ci->phy = ci->platdata->phy;
1093 	} else if (ci->platdata->usb_phy) {
1094 		ci->usb_phy = ci->platdata->usb_phy;
1095 	} else {
1096 		/* Look for a generic PHY first */
1097 		ci->phy = devm_phy_get(dev->parent, "usb-phy");
1098 
1099 		if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1100 			ret = -EPROBE_DEFER;
1101 			goto ulpi_exit;
1102 		} else if (IS_ERR(ci->phy)) {
1103 			ci->phy = NULL;
1104 		}
1105 
1106 		/* Look for a legacy USB PHY from device-tree next */
1107 		if (!ci->phy) {
1108 			ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1109 								  "phys", 0);
1110 
1111 			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1112 				ret = -EPROBE_DEFER;
1113 				goto ulpi_exit;
1114 			} else if (IS_ERR(ci->usb_phy)) {
1115 				ci->usb_phy = NULL;
1116 			}
1117 		}
1118 
1119 		/* Look for any registered legacy USB PHY as last resort */
1120 		if (!ci->phy && !ci->usb_phy) {
1121 			ci->usb_phy = devm_usb_get_phy(dev->parent,
1122 						       USB_PHY_TYPE_USB2);
1123 
1124 			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1125 				ret = -EPROBE_DEFER;
1126 				goto ulpi_exit;
1127 			} else if (IS_ERR(ci->usb_phy)) {
1128 				ci->usb_phy = NULL;
1129 			}
1130 		}
1131 
1132 		/* No USB PHY was found in the end */
1133 		if (!ci->phy && !ci->usb_phy) {
1134 			ret = -ENXIO;
1135 			goto ulpi_exit;
1136 		}
1137 	}
1138 
1139 	ret = ci_usb_phy_init(ci);
1140 	if (ret) {
1141 		dev_err(dev, "unable to init phy: %d\n", ret);
1142 		goto ulpi_exit;
1143 	}
1144 
1145 	ci->hw_bank.phys = res->start;
1146 
1147 	ci->irq = platform_get_irq(pdev, 0);
1148 	if (ci->irq < 0) {
1149 		ret = ci->irq;
1150 		goto deinit_phy;
1151 	}
1152 
1153 	ci_get_otg_capable(ci);
1154 
1155 	dr_mode = ci->platdata->dr_mode;
1156 	/* initialize role(s) before the interrupt is requested */
1157 	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1158 		ret = ci_hdrc_host_init(ci);
1159 		if (ret) {
1160 			if (ret == -ENXIO)
1161 				dev_info(dev, "doesn't support host\n");
1162 			else
1163 				goto deinit_phy;
1164 		}
1165 	}
1166 
1167 	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1168 		ret = ci_hdrc_gadget_init(ci);
1169 		if (ret) {
1170 			if (ret == -ENXIO)
1171 				dev_info(dev, "doesn't support gadget\n");
1172 			else
1173 				goto deinit_host;
1174 		}
1175 	}
1176 
1177 	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1178 		dev_err(dev, "no supported roles\n");
1179 		ret = -ENODEV;
1180 		goto deinit_gadget;
1181 	}
1182 
1183 	if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1184 		ret = ci_hdrc_otg_init(ci);
1185 		if (ret) {
1186 			dev_err(dev, "init otg fails, ret = %d\n", ret);
1187 			goto deinit_gadget;
1188 		}
1189 	}
1190 
1191 	if (ci_role_switch.fwnode) {
1192 		ci_role_switch.driver_data = ci;
1193 		ci->role_switch = usb_role_switch_register(dev,
1194 					&ci_role_switch);
1195 		if (IS_ERR(ci->role_switch)) {
1196 			ret = PTR_ERR(ci->role_switch);
1197 			goto deinit_otg;
1198 		}
1199 	}
1200 
1201 	ci->role = ci_get_role(ci);
1202 	if (!ci_otg_is_fsm_mode(ci)) {
1203 		/* only update vbus status for peripheral */
1204 		if (ci->role == CI_ROLE_GADGET) {
1205 			/* Pull down DP for possible charger detection */
1206 			hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1207 			ci_handle_vbus_change(ci);
1208 		}
1209 
1210 		ret = ci_role_start(ci, ci->role);
1211 		if (ret) {
1212 			dev_err(dev, "can't start %s role\n",
1213 						ci_role(ci)->name);
1214 			goto stop;
1215 		}
1216 	}
1217 
1218 	ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1219 			ci->platdata->name, ci);
1220 	if (ret)
1221 		goto stop;
1222 
1223 	ret = ci_extcon_register(ci);
1224 	if (ret)
1225 		goto stop;
1226 
1227 	if (ci->supports_runtime_pm) {
1228 		pm_runtime_set_active(&pdev->dev);
1229 		pm_runtime_enable(&pdev->dev);
1230 		pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1231 		pm_runtime_mark_last_busy(ci->dev);
1232 		pm_runtime_use_autosuspend(&pdev->dev);
1233 	}
1234 
1235 	if (ci_otg_is_fsm_mode(ci))
1236 		ci_hdrc_otg_fsm_start(ci);
1237 
1238 	device_set_wakeup_capable(&pdev->dev, true);
1239 	dbg_create_files(ci);
1240 
1241 	return 0;
1242 
1243 stop:
1244 	if (ci->role_switch)
1245 		usb_role_switch_unregister(ci->role_switch);
1246 deinit_otg:
1247 	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1248 		ci_hdrc_otg_destroy(ci);
1249 deinit_gadget:
1250 	ci_hdrc_gadget_destroy(ci);
1251 deinit_host:
1252 	ci_hdrc_host_destroy(ci);
1253 deinit_phy:
1254 	ci_usb_phy_exit(ci);
1255 ulpi_exit:
1256 	ci_ulpi_exit(ci);
1257 
1258 	return ret;
1259 }
1260 
ci_hdrc_remove(struct platform_device * pdev)1261 static void ci_hdrc_remove(struct platform_device *pdev)
1262 {
1263 	struct ci_hdrc *ci = platform_get_drvdata(pdev);
1264 
1265 	if (ci->role_switch)
1266 		usb_role_switch_unregister(ci->role_switch);
1267 
1268 	if (ci->supports_runtime_pm) {
1269 		pm_runtime_get_sync(&pdev->dev);
1270 		pm_runtime_disable(&pdev->dev);
1271 		pm_runtime_put_noidle(&pdev->dev);
1272 	}
1273 
1274 	dbg_remove_files(ci);
1275 	ci_role_destroy(ci);
1276 	ci_hdrc_enter_lpm(ci, true);
1277 	ci_usb_phy_exit(ci);
1278 	ci_ulpi_exit(ci);
1279 }
1280 
1281 #ifdef CONFIG_PM
1282 /* Prepare wakeup by SRP before suspend */
ci_otg_fsm_suspend_for_srp(struct ci_hdrc * ci)1283 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1284 {
1285 	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1286 				!hw_read_otgsc(ci, OTGSC_ID)) {
1287 		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1288 								PORTSC_PP);
1289 		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1290 								PORTSC_WKCN);
1291 	}
1292 }
1293 
1294 /* Handle SRP when wakeup by data pulse */
ci_otg_fsm_wakeup_by_srp(struct ci_hdrc * ci)1295 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1296 {
1297 	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1298 		(ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1299 		if (!hw_read_otgsc(ci, OTGSC_ID)) {
1300 			ci->fsm.a_srp_det = 1;
1301 			ci->fsm.a_bus_drop = 0;
1302 		} else {
1303 			ci->fsm.id = 1;
1304 		}
1305 		ci_otg_queue_work(ci);
1306 	}
1307 }
1308 
ci_controller_suspend(struct ci_hdrc * ci)1309 static void ci_controller_suspend(struct ci_hdrc *ci)
1310 {
1311 	disable_irq(ci->irq);
1312 	ci_hdrc_enter_lpm(ci, true);
1313 	if (ci->platdata->phy_clkgate_delay_us)
1314 		usleep_range(ci->platdata->phy_clkgate_delay_us,
1315 			     ci->platdata->phy_clkgate_delay_us + 50);
1316 	usb_phy_set_suspend(ci->usb_phy, 1);
1317 	ci->in_lpm = true;
1318 	enable_irq(ci->irq);
1319 }
1320 
1321 /*
1322  * Handle the wakeup interrupt triggered by extcon connector
1323  * We need to call ci_irq again for extcon since the first
1324  * interrupt (wakeup int) only let the controller be out of
1325  * low power mode, but not handle any interrupts.
1326  */
ci_extcon_wakeup_int(struct ci_hdrc * ci)1327 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1328 {
1329 	struct ci_hdrc_cable *cable_id, *cable_vbus;
1330 	u32 otgsc = hw_read_otgsc(ci, ~0);
1331 
1332 	cable_id = &ci->platdata->id_extcon;
1333 	cable_vbus = &ci->platdata->vbus_extcon;
1334 
1335 	if ((!IS_ERR(cable_id->edev) || ci->role_switch)
1336 		&& ci->is_otg &&
1337 		(otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1338 		ci_irq(ci);
1339 
1340 	if ((!IS_ERR(cable_vbus->edev) || ci->role_switch)
1341 		&& ci->is_otg &&
1342 		(otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1343 		ci_irq(ci);
1344 }
1345 
ci_controller_resume(struct device * dev)1346 static int ci_controller_resume(struct device *dev)
1347 {
1348 	struct ci_hdrc *ci = dev_get_drvdata(dev);
1349 	int ret;
1350 
1351 	dev_dbg(dev, "at %s\n", __func__);
1352 
1353 	if (!ci->in_lpm) {
1354 		WARN_ON(1);
1355 		return 0;
1356 	}
1357 
1358 	ci_hdrc_enter_lpm(ci, false);
1359 
1360 	ret = ci_ulpi_resume(ci);
1361 	if (ret)
1362 		return ret;
1363 
1364 	if (ci->usb_phy) {
1365 		usb_phy_set_suspend(ci->usb_phy, 0);
1366 		usb_phy_set_wakeup(ci->usb_phy, false);
1367 		hw_wait_phy_stable();
1368 	}
1369 
1370 	ci->in_lpm = false;
1371 	if (ci->wakeup_int) {
1372 		ci->wakeup_int = false;
1373 		pm_runtime_mark_last_busy(ci->dev);
1374 		pm_runtime_put_autosuspend(ci->dev);
1375 		enable_irq(ci->irq);
1376 		if (ci_otg_is_fsm_mode(ci))
1377 			ci_otg_fsm_wakeup_by_srp(ci);
1378 		ci_extcon_wakeup_int(ci);
1379 	}
1380 
1381 	return 0;
1382 }
1383 
1384 #ifdef CONFIG_PM_SLEEP
ci_suspend(struct device * dev)1385 static int ci_suspend(struct device *dev)
1386 {
1387 	struct ci_hdrc *ci = dev_get_drvdata(dev);
1388 
1389 	if (ci->wq)
1390 		flush_workqueue(ci->wq);
1391 	/*
1392 	 * Controller needs to be active during suspend, otherwise the core
1393 	 * may run resume when the parent is at suspend if other driver's
1394 	 * suspend fails, it occurs before parent's suspend has not started,
1395 	 * but the core suspend has finished.
1396 	 */
1397 	if (ci->in_lpm)
1398 		pm_runtime_resume(dev);
1399 
1400 	if (ci->in_lpm) {
1401 		WARN_ON(1);
1402 		return 0;
1403 	}
1404 
1405 	/* Extra routine per role before system suspend */
1406 	if (ci->role != CI_ROLE_END && ci_role(ci)->suspend)
1407 		ci_role(ci)->suspend(ci);
1408 
1409 	if (device_may_wakeup(dev)) {
1410 		if (ci_otg_is_fsm_mode(ci))
1411 			ci_otg_fsm_suspend_for_srp(ci);
1412 
1413 		usb_phy_set_wakeup(ci->usb_phy, true);
1414 		enable_irq_wake(ci->irq);
1415 	}
1416 
1417 	ci_controller_suspend(ci);
1418 
1419 	return 0;
1420 }
1421 
ci_resume(struct device * dev)1422 static int ci_resume(struct device *dev)
1423 {
1424 	struct ci_hdrc *ci = dev_get_drvdata(dev);
1425 	bool power_lost;
1426 	int ret;
1427 
1428 	/* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device
1429 	 * mode) share the same register address. We can check if
1430 	 * controller resume from power lost based on this address
1431 	 * due to this register will be reset after power lost.
1432 	 */
1433 	power_lost = !hw_read(ci, OP_ENDPTLISTADDR, ~0);
1434 
1435 	if (device_may_wakeup(dev))
1436 		disable_irq_wake(ci->irq);
1437 
1438 	ret = ci_controller_resume(dev);
1439 	if (ret)
1440 		return ret;
1441 
1442 	if (power_lost) {
1443 		/* shutdown and re-init for phy */
1444 		ci_usb_phy_exit(ci);
1445 		ci_usb_phy_init(ci);
1446 	}
1447 
1448 	/* Extra routine per role after system resume */
1449 	if (ci->role != CI_ROLE_END && ci_role(ci)->resume)
1450 		ci_role(ci)->resume(ci, power_lost);
1451 
1452 	if (power_lost)
1453 		queue_work(system_freezable_wq, &ci->power_lost_work);
1454 
1455 	if (ci->supports_runtime_pm) {
1456 		pm_runtime_disable(dev);
1457 		pm_runtime_set_active(dev);
1458 		pm_runtime_enable(dev);
1459 	}
1460 
1461 	return ret;
1462 }
1463 #endif /* CONFIG_PM_SLEEP */
1464 
ci_runtime_suspend(struct device * dev)1465 static int ci_runtime_suspend(struct device *dev)
1466 {
1467 	struct ci_hdrc *ci = dev_get_drvdata(dev);
1468 
1469 	dev_dbg(dev, "at %s\n", __func__);
1470 
1471 	if (ci->in_lpm) {
1472 		WARN_ON(1);
1473 		return 0;
1474 	}
1475 
1476 	if (ci_otg_is_fsm_mode(ci))
1477 		ci_otg_fsm_suspend_for_srp(ci);
1478 
1479 	usb_phy_set_wakeup(ci->usb_phy, true);
1480 	ci_controller_suspend(ci);
1481 
1482 	return 0;
1483 }
1484 
ci_runtime_resume(struct device * dev)1485 static int ci_runtime_resume(struct device *dev)
1486 {
1487 	return ci_controller_resume(dev);
1488 }
1489 
1490 #endif /* CONFIG_PM */
1491 static const struct dev_pm_ops ci_pm_ops = {
1492 	SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1493 	SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1494 };
1495 
1496 static struct platform_driver ci_hdrc_driver = {
1497 	.probe	= ci_hdrc_probe,
1498 	.remove_new = ci_hdrc_remove,
1499 	.driver	= {
1500 		.name	= "ci_hdrc",
1501 		.pm	= &ci_pm_ops,
1502 		.dev_groups = ci_groups,
1503 	},
1504 };
1505 
ci_hdrc_platform_register(void)1506 static int __init ci_hdrc_platform_register(void)
1507 {
1508 	ci_hdrc_host_driver_init();
1509 	return platform_driver_register(&ci_hdrc_driver);
1510 }
1511 module_init(ci_hdrc_platform_register);
1512 
ci_hdrc_platform_unregister(void)1513 static void __exit ci_hdrc_platform_unregister(void)
1514 {
1515 	platform_driver_unregister(&ci_hdrc_driver);
1516 }
1517 module_exit(ci_hdrc_platform_unregister);
1518 
1519 MODULE_ALIAS("platform:ci_hdrc");
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1522 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1523