1 /* 2 * Copyright (C) 2017 Spreadtrum Communications Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/hwspinlock.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/reboot.h> 16 #include <linux/spi/spi.h> 17 #include <linux/sizes.h> 18 19 /* Registers definitions for ADI controller */ 20 #define REG_ADI_CTRL0 0x4 21 #define REG_ADI_CHN_PRIL 0x8 22 #define REG_ADI_CHN_PRIH 0xc 23 #define REG_ADI_INT_EN 0x10 24 #define REG_ADI_INT_RAW 0x14 25 #define REG_ADI_INT_MASK 0x18 26 #define REG_ADI_INT_CLR 0x1c 27 #define REG_ADI_GSSI_CFG0 0x20 28 #define REG_ADI_GSSI_CFG1 0x24 29 #define REG_ADI_RD_CMD 0x28 30 #define REG_ADI_RD_DATA 0x2c 31 #define REG_ADI_ARM_FIFO_STS 0x30 32 #define REG_ADI_STS 0x34 33 #define REG_ADI_EVT_FIFO_STS 0x38 34 #define REG_ADI_ARM_CMD_STS 0x3c 35 #define REG_ADI_CHN_EN 0x40 36 #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4) 37 #define REG_ADI_CHN_EN1 0x20c 38 39 /* Bits definitions for register REG_ADI_GSSI_CFG0 */ 40 #define BIT_CLK_ALL_ON BIT(30) 41 42 /* Bits definitions for register REG_ADI_RD_DATA */ 43 #define BIT_RD_CMD_BUSY BIT(31) 44 #define RD_ADDR_SHIFT 16 45 #define RD_VALUE_MASK GENMASK(15, 0) 46 #define RD_ADDR_MASK GENMASK(30, 16) 47 48 /* Bits definitions for register REG_ADI_ARM_FIFO_STS */ 49 #define BIT_FIFO_FULL BIT(11) 50 #define BIT_FIFO_EMPTY BIT(10) 51 52 /* 53 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on. 54 * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or 55 * later versions. Since bit[1:0] are zero, so the spec describe them as 56 * 10/12/15bit address mode. 57 * The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the 58 * high two bits is slave_id. 59 * The slave devices address offset is 0x8000 for 10/12bit address mode, 60 * and 0x20000 for 15bit mode. 61 */ 62 #define ADI_10BIT_SLAVE_ADDR_SIZE SZ_4K 63 #define ADI_10BIT_SLAVE_OFFSET 0x8000 64 #define ADI_12BIT_SLAVE_ADDR_SIZE SZ_16K 65 #define ADI_12BIT_SLAVE_OFFSET 0x8000 66 #define ADI_15BIT_SLAVE_ADDR_SIZE SZ_128K 67 #define ADI_15BIT_SLAVE_OFFSET 0x20000 68 69 /* Timeout (ms) for the trylock of hardware spinlocks */ 70 #define ADI_HWSPINLOCK_TIMEOUT 5000 71 /* 72 * ADI controller has 50 channels including 2 software channels 73 * and 48 hardware channels. 74 */ 75 #define ADI_HW_CHNS 50 76 77 #define ADI_FIFO_DRAIN_TIMEOUT 1000 78 #define ADI_READ_TIMEOUT 2000 79 80 /* 81 * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to: 82 * REG_ADI_RD_CMD bit[14:0] for r2p0 83 * REG_ADI_RD_CMD bit[16:2] for r3p0 84 */ 85 #define RDBACK_ADDR_MASK_R2 GENMASK(14, 0) 86 #define RDBACK_ADDR_MASK_R3 GENMASK(16, 2) 87 #define RDBACK_ADDR_SHIFT_R3 2 88 89 /* Registers definitions for PMIC watchdog controller */ 90 #define REG_WDG_LOAD_LOW 0x0 91 #define REG_WDG_LOAD_HIGH 0x4 92 #define REG_WDG_CTRL 0x8 93 #define REG_WDG_LOCK 0x20 94 95 /* Bits definitions for register REG_WDG_CTRL */ 96 #define BIT_WDG_RUN BIT(1) 97 #define BIT_WDG_NEW BIT(2) 98 #define BIT_WDG_RST BIT(3) 99 100 /* Bits definitions for register REG_MODULE_EN */ 101 #define BIT_WDG_EN BIT(2) 102 103 /* Registers definitions for PMIC */ 104 #define PMIC_RST_STATUS 0xee8 105 #define PMIC_MODULE_EN 0xc08 106 #define PMIC_CLK_EN 0xc18 107 #define PMIC_WDG_BASE 0x80 108 109 /* Definition of PMIC reset status register */ 110 #define HWRST_STATUS_SECURITY 0x02 111 #define HWRST_STATUS_RECOVERY 0x20 112 #define HWRST_STATUS_NORMAL 0x40 113 #define HWRST_STATUS_ALARM 0x50 114 #define HWRST_STATUS_SLEEP 0x60 115 #define HWRST_STATUS_FASTBOOT 0x30 116 #define HWRST_STATUS_SPECIAL 0x70 117 #define HWRST_STATUS_PANIC 0x80 118 #define HWRST_STATUS_CFTREBOOT 0x90 119 #define HWRST_STATUS_AUTODLOADER 0xa0 120 #define HWRST_STATUS_IQMODE 0xb0 121 #define HWRST_STATUS_SPRDISK 0xc0 122 #define HWRST_STATUS_FACTORYTEST 0xe0 123 #define HWRST_STATUS_WATCHDOG 0xf0 124 125 /* Use default timeout 50 ms that converts to watchdog values */ 126 #define WDG_LOAD_VAL ((50 * 32768) / 1000) 127 #define WDG_LOAD_MASK GENMASK(15, 0) 128 #define WDG_UNLOCK_KEY 0xe551 129 130 struct sprd_adi_wdg { 131 u32 base; 132 u32 rst_sts; 133 u32 wdg_en; 134 u32 wdg_clk; 135 }; 136 137 struct sprd_adi_data { 138 u32 slave_offset; 139 u32 slave_addr_size; 140 int (*read_check)(u32 val, u32 reg); 141 int (*restart)(struct notifier_block *this, 142 unsigned long mode, void *cmd); 143 void (*wdg_rst)(void *p); 144 }; 145 146 struct sprd_adi { 147 struct spi_controller *ctlr; 148 struct device *dev; 149 void __iomem *base; 150 struct hwspinlock *hwlock; 151 unsigned long slave_vbase; 152 unsigned long slave_pbase; 153 struct notifier_block restart_handler; 154 const struct sprd_adi_data *data; 155 }; 156 sprd_adi_check_addr(struct sprd_adi * sadi,u32 reg)157 static int sprd_adi_check_addr(struct sprd_adi *sadi, u32 reg) 158 { 159 if (reg >= sadi->data->slave_addr_size) { 160 dev_err(sadi->dev, 161 "slave address offset is incorrect, reg = 0x%x\n", 162 reg); 163 return -EINVAL; 164 } 165 166 return 0; 167 } 168 sprd_adi_drain_fifo(struct sprd_adi * sadi)169 static int sprd_adi_drain_fifo(struct sprd_adi *sadi) 170 { 171 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT; 172 u32 sts; 173 174 do { 175 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS); 176 if (sts & BIT_FIFO_EMPTY) 177 break; 178 179 cpu_relax(); 180 } while (--timeout); 181 182 if (timeout == 0) { 183 dev_err(sadi->dev, "drain write fifo timeout\n"); 184 return -EBUSY; 185 } 186 187 return 0; 188 } 189 sprd_adi_fifo_is_full(struct sprd_adi * sadi)190 static int sprd_adi_fifo_is_full(struct sprd_adi *sadi) 191 { 192 return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL; 193 } 194 sprd_adi_read_check(u32 val,u32 addr)195 static int sprd_adi_read_check(u32 val, u32 addr) 196 { 197 u32 rd_addr; 198 199 rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT; 200 201 if (rd_addr != addr) { 202 pr_err("ADI read error, addr = 0x%x, val = 0x%x\n", addr, val); 203 return -EIO; 204 } 205 206 return 0; 207 } 208 sprd_adi_read_check_r2(u32 val,u32 reg)209 static int sprd_adi_read_check_r2(u32 val, u32 reg) 210 { 211 return sprd_adi_read_check(val, reg & RDBACK_ADDR_MASK_R2); 212 } 213 sprd_adi_read_check_r3(u32 val,u32 reg)214 static int sprd_adi_read_check_r3(u32 val, u32 reg) 215 { 216 return sprd_adi_read_check(val, (reg & RDBACK_ADDR_MASK_R3) >> RDBACK_ADDR_SHIFT_R3); 217 } 218 sprd_adi_read(struct sprd_adi * sadi,u32 reg,u32 * read_val)219 static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val) 220 { 221 int read_timeout = ADI_READ_TIMEOUT; 222 unsigned long flags; 223 u32 val; 224 int ret = 0; 225 226 if (sadi->hwlock) { 227 ret = hwspin_lock_timeout_irqsave(sadi->hwlock, 228 ADI_HWSPINLOCK_TIMEOUT, 229 &flags); 230 if (ret) { 231 dev_err(sadi->dev, "get the hw lock failed\n"); 232 return ret; 233 } 234 } 235 236 ret = sprd_adi_check_addr(sadi, reg); 237 if (ret) 238 goto out; 239 240 /* 241 * Set the slave address offset need to read into RD_CMD register, 242 * then ADI controller will start to transfer automatically. 243 */ 244 writel_relaxed(reg, sadi->base + REG_ADI_RD_CMD); 245 246 /* 247 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set 248 * simultaneously when writing read command to register, and the 249 * BIT_RD_CMD_BUSY will be cleared after the read operation is 250 * completed. 251 */ 252 do { 253 val = readl_relaxed(sadi->base + REG_ADI_RD_DATA); 254 if (!(val & BIT_RD_CMD_BUSY)) 255 break; 256 257 cpu_relax(); 258 } while (--read_timeout); 259 260 if (read_timeout == 0) { 261 dev_err(sadi->dev, "ADI read timeout\n"); 262 ret = -EBUSY; 263 goto out; 264 } 265 266 /* 267 * The return value before adi r5p0 includes data and read register 268 * address, from bit 0to bit 15 are data, and from bit 16 to bit 30 269 * are read register address. Then we can check the returned register 270 * address to validate data. 271 */ 272 if (sadi->data->read_check) { 273 ret = sadi->data->read_check(val, reg); 274 if (ret < 0) 275 goto out; 276 } 277 278 *read_val = val & RD_VALUE_MASK; 279 280 out: 281 if (sadi->hwlock) 282 hwspin_unlock_irqrestore(sadi->hwlock, &flags); 283 return ret; 284 } 285 sprd_adi_write(struct sprd_adi * sadi,u32 reg,u32 val)286 static int sprd_adi_write(struct sprd_adi *sadi, u32 reg, u32 val) 287 { 288 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT; 289 unsigned long flags; 290 int ret; 291 292 if (sadi->hwlock) { 293 ret = hwspin_lock_timeout_irqsave(sadi->hwlock, 294 ADI_HWSPINLOCK_TIMEOUT, 295 &flags); 296 if (ret) { 297 dev_err(sadi->dev, "get the hw lock failed\n"); 298 return ret; 299 } 300 } 301 302 ret = sprd_adi_check_addr(sadi, reg); 303 if (ret) 304 goto out; 305 306 ret = sprd_adi_drain_fifo(sadi); 307 if (ret < 0) 308 goto out; 309 310 /* 311 * we should wait for write fifo is empty before writing data to PMIC 312 * registers. 313 */ 314 do { 315 if (!sprd_adi_fifo_is_full(sadi)) { 316 /* we need virtual register address to write. */ 317 writel_relaxed(val, (void __iomem *)(sadi->slave_vbase + reg)); 318 break; 319 } 320 321 cpu_relax(); 322 } while (--timeout); 323 324 if (timeout == 0) { 325 dev_err(sadi->dev, "write fifo is full\n"); 326 ret = -EBUSY; 327 } 328 329 out: 330 if (sadi->hwlock) 331 hwspin_unlock_irqrestore(sadi->hwlock, &flags); 332 return ret; 333 } 334 sprd_adi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi_dev,struct spi_transfer * t)335 static int sprd_adi_transfer_one(struct spi_controller *ctlr, 336 struct spi_device *spi_dev, 337 struct spi_transfer *t) 338 { 339 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr); 340 u32 reg, val; 341 int ret; 342 343 if (t->rx_buf) { 344 reg = *(u32 *)t->rx_buf; 345 ret = sprd_adi_read(sadi, reg, &val); 346 *(u32 *)t->rx_buf = val; 347 } else if (t->tx_buf) { 348 u32 *p = (u32 *)t->tx_buf; 349 reg = *p++; 350 val = *p; 351 ret = sprd_adi_write(sadi, reg, val); 352 } else { 353 dev_err(sadi->dev, "no buffer for transfer\n"); 354 ret = -EINVAL; 355 } 356 357 return ret; 358 } 359 sprd_adi_set_wdt_rst_mode(void * p)360 static void sprd_adi_set_wdt_rst_mode(void *p) 361 { 362 #if IS_ENABLED(CONFIG_SPRD_WATCHDOG) 363 u32 val; 364 struct sprd_adi *sadi = (struct sprd_adi *)p; 365 366 /* Init watchdog reset mode */ 367 sprd_adi_read(sadi, PMIC_RST_STATUS, &val); 368 val |= HWRST_STATUS_WATCHDOG; 369 sprd_adi_write(sadi, PMIC_RST_STATUS, val); 370 #endif 371 } 372 sprd_adi_restart(struct notifier_block * this,unsigned long mode,void * cmd,struct sprd_adi_wdg * wdg)373 static int sprd_adi_restart(struct notifier_block *this, unsigned long mode, 374 void *cmd, struct sprd_adi_wdg *wdg) 375 { 376 struct sprd_adi *sadi = container_of(this, struct sprd_adi, 377 restart_handler); 378 u32 val, reboot_mode = 0; 379 380 if (!cmd) 381 reboot_mode = HWRST_STATUS_NORMAL; 382 else if (!strncmp(cmd, "recovery", 8)) 383 reboot_mode = HWRST_STATUS_RECOVERY; 384 else if (!strncmp(cmd, "alarm", 5)) 385 reboot_mode = HWRST_STATUS_ALARM; 386 else if (!strncmp(cmd, "fastsleep", 9)) 387 reboot_mode = HWRST_STATUS_SLEEP; 388 else if (!strncmp(cmd, "bootloader", 10)) 389 reboot_mode = HWRST_STATUS_FASTBOOT; 390 else if (!strncmp(cmd, "panic", 5)) 391 reboot_mode = HWRST_STATUS_PANIC; 392 else if (!strncmp(cmd, "special", 7)) 393 reboot_mode = HWRST_STATUS_SPECIAL; 394 else if (!strncmp(cmd, "cftreboot", 9)) 395 reboot_mode = HWRST_STATUS_CFTREBOOT; 396 else if (!strncmp(cmd, "autodloader", 11)) 397 reboot_mode = HWRST_STATUS_AUTODLOADER; 398 else if (!strncmp(cmd, "iqmode", 6)) 399 reboot_mode = HWRST_STATUS_IQMODE; 400 else if (!strncmp(cmd, "sprdisk", 7)) 401 reboot_mode = HWRST_STATUS_SPRDISK; 402 else if (!strncmp(cmd, "tospanic", 8)) 403 reboot_mode = HWRST_STATUS_SECURITY; 404 else if (!strncmp(cmd, "factorytest", 11)) 405 reboot_mode = HWRST_STATUS_FACTORYTEST; 406 else 407 reboot_mode = HWRST_STATUS_NORMAL; 408 409 /* Record the reboot mode */ 410 sprd_adi_read(sadi, wdg->rst_sts, &val); 411 val &= ~HWRST_STATUS_WATCHDOG; 412 val |= reboot_mode; 413 sprd_adi_write(sadi, wdg->rst_sts, val); 414 415 /* Enable the interface clock of the watchdog */ 416 sprd_adi_read(sadi, wdg->wdg_en, &val); 417 val |= BIT_WDG_EN; 418 sprd_adi_write(sadi, wdg->wdg_en, val); 419 420 /* Enable the work clock of the watchdog */ 421 sprd_adi_read(sadi, wdg->wdg_clk, &val); 422 val |= BIT_WDG_EN; 423 sprd_adi_write(sadi, wdg->wdg_clk, val); 424 425 /* Unlock the watchdog */ 426 sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, WDG_UNLOCK_KEY); 427 428 sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val); 429 val |= BIT_WDG_NEW; 430 sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val); 431 432 /* Load the watchdog timeout value, 50ms is always enough. */ 433 sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_HIGH, 0); 434 sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_LOW, 435 WDG_LOAD_VAL & WDG_LOAD_MASK); 436 437 /* Start the watchdog to reset system */ 438 sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val); 439 val |= BIT_WDG_RUN | BIT_WDG_RST; 440 sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val); 441 442 /* Lock the watchdog */ 443 sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, ~WDG_UNLOCK_KEY); 444 445 mdelay(1000); 446 447 dev_emerg(sadi->dev, "Unable to restart system\n"); 448 return NOTIFY_DONE; 449 } 450 sprd_adi_restart_sc9860(struct notifier_block * this,unsigned long mode,void * cmd)451 static int sprd_adi_restart_sc9860(struct notifier_block *this, 452 unsigned long mode, void *cmd) 453 { 454 struct sprd_adi_wdg wdg = { 455 .base = PMIC_WDG_BASE, 456 .rst_sts = PMIC_RST_STATUS, 457 .wdg_en = PMIC_MODULE_EN, 458 .wdg_clk = PMIC_CLK_EN, 459 }; 460 461 return sprd_adi_restart(this, mode, cmd, &wdg); 462 } 463 sprd_adi_hw_init(struct sprd_adi * sadi)464 static void sprd_adi_hw_init(struct sprd_adi *sadi) 465 { 466 struct device_node *np = sadi->dev->of_node; 467 int i, size, chn_cnt; 468 const __be32 *list; 469 u32 tmp; 470 471 /* Set all channels as default priority */ 472 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); 473 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH); 474 475 /* Set clock auto gate mode */ 476 tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0); 477 tmp &= ~BIT_CLK_ALL_ON; 478 writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0); 479 480 /* Set hardware channels setting */ 481 list = of_get_property(np, "sprd,hw-channels", &size); 482 if (!list || !size) { 483 dev_info(sadi->dev, "no hw channels setting in node\n"); 484 return; 485 } 486 487 chn_cnt = size / 8; 488 for (i = 0; i < chn_cnt; i++) { 489 u32 value; 490 u32 chn_id = be32_to_cpu(*list++); 491 u32 chn_config = be32_to_cpu(*list++); 492 493 /* Channel 0 and 1 are software channels */ 494 if (chn_id < 2) 495 continue; 496 497 writel_relaxed(chn_config, sadi->base + 498 REG_ADI_CHN_ADDR(chn_id)); 499 500 if (chn_id < 32) { 501 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN); 502 value |= BIT(chn_id); 503 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN); 504 } else if (chn_id < ADI_HW_CHNS) { 505 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1); 506 value |= BIT(chn_id - 32); 507 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1); 508 } 509 } 510 } 511 sprd_adi_probe(struct platform_device * pdev)512 static int sprd_adi_probe(struct platform_device *pdev) 513 { 514 struct device_node *np = pdev->dev.of_node; 515 const struct sprd_adi_data *data; 516 struct spi_controller *ctlr; 517 struct sprd_adi *sadi; 518 struct resource *res; 519 u16 num_chipselect; 520 int ret; 521 522 if (!np) { 523 dev_err(&pdev->dev, "can not find the adi bus node\n"); 524 return -ENODEV; 525 } 526 527 data = of_device_get_match_data(&pdev->dev); 528 if (!data) { 529 dev_err(&pdev->dev, "no matching driver data found\n"); 530 return -EINVAL; 531 } 532 533 pdev->id = of_alias_get_id(np, "spi"); 534 num_chipselect = of_get_child_count(np); 535 536 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi)); 537 if (!ctlr) 538 return -ENOMEM; 539 540 dev_set_drvdata(&pdev->dev, ctlr); 541 sadi = spi_controller_get_devdata(ctlr); 542 543 sadi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 544 if (IS_ERR(sadi->base)) { 545 ret = PTR_ERR(sadi->base); 546 goto put_ctlr; 547 } 548 549 sadi->slave_vbase = (unsigned long)sadi->base + 550 data->slave_offset; 551 sadi->slave_pbase = res->start + data->slave_offset; 552 sadi->ctlr = ctlr; 553 sadi->dev = &pdev->dev; 554 sadi->data = data; 555 ret = of_hwspin_lock_get_id(np, 0); 556 if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) { 557 sadi->hwlock = 558 devm_hwspin_lock_request_specific(&pdev->dev, ret); 559 if (!sadi->hwlock) { 560 ret = -ENXIO; 561 goto put_ctlr; 562 } 563 } else { 564 switch (ret) { 565 case -ENOENT: 566 dev_info(&pdev->dev, "no hardware spinlock supplied\n"); 567 break; 568 default: 569 dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n"); 570 goto put_ctlr; 571 } 572 } 573 574 sprd_adi_hw_init(sadi); 575 576 if (sadi->data->wdg_rst) 577 sadi->data->wdg_rst(sadi); 578 579 ctlr->dev.of_node = pdev->dev.of_node; 580 ctlr->bus_num = pdev->id; 581 ctlr->num_chipselect = num_chipselect; 582 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; 583 ctlr->bits_per_word_mask = 0; 584 ctlr->transfer_one = sprd_adi_transfer_one; 585 586 ret = devm_spi_register_controller(&pdev->dev, ctlr); 587 if (ret) { 588 dev_err(&pdev->dev, "failed to register SPI controller\n"); 589 goto put_ctlr; 590 } 591 592 if (sadi->data->restart) { 593 sadi->restart_handler.notifier_call = sadi->data->restart; 594 sadi->restart_handler.priority = 128; 595 ret = register_restart_handler(&sadi->restart_handler); 596 if (ret) { 597 dev_err(&pdev->dev, "can not register restart handler\n"); 598 goto put_ctlr; 599 } 600 } 601 602 return 0; 603 604 put_ctlr: 605 spi_controller_put(ctlr); 606 return ret; 607 } 608 sprd_adi_remove(struct platform_device * pdev)609 static void sprd_adi_remove(struct platform_device *pdev) 610 { 611 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); 612 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr); 613 614 unregister_restart_handler(&sadi->restart_handler); 615 } 616 617 static struct sprd_adi_data sc9860_data = { 618 .slave_offset = ADI_10BIT_SLAVE_OFFSET, 619 .slave_addr_size = ADI_10BIT_SLAVE_ADDR_SIZE, 620 .read_check = sprd_adi_read_check_r2, 621 .restart = sprd_adi_restart_sc9860, 622 .wdg_rst = sprd_adi_set_wdt_rst_mode, 623 }; 624 625 static struct sprd_adi_data sc9863_data = { 626 .slave_offset = ADI_12BIT_SLAVE_OFFSET, 627 .slave_addr_size = ADI_12BIT_SLAVE_ADDR_SIZE, 628 .read_check = sprd_adi_read_check_r3, 629 }; 630 631 static struct sprd_adi_data ums512_data = { 632 .slave_offset = ADI_15BIT_SLAVE_OFFSET, 633 .slave_addr_size = ADI_15BIT_SLAVE_ADDR_SIZE, 634 .read_check = sprd_adi_read_check_r3, 635 }; 636 637 static const struct of_device_id sprd_adi_of_match[] = { 638 { 639 .compatible = "sprd,sc9860-adi", 640 .data = &sc9860_data, 641 }, 642 { 643 .compatible = "sprd,sc9863-adi", 644 .data = &sc9863_data, 645 }, 646 { 647 .compatible = "sprd,ums512-adi", 648 .data = &ums512_data, 649 }, 650 { }, 651 }; 652 MODULE_DEVICE_TABLE(of, sprd_adi_of_match); 653 654 static struct platform_driver sprd_adi_driver = { 655 .driver = { 656 .name = "sprd-adi", 657 .of_match_table = sprd_adi_of_match, 658 }, 659 .probe = sprd_adi_probe, 660 .remove_new = sprd_adi_remove, 661 }; 662 module_platform_driver(sprd_adi_driver); 663 664 MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver"); 665 MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>"); 666 MODULE_LICENSE("GPL v2"); 667