1 /*
2  * Copyright (c)  2018-present Facebook. All Rights Reserved.
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #pragma once
18 
19 enum ipmi_fb_net_fns
20 {
21     NETFN_OEM_USB_DBG_REQ = 0x3C,
22     NETFN_OEM_USB_DBG_RES = 0x3D,
23 };
24 
25 // OEM Command Codes for USB basded Debug Card
26 enum oem_usb_dbg_cmds
27 {
28     CMD_OEM_USB_DBG_GET_FRAME_INFO = 0x1,
29     CMD_OEM_USB_DBG_GET_UPDATED_FRAMES = 0x2,
30     CMD_OEM_USB_DBG_GET_POST_DESC = 0x3,
31     CMD_OEM_USB_DBG_GET_GPIO_DESC = 0x4,
32     CMD_OEM_USB_DBG_GET_FRAME_DATA = 0x5,
33     CMD_OEM_USB_DBG_CTRL_PANEL = 0x6,
34 };
35 
36 // OEM Command Codes for FB 1S/2S servers
37 enum fb_oem_cmds
38 {
39     CMD_OEM_ADD_RAS_SEL = 0x10,
40     CMD_OEM_ADD_IMC_LOG = 0x11,
41     CMD_OEM_SET_MAC_ADDR = 0x18,
42     CMD_OEM_GET_MAC_ADDR = 0x19,
43     CMD_OEM_SET_PROC_INFO = 0x1A,
44     CMD_OEM_GET_PROC_INFO = 0x1B,
45     CMD_OEM_SET_DIMM_INFO = 0x1C,
46     CMD_OEM_GET_DIMM_INFO = 0x1D,
47     CMD_OEM_BYPASS_CMD = 0x34,
48     CMD_OEM_GET_BOARD_ID = 0x37,
49     CMD_OEM_GET_80PORT_RECORD = 0x49,
50     CMD_OEM_SET_BOOT_ORDER = 0x52,
51     CMD_OEM_GET_BOOT_ORDER = 0x53,
52     CMD_OEM_GET_HTTPS_BOOT_DATA = 0x57,
53     CMD_OEM_GET_HTTPS_BOOT_ATTR = 0x58,
54     CMD_OEM_SET_MACHINE_CONFIG_INFO = 0x6A,
55     CMD_OEM_LEGACY_SET_PPR = 0x6E,
56     CMD_OEM_LEGACY_GET_PPR = 0x6F,
57     CMD_OEM_SET_POST_START = 0x73,
58     CMD_OEM_SET_POST_END = 0x74,
59     CMD_OEM_SET_PPIN_INFO = 0x77,
60     CMD_OEM_SET_ADR_TRIGGER = 0x7A,
61     CMD_OEM_GET_PLAT_INFO = 0x7E,
62     CMD_OEM_SET_SYSTEM_GUID = 0xEF,
63     CMD_OEM_GET_FW_INFO = 0xF2,
64     CMD_OEM_SLED_AC_CYCLE = 0xF3,
65     CMD_OEM_GET_PCIE_CONFIG = 0xF4,
66     CMD_OEM_SET_IMC_VERSION = 0xF5,
67     CMD_OEM_SET_FW_UPDATE_STATE = 0xF6,
68     CMD_OEM_GET_BIOS_FLASH_INFO = 0x55,
69     CMD_OEM_GET_PCIE_PORT_CONFIG = 0x80,
70     CMD_OEM_SET_PCIE_PORT_CONFIG = 0x81,
71     CMD_OEM_GET_TPM_PRESENCE = 0x82,
72     CMD_OEM_SET_TPM_PRESENCE = 0x83,
73     CMD_OEM_SET_BIOS_FLASH_INFO = 0x87,
74     CMD_OEM_SET_PPR = 0x90,
75     CMD_OEM_GET_PPR = 0x91,
76     CMD_OEM_SET_IPMB_OFFONLINE = 0xE6,
77     CMD_OEM_RISER_SENSOR_MON_CRL = 0xE7,
78     CMD_OEM_BBV_POWER_CYCLE = 0xE9,
79     CMD_OEM_CRASHDUMP = 0x70,
80 
81 };
82 
83 // OEM Command Codes for QC
84 enum fb_oem_qc_cmds
85 {
86     CMD_OEM_Q_SET_PROC_INFO = 0x10,
87     CMD_OEM_Q_GET_PROC_INFO = 0x11,
88     CMD_OEM_Q_SET_DIMM_INFO = 0x12,
89     CMD_OEM_Q_GET_DIMM_INFO = 0x13,
90     CMD_OEM_Q_SET_DRIVE_INFO = 0x14,
91     CMD_OEM_Q_GET_DRIVE_INFO = 0x15,
92 };
93 
94 /* To handle the processor product
95  * name (ASCII code). */
96 #define MAX_BUF 50
97 
98 #define BMC_POS 0
99 #define SIZE_CPU_PPIN 8
100 #define SIZE_BOOT_ORDER 6
101 #define BOOT_MODE_UEFI 0x01
102 #define BOOT_MODE_CMOS_CLR 0x02
103 #define BOOT_MODE_FORCE_BOOT 0x04
104 #define BOOT_MODE_BOOT_FLAG 0x80
105 #define BIT_0 0x01
106 #define BIT_1 0x02
107 #define BIT_2 0x04
108 #define BIT_3 0x08
109 
110 #define KEY_PROC_NAME "product_name"
111 #define KEY_BASIC_INFO "basic_info"
112 #define DIMM_TYPE "type"
113 #define DIMM_SPEED "speed"
114 #define JSON_DIMM_TYPE_FILE "/usr/share/lcd-debug/dimm_type.json"
115 #define JSON_OEM_DATA_FILE "/etc/oemData.json"
116 #define KEY_PPIN_INFO "mb_cpu_ppin"
117 #define KEY_MC_CONFIG "mb_machine_config"
118 #define KEY_MC_CHAS_TYPE "chassis_type"
119 #define KEY_MC_MB_TYPE "mb_type"
120 #define KEY_MC_PROC_CNT "processor_count"
121 #define KEY_MC_MEM_CNT "memory_count"
122 #define KEY_MC_HDD35_CNT "hdd35_count"
123 #define KEY_MC_HDD25_CNT "hdd25_count"
124 #define KEY_MC_RSR_TYPE "riser_type"
125 #define KEY_MC_PCIE_LOC "pcie_card_loc"
126 #define KEY_MC_SLOT1_TYPE "slot1_pcie_type"
127 #define KEY_MC_SLOT2_TYPE "slot2_pcie_type"
128 #define KEY_MC_SLOT3_TYPE "slot3_pcie_type"
129 #define KEY_MC_SLOT4_TYPE "slot4_pcie_type"
130 #define KEY_MC_AEP_CNT "aep_mem_count"
131 
132 #define KEY_TS_SLED "timestamp_sled"
133 #define KEY_BOOT_ORDER "server_boot_order"
134 #define KEY_BOOT_MODE "boot_mode"
135 #define KEY_BOOT_SEQ "boot_sequence"
136 #define KEY_SYS_CONFIG "sys_config"
137 #define KEY_DIMM_INDEX "dimm_index"
138 #define KEY_DIMM_TYPE "dimm_type"
139 #define KEY_DIMM_SPEED "dimm_speed"
140 #define KEY_DIMM_SIZE "dimm_size"
141 #define KEY_PPR "ppr"
142 #define KEY_PPR_ACTION "ppr_row_action"
143 #define KEY_PPR_ROW_COUNT "ppr_row_count"
144 #define KEY_PPR_INDEX "ppr_index"
145 #define KEY_PPR_ROW_ADDR "ppr_row_addr"
146 #define KEY_PPR_HST_DATA "ppr_history_data"
147 #define CC_PARAM_NOT_SUPP_IN_CURR_STATE 0xD5
148 #define PPR_ROW_ADDR_LEN 8
149 #define PPR_HST_DATA_LEN 17
150 
151 #define BOOT_SEQ_ARRAY_SIZE 10
152 
153 const char* bootSeqDefine[] = {"USB_DEV", "NET_IPV4", "SATA_HDD", "SATA_CD",
154                                "OTHER",   "",         "",         "",
155                                "",        "NET_IPV6"};
156 
157 /*
158 Byte 2-6– Boot sequence
159     Bit 2:0 – boot device id
160         000b: USB device
161         001b: Network
162         010b: SATA HDD
163         011b: SATA-CDROM
164         100b: Other removable Device
165     Bit 7:3 – reserve for boot device special request
166         If Bit 2:0 is 001b (Network), Bit3 is IPv4/IPv6 order
167            Bit3=0b: IPv4 first
168            Bit3=1b: IPv6 first
169 */
170 std::map<std::string, int> bootMap = {
171     {"USB_DEV", 0},  {"NET_IPV4", 1}, {"NET_IPV6", 9},
172     {"SATA_HDD", 2}, {"SATA_CD", 3},  {"OTHER", 4}};
173 
174 std::map<size_t, std::string> dimmVenMap = {
175     {0xce, "Samsung"}, {0xad, "Hynix"}, {0x2c, "Micron"}};
176 
177 const char* chassisType[] = {"ORV1", "ORV2"};
178 const char* mbType[] = {"SS", "DS", "TYPE3"};
179 const char* riserType[] = {"NO_CARD", "2_SLOT", "3_SLOT"};
180 const char* pcieType[] = {"ABSENT", "AVA1",     "AVA2", "AVA3",
181                           "AVA4",   "Re-timer", "HBA",  "OTHER"};
182 
183 enum fb_ppr_sel
184 {
185     PPR_ACTION = 1,
186     PPR_ROW_COUNT,
187     PPR_ROW_ADDR,
188     PPR_HISTORY_DATA,
189 };
190 
191 typedef struct
192 {
193     uint8_t chassis_type; // 00 - ORv1, 01 - ORv2 (FBTP)
194     uint8_t mb_type;      // 00 - SS, 01 - DS, 02 - Type3
195     uint8_t proc_cnt;
196     uint8_t mem_cnt;
197     uint8_t hdd35_cnt;       // 0/1 in FBTP, ff - unknown
198     uint8_t hdd25_cnt;       // 0 for FBTP
199     uint8_t riser_type;      // 00 - not installed, 01 - 2 slot, 02 - 3 slot
200     uint8_t pcie_card_loc;   // Bit0 - Slot1 Present/Absent, Bit1 - Slot 2
201                              // Present/Absent etc.
202     uint8_t slot1_pcie_type; // Always NIC for FBTP
203     uint8_t slot2_pcie_type; // 2-4: 00 - Absent, 01 - AVA 2 x m.2, 02 - AVA
204                              // 3x m.2,
205     uint8_t slot3_pcie_type; // 03 - AVA 4 x m.2, 04 - Re-timer, 05 - HBA
206     uint8_t slot4_pcie_type; // 06 - Other flash cards (Intel, HGST),
207                              // 80 - Unknown
208     uint8_t aep_mem_cnt;
209 } machineConfigInfo_t;
210 
211 /* FB OEM QC commands data structures */
212 
213 #define NETFUN_FB_OEM_QC 0x36
214 
215 #define KEY_Q_PROC_INFO "q_proc_info"
216 #define KEY_PROC_INDEX "proc_index"
217 #define KEY_Q_DIMM_INFO "q_dimm_info"
218 #define KEY_DIMM_INDEX "dimm_index"
219 #define KEY_Q_DRIVE_INFO "q_drive_info"
220 #define KEY_HDD_CTRL_TYPE "hdd_ctrl_type"
221 #define KEY_HDD_INDEX "hdd_index"
222 
223 typedef struct
224 {
225     uint8_t mfrId[3];
226     uint8_t procIndex;
227     uint8_t paramSel;
228     uint8_t data[];
229 } qProcInfo_t;
230 
231 typedef struct
232 {
233     uint8_t mfrId[3];
234     uint8_t dimmIndex;
235     uint8_t paramSel;
236     uint8_t data[];
237 } qDimmInfo_t;
238 
239 typedef struct
240 {
241     uint8_t mfrId[3];
242     uint8_t hddCtrlType;
243     uint8_t hddIndex;
244     uint8_t paramSel;
245     uint8_t data[];
246 } qDriveInfo_t;
247 
248 enum class HttpsBootAttr : uint8_t
249 {
250     certSize = 0x00,
251     certCrc = 0x01
252 };
253 
254 enum class BankType : uint8_t
255 {
256     mca = 0x01,
257     virt = 0x02,
258     cpuWdt = 0x03,
259     tcdx = 0x06,
260     cake = 0x07,
261     pie0 = 0x08,
262     iom = 0x09,
263     ccix = 0x0a,
264     cs = 0x0b,
265     pcieAer = 0x0c,
266     wdtReg = 0x0d,
267     ctrl = 0x80,
268     crdHdr = 0x81
269 };
270 
271 enum class CrdState
272 {
273     free = 0x01,
274     waitData = 0x02,
275     packing = 0x03
276 };
277 
278 enum class CrdCtrl
279 {
280     getState = 0x01,
281     finish = 0x02
282 };
283 
284 constexpr uint8_t ccmNum = 8;
285 constexpr uint8_t tcdxNum = 12;
286 constexpr uint8_t cakeNum = 6;
287 constexpr uint8_t pie0Num = 1;
288 constexpr uint8_t iomNum = 4;
289 constexpr uint8_t ccixNum = 4;
290 constexpr uint8_t csNum = 8;
291 
292 #pragma pack(push, 1)
293 
294 struct HttpsDataReq
295 {
296     uint16_t offset;
297     uint8_t length;
298 };
299 
300 struct CrdCmdHdr
301 {
302     uint8_t version;
303     uint8_t reserved[3];
304 };
305 
306 struct CrdBankHdr
307 {
308     BankType bankType;
309     uint8_t version;
310     union
311     {
312         struct
313         {
314             uint8_t bankId;
315             uint8_t coreId;
316         };
317         uint8_t reserved[2];
318     };
319 };
320 
321 struct CrashDumpHdr
322 {
323     CrdCmdHdr cmdHdr;
324     CrdBankHdr bankHdr;
325 };
326 
327 // Type 0x01: MCA Bank
328 struct CrdMcaBank
329 {
330     uint64_t mcaCtrl;
331     uint64_t mcaSts;
332     uint64_t mcaAddr;
333     uint64_t mcaMisc0;
334     uint64_t mcaCtrlMask;
335     uint64_t mcaConfig;
336     uint64_t mcaIpid;
337     uint64_t mcaSynd;
338     uint64_t mcaDestat;
339     uint64_t mcaDeaddr;
340     uint64_t mcaMisc1;
341 };
342 
343 struct BankCorePair
344 {
345     uint8_t bankId;
346     uint8_t coreId;
347 };
348 
349 // Type 0x02: Virtual/Global Bank
350 struct CrdVirtualBankV2
351 {
352     uint32_t s5ResetSts;
353     uint32_t breakevent;
354     uint16_t mcaCount;
355     uint16_t procNum;
356     uint32_t apicId;
357     uint32_t eax;
358     uint32_t ebx;
359     uint32_t ecx;
360     uint32_t edx;
361     struct BankCorePair mcaList[];
362 };
363 
364 struct CrdVirtualBankV3
365 {
366     uint32_t s5ResetSts;
367     uint32_t breakevent;
368     uint32_t rstSts;
369     uint16_t mcaCount;
370     uint16_t procNum;
371     uint32_t apicId;
372     uint32_t eax;
373     uint32_t ebx;
374     uint32_t ecx;
375     uint32_t edx;
376     struct BankCorePair mcaList[];
377 };
378 
379 // Type 0x03: CPU/Data Fabric Watchdog Timer Bank
380 struct CrdCpuWdtBank
381 {
382     uint32_t hwAssertStsHi[ccmNum];
383     uint32_t hwAssertStsLo[ccmNum];
384     uint32_t origWdtAddrLogHi[ccmNum];
385     uint32_t origWdtAddrLogLo[ccmNum];
386     uint32_t hwAssertMskHi[ccmNum];
387     uint32_t hwAssertMskLo[ccmNum];
388     uint32_t origWdtAddrLogStat[ccmNum];
389 };
390 
391 template <size_t N>
392 struct CrdHwAssertBank
393 {
394     uint32_t hwAssertStsHi[N];
395     uint32_t hwAssertStsLo[N];
396     uint32_t hwAssertMskHi[N];
397     uint32_t hwAssertMskLo[N];
398 };
399 
400 // Type 0x0C: PCIe AER Bank
401 struct CrdPcieAerBank
402 {
403     uint8_t bus;
404     uint8_t dev;
405     uint8_t fun;
406     uint16_t cmd;
407     uint16_t sts;
408     uint16_t slot;
409     uint8_t secondBus;
410     uint16_t vendorId;
411     uint16_t devId;
412     uint16_t classCodeLo; // Class Code 3 byte
413     uint8_t classCodeHi;
414     uint16_t secondSts;
415     uint16_t ctrl;
416     uint32_t uncorrErrSts;
417     uint32_t uncorrErrMsk;
418     uint32_t uncorrErrSeverity;
419     uint32_t corrErrSts;
420     uint32_t corrErrMsk;
421     uint32_t hdrLogDw0;
422     uint32_t hdrLogDw1;
423     uint32_t hdrLogDw2;
424     uint32_t hdrLogDw3;
425     uint32_t rootErrSts;
426     uint16_t corrErrSrcId;
427     uint16_t errSrcId;
428     uint32_t laneErrSts;
429 };
430 
431 // Type 0x0D: SMU/PSP/PTDMA Watchdog Timers Register Bank
432 struct CrdWdtRegBank
433 {
434     uint8_t nbio;
435     char name[32];
436     uint32_t addr;
437     uint8_t count;
438     uint32_t data[];
439 };
440 
441 // Type 0x81: Crashdump Header
442 struct CrdHdrBank
443 {
444     uint64_t ppin;
445     uint32_t ucodeVer;
446     uint32_t pmio;
447 };
448 
449 #pragma pack(pop)
450 
451 const char* cpuInfoKey[] = {"",     "product_name", "basic_info",
452                             "type", "micro_code",   "turbo_mode"};
453 
454 const char* dimmInfoKey[] = {
455     "",           "location",        "type",   "speed",      "part_name",
456     "serial_num", "manufacturer_id", "status", "present_bit"};
457 
458 const char* driveInfoKey[] = {"location",   "serial_num", "model_name",
459                               "fw_version", "capacity",   "quantity",
460                               "type",       "wwn"};
461 
462 const char* ctrlTypeKey[] = {"bios", "expander", "lsi"};
463