1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/mach-imx/sys_proto.h>
12 #include <netdev.h>
13 #ifdef CONFIG_FSL_ESDHC
14 #include <fsl_esdhc.h>
15 #endif
16
17 #ifdef CONFIG_FSL_ESDHC
18 DECLARE_GLOBAL_DATA_PTR;
19 #endif
20
21 static char soc_type[] = "xx0";
22
23 #ifdef CONFIG_MXC_OCOTP
enable_ocotp_clk(unsigned char enable)24 void enable_ocotp_clk(unsigned char enable)
25 {
26 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
27 u32 reg;
28
29 reg = readl(&ccm->ccgr6);
30 if (enable)
31 reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
32 else
33 reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
34 writel(reg, &ccm->ccgr6);
35 }
36 #endif
37
get_mcu_main_clk(void)38 static u32 get_mcu_main_clk(void)
39 {
40 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
41 u32 ccm_ccsr, ccm_cacrr, armclk_div;
42 u32 sysclk_sel, pll_pfd_sel = 0;
43 u32 freq = 0;
44
45 ccm_ccsr = readl(&ccm->ccsr);
46 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
47 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
48
49 ccm_cacrr = readl(&ccm->cacrr);
50 armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
51 armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
52 armclk_div += 1;
53
54 switch (sysclk_sel) {
55 case 0:
56 freq = FASE_CLK_FREQ;
57 break;
58 case 1:
59 freq = SLOW_CLK_FREQ;
60 break;
61 case 2:
62 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
63 pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
64 if (pll_pfd_sel == 0)
65 freq = PLL2_MAIN_FREQ;
66 else if (pll_pfd_sel == 1)
67 freq = PLL2_PFD1_FREQ;
68 else if (pll_pfd_sel == 2)
69 freq = PLL2_PFD2_FREQ;
70 else if (pll_pfd_sel == 3)
71 freq = PLL2_PFD3_FREQ;
72 else if (pll_pfd_sel == 4)
73 freq = PLL2_PFD4_FREQ;
74 break;
75 case 3:
76 freq = PLL2_MAIN_FREQ;
77 break;
78 case 4:
79 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
80 pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
81 if (pll_pfd_sel == 0)
82 freq = PLL1_MAIN_FREQ;
83 else if (pll_pfd_sel == 1)
84 freq = PLL1_PFD1_FREQ;
85 else if (pll_pfd_sel == 2)
86 freq = PLL1_PFD2_FREQ;
87 else if (pll_pfd_sel == 3)
88 freq = PLL1_PFD3_FREQ;
89 else if (pll_pfd_sel == 4)
90 freq = PLL1_PFD4_FREQ;
91 break;
92 case 5:
93 freq = PLL3_MAIN_FREQ;
94 break;
95 default:
96 printf("unsupported system clock select\n");
97 }
98
99 return freq / armclk_div;
100 }
101
get_bus_clk(void)102 static u32 get_bus_clk(void)
103 {
104 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
105 u32 ccm_cacrr, busclk_div;
106
107 ccm_cacrr = readl(&ccm->cacrr);
108
109 busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
110 busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
111 busclk_div += 1;
112
113 return get_mcu_main_clk() / busclk_div;
114 }
115
get_ipg_clk(void)116 static u32 get_ipg_clk(void)
117 {
118 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
119 u32 ccm_cacrr, ipgclk_div;
120
121 ccm_cacrr = readl(&ccm->cacrr);
122
123 ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
124 ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
125 ipgclk_div += 1;
126
127 return get_bus_clk() / ipgclk_div;
128 }
129
get_uart_clk(void)130 static u32 get_uart_clk(void)
131 {
132 return get_ipg_clk();
133 }
134
get_sdhc_clk(void)135 static u32 get_sdhc_clk(void)
136 {
137 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
138 u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
139 u32 freq = 0;
140
141 ccm_cscmr1 = readl(&ccm->cscmr1);
142 sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
143 sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
144
145 ccm_cscdr2 = readl(&ccm->cscdr2);
146 sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
147 sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
148 sdhc_clk_div += 1;
149
150 switch (sdhc_clk_sel) {
151 case 0:
152 freq = PLL3_MAIN_FREQ;
153 break;
154 case 1:
155 freq = PLL3_PFD3_FREQ;
156 break;
157 case 2:
158 freq = PLL1_PFD3_FREQ;
159 break;
160 case 3:
161 freq = get_bus_clk();
162 break;
163 }
164
165 return freq / sdhc_clk_div;
166 }
167
get_fec_clk(void)168 u32 get_fec_clk(void)
169 {
170 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
171 u32 ccm_cscmr2, rmii_clk_sel;
172 u32 freq = 0;
173
174 ccm_cscmr2 = readl(&ccm->cscmr2);
175 rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
176 rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
177
178 switch (rmii_clk_sel) {
179 case 0:
180 freq = ENET_EXTERNAL_CLK;
181 break;
182 case 1:
183 freq = AUDIO_EXTERNAL_CLK;
184 break;
185 case 2:
186 freq = PLL5_MAIN_FREQ;
187 break;
188 case 3:
189 freq = PLL5_MAIN_FREQ / 2;
190 break;
191 }
192
193 return freq;
194 }
195
get_i2c_clk(void)196 static u32 get_i2c_clk(void)
197 {
198 return get_ipg_clk();
199 }
200
get_dspi_clk(void)201 static u32 get_dspi_clk(void)
202 {
203 return get_ipg_clk();
204 }
205
get_lpuart_clk(void)206 u32 get_lpuart_clk(void)
207 {
208 return get_uart_clk();
209 }
210
mxc_get_clock(enum mxc_clock clk)211 unsigned int mxc_get_clock(enum mxc_clock clk)
212 {
213 switch (clk) {
214 case MXC_ARM_CLK:
215 return get_mcu_main_clk();
216 case MXC_BUS_CLK:
217 return get_bus_clk();
218 case MXC_IPG_CLK:
219 return get_ipg_clk();
220 case MXC_UART_CLK:
221 return get_uart_clk();
222 case MXC_ESDHC_CLK:
223 return get_sdhc_clk();
224 case MXC_FEC_CLK:
225 return get_fec_clk();
226 case MXC_I2C_CLK:
227 return get_i2c_clk();
228 case MXC_DSPI_CLK:
229 return get_dspi_clk();
230 default:
231 break;
232 }
233 return -1;
234 }
235
236 /* Dump some core clocks */
do_vf610_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])237 int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
238 char * const argv[])
239 {
240 printf("\n");
241 printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
242 printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
243 printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
244
245 return 0;
246 }
247
248 U_BOOT_CMD(
249 clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
250 "display clocks",
251 ""
252 );
253
254 #ifdef CONFIG_FEC_MXC
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)255 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
256 {
257 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
258 struct fuse_bank *bank = &ocotp->bank[4];
259 struct fuse_bank4_regs *fuse =
260 (struct fuse_bank4_regs *)bank->fuse_regs;
261
262 u32 value = readl(&fuse->mac_addr0);
263 mac[0] = (value >> 8);
264 mac[1] = value;
265
266 value = readl(&fuse->mac_addr1);
267 mac[2] = value >> 24;
268 mac[3] = value >> 16;
269 mac[4] = value >> 8;
270 mac[5] = value;
271 }
272 #endif
273
get_cpu_rev(void)274 u32 get_cpu_rev(void)
275 {
276 return MXC_CPU_VF610 << 12;
277 }
278
279 #if defined(CONFIG_DISPLAY_CPUINFO)
get_reset_cause(void)280 static char *get_reset_cause(void)
281 {
282 u32 cause;
283 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
284
285 cause = readl(&src_regs->srsr);
286 writel(cause, &src_regs->srsr);
287
288 if (cause & SRC_SRSR_POR_RST)
289 return "POWER ON RESET";
290 else if (cause & SRC_SRSR_WDOG_A5)
291 return "WDOG A5";
292 else if (cause & SRC_SRSR_WDOG_M4)
293 return "WDOG M4";
294 else if (cause & SRC_SRSR_JTAG_RST)
295 return "JTAG HIGH-Z";
296 else if (cause & SRC_SRSR_SW_RST)
297 return "SW RESET";
298 else if (cause & SRC_SRSR_RESETB)
299 return "EXTERNAL RESET";
300 else
301 return "unknown reset";
302 }
303
print_cpuinfo(void)304 int print_cpuinfo(void)
305 {
306 printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
307 soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
308 printf("Reset cause: %s\n", get_reset_cause());
309
310 return 0;
311 }
312 #endif
313
arch_cpu_init(void)314 int arch_cpu_init(void)
315 {
316 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
317
318 soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
319 soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
320
321 return 0;
322 }
323
324 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)325 int arch_misc_init(void)
326 {
327 char soc[6];
328
329 strcpy(soc, "vf");
330 strcat(soc, soc_type);
331 env_set("soc", soc);
332
333 return 0;
334 }
335 #endif
336
cpu_eth_init(bd_t * bis)337 int cpu_eth_init(bd_t *bis)
338 {
339 int rc = -ENODEV;
340
341 #if defined(CONFIG_FEC_MXC)
342 rc = fecmxc_initialize(bis);
343 #endif
344
345 return rc;
346 }
347
348 #ifdef CONFIG_FSL_ESDHC
cpu_mmc_init(bd_t * bis)349 int cpu_mmc_init(bd_t *bis)
350 {
351 return fsl_esdhc_mmc_init(bis);
352 }
353 #endif
354
get_clocks(void)355 int get_clocks(void)
356 {
357 #ifdef CONFIG_FSL_ESDHC
358 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
359 #endif
360 return 0;
361 }
362
363 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)364 void enable_caches(void)
365 {
366 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
367 enum dcache_option option = DCACHE_WRITETHROUGH;
368 #else
369 enum dcache_option option = DCACHE_WRITEBACK;
370 #endif
371 dcache_enable();
372 icache_enable();
373
374 /* Enable caching on OCRAM */
375 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
376 }
377 #endif
378