1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4  * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <miiphy.h>
10 #include <tpm-v1.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm-generic/gpio.h>
14 
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
17 
18 #include "keyprogram.h"
19 #include "dt_helpers.h"
20 #include "hydra.h"
21 #include "ihs_phys.h"
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
26 #define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
27 
28 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
29 #define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
30 #define DB_GP_88F68XX_GPP_POL_LOW	0x0
31 #define DB_GP_88F68XX_GPP_POL_MID	0x0
32 
get_tpm(struct udevice ** devp)33 static int get_tpm(struct udevice **devp)
34 {
35 	int rc;
36 
37 	rc = uclass_first_device_err(UCLASS_TPM, devp);
38 	if (rc) {
39 		printf("Could not find TPM (ret=%d)\n", rc);
40 		return CMD_RET_FAILURE;
41 	}
42 
43 	return 0;
44 }
45 
46 /*
47  * Define the DDR layout / topology here in the board file. This will
48  * be used by the DDR3 init code in the SPL U-Boot version to configure
49  * the DDR3 controller.
50  */
51 static struct mv_ddr_topology_map ddr_topology_map = {
52 	DEBUG_LEVEL_ERROR,
53 	0x1, /* active interfaces */
54 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
55 	{ { { {0x1, 0, 0, 0},
56 	      {0x1, 0, 0, 0},
57 	      {0x1, 0, 0, 0},
58 	      {0x1, 0, 0, 0},
59 	      {0x1, 0, 0, 0} },
60 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
61 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
62 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
63 	    MV_DDR_FREQ_533,		/* frequency */
64 	    0, 0,			/* cas_wl cas_l */
65 	    MV_DDR_TEMP_LOW,		/* temperature */
66 	    MV_DDR_TIM_DEFAULT} },	/* timing */
67 	BUS_MASK_32BIT,			/* Busses mask */
68 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
69 	{ {0} },			/* raw spd data */
70 	{0}				/* timing parameters */
71 
72 };
73 
74 static struct serdes_map serdes_topology_map[] = {
75 	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
76 	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
77 	/* SATA tx polarity is inverted */
78 	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
79 	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
80 	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
81 	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
82 };
83 
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)84 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
85 {
86 	*serdes_map_array = serdes_topology_map;
87 	*count = ARRAY_SIZE(serdes_topology_map);
88 	return 0;
89 }
90 
board_pex_config(void)91 void board_pex_config(void)
92 {
93 #ifdef CONFIG_SPL_BUILD
94 	uint k;
95 	struct gpio_desc gpio = {};
96 
97 	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
98 		/* prepare FPGA reconfiguration */
99 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
100 		dm_gpio_set_value(&gpio, 0);
101 
102 		/* give lunatic PCIe clock some time to stabilize */
103 		mdelay(500);
104 
105 		/* start FPGA reconfiguration */
106 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
107 	}
108 
109 	/* wait for FPGA done */
110 	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
111 		for (k = 0; k < 20; ++k) {
112 			if (dm_gpio_get_value(&gpio)) {
113 				printf("FPGA done after %u rounds\n", k);
114 				break;
115 			}
116 			mdelay(100);
117 		}
118 	}
119 
120 	/* disable FPGA reset */
121 	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
122 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
123 		dm_gpio_set_value(&gpio, 1);
124 	}
125 
126 	/* wait for FPGA ready */
127 	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
128 		for (k = 0; k < 2; ++k) {
129 			if (!dm_gpio_get_value(&gpio))
130 				break;
131 			mdelay(100);
132 		}
133 	}
134 #endif
135 }
136 
mv_ddr_topology_map_get(void)137 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
138 {
139 	return &ddr_topology_map;
140 }
141 
board_early_init_f(void)142 int board_early_init_f(void)
143 {
144 #ifdef CONFIG_SPL_BUILD
145 	/* Configure MPP */
146 	writel(0x00111111, MVEBU_MPP_BASE + 0x00);
147 	writel(0x40040000, MVEBU_MPP_BASE + 0x04);
148 	writel(0x00466444, MVEBU_MPP_BASE + 0x08);
149 	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
150 	writel(0x44400000, MVEBU_MPP_BASE + 0x10);
151 	writel(0x20000334, MVEBU_MPP_BASE + 0x14);
152 	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
153 	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
154 
155 	/* Set GPP Out value */
156 	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
157 	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
158 
159 	/* Set GPP Polarity */
160 	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
161 	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
162 
163 	/* Set GPP Out Enable */
164 	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
165 	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
166 #endif
167 
168 	return 0;
169 }
170 
board_init(void)171 int board_init(void)
172 {
173 	/* Address of boot parameters */
174 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
175 
176 	return 0;
177 }
178 
179 #ifndef CONFIG_SPL_BUILD
init_host_phys(struct mii_dev * bus)180 void init_host_phys(struct mii_dev *bus)
181 {
182 	uint k;
183 
184 	for (k = 0; k < 2; ++k) {
185 		struct phy_device *phydev;
186 
187 		phydev = phy_find_by_mask(bus, 1 << k,
188 					  PHY_INTERFACE_MODE_SGMII);
189 
190 		if (phydev)
191 			phy_config(phydev);
192 	}
193 }
194 
ccdc_eth_init(void)195 int ccdc_eth_init(void)
196 {
197 	uint k;
198 	uint octo_phy_mask = 0;
199 	int ret;
200 	struct mii_dev *bus;
201 
202 	/* Init SoC's phys */
203 	bus = miiphy_get_dev_by_name("ethernet@34000");
204 
205 	if (bus)
206 		init_host_phys(bus);
207 
208 	bus = miiphy_get_dev_by_name("ethernet@70000");
209 
210 	if (bus)
211 		init_host_phys(bus);
212 
213 	/* Init octo phys */
214 	octo_phy_mask = calculate_octo_phy_mask();
215 
216 	printf("IHS PHYS: %08x", octo_phy_mask);
217 
218 	ret = init_octo_phys(octo_phy_mask);
219 
220 	if (ret)
221 		return ret;
222 
223 	printf("\n");
224 
225 	if (!get_fpga()) {
226 		puts("fpga was NULL\n");
227 		return 1;
228 	}
229 
230 	/* reset all FPGA-QSGMII instances */
231 	for (k = 0; k < 80; ++k)
232 		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
233 
234 	udelay(100);
235 
236 	for (k = 0; k < 80; ++k)
237 		writel(0, get_fpga()->qsgmii_port_state[k]);
238 	return 0;
239 }
240 
241 #endif
242 
board_late_init(void)243 int board_late_init(void)
244 {
245 #ifndef CONFIG_SPL_BUILD
246 	hydra_initialize();
247 #endif
248 	return 0;
249 }
250 
board_fix_fdt(void * rw_fdt_blob)251 int board_fix_fdt(void *rw_fdt_blob)
252 {
253 	struct udevice *bus = NULL;
254 	uint k;
255 	char name[64];
256 	int err;
257 
258 	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
259 
260 	if (err) {
261 		printf("Could not get I2C bus.\n");
262 		return err;
263 	}
264 
265 	for (k = 0x21; k <= 0x26; k++) {
266 		snprintf(name, 64,
267 			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
268 
269 		if (!dm_i2c_simple_probe(bus, k))
270 			fdt_disable_by_ofname(rw_fdt_blob, name);
271 	}
272 
273 	return 0;
274 }
275 
last_stage_init(void)276 int last_stage_init(void)
277 {
278 	struct udevice *tpm;
279 	int ret;
280 
281 #ifndef CONFIG_SPL_BUILD
282 	ccdc_eth_init();
283 #endif
284 	ret = get_tpm(&tpm);
285 	if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
286 	    tpm_continue_self_test(tpm)) {
287 		return 1;
288 	}
289 
290 	mdelay(37);
291 
292 	flush_keys(tpm);
293 	load_and_run_keyprog(tpm);
294 
295 	return 0;
296 }
297