1 /* 2 * QEMU emulation of an AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015, 2016 David Kiarie Kahurani 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef AMD_IOMMU_H 22 #define AMD_IOMMU_H 23 24 #include "hw/pci/pci.h" 25 #include "hw/i386/x86-iommu.h" 26 #include "qom/object.h" 27 28 #define GENMASK64(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) 29 30 /* Capability registers */ 31 #define AMDVI_CAPAB_BAR_LOW 0x04 32 #define AMDVI_CAPAB_BAR_HIGH 0x08 33 #define AMDVI_CAPAB_RANGE 0x0C 34 #define AMDVI_CAPAB_MISC 0x10 35 36 #define AMDVI_CAPAB_SIZE 0x18 37 #define AMDVI_CAPAB_REG_SIZE 0x04 38 39 /* Capability header data */ 40 #define AMDVI_CAPAB_ID_SEC 0xf 41 #define AMDVI_CAPAB_FLAT_EXT (1 << 28) 42 #define AMDVI_CAPAB_EFR_SUP (1 << 27) 43 #define AMDVI_CAPAB_FLAG_NPCACHE (1 << 26) 44 #define AMDVI_CAPAB_FLAG_HTTUNNEL (1 << 25) 45 #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) 46 #define AMDVI_CAPAB_INIT_TYPE (3 << 16) 47 48 /* No. of used MMIO registers */ 49 #define AMDVI_MMIO_REGS_HIGH 7 50 #define AMDVI_MMIO_REGS_LOW 8 51 52 /* MMIO registers */ 53 #define AMDVI_MMIO_DEVICE_TABLE 0x0000 54 #define AMDVI_MMIO_COMMAND_BASE 0x0008 55 #define AMDVI_MMIO_EVENT_BASE 0x0010 56 #define AMDVI_MMIO_CONTROL 0x0018 57 #define AMDVI_MMIO_EXCL_BASE 0x0020 58 #define AMDVI_MMIO_EXCL_LIMIT 0x0028 59 #define AMDVI_MMIO_EXT_FEATURES 0x0030 60 #define AMDVI_MMIO_COMMAND_HEAD 0x2000 61 #define AMDVI_MMIO_COMMAND_TAIL 0x2008 62 #define AMDVI_MMIO_EVENT_HEAD 0x2010 63 #define AMDVI_MMIO_EVENT_TAIL 0x2018 64 #define AMDVI_MMIO_STATUS 0x2020 65 #define AMDVI_MMIO_PPR_BASE 0x0038 66 #define AMDVI_MMIO_PPR_HEAD 0x2030 67 #define AMDVI_MMIO_PPR_TAIL 0x2038 68 69 #define AMDVI_MMIO_SIZE 0x4000 70 71 #define AMDVI_MMIO_DEVTAB_SIZE_MASK GENMASK64(8, 0) 72 #define AMDVI_MMIO_DEVTAB_BASE_MASK GENMASK64(51, 12) 73 74 #define AMDVI_MMIO_DEVTAB_ENTRY_SIZE 32 75 #define AMDVI_MMIO_DEVTAB_SIZE_UNIT 4096 76 77 /* some of this are similar but just for readability */ 78 #define AMDVI_MMIO_CMDBUF_SIZE_BYTE (AMDVI_MMIO_COMMAND_BASE + 7) 79 #define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f 80 #define AMDVI_MMIO_CMDBUF_BASE_MASK GENMASK64(51, 12) 81 #define AMDVI_MMIO_CMDBUF_HEAD_MASK GENMASK64(18, 4) 82 #define AMDVI_MMIO_CMDBUF_TAIL_MASK GENMASK64(18, 4) 83 84 #define AMDVI_MMIO_EVTLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7) 85 #define AMDVI_MMIO_EVTLOG_SIZE_MASK 0x0f 86 #define AMDVI_MMIO_EVTLOG_BASE_MASK GENMASK64(51, 12) 87 #define AMDVI_MMIO_EVTLOG_HEAD_MASK GENMASK64(18, 4) 88 #define AMDVI_MMIO_EVTLOG_TAIL_MASK GENMASK64(18, 4) 89 90 #define AMDVI_MMIO_PPRLOG_SIZE_BYTE (AMDVI_MMIO_PPR_BASE + 7) 91 #define AMDVI_MMIO_PPRLOG_SIZE_MASK 0x0f 92 #define AMDVI_MMIO_PPRLOG_BASE_MASK GENMASK64(51, 12) 93 #define AMDVI_MMIO_PPRLOG_HEAD_MASK GENMASK64(18, 4) 94 #define AMDVI_MMIO_PPRLOG_TAIL_MASK GENMASK64(18, 4) 95 96 #define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0) 97 #define AMDVI_MMIO_EXCL_ALLOW_MASK (1ULL << 1) 98 #define AMDVI_MMIO_EXCL_LIMIT_MASK GENMASK64(51, 12) 99 #define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff 100 101 /* mmio control register flags */ 102 #define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0) 103 #define AMDVI_MMIO_CONTROL_HTTUNEN (1ULL << 1) 104 #define AMDVI_MMIO_CONTROL_EVENTLOGEN (1ULL << 2) 105 #define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3) 106 #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) 107 #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) 108 #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) 109 110 /* MMIO status register bits */ 111 #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) 112 #define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) 113 #define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) 114 #define AMDVI_MMIO_STATUS_EVENT_INT (1 << 1) 115 #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) 116 117 #define AMDVI_CMDBUF_ID_BYTE 0x07 118 #define AMDVI_CMDBUF_ID_RSHIFT 4 119 120 #define AMDVI_CMD_COMPLETION_WAIT 0x01 121 #define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02 122 #define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03 123 #define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04 124 #define AMDVI_CMD_INVAL_INTR_TABLE 0x05 125 #define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06 126 #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 127 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 128 129 130 #define AMDVI_CMD_INVAL_IOMMU_PAGES_S (1ULL << 0) 131 #define AMDVI_INV_ALL_PAGES (1ULL << 52) 132 133 #define AMDVI_DEVTAB_ENTRY_SIZE 32 134 135 /* Device table entry bits 0:63 */ 136 #define AMDVI_DEV_VALID (1ULL << 0) 137 #define AMDVI_DEV_TRANSLATION_VALID (1ULL << 1) 138 #define AMDVI_DEV_MODE_MASK 0x7 139 #define AMDVI_DEV_MODE_RSHIFT 9 140 #define AMDVI_DEV_PT_ROOT_MASK GENMASK64(51, 12) 141 #define AMDVI_DEV_PT_ROOT_RSHIFT 12 142 #define AMDVI_DEV_PERM_SHIFT 61 143 #define AMDVI_DEV_PERM_READ (1ULL << 61) 144 #define AMDVI_DEV_PERM_WRITE (1ULL << 62) 145 146 /* Device table entry bits 64:127 */ 147 #define AMDVI_DEV_DOMID_ID_MASK GENMASK64(15, 0) 148 149 /* Event codes and flags, as stored in the info field */ 150 #define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12) 151 #define AMDVI_EVENT_IOPF (0x2U << 12) 152 #define AMDVI_EVENT_IOPF_I (1U << 3) 153 #define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12) 154 #define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12) 155 #define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12) 156 #define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12) 157 158 #define AMDVI_EVENT_LEN 16 159 #define AMDVI_PERM_READ (1 << 0) 160 #define AMDVI_PERM_WRITE (1 << 1) 161 162 #define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */ 163 #define AMDVI_FEATURE_PPR (1ULL << 1) /* PPR Support */ 164 #define AMDVI_FEATURE_XT (1ULL << 2) /* x2APIC Support */ 165 #define AMDVI_FEATURE_GT (1ULL << 4) /* Guest Translation */ 166 #define AMDVI_FEATURE_IA (1ULL << 6) /* inval all support */ 167 #define AMDVI_FEATURE_GA (1ULL << 7) /* guest VAPIC support */ 168 #define AMDVI_FEATURE_HE (1ULL << 8) /* hardware error regs */ 169 #define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */ 170 171 /* reserved DTE bits */ 172 #define AMDVI_DTE_QUAD0_RESERVED (GENMASK64(6, 2) | GENMASK64(63, 63)) 173 #define AMDVI_DTE_QUAD1_RESERVED 0 174 #define AMDVI_DTE_QUAD2_RESERVED GENMASK64(53, 52) 175 #define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48)) 176 177 /* AMDVI paging mode */ 178 #define AMDVI_GATS_MODE (2ULL << 12) 179 #define AMDVI_HATS_MODE (2ULL << 10) 180 #define AMDVI_HATS_MODE_RESERVED (3ULL << 10) 181 182 /* Page Table format */ 183 184 #define AMDVI_PTE_PR (1ULL << 0) 185 #define AMDVI_PTE_NEXT_LEVEL_MASK GENMASK64(11, 9) 186 187 #define IOMMU_PTE_PRESENT(pte) ((pte) & AMDVI_PTE_PR) 188 189 /* Using level=0 for leaf PTE at 4K page size */ 190 #define PT_LEVEL_SHIFT(level) (12 + ((level) * 9)) 191 192 /* Return IOVA bit group used to index the Page Table at specific level */ 193 #define PT_LEVEL_INDEX(level, iova) (((iova) >> PT_LEVEL_SHIFT(level)) & \ 194 GENMASK64(8, 0)) 195 196 /* Return the max address for a specified level i.e. max_oaddr */ 197 #define PT_LEVEL_MAX_ADDR(x) (((x) < 5) ? \ 198 ((1ULL << PT_LEVEL_SHIFT((x + 1))) - 1) : \ 199 (~(0ULL))) 200 201 /* Extract the NextLevel field from PTE/PDE */ 202 #define PTE_NEXT_LEVEL(pte) (((pte) & AMDVI_PTE_NEXT_LEVEL_MASK) >> 9) 203 204 /* Take page table level and return default pagetable size for level */ 205 #define PTE_LEVEL_PAGE_SIZE(level) (1ULL << (PT_LEVEL_SHIFT(level))) 206 207 /* 208 * Return address of lower level page table encoded in PTE and specified by 209 * current level and corresponding IOVA bit group at such level. 210 */ 211 #define NEXT_PTE_ADDR(pte, level, iova) (((pte) & AMDVI_DEV_PT_ROOT_MASK) + \ 212 (PT_LEVEL_INDEX(level, iova) * 8)) 213 214 /* 215 * Take a PTE value with mode=0x07 and return the page size it encodes. 216 */ 217 #define PTE_LARGE_PAGE_SIZE(pte) (1ULL << (1 + cto64(((pte) | 0xfffULL)))) 218 219 /* Return number of PTEs to use for a given page size (expected power of 2) */ 220 #define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) 221 222 /* IOTLB */ 223 #define AMDVI_IOTLB_MAX_SIZE 1024 224 #define AMDVI_GET_IOTLB_GFN(addr) (addr >> AMDVI_PAGE_SHIFT_4K) 225 226 /* default extended feature */ 227 #define AMDVI_DEFAULT_EXT_FEATURES \ 228 (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ 229 AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ 230 AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) 231 232 /* capabilities header */ 233 #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ 234 AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ 235 | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \ 236 AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP) 237 238 /* AMDVI default address */ 239 #define AMDVI_BASE_ADDR 0xfed80000ULL 240 241 /* page management constants */ 242 #define AMDVI_PAGE_SHIFT 12 243 #define AMDVI_PAGE_SIZE (1ULL << AMDVI_PAGE_SHIFT) 244 245 #define AMDVI_PAGE_SHIFT_4K 12 246 #define AMDVI_PAGE_MASK_4K GENMASK64(63, 12) 247 248 #define AMDVI_MAX_GVA_ADDR (2UL << 5) 249 #define AMDVI_MAX_PH_ADDR (40UL << 8) 250 #define AMDVI_MAX_VA_ADDR (48UL << 15) 251 252 /* Completion Wait data size */ 253 #define AMDVI_COMPLETION_DATA_SIZE 8 254 255 #define AMDVI_COMMAND_SIZE 16 256 257 #define AMDVI_INT_ADDR_FIRST 0xfee00000 258 #define AMDVI_INT_ADDR_LAST 0xfeefffff 259 #define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1) 260 261 /* SB IOAPIC is always on this device in AMD systems */ 262 #define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 263 264 /* Interrupt remapping errors */ 265 #define AMDVI_IR_ERR 0x1 266 #define AMDVI_IR_GET_IRTE 0x2 267 #define AMDVI_IR_TARGET_ABORT 0x3 268 269 /* Interrupt remapping */ 270 #define AMDVI_IR_REMAP_ENABLE 1ULL 271 #define AMDVI_IR_INTCTL_SHIFT 60 272 #define AMDVI_IR_INTCTL_ABORT 0 273 #define AMDVI_IR_INTCTL_PASS 1 274 #define AMDVI_IR_INTCTL_REMAP 2 275 276 #define AMDVI_IR_PHYS_ADDR_MASK GENMASK64(51, 6) 277 278 /* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */ 279 #define AMDVI_IRTE_OFFSET 0x7ff 280 281 /* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */ 282 #define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0 283 #define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1 284 #define AMDVI_IOAPIC_INT_TYPE_SMI 0x2 285 #define AMDVI_IOAPIC_INT_TYPE_NMI 0x4 286 #define AMDVI_IOAPIC_INT_TYPE_INIT 0x5 287 #define AMDVI_IOAPIC_INT_TYPE_EINT 0x7 288 289 /* Pass through interrupt */ 290 #define AMDVI_DEV_INT_PASS_MASK (1ULL << 56) 291 #define AMDVI_DEV_EINT_PASS_MASK (1ULL << 57) 292 #define AMDVI_DEV_NMI_PASS_MASK (1ULL << 58) 293 #define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62) 294 #define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63) 295 296 /* Interrupt remapping table fields (Guest VAPIC not enabled) */ 297 union irte { 298 uint32_t val; 299 struct { 300 uint32_t valid:1, 301 no_fault:1, 302 int_type:3, 303 rq_eoi:1, 304 dm:1, 305 guest_mode:1, 306 destination:8, 307 vector:8, 308 rsvd:8; 309 } fields; 310 }; 311 312 /* Interrupt remapping table fields (Guest VAPIC is enabled) */ 313 union irte_ga_lo { 314 uint64_t val; 315 316 /* For int remapping */ 317 struct { 318 uint64_t valid:1, 319 no_fault:1, 320 /* ------ */ 321 int_type:3, 322 rq_eoi:1, 323 dm:1, 324 /* ------ */ 325 guest_mode:1, 326 destination:24, 327 rsvd_1:32; 328 } fields_remap; 329 }; 330 331 union irte_ga_hi { 332 uint64_t val; 333 struct { 334 uint64_t vector:8, 335 rsvd_2:48, 336 destination_hi:8; 337 } fields; 338 }; 339 340 struct irte_ga { 341 union irte_ga_lo lo; 342 union irte_ga_hi hi; 343 }; 344 345 #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" 346 OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) 347 348 #define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" 349 OBJECT_DECLARE_SIMPLE_TYPE(AMDVIPCIState, AMD_IOMMU_PCI) 350 351 #define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region" 352 353 typedef struct AMDVIAddressSpace AMDVIAddressSpace; 354 355 /* functions to steal PCI config space */ 356 struct AMDVIPCIState { 357 PCIDevice dev; /* The PCI device itself */ 358 uint32_t capab_offset; /* capability offset pointer */ 359 }; 360 361 struct AMDVIState { 362 X86IOMMUState iommu; /* IOMMU bus device */ 363 AMDVIPCIState *pci; /* IOMMU PCI device */ 364 char *pci_id; /* ID of AMDVI-PCI device, if user created */ 365 366 uint32_t version; 367 368 uint64_t mmio_addr; 369 370 bool enabled; /* IOMMU enabled */ 371 bool cmdbuf_enabled; /* command buffer enabled */ 372 bool evtlog_enabled; /* event log enabled */ 373 bool excl_enabled; 374 375 hwaddr devtab; /* base address device table */ 376 uint64_t devtab_len; /* device table length */ 377 378 hwaddr cmdbuf; /* command buffer base address */ 379 uint64_t cmdbuf_len; /* command buffer length */ 380 uint32_t cmdbuf_head; /* current IOMMU read position */ 381 uint32_t cmdbuf_tail; /* next Software write position */ 382 bool completion_wait_intr; 383 384 hwaddr evtlog; /* base address event log */ 385 bool evtlog_intr; 386 uint32_t evtlog_len; /* event log length */ 387 uint32_t evtlog_head; /* current IOMMU write position */ 388 uint32_t evtlog_tail; /* current Software read position */ 389 390 /* unused for now */ 391 hwaddr excl_base; /* base DVA - IOMMU exclusion range */ 392 hwaddr excl_limit; /* limit of IOMMU exclusion range */ 393 bool excl_allow; /* translate accesses to the exclusion range */ 394 bool excl_enable; /* exclusion range enabled */ 395 396 hwaddr ppr_log; /* base address ppr log */ 397 uint32_t pprlog_len; /* ppr log len */ 398 uint32_t pprlog_head; /* ppr log head */ 399 uint32_t pprlog_tail; /* ppr log tail */ 400 401 MemoryRegion mr_mmio; /* MMIO region */ 402 MemoryRegion mr_sys; 403 MemoryRegion mr_nodma; 404 MemoryRegion mr_ir; 405 uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */ 406 uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ 407 uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */ 408 bool mmio_enabled; 409 410 /* for each served device */ 411 GHashTable *address_spaces; 412 413 /* list of address spaces with registered notifiers */ 414 QLIST_HEAD(, AMDVIAddressSpace) amdvi_as_with_notifiers; 415 416 /* IOTLB */ 417 GHashTable *iotlb; 418 419 /* Interrupt remapping */ 420 bool ga_enabled; 421 bool xtsup; 422 423 /* DMA address translation */ 424 bool dma_remap; 425 }; 426 427 uint64_t amdvi_extended_feature_register(AMDVIState *s); 428 429 #endif 430