1 #ifndef QEMU_PCI_DEVICE_H
2 #define QEMU_PCI_DEVICE_H
3
4 #include "hw/pci/pci.h"
5 #include "hw/pci/pcie.h"
6 #include "hw/pci/pcie_doe.h"
7
8 #define TYPE_PCI_DEVICE "pci-device"
9 typedef struct PCIDeviceClass PCIDeviceClass;
10 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
11 PCI_DEVICE, TYPE_PCI_DEVICE)
12
13 /*
14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
15 * actually a "CXL Component, but we name it device to match the PCI naming.
16 */
17 #define INTERFACE_CXL_DEVICE "cxl-device"
18
19 /* Implemented by devices that can be plugged on PCI Express buses */
20 #define INTERFACE_PCIE_DEVICE "pci-express-device"
21
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
23 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
24
25 struct PCIDeviceClass {
26 DeviceClass parent_class;
27
28 void (*realize)(PCIDevice *dev, Error **errp);
29 PCIUnregisterFunc *exit;
30 PCIConfigReadFunc *config_read;
31 PCIConfigWriteFunc *config_write;
32
33 uint16_t vendor_id;
34 uint16_t device_id;
35 uint8_t revision;
36 uint16_t class_id;
37 uint16_t subsystem_vendor_id; /* only for header type = 0 */
38 uint16_t subsystem_id; /* only for header type = 0 */
39
40 const char *romfile; /* rom bar */
41 };
42
43 enum PCIReqIDType {
44 PCI_REQ_ID_INVALID = 0,
45 PCI_REQ_ID_BDF,
46 PCI_REQ_ID_SECONDARY_BUS,
47 PCI_REQ_ID_MAX,
48 };
49 typedef enum PCIReqIDType PCIReqIDType;
50
51 struct PCIReqIDCache {
52 PCIDevice *dev;
53 PCIReqIDType type;
54 };
55 typedef struct PCIReqIDCache PCIReqIDCache;
56
57 struct PCIDevice {
58 DeviceState qdev;
59 bool partially_hotplugged;
60 bool enabled;
61
62 /* PCI config space */
63 uint8_t *config;
64
65 /*
66 * Used to enable config checks on load. Note that writable bits are
67 * never checked even if set in cmask.
68 */
69 uint8_t *cmask;
70
71 /* Used to implement R/W bytes */
72 uint8_t *wmask;
73
74 /* Used to implement RW1C(Write 1 to Clear) bytes */
75 uint8_t *w1cmask;
76
77 /* Used to allocate config space for capabilities. */
78 uint8_t *used;
79
80 /* the following fields are read only */
81 int32_t devfn;
82 /*
83 * Cached device to fetch requester ID from, to avoid the PCI tree
84 * walking every time we invoke PCI request (e.g., MSI). For
85 * conventional PCI root complex, this field is meaningless.
86 */
87 PCIReqIDCache requester_id_cache;
88 char name[64];
89 PCIIORegion io_regions[PCI_NUM_REGIONS];
90 AddressSpace bus_master_as;
91 MemoryRegion bus_master_container_region;
92 MemoryRegion bus_master_enable_region;
93
94 /* do not access the following fields */
95 PCIConfigReadFunc *config_read;
96 PCIConfigWriteFunc *config_write;
97
98 /* Legacy PCI VGA regions */
99 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
100 bool has_vga;
101
102 /* Current IRQ levels. Used internally by the generic PCI code. */
103 uint8_t irq_state;
104
105 /* Capability bits */
106 uint32_t cap_present;
107
108 /* Offset of PM capability in config space */
109 uint8_t pm_cap;
110
111 /* Offset of MSI-X capability in config space */
112 uint8_t msix_cap;
113
114 /* MSI-X entries */
115 int msix_entries_nr;
116
117 /* Space to store MSIX table & pending bit array */
118 uint8_t *msix_table;
119 uint8_t *msix_pba;
120
121 /* May be used by INTx or MSI during interrupt notification */
122 void *irq_opaque;
123
124 MSITriggerFunc *msi_trigger;
125 MSIPrepareMessageFunc *msi_prepare_message;
126 MSIxPrepareMessageFunc *msix_prepare_message;
127
128 /* MemoryRegion container for msix exclusive BAR setup */
129 MemoryRegion msix_exclusive_bar;
130 /* Memory Regions for MSIX table and pending bit entries. */
131 MemoryRegion msix_table_mmio;
132 MemoryRegion msix_pba_mmio;
133 /* Reference-count for entries actually in use by driver. */
134 unsigned *msix_entry_used;
135 /* MSIX function mask set or MSIX disabled */
136 bool msix_function_masked;
137 /* Version id needed for VMState */
138 int32_t version_id;
139
140 /* Offset of MSI capability in config space */
141 uint8_t msi_cap;
142
143 /* PCI Express */
144 PCIExpressDevice exp;
145
146 /* SHPC */
147 SHPCDevice *shpc;
148
149 /* Location of option rom */
150 char *romfile;
151 uint32_t romsize;
152 bool has_rom;
153 MemoryRegion rom;
154 int32_t rom_bar;
155
156 /* INTx routing notifier */
157 PCIINTxRoutingNotifier intx_routing_notifier;
158
159 /* MSI-X notifiers */
160 MSIVectorUseNotifier msix_vector_use_notifier;
161 MSIVectorReleaseNotifier msix_vector_release_notifier;
162 MSIVectorPollNotifier msix_vector_poll_notifier;
163
164 /* SPDM */
165 uint16_t spdm_port;
166
167 /* DOE */
168 DOECap doe_spdm;
169
170 /* ID of standby device in net_failover pair */
171 char *failover_pair_id;
172 uint32_t acpi_index;
173
174 /*
175 * Indirect DMA region bounce buffer size as configured for the device. This
176 * is a configuration parameter that is reflected into bus_master_as when
177 * realizing the device.
178 */
179 uint32_t max_bounce_buffer_size;
180 };
181
pci_intx(PCIDevice * pci_dev)182 static inline int pci_intx(PCIDevice *pci_dev)
183 {
184 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
185 }
186
pci_is_cxl(const PCIDevice * d)187 static inline int pci_is_cxl(const PCIDevice *d)
188 {
189 return d->cap_present & QEMU_PCIE_CAP_CXL;
190 }
191
pci_is_express(const PCIDevice * d)192 static inline int pci_is_express(const PCIDevice *d)
193 {
194 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
195 }
196
pci_is_express_downstream_port(const PCIDevice * d)197 static inline int pci_is_express_downstream_port(const PCIDevice *d)
198 {
199 uint8_t type;
200
201 if (!pci_is_express(d) || !d->exp.exp_cap) {
202 return 0;
203 }
204
205 type = pcie_cap_get_type(d);
206
207 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
208 }
209
pci_is_vf(const PCIDevice * d)210 static inline int pci_is_vf(const PCIDevice *d)
211 {
212 return d->exp.sriov_vf.pf != NULL;
213 }
214
pci_config_size(const PCIDevice * d)215 static inline uint32_t pci_config_size(const PCIDevice *d)
216 {
217 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
218 }
219
pci_get_bdf(PCIDevice * dev)220 static inline uint16_t pci_get_bdf(PCIDevice *dev)
221 {
222 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
223 }
224
225 uint16_t pci_requester_id(PCIDevice *dev);
226
227 /* DMA access functions */
pci_get_address_space(PCIDevice * dev)228 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
229 {
230 return &dev->bus_master_as;
231 }
232
233 /**
234 * pci_dma_rw: Read from or write to an address space from PCI device.
235 *
236 * Return a MemTxResult indicating whether the operation succeeded
237 * or failed (eg unassigned memory, device rejected the transaction,
238 * IOMMU fault).
239 *
240 * @dev: #PCIDevice doing the memory access
241 * @addr: address within the #PCIDevice address space
242 * @buf: buffer with the data transferred
243 * @len: the number of bytes to read or write
244 * @dir: indicates the transfer direction
245 */
pci_dma_rw(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len,DMADirection dir,MemTxAttrs attrs)246 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
247 void *buf, dma_addr_t len,
248 DMADirection dir, MemTxAttrs attrs)
249 {
250 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
251 dir, attrs);
252 }
253
254 /**
255 * pci_dma_read: Read from an address space from PCI device.
256 *
257 * Return a MemTxResult indicating whether the operation succeeded
258 * or failed (eg unassigned memory, device rejected the transaction,
259 * IOMMU fault). Called within RCU critical section.
260 *
261 * @dev: #PCIDevice doing the memory access
262 * @addr: address within the #PCIDevice address space
263 * @buf: buffer with the data transferred
264 * @len: length of the data transferred
265 */
pci_dma_read(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len)266 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
267 void *buf, dma_addr_t len)
268 {
269 return pci_dma_rw(dev, addr, buf, len,
270 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
271 }
272
273 /**
274 * pci_dma_write: Write to address space from PCI device.
275 *
276 * Return a MemTxResult indicating whether the operation succeeded
277 * or failed (eg unassigned memory, device rejected the transaction,
278 * IOMMU fault).
279 *
280 * @dev: #PCIDevice doing the memory access
281 * @addr: address within the #PCIDevice address space
282 * @buf: buffer with the data transferred
283 * @len: the number of bytes to write
284 */
pci_dma_write(PCIDevice * dev,dma_addr_t addr,const void * buf,dma_addr_t len)285 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
286 const void *buf, dma_addr_t len)
287 {
288 return pci_dma_rw(dev, addr, (void *) buf, len,
289 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
290 }
291
292 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
293 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
294 dma_addr_t addr, \
295 uint##_bits##_t *val, \
296 MemTxAttrs attrs) \
297 { \
298 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
299 } \
300 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
301 dma_addr_t addr, \
302 uint##_bits##_t val, \
303 MemTxAttrs attrs) \
304 { \
305 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
306 }
307
308 PCI_DMA_DEFINE_LDST(ub, b, 8);
309 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
310 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
311 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
312 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
313 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
314 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
315
316 #undef PCI_DMA_DEFINE_LDST
317
318 /**
319 * pci_dma_map: Map device PCI address space range into host virtual address
320 * @dev: #PCIDevice to be accessed
321 * @addr: address within that device's address space
322 * @plen: pointer to length of buffer; updated on return to indicate
323 * if only a subset of the requested range has been mapped
324 * @dir: indicates the transfer direction
325 *
326 * Return: A host pointer, or %NULL if the resources needed to
327 * perform the mapping are exhausted (in that case *@plen
328 * is set to zero).
329 */
pci_dma_map(PCIDevice * dev,dma_addr_t addr,dma_addr_t * plen,DMADirection dir)330 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
331 dma_addr_t *plen, DMADirection dir)
332 {
333 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
334 MEMTXATTRS_UNSPECIFIED);
335 }
336
pci_dma_unmap(PCIDevice * dev,void * buffer,dma_addr_t len,DMADirection dir,dma_addr_t access_len)337 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
338 DMADirection dir, dma_addr_t access_len)
339 {
340 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
341 }
342
pci_dma_sglist_init(QEMUSGList * qsg,PCIDevice * dev,int alloc_hint)343 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
344 int alloc_hint)
345 {
346 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
347 }
348
349 extern const VMStateDescription vmstate_pci_device;
350
351 #define VMSTATE_PCI_DEVICE(_field, _state) { \
352 .name = (stringify(_field)), \
353 .size = sizeof(PCIDevice), \
354 .vmsd = &vmstate_pci_device, \
355 .flags = VMS_STRUCT, \
356 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
357 }
358
359 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
360 .name = (stringify(_field)), \
361 .size = sizeof(PCIDevice), \
362 .vmsd = &vmstate_pci_device, \
363 .flags = VMS_STRUCT | VMS_POINTER, \
364 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
365 }
366
367 #endif
368