1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss.c
4 *
5 * Qualcomm MSM Camera Subsystem - Core
6 *
7 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
9 */
10 #include <linux/clk.h>
11 #include <linux/interconnect.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/media.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of.h>
17 #include <linux/of_graph.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/pm_domain.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22
23 #include <media/media-device.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-mc.h>
27 #include <media/v4l2-fwnode.h>
28
29 #include "camss.h"
30
31 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105
32 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
33
34 static const struct resources csiphy_res_8x16[] = {
35 /* CSIPHY0 */
36 {
37 .regulators = {},
38 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
39 .clock_rate = { { 0 },
40 { 0 },
41 { 0 },
42 { 100000000, 200000000 } },
43 .reg = { "csiphy0", "csiphy0_clk_mux" },
44 .interrupt = { "csiphy0" }
45 },
46
47 /* CSIPHY1 */
48 {
49 .regulators = {},
50 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
51 .clock_rate = { { 0 },
52 { 0 },
53 { 0 },
54 { 100000000, 200000000 } },
55 .reg = { "csiphy1", "csiphy1_clk_mux" },
56 .interrupt = { "csiphy1" }
57 }
58 };
59
60 static const struct resources csid_res_8x16[] = {
61 /* CSID0 */
62 {
63 .regulators = { "vdda" },
64 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
65 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
66 .clock_rate = { { 0 },
67 { 0 },
68 { 0 },
69 { 0 },
70 { 100000000, 200000000 },
71 { 0 },
72 { 0 },
73 { 0 } },
74 .reg = { "csid0" },
75 .interrupt = { "csid0" }
76 },
77
78 /* CSID1 */
79 {
80 .regulators = { "vdda" },
81 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
82 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
83 .clock_rate = { { 0 },
84 { 0 },
85 { 0 },
86 { 0 },
87 { 100000000, 200000000 },
88 { 0 },
89 { 0 },
90 { 0 } },
91 .reg = { "csid1" },
92 .interrupt = { "csid1" }
93 },
94 };
95
96 static const struct resources_ispif ispif_res_8x16 = {
97 /* ISPIF */
98 .clock = { "top_ahb", "ahb", "ispif_ahb",
99 "csi0", "csi0_pix", "csi0_rdi",
100 "csi1", "csi1_pix", "csi1_rdi" },
101 .clock_for_reset = { "vfe0", "csi_vfe0" },
102 .reg = { "ispif", "csi_clk_mux" },
103 .interrupt = "ispif"
104
105 };
106
107 static const struct resources vfe_res_8x16[] = {
108 /* VFE0 */
109 {
110 .regulators = {},
111 .clock = { "top_ahb", "vfe0", "csi_vfe0",
112 "vfe_ahb", "vfe_axi", "ahb" },
113 .clock_rate = { { 0 },
114 { 50000000, 80000000, 100000000, 160000000,
115 177780000, 200000000, 266670000, 320000000,
116 400000000, 465000000 },
117 { 0 },
118 { 0 },
119 { 0 },
120 { 0 },
121 { 0 },
122 { 0 },
123 { 0 } },
124 .reg = { "vfe0" },
125 .interrupt = { "vfe0" }
126 }
127 };
128
129 static const struct resources csiphy_res_8x96[] = {
130 /* CSIPHY0 */
131 {
132 .regulators = {},
133 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
134 .clock_rate = { { 0 },
135 { 0 },
136 { 0 },
137 { 100000000, 200000000, 266666667 } },
138 .reg = { "csiphy0", "csiphy0_clk_mux" },
139 .interrupt = { "csiphy0" }
140 },
141
142 /* CSIPHY1 */
143 {
144 .regulators = {},
145 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
146 .clock_rate = { { 0 },
147 { 0 },
148 { 0 },
149 { 100000000, 200000000, 266666667 } },
150 .reg = { "csiphy1", "csiphy1_clk_mux" },
151 .interrupt = { "csiphy1" }
152 },
153
154 /* CSIPHY2 */
155 {
156 .regulators = {},
157 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
158 .clock_rate = { { 0 },
159 { 0 },
160 { 0 },
161 { 100000000, 200000000, 266666667 } },
162 .reg = { "csiphy2", "csiphy2_clk_mux" },
163 .interrupt = { "csiphy2" }
164 }
165 };
166
167 static const struct resources csid_res_8x96[] = {
168 /* CSID0 */
169 {
170 .regulators = { "vdda" },
171 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
172 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
173 .clock_rate = { { 0 },
174 { 0 },
175 { 0 },
176 { 0 },
177 { 100000000, 200000000, 266666667 },
178 { 0 },
179 { 0 },
180 { 0 } },
181 .reg = { "csid0" },
182 .interrupt = { "csid0" }
183 },
184
185 /* CSID1 */
186 {
187 .regulators = { "vdda" },
188 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
189 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
190 .clock_rate = { { 0 },
191 { 0 },
192 { 0 },
193 { 0 },
194 { 100000000, 200000000, 266666667 },
195 { 0 },
196 { 0 },
197 { 0 } },
198 .reg = { "csid1" },
199 .interrupt = { "csid1" }
200 },
201
202 /* CSID2 */
203 {
204 .regulators = { "vdda" },
205 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
206 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
207 .clock_rate = { { 0 },
208 { 0 },
209 { 0 },
210 { 0 },
211 { 100000000, 200000000, 266666667 },
212 { 0 },
213 { 0 },
214 { 0 } },
215 .reg = { "csid2" },
216 .interrupt = { "csid2" }
217 },
218
219 /* CSID3 */
220 {
221 .regulators = { "vdda" },
222 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
223 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
224 .clock_rate = { { 0 },
225 { 0 },
226 { 0 },
227 { 0 },
228 { 100000000, 200000000, 266666667 },
229 { 0 },
230 { 0 },
231 { 0 } },
232 .reg = { "csid3" },
233 .interrupt = { "csid3" }
234 }
235 };
236
237 static const struct resources_ispif ispif_res_8x96 = {
238 /* ISPIF */
239 .clock = { "top_ahb", "ahb", "ispif_ahb",
240 "csi0", "csi0_pix", "csi0_rdi",
241 "csi1", "csi1_pix", "csi1_rdi",
242 "csi2", "csi2_pix", "csi2_rdi",
243 "csi3", "csi3_pix", "csi3_rdi" },
244 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
245 .reg = { "ispif", "csi_clk_mux" },
246 .interrupt = "ispif"
247 };
248
249 static const struct resources vfe_res_8x96[] = {
250 /* VFE0 */
251 {
252 .regulators = {},
253 .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
254 "vfe0_ahb", "vfe_axi", "vfe0_stream"},
255 .clock_rate = { { 0 },
256 { 0 },
257 { 75000000, 100000000, 300000000,
258 320000000, 480000000, 600000000 },
259 { 0 },
260 { 0 },
261 { 0 },
262 { 0 },
263 { 0 } },
264 .reg = { "vfe0" },
265 .interrupt = { "vfe0" }
266 },
267
268 /* VFE1 */
269 {
270 .regulators = {},
271 .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
272 "vfe1_ahb", "vfe_axi", "vfe1_stream"},
273 .clock_rate = { { 0 },
274 { 0 },
275 { 75000000, 100000000, 300000000,
276 320000000, 480000000, 600000000 },
277 { 0 },
278 { 0 },
279 { 0 },
280 { 0 },
281 { 0 } },
282 .reg = { "vfe1" },
283 .interrupt = { "vfe1" }
284 }
285 };
286
287 static const struct resources csiphy_res_660[] = {
288 /* CSIPHY0 */
289 {
290 .regulators = {},
291 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer",
292 "csi0_phy", "csiphy_ahb2crif" },
293 .clock_rate = { { 0 },
294 { 0 },
295 { 0 },
296 { 100000000, 200000000, 269333333 },
297 { 0 } },
298 .reg = { "csiphy0", "csiphy0_clk_mux" },
299 .interrupt = { "csiphy0" }
300 },
301
302 /* CSIPHY1 */
303 {
304 .regulators = {},
305 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer",
306 "csi1_phy", "csiphy_ahb2crif" },
307 .clock_rate = { { 0 },
308 { 0 },
309 { 0 },
310 { 100000000, 200000000, 269333333 },
311 { 0 } },
312 .reg = { "csiphy1", "csiphy1_clk_mux" },
313 .interrupt = { "csiphy1" }
314 },
315
316 /* CSIPHY2 */
317 {
318 .regulators = {},
319 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer",
320 "csi2_phy", "csiphy_ahb2crif" },
321 .clock_rate = { { 0 },
322 { 0 },
323 { 0 },
324 { 100000000, 200000000, 269333333 },
325 { 0 } },
326 .reg = { "csiphy2", "csiphy2_clk_mux" },
327 .interrupt = { "csiphy2" }
328 }
329 };
330
331 static const struct resources csid_res_660[] = {
332 /* CSID0 */
333 {
334 .regulators = { "vdda", "vdd_sec" },
335 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
336 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi",
337 "cphy_csid0" },
338 .clock_rate = { { 0 },
339 { 0 },
340 { 0 },
341 { 0 },
342 { 100000000, 200000000, 310000000,
343 404000000, 465000000 },
344 { 0 },
345 { 0 },
346 { 0 },
347 { 0 } },
348 .reg = { "csid0" },
349 .interrupt = { "csid0" }
350 },
351
352 /* CSID1 */
353 {
354 .regulators = { "vdda", "vdd_sec" },
355 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
356 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi",
357 "cphy_csid1" },
358 .clock_rate = { { 0 },
359 { 0 },
360 { 0 },
361 { 0 },
362 { 100000000, 200000000, 310000000,
363 404000000, 465000000 },
364 { 0 },
365 { 0 },
366 { 0 },
367 { 0 } },
368 .reg = { "csid1" },
369 .interrupt = { "csid1" }
370 },
371
372 /* CSID2 */
373 {
374 .regulators = { "vdda", "vdd_sec" },
375 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
376 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi",
377 "cphy_csid2" },
378 .clock_rate = { { 0 },
379 { 0 },
380 { 0 },
381 { 0 },
382 { 100000000, 200000000, 310000000,
383 404000000, 465000000 },
384 { 0 },
385 { 0 },
386 { 0 },
387 { 0 } },
388 .reg = { "csid2" },
389 .interrupt = { "csid2" }
390 },
391
392 /* CSID3 */
393 {
394 .regulators = { "vdda", "vdd_sec" },
395 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
396 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi",
397 "cphy_csid3" },
398 .clock_rate = { { 0 },
399 { 0 },
400 { 0 },
401 { 0 },
402 { 100000000, 200000000, 310000000,
403 404000000, 465000000 },
404 { 0 },
405 { 0 },
406 { 0 },
407 { 0 } },
408 .reg = { "csid3" },
409 .interrupt = { "csid3" }
410 }
411 };
412
413 static const struct resources_ispif ispif_res_660 = {
414 /* ISPIF */
415 .clock = { "top_ahb", "ahb", "ispif_ahb",
416 "csi0", "csi0_pix", "csi0_rdi",
417 "csi1", "csi1_pix", "csi1_rdi",
418 "csi2", "csi2_pix", "csi2_rdi",
419 "csi3", "csi3_pix", "csi3_rdi" },
420 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
421 .reg = { "ispif", "csi_clk_mux" },
422 .interrupt = "ispif"
423 };
424
425 static const struct resources vfe_res_660[] = {
426 /* VFE0 */
427 {
428 .regulators = {},
429 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0",
430 "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi",
431 "vfe0_stream"},
432 .clock_rate = { { 0 },
433 { 0 },
434 { 0 },
435 { 120000000, 200000000, 256000000,
436 300000000, 404000000, 480000000,
437 540000000, 576000000 },
438 { 0 },
439 { 0 },
440 { 0 },
441 { 0 },
442 { 0 } },
443 .reg = { "vfe0" },
444 .interrupt = { "vfe0" }
445 },
446
447 /* VFE1 */
448 {
449 .regulators = {},
450 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1",
451 "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi",
452 "vfe1_stream"},
453 .clock_rate = { { 0 },
454 { 0 },
455 { 0 },
456 { 120000000, 200000000, 256000000,
457 300000000, 404000000, 480000000,
458 540000000, 576000000 },
459 { 0 },
460 { 0 },
461 { 0 },
462 { 0 },
463 { 0 } },
464 .reg = { "vfe1" },
465 .interrupt = { "vfe1" }
466 }
467 };
468
469 static const struct resources csiphy_res_845[] = {
470 /* CSIPHY0 */
471 {
472 .regulators = {},
473 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
474 "cpas_ahb", "cphy_rx_src", "csiphy0",
475 "csiphy0_timer_src", "csiphy0_timer" },
476 .clock_rate = { { 0 },
477 { 0 },
478 { 0 },
479 { 0 },
480 { 0 },
481 { 0 },
482 { 0 },
483 { 19200000, 240000000, 269333333 } },
484 .reg = { "csiphy0" },
485 .interrupt = { "csiphy0" }
486 },
487
488 /* CSIPHY1 */
489 {
490 .regulators = {},
491 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
492 "cpas_ahb", "cphy_rx_src", "csiphy1",
493 "csiphy1_timer_src", "csiphy1_timer" },
494 .clock_rate = { { 0 },
495 { 0 },
496 { 0 },
497 { 0 },
498 { 0 },
499 { 0 },
500 { 0 },
501 { 19200000, 240000000, 269333333 } },
502 .reg = { "csiphy1" },
503 .interrupt = { "csiphy1" }
504 },
505
506 /* CSIPHY2 */
507 {
508 .regulators = {},
509 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
510 "cpas_ahb", "cphy_rx_src", "csiphy2",
511 "csiphy2_timer_src", "csiphy2_timer" },
512 .clock_rate = { { 0 },
513 { 0 },
514 { 0 },
515 { 0 },
516 { 0 },
517 { 0 },
518 { 0 },
519 { 19200000, 240000000, 269333333 } },
520 .reg = { "csiphy2" },
521 .interrupt = { "csiphy2" }
522 },
523
524 /* CSIPHY3 */
525 {
526 .regulators = {},
527 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
528 "cpas_ahb", "cphy_rx_src", "csiphy3",
529 "csiphy3_timer_src", "csiphy3_timer" },
530 .clock_rate = { { 0 },
531 { 0 },
532 { 0 },
533 { 0 },
534 { 0 },
535 { 0 },
536 { 0 },
537 { 19200000, 240000000, 269333333 } },
538 .reg = { "csiphy3" },
539 .interrupt = { "csiphy3" }
540 }
541 };
542
543 static const struct resources csid_res_845[] = {
544 /* CSID0 */
545 {
546 .regulators = { "vdda-phy", "vdda-pll" },
547 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
548 "soc_ahb", "vfe0", "vfe0_src",
549 "vfe0_cphy_rx", "csi0",
550 "csi0_src" },
551 .clock_rate = { { 0 },
552 { 384000000 },
553 { 80000000 },
554 { 0 },
555 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
556 { 320000000 },
557 { 0 },
558 { 19200000, 75000000, 384000000, 538666667 },
559 { 384000000 } },
560 .reg = { "csid0" },
561 .interrupt = { "csid0" }
562 },
563
564 /* CSID1 */
565 {
566 .regulators = { "vdda-phy", "vdda-pll" },
567 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
568 "soc_ahb", "vfe1", "vfe1_src",
569 "vfe1_cphy_rx", "csi1",
570 "csi1_src" },
571 .clock_rate = { { 0 },
572 { 384000000 },
573 { 80000000 },
574 { 0 },
575 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
576 { 320000000 },
577 { 0 },
578 { 19200000, 75000000, 384000000, 538666667 },
579 { 384000000 } },
580 .reg = { "csid1" },
581 .interrupt = { "csid1" }
582 },
583
584 /* CSID2 */
585 {
586 .regulators = { "vdda-phy", "vdda-pll" },
587 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
588 "soc_ahb", "vfe_lite", "vfe_lite_src",
589 "vfe_lite_cphy_rx", "csi2",
590 "csi2_src" },
591 .clock_rate = { { 0 },
592 { 384000000 },
593 { 80000000 },
594 { 0 },
595 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
596 { 320000000 },
597 { 0 },
598 { 19200000, 75000000, 384000000, 538666667 },
599 { 384000000 } },
600 .reg = { "csid2" },
601 .interrupt = { "csid2" }
602 }
603 };
604
605 static const struct resources vfe_res_845[] = {
606 /* VFE0 */
607 {
608 .regulators = {},
609 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
610 "soc_ahb", "vfe0", "vfe0_axi",
611 "vfe0_src", "csi0",
612 "csi0_src"},
613 .clock_rate = { { 0 },
614 { 0 },
615 { 80000000 },
616 { 0 },
617 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
618 { 0 },
619 { 320000000 },
620 { 19200000, 75000000, 384000000, 538666667 },
621 { 384000000 } },
622 .reg = { "vfe0" },
623 .interrupt = { "vfe0" }
624 },
625
626 /* VFE1 */
627 {
628 .regulators = {},
629 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
630 "soc_ahb", "vfe1", "vfe1_axi",
631 "vfe1_src", "csi1",
632 "csi1_src"},
633 .clock_rate = { { 0 },
634 { 0 },
635 { 80000000 },
636 { 0 },
637 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
638 { 0 },
639 { 320000000 },
640 { 19200000, 75000000, 384000000, 538666667 },
641 { 384000000 } },
642 .reg = { "vfe1" },
643 .interrupt = { "vfe1" }
644 },
645
646 /* VFE-lite */
647 {
648 .regulators = {},
649 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
650 "soc_ahb", "vfe_lite",
651 "vfe_lite_src", "csi2",
652 "csi2_src"},
653 .clock_rate = { { 0 },
654 { 0 },
655 { 80000000 },
656 { 0 },
657 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
658 { 320000000 },
659 { 19200000, 75000000, 384000000, 538666667 },
660 { 384000000 } },
661 .reg = { "vfe_lite" },
662 .interrupt = { "vfe_lite" }
663 }
664 };
665
666 static const struct resources csiphy_res_8250[] = {
667 /* CSIPHY0 */
668 {
669 .regulators = {},
670 .clock = { "csiphy0", "csiphy0_timer" },
671 .clock_rate = { { 400000000 },
672 { 300000000 } },
673 .reg = { "csiphy0" },
674 .interrupt = { "csiphy0" }
675 },
676 /* CSIPHY1 */
677 {
678 .regulators = {},
679 .clock = { "csiphy1", "csiphy1_timer" },
680 .clock_rate = { { 400000000 },
681 { 300000000 } },
682 .reg = { "csiphy1" },
683 .interrupt = { "csiphy1" }
684 },
685 /* CSIPHY2 */
686 {
687 .regulators = {},
688 .clock = { "csiphy2", "csiphy2_timer" },
689 .clock_rate = { { 400000000 },
690 { 300000000 } },
691 .reg = { "csiphy2" },
692 .interrupt = { "csiphy2" }
693 },
694 /* CSIPHY3 */
695 {
696 .regulators = {},
697 .clock = { "csiphy3", "csiphy3_timer" },
698 .clock_rate = { { 400000000 },
699 { 300000000 } },
700 .reg = { "csiphy3" },
701 .interrupt = { "csiphy3" }
702 },
703 /* CSIPHY4 */
704 {
705 .regulators = {},
706 .clock = { "csiphy4", "csiphy4_timer" },
707 .clock_rate = { { 400000000 },
708 { 300000000 } },
709 .reg = { "csiphy4" },
710 .interrupt = { "csiphy4" }
711 },
712 /* CSIPHY5 */
713 {
714 .regulators = {},
715 .clock = { "csiphy5", "csiphy5_timer" },
716 .clock_rate = { { 400000000 },
717 { 300000000 } },
718 .reg = { "csiphy5" },
719 .interrupt = { "csiphy5" }
720 }
721 };
722
723 static const struct resources csid_res_8250[] = {
724 /* CSID0 */
725 {
726 .regulators = { "vdda-phy", "vdda-pll" },
727 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
728 .clock_rate = { { 400000000 },
729 { 400000000 },
730 { 350000000, 475000000, 576000000, 720000000 },
731 { 100000000, 200000000, 300000000, 400000000 },
732 { 0 } },
733 .reg = { "csid0" },
734 .interrupt = { "csid0" }
735 },
736 /* CSID1 */
737 {
738 .regulators = { "vdda-phy", "vdda-pll" },
739 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
740 .clock_rate = { { 400000000 },
741 { 400000000 },
742 { 350000000, 475000000, 576000000, 720000000 },
743 { 100000000, 200000000, 300000000, 400000000 },
744 { 0 } },
745 .reg = { "csid1" },
746 .interrupt = { "csid1" }
747 },
748 /* CSID2 */
749 {
750 .regulators = { "vdda-phy", "vdda-pll" },
751 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
752 .clock_rate = { { 400000000 },
753 { 400000000 },
754 { 400000000, 480000000 },
755 { 0 } },
756 .reg = { "csid2" },
757 .interrupt = { "csid2" }
758 },
759 /* CSID3 */
760 {
761 .regulators = { "vdda-phy", "vdda-pll" },
762 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
763 .clock_rate = { { 400000000 },
764 { 400000000 },
765 { 400000000, 480000000 },
766 { 0 } },
767 .reg = { "csid3" },
768 .interrupt = { "csid3" }
769 }
770 };
771
772 static const struct resources vfe_res_8250[] = {
773 /* VFE0 */
774 {
775 .regulators = {},
776 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
777 "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0",
778 "vfe0_axi", "cam_hf_axi" },
779 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
780 { 19200000, 80000000 },
781 { 19200000 },
782 { 0 },
783 { 0 },
784 { 100000000, 200000000, 300000000, 400000000 },
785 { 350000000, 475000000, 576000000, 720000000 },
786 { 0 },
787 { 0 } },
788 .reg = { "vfe0" },
789 .interrupt = { "vfe0" }
790 },
791 /* VFE1 */
792 {
793 .regulators = {},
794 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
795 "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1",
796 "vfe1_axi", "cam_hf_axi" },
797 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
798 { 19200000, 80000000 },
799 { 19200000 },
800 { 0 },
801 { 0 },
802 { 100000000, 200000000, 300000000, 400000000 },
803 { 350000000, 475000000, 576000000, 720000000 },
804 { 0 },
805 { 0 } },
806 .reg = { "vfe1" },
807 .interrupt = { "vfe1" }
808 },
809 /* VFE2 (lite) */
810 {
811 .regulators = {},
812 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
813 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
814 "vfe_lite", "cam_hf_axi" },
815 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
816 { 19200000, 80000000 },
817 { 19200000 },
818 { 0 },
819 { 0 },
820 { 0 },
821 { 400000000, 480000000 },
822 { 0 } },
823 .reg = { "vfe_lite0" },
824 .interrupt = { "vfe_lite0" }
825 },
826 /* VFE3 (lite) */
827 {
828 .regulators = {},
829 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
830 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
831 "vfe_lite", "cam_hf_axi" },
832 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
833 { 19200000, 80000000 },
834 { 19200000 },
835 { 0 },
836 { 0 },
837 { 0 },
838 { 400000000, 480000000 },
839 { 0 } },
840 .reg = { "vfe_lite1" },
841 .interrupt = { "vfe_lite1" }
842 },
843 };
844
845 static const struct resources_icc icc_res_sm8250[] = {
846 {
847 .name = "cam_ahb",
848 .icc_bw_tbl.avg = 38400,
849 .icc_bw_tbl.peak = 76800,
850 },
851 {
852 .name = "cam_hf_0_mnoc",
853 .icc_bw_tbl.avg = 2097152,
854 .icc_bw_tbl.peak = 2097152,
855 },
856 {
857 .name = "cam_sf_0_mnoc",
858 .icc_bw_tbl.avg = 0,
859 .icc_bw_tbl.peak = 2097152,
860 },
861 {
862 .name = "cam_sf_icp_mnoc",
863 .icc_bw_tbl.avg = 2097152,
864 .icc_bw_tbl.peak = 2097152,
865 },
866 };
867
868 /*
869 * camss_add_clock_margin - Add margin to clock frequency rate
870 * @rate: Clock frequency rate
871 *
872 * When making calculations with physical clock frequency values
873 * some safety margin must be added. Add it.
874 */
camss_add_clock_margin(u64 * rate)875 inline void camss_add_clock_margin(u64 *rate)
876 {
877 *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
878 *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
879 }
880
881 /*
882 * camss_enable_clocks - Enable multiple clocks
883 * @nclocks: Number of clocks in clock array
884 * @clock: Clock array
885 * @dev: Device
886 *
887 * Return 0 on success or a negative error code otherwise
888 */
camss_enable_clocks(int nclocks,struct camss_clock * clock,struct device * dev)889 int camss_enable_clocks(int nclocks, struct camss_clock *clock,
890 struct device *dev)
891 {
892 int ret;
893 int i;
894
895 for (i = 0; i < nclocks; i++) {
896 ret = clk_prepare_enable(clock[i].clk);
897 if (ret) {
898 dev_err(dev, "clock enable failed: %d\n", ret);
899 goto error;
900 }
901 }
902
903 return 0;
904
905 error:
906 for (i--; i >= 0; i--)
907 clk_disable_unprepare(clock[i].clk);
908
909 return ret;
910 }
911
912 /*
913 * camss_disable_clocks - Disable multiple clocks
914 * @nclocks: Number of clocks in clock array
915 * @clock: Clock array
916 */
camss_disable_clocks(int nclocks,struct camss_clock * clock)917 void camss_disable_clocks(int nclocks, struct camss_clock *clock)
918 {
919 int i;
920
921 for (i = nclocks - 1; i >= 0; i--)
922 clk_disable_unprepare(clock[i].clk);
923 }
924
925 /*
926 * camss_find_sensor - Find a linked media entity which represents a sensor
927 * @entity: Media entity to start searching from
928 *
929 * Return a pointer to sensor media entity or NULL if not found
930 */
camss_find_sensor(struct media_entity * entity)931 struct media_entity *camss_find_sensor(struct media_entity *entity)
932 {
933 struct media_pad *pad;
934
935 while (1) {
936 pad = &entity->pads[0];
937 if (!(pad->flags & MEDIA_PAD_FL_SINK))
938 return NULL;
939
940 pad = media_pad_remote_pad_first(pad);
941 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
942 return NULL;
943
944 entity = pad->entity;
945
946 if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
947 return entity;
948 }
949 }
950
951 /**
952 * camss_get_link_freq - Get link frequency from sensor
953 * @entity: Media entity in the current pipeline
954 * @bpp: Number of bits per pixel for the current format
955 * @lanes: Number of lanes in the link to the sensor
956 *
957 * Return link frequency on success or a negative error code otherwise
958 */
camss_get_link_freq(struct media_entity * entity,unsigned int bpp,unsigned int lanes)959 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
960 unsigned int lanes)
961 {
962 struct media_entity *sensor;
963 struct v4l2_subdev *subdev;
964
965 sensor = camss_find_sensor(entity);
966 if (!sensor)
967 return -ENODEV;
968
969 subdev = media_entity_to_v4l2_subdev(sensor);
970
971 return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes);
972 }
973
974 /*
975 * camss_get_pixel_clock - Get pixel clock rate from sensor
976 * @entity: Media entity in the current pipeline
977 * @pixel_clock: Received pixel clock value
978 *
979 * Return 0 on success or a negative error code otherwise
980 */
camss_get_pixel_clock(struct media_entity * entity,u64 * pixel_clock)981 int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock)
982 {
983 struct media_entity *sensor;
984 struct v4l2_subdev *subdev;
985 struct v4l2_ctrl *ctrl;
986
987 sensor = camss_find_sensor(entity);
988 if (!sensor)
989 return -ENODEV;
990
991 subdev = media_entity_to_v4l2_subdev(sensor);
992
993 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
994
995 if (!ctrl)
996 return -EINVAL;
997
998 *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
999
1000 return 0;
1001 }
1002
camss_pm_domain_on(struct camss * camss,int id)1003 int camss_pm_domain_on(struct camss *camss, int id)
1004 {
1005 int ret = 0;
1006
1007 if (id < camss->vfe_num) {
1008 struct vfe_device *vfe = &camss->vfe[id];
1009
1010 ret = vfe->ops->pm_domain_on(vfe);
1011 }
1012
1013 return ret;
1014 }
1015
camss_pm_domain_off(struct camss * camss,int id)1016 void camss_pm_domain_off(struct camss *camss, int id)
1017 {
1018 if (id < camss->vfe_num) {
1019 struct vfe_device *vfe = &camss->vfe[id];
1020
1021 vfe->ops->pm_domain_off(vfe);
1022 }
1023 }
1024
1025 /*
1026 * camss_of_parse_endpoint_node - Parse port endpoint node
1027 * @dev: Device
1028 * @node: Device node to be parsed
1029 * @csd: Parsed data from port endpoint node
1030 *
1031 * Return 0 on success or a negative error code on failure
1032 */
camss_of_parse_endpoint_node(struct device * dev,struct device_node * node,struct camss_async_subdev * csd)1033 static int camss_of_parse_endpoint_node(struct device *dev,
1034 struct device_node *node,
1035 struct camss_async_subdev *csd)
1036 {
1037 struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg;
1038 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2;
1039 struct v4l2_fwnode_endpoint vep = { { 0 } };
1040 unsigned int i;
1041 int ret;
1042
1043 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
1044 if (ret)
1045 return ret;
1046
1047 csd->interface.csiphy_id = vep.base.port;
1048
1049 mipi_csi2 = &vep.bus.mipi_csi2;
1050 lncfg->clk.pos = mipi_csi2->clock_lane;
1051 lncfg->clk.pol = mipi_csi2->lane_polarities[0];
1052 lncfg->num_data = mipi_csi2->num_data_lanes;
1053
1054 lncfg->data = devm_kcalloc(dev,
1055 lncfg->num_data, sizeof(*lncfg->data),
1056 GFP_KERNEL);
1057 if (!lncfg->data)
1058 return -ENOMEM;
1059
1060 for (i = 0; i < lncfg->num_data; i++) {
1061 lncfg->data[i].pos = mipi_csi2->data_lanes[i];
1062 lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1];
1063 }
1064
1065 return 0;
1066 }
1067
1068 /*
1069 * camss_of_parse_ports - Parse ports node
1070 * @dev: Device
1071 * @notifier: v4l2_device notifier data
1072 *
1073 * Return number of "port" nodes found in "ports" node
1074 */
camss_of_parse_ports(struct camss * camss)1075 static int camss_of_parse_ports(struct camss *camss)
1076 {
1077 struct device *dev = camss->dev;
1078 struct device_node *node = NULL;
1079 struct device_node *remote = NULL;
1080 int ret, num_subdevs = 0;
1081
1082 for_each_endpoint_of_node(dev->of_node, node) {
1083 struct camss_async_subdev *csd;
1084
1085 if (!of_device_is_available(node))
1086 continue;
1087
1088 remote = of_graph_get_remote_port_parent(node);
1089 if (!remote) {
1090 dev_err(dev, "Cannot get remote parent\n");
1091 ret = -EINVAL;
1092 goto err_cleanup;
1093 }
1094
1095 csd = v4l2_async_nf_add_fwnode(&camss->notifier,
1096 of_fwnode_handle(remote),
1097 struct camss_async_subdev);
1098 of_node_put(remote);
1099 if (IS_ERR(csd)) {
1100 ret = PTR_ERR(csd);
1101 goto err_cleanup;
1102 }
1103
1104 ret = camss_of_parse_endpoint_node(dev, node, csd);
1105 if (ret < 0)
1106 goto err_cleanup;
1107
1108 num_subdevs++;
1109 }
1110
1111 return num_subdevs;
1112
1113 err_cleanup:
1114 of_node_put(node);
1115 return ret;
1116 }
1117
1118 /*
1119 * camss_init_subdevices - Initialize subdev structures and resources
1120 * @camss: CAMSS device
1121 *
1122 * Return 0 on success or a negative error code on failure
1123 */
camss_init_subdevices(struct camss * camss)1124 static int camss_init_subdevices(struct camss *camss)
1125 {
1126 const struct resources *csiphy_res;
1127 const struct resources *csid_res;
1128 const struct resources_ispif *ispif_res;
1129 const struct resources *vfe_res;
1130 unsigned int i;
1131 int ret;
1132
1133 if (camss->version == CAMSS_8x16) {
1134 csiphy_res = csiphy_res_8x16;
1135 csid_res = csid_res_8x16;
1136 ispif_res = &ispif_res_8x16;
1137 vfe_res = vfe_res_8x16;
1138 } else if (camss->version == CAMSS_8x96) {
1139 csiphy_res = csiphy_res_8x96;
1140 csid_res = csid_res_8x96;
1141 ispif_res = &ispif_res_8x96;
1142 vfe_res = vfe_res_8x96;
1143 } else if (camss->version == CAMSS_660) {
1144 csiphy_res = csiphy_res_660;
1145 csid_res = csid_res_660;
1146 ispif_res = &ispif_res_660;
1147 vfe_res = vfe_res_660;
1148 } else if (camss->version == CAMSS_845) {
1149 csiphy_res = csiphy_res_845;
1150 csid_res = csid_res_845;
1151 /* Titan VFEs don't have an ISPIF */
1152 ispif_res = NULL;
1153 vfe_res = vfe_res_845;
1154 } else if (camss->version == CAMSS_8250) {
1155 csiphy_res = csiphy_res_8250;
1156 csid_res = csid_res_8250;
1157 /* Titan VFEs don't have an ISPIF */
1158 ispif_res = NULL;
1159 vfe_res = vfe_res_8250;
1160 } else {
1161 return -EINVAL;
1162 }
1163
1164 for (i = 0; i < camss->csiphy_num; i++) {
1165 ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i],
1166 &csiphy_res[i], i);
1167 if (ret < 0) {
1168 dev_err(camss->dev,
1169 "Failed to init csiphy%d sub-device: %d\n",
1170 i, ret);
1171 return ret;
1172 }
1173 }
1174
1175 /* note: SM8250 requires VFE to be initialized before CSID */
1176 for (i = 0; i < camss->vfe_num + camss->vfe_lite_num; i++) {
1177 ret = msm_vfe_subdev_init(camss, &camss->vfe[i],
1178 &vfe_res[i], i);
1179 if (ret < 0) {
1180 dev_err(camss->dev,
1181 "Fail to init vfe%d sub-device: %d\n", i, ret);
1182 return ret;
1183 }
1184 }
1185
1186 for (i = 0; i < camss->csid_num; i++) {
1187 ret = msm_csid_subdev_init(camss, &camss->csid[i],
1188 &csid_res[i], i);
1189 if (ret < 0) {
1190 dev_err(camss->dev,
1191 "Failed to init csid%d sub-device: %d\n",
1192 i, ret);
1193 return ret;
1194 }
1195 }
1196
1197 ret = msm_ispif_subdev_init(camss, ispif_res);
1198 if (ret < 0) {
1199 dev_err(camss->dev, "Failed to init ispif sub-device: %d\n",
1200 ret);
1201 return ret;
1202 }
1203
1204 return 0;
1205 }
1206
1207 /*
1208 * camss_register_entities - Register subdev nodes and create links
1209 * @camss: CAMSS device
1210 *
1211 * Return 0 on success or a negative error code on failure
1212 */
camss_register_entities(struct camss * camss)1213 static int camss_register_entities(struct camss *camss)
1214 {
1215 int i, j, k;
1216 int ret;
1217
1218 for (i = 0; i < camss->csiphy_num; i++) {
1219 ret = msm_csiphy_register_entity(&camss->csiphy[i],
1220 &camss->v4l2_dev);
1221 if (ret < 0) {
1222 dev_err(camss->dev,
1223 "Failed to register csiphy%d entity: %d\n",
1224 i, ret);
1225 goto err_reg_csiphy;
1226 }
1227 }
1228
1229 for (i = 0; i < camss->csid_num; i++) {
1230 ret = msm_csid_register_entity(&camss->csid[i],
1231 &camss->v4l2_dev);
1232 if (ret < 0) {
1233 dev_err(camss->dev,
1234 "Failed to register csid%d entity: %d\n",
1235 i, ret);
1236 goto err_reg_csid;
1237 }
1238 }
1239
1240 ret = msm_ispif_register_entities(camss->ispif,
1241 &camss->v4l2_dev);
1242 if (ret < 0) {
1243 dev_err(camss->dev, "Failed to register ispif entities: %d\n",
1244 ret);
1245 goto err_reg_ispif;
1246 }
1247
1248 for (i = 0; i < camss->vfe_num + camss->vfe_lite_num; i++) {
1249 ret = msm_vfe_register_entities(&camss->vfe[i],
1250 &camss->v4l2_dev);
1251 if (ret < 0) {
1252 dev_err(camss->dev,
1253 "Failed to register vfe%d entities: %d\n",
1254 i, ret);
1255 goto err_reg_vfe;
1256 }
1257 }
1258
1259 for (i = 0; i < camss->csiphy_num; i++) {
1260 for (j = 0; j < camss->csid_num; j++) {
1261 ret = media_create_pad_link(
1262 &camss->csiphy[i].subdev.entity,
1263 MSM_CSIPHY_PAD_SRC,
1264 &camss->csid[j].subdev.entity,
1265 MSM_CSID_PAD_SINK,
1266 0);
1267 if (ret < 0) {
1268 dev_err(camss->dev,
1269 "Failed to link %s->%s entities: %d\n",
1270 camss->csiphy[i].subdev.entity.name,
1271 camss->csid[j].subdev.entity.name,
1272 ret);
1273 goto err_link;
1274 }
1275 }
1276 }
1277
1278 if (camss->ispif) {
1279 for (i = 0; i < camss->csid_num; i++) {
1280 for (j = 0; j < camss->ispif->line_num; j++) {
1281 ret = media_create_pad_link(
1282 &camss->csid[i].subdev.entity,
1283 MSM_CSID_PAD_SRC,
1284 &camss->ispif->line[j].subdev.entity,
1285 MSM_ISPIF_PAD_SINK,
1286 0);
1287 if (ret < 0) {
1288 dev_err(camss->dev,
1289 "Failed to link %s->%s entities: %d\n",
1290 camss->csid[i].subdev.entity.name,
1291 camss->ispif->line[j].subdev.entity.name,
1292 ret);
1293 goto err_link;
1294 }
1295 }
1296 }
1297
1298 for (i = 0; i < camss->ispif->line_num; i++)
1299 for (k = 0; k < camss->vfe_num; k++)
1300 for (j = 0; j < camss->vfe[k].line_num; j++) {
1301 struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
1302 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
1303
1304 ret = media_create_pad_link(&ispif->entity,
1305 MSM_ISPIF_PAD_SRC,
1306 &vfe->entity,
1307 MSM_VFE_PAD_SINK,
1308 0);
1309 if (ret < 0) {
1310 dev_err(camss->dev,
1311 "Failed to link %s->%s entities: %d\n",
1312 ispif->entity.name,
1313 vfe->entity.name,
1314 ret);
1315 goto err_link;
1316 }
1317 }
1318 } else {
1319 for (i = 0; i < camss->csid_num; i++)
1320 for (k = 0; k < camss->vfe_num + camss->vfe_lite_num; k++)
1321 for (j = 0; j < camss->vfe[k].line_num; j++) {
1322 struct v4l2_subdev *csid = &camss->csid[i].subdev;
1323 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
1324
1325 ret = media_create_pad_link(&csid->entity,
1326 MSM_CSID_PAD_FIRST_SRC + j,
1327 &vfe->entity,
1328 MSM_VFE_PAD_SINK,
1329 0);
1330 if (ret < 0) {
1331 dev_err(camss->dev,
1332 "Failed to link %s->%s entities: %d\n",
1333 csid->entity.name,
1334 vfe->entity.name,
1335 ret);
1336 goto err_link;
1337 }
1338 }
1339 }
1340
1341 return 0;
1342
1343 err_link:
1344 i = camss->vfe_num + camss->vfe_lite_num;
1345 err_reg_vfe:
1346 for (i--; i >= 0; i--)
1347 msm_vfe_unregister_entities(&camss->vfe[i]);
1348
1349 err_reg_ispif:
1350 msm_ispif_unregister_entities(camss->ispif);
1351
1352 i = camss->csid_num;
1353 err_reg_csid:
1354 for (i--; i >= 0; i--)
1355 msm_csid_unregister_entity(&camss->csid[i]);
1356
1357 i = camss->csiphy_num;
1358 err_reg_csiphy:
1359 for (i--; i >= 0; i--)
1360 msm_csiphy_unregister_entity(&camss->csiphy[i]);
1361
1362 return ret;
1363 }
1364
1365 /*
1366 * camss_unregister_entities - Unregister subdev nodes
1367 * @camss: CAMSS device
1368 *
1369 * Return 0 on success or a negative error code on failure
1370 */
camss_unregister_entities(struct camss * camss)1371 static void camss_unregister_entities(struct camss *camss)
1372 {
1373 unsigned int i;
1374
1375 for (i = 0; i < camss->csiphy_num; i++)
1376 msm_csiphy_unregister_entity(&camss->csiphy[i]);
1377
1378 for (i = 0; i < camss->csid_num; i++)
1379 msm_csid_unregister_entity(&camss->csid[i]);
1380
1381 msm_ispif_unregister_entities(camss->ispif);
1382
1383 for (i = 0; i < camss->vfe_num + camss->vfe_lite_num; i++)
1384 msm_vfe_unregister_entities(&camss->vfe[i]);
1385 }
1386
camss_subdev_notifier_bound(struct v4l2_async_notifier * async,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)1387 static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async,
1388 struct v4l2_subdev *subdev,
1389 struct v4l2_async_connection *asd)
1390 {
1391 struct camss *camss = container_of(async, struct camss, notifier);
1392 struct camss_async_subdev *csd =
1393 container_of(asd, struct camss_async_subdev, asd);
1394 u8 id = csd->interface.csiphy_id;
1395 struct csiphy_device *csiphy = &camss->csiphy[id];
1396
1397 csiphy->cfg.csi2 = &csd->interface.csi2;
1398 subdev->host_priv = csiphy;
1399
1400 return 0;
1401 }
1402
camss_subdev_notifier_complete(struct v4l2_async_notifier * async)1403 static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
1404 {
1405 struct camss *camss = container_of(async, struct camss, notifier);
1406 struct v4l2_device *v4l2_dev = &camss->v4l2_dev;
1407 struct v4l2_subdev *sd;
1408 int ret;
1409
1410 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
1411 if (sd->host_priv) {
1412 struct media_entity *sensor = &sd->entity;
1413 struct csiphy_device *csiphy =
1414 (struct csiphy_device *) sd->host_priv;
1415 struct media_entity *input = &csiphy->subdev.entity;
1416 unsigned int i;
1417
1418 for (i = 0; i < sensor->num_pads; i++) {
1419 if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1420 break;
1421 }
1422 if (i == sensor->num_pads) {
1423 dev_err(camss->dev,
1424 "No source pad in external entity\n");
1425 return -EINVAL;
1426 }
1427
1428 ret = media_create_pad_link(sensor, i,
1429 input, MSM_CSIPHY_PAD_SINK,
1430 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1431 if (ret < 0) {
1432 dev_err(camss->dev,
1433 "Failed to link %s->%s entities: %d\n",
1434 sensor->name, input->name, ret);
1435 return ret;
1436 }
1437 }
1438 }
1439
1440 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
1441 if (ret < 0)
1442 return ret;
1443
1444 return media_device_register(&camss->media_dev);
1445 }
1446
1447 static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
1448 .bound = camss_subdev_notifier_bound,
1449 .complete = camss_subdev_notifier_complete,
1450 };
1451
1452 static const struct media_device_ops camss_media_ops = {
1453 .link_notify = v4l2_pipeline_link_notify,
1454 };
1455
camss_configure_pd(struct camss * camss)1456 static int camss_configure_pd(struct camss *camss)
1457 {
1458 struct device *dev = camss->dev;
1459 int i;
1460 int ret;
1461
1462 camss->genpd_num = of_count_phandle_with_args(dev->of_node,
1463 "power-domains",
1464 "#power-domain-cells");
1465 if (camss->genpd_num < 0) {
1466 dev_err(dev, "Power domains are not defined for camss\n");
1467 return camss->genpd_num;
1468 }
1469
1470 /*
1471 * If a platform device has just one power domain, then it is attached
1472 * at platform_probe() level, thus there shall be no need and even no
1473 * option to attach it again, this is the case for CAMSS on MSM8916.
1474 */
1475 if (camss->genpd_num == 1)
1476 return 0;
1477
1478 camss->genpd = devm_kmalloc_array(dev, camss->genpd_num,
1479 sizeof(*camss->genpd), GFP_KERNEL);
1480 if (!camss->genpd)
1481 return -ENOMEM;
1482
1483 camss->genpd_link = devm_kmalloc_array(dev, camss->genpd_num,
1484 sizeof(*camss->genpd_link),
1485 GFP_KERNEL);
1486 if (!camss->genpd_link)
1487 return -ENOMEM;
1488
1489 /*
1490 * VFE power domains are in the beginning of the list, and while all
1491 * power domains should be attached, only if TITAN_TOP power domain is
1492 * found in the list, it should be linked over here.
1493 */
1494 for (i = 0; i < camss->genpd_num; i++) {
1495 camss->genpd[i] = dev_pm_domain_attach_by_id(camss->dev, i);
1496 if (IS_ERR(camss->genpd[i])) {
1497 ret = PTR_ERR(camss->genpd[i]);
1498 goto fail_pm;
1499 }
1500 }
1501
1502 if (i > camss->vfe_num) {
1503 camss->genpd_link[i - 1] = device_link_add(camss->dev, camss->genpd[i - 1],
1504 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
1505 DL_FLAG_RPM_ACTIVE);
1506 if (!camss->genpd_link[i - 1]) {
1507 ret = -EINVAL;
1508 goto fail_pm;
1509 }
1510 }
1511
1512 return 0;
1513
1514 fail_pm:
1515 for (--i ; i >= 0; i--)
1516 dev_pm_domain_detach(camss->genpd[i], true);
1517
1518 return ret;
1519 }
1520
camss_icc_get(struct camss * camss)1521 static int camss_icc_get(struct camss *camss)
1522 {
1523 const struct resources_icc *icc_res;
1524 int nbr_icc_paths = 0;
1525 int i;
1526
1527 if (camss->version == CAMSS_8250) {
1528 icc_res = &icc_res_sm8250[0];
1529 nbr_icc_paths = ICC_SM8250_COUNT;
1530 }
1531
1532 for (i = 0; i < nbr_icc_paths; i++) {
1533 camss->icc_path[i] = devm_of_icc_get(camss->dev,
1534 icc_res[i].name);
1535 if (IS_ERR(camss->icc_path[i]))
1536 return PTR_ERR(camss->icc_path[i]);
1537
1538 camss->icc_bw_tbl[i] = icc_res[i].icc_bw_tbl;
1539 }
1540
1541 return 0;
1542 }
1543
camss_genpd_cleanup(struct camss * camss)1544 static void camss_genpd_cleanup(struct camss *camss)
1545 {
1546 int i;
1547
1548 if (camss->genpd_num == 1)
1549 return;
1550
1551 if (camss->genpd_num > camss->vfe_num)
1552 device_link_del(camss->genpd_link[camss->genpd_num - 1]);
1553
1554 for (i = 0; i < camss->genpd_num; i++)
1555 dev_pm_domain_detach(camss->genpd[i], true);
1556 }
1557
1558 /*
1559 * camss_probe - Probe CAMSS platform device
1560 * @pdev: Pointer to CAMSS platform device
1561 *
1562 * Return 0 on success or a negative error code on failure
1563 */
camss_probe(struct platform_device * pdev)1564 static int camss_probe(struct platform_device *pdev)
1565 {
1566 struct device *dev = &pdev->dev;
1567 struct camss *camss;
1568 int num_subdevs, ret;
1569
1570 camss = devm_kzalloc(dev, sizeof(*camss), GFP_KERNEL);
1571 if (!camss)
1572 return -ENOMEM;
1573
1574 atomic_set(&camss->ref_count, 0);
1575 camss->dev = dev;
1576 platform_set_drvdata(pdev, camss);
1577
1578 if (of_device_is_compatible(dev->of_node, "qcom,msm8916-camss")) {
1579 camss->version = CAMSS_8x16;
1580 camss->csiphy_num = 2;
1581 camss->csid_num = 2;
1582 camss->vfe_num = 1;
1583 } else if (of_device_is_compatible(dev->of_node,
1584 "qcom,msm8996-camss")) {
1585 camss->version = CAMSS_8x96;
1586 camss->csiphy_num = 3;
1587 camss->csid_num = 4;
1588 camss->vfe_num = 2;
1589 } else if (of_device_is_compatible(dev->of_node,
1590 "qcom,sdm660-camss")) {
1591 camss->version = CAMSS_660;
1592 camss->csiphy_num = 3;
1593 camss->csid_num = 4;
1594 camss->vfe_num = 2;
1595 } else if (of_device_is_compatible(dev->of_node,
1596 "qcom,sdm845-camss")) {
1597 camss->version = CAMSS_845;
1598 camss->csiphy_num = 4;
1599 camss->csid_num = 3;
1600 camss->vfe_num = 2;
1601 camss->vfe_lite_num = 1;
1602 } else if (of_device_is_compatible(dev->of_node,
1603 "qcom,sm8250-camss")) {
1604 camss->version = CAMSS_8250;
1605 camss->csiphy_num = 6;
1606 camss->csid_num = 4;
1607 camss->vfe_num = 2;
1608 camss->vfe_lite_num = 2;
1609 } else {
1610 return -EINVAL;
1611 }
1612
1613 camss->csiphy = devm_kcalloc(dev, camss->csiphy_num,
1614 sizeof(*camss->csiphy), GFP_KERNEL);
1615 if (!camss->csiphy)
1616 return -ENOMEM;
1617
1618 camss->csid = devm_kcalloc(dev, camss->csid_num, sizeof(*camss->csid),
1619 GFP_KERNEL);
1620 if (!camss->csid)
1621 return -ENOMEM;
1622
1623 if (camss->version == CAMSS_8x16 ||
1624 camss->version == CAMSS_8x96) {
1625 camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL);
1626 if (!camss->ispif)
1627 return -ENOMEM;
1628 }
1629
1630 camss->vfe = devm_kcalloc(dev, camss->vfe_num + camss->vfe_lite_num,
1631 sizeof(*camss->vfe), GFP_KERNEL);
1632 if (!camss->vfe)
1633 return -ENOMEM;
1634
1635 ret = camss_icc_get(camss);
1636 if (ret < 0)
1637 return ret;
1638
1639 ret = camss_configure_pd(camss);
1640 if (ret < 0) {
1641 dev_err(dev, "Failed to configure power domains: %d\n", ret);
1642 return ret;
1643 }
1644
1645 ret = camss_init_subdevices(camss);
1646 if (ret < 0)
1647 goto err_genpd_cleanup;
1648
1649 ret = dma_set_mask_and_coherent(dev, 0xffffffff);
1650 if (ret)
1651 goto err_genpd_cleanup;
1652
1653 camss->media_dev.dev = camss->dev;
1654 strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem",
1655 sizeof(camss->media_dev.model));
1656 camss->media_dev.ops = &camss_media_ops;
1657 media_device_init(&camss->media_dev);
1658
1659 camss->v4l2_dev.mdev = &camss->media_dev;
1660 ret = v4l2_device_register(camss->dev, &camss->v4l2_dev);
1661 if (ret < 0) {
1662 dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
1663 goto err_genpd_cleanup;
1664 }
1665
1666 v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev);
1667
1668 num_subdevs = camss_of_parse_ports(camss);
1669 if (num_subdevs < 0) {
1670 ret = num_subdevs;
1671 goto err_v4l2_device_unregister;
1672 }
1673
1674 ret = camss_register_entities(camss);
1675 if (ret < 0)
1676 goto err_v4l2_device_unregister;
1677
1678 if (num_subdevs) {
1679 camss->notifier.ops = &camss_subdev_notifier_ops;
1680
1681 ret = v4l2_async_nf_register(&camss->notifier);
1682 if (ret) {
1683 dev_err(dev,
1684 "Failed to register async subdev nodes: %d\n",
1685 ret);
1686 goto err_register_subdevs;
1687 }
1688 } else {
1689 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
1690 if (ret < 0) {
1691 dev_err(dev, "Failed to register subdev nodes: %d\n",
1692 ret);
1693 goto err_register_subdevs;
1694 }
1695
1696 ret = media_device_register(&camss->media_dev);
1697 if (ret < 0) {
1698 dev_err(dev, "Failed to register media device: %d\n",
1699 ret);
1700 goto err_register_subdevs;
1701 }
1702 }
1703
1704 pm_runtime_enable(dev);
1705
1706 return 0;
1707
1708 err_register_subdevs:
1709 camss_unregister_entities(camss);
1710 err_v4l2_device_unregister:
1711 v4l2_device_unregister(&camss->v4l2_dev);
1712 v4l2_async_nf_cleanup(&camss->notifier);
1713 err_genpd_cleanup:
1714 camss_genpd_cleanup(camss);
1715
1716 return ret;
1717 }
1718
camss_delete(struct camss * camss)1719 void camss_delete(struct camss *camss)
1720 {
1721 v4l2_device_unregister(&camss->v4l2_dev);
1722 media_device_unregister(&camss->media_dev);
1723 media_device_cleanup(&camss->media_dev);
1724
1725 pm_runtime_disable(camss->dev);
1726 }
1727
1728 /*
1729 * camss_remove - Remove CAMSS platform device
1730 * @pdev: Pointer to CAMSS platform device
1731 *
1732 * Always returns 0.
1733 */
camss_remove(struct platform_device * pdev)1734 static void camss_remove(struct platform_device *pdev)
1735 {
1736 struct camss *camss = platform_get_drvdata(pdev);
1737
1738 v4l2_async_nf_unregister(&camss->notifier);
1739 v4l2_async_nf_cleanup(&camss->notifier);
1740 camss_unregister_entities(camss);
1741
1742 if (atomic_read(&camss->ref_count) == 0)
1743 camss_delete(camss);
1744
1745 camss_genpd_cleanup(camss);
1746 }
1747
1748 static const struct of_device_id camss_dt_match[] = {
1749 { .compatible = "qcom,msm8916-camss" },
1750 { .compatible = "qcom,msm8996-camss" },
1751 { .compatible = "qcom,sdm660-camss" },
1752 { .compatible = "qcom,sdm845-camss" },
1753 { .compatible = "qcom,sm8250-camss" },
1754 { }
1755 };
1756
1757 MODULE_DEVICE_TABLE(of, camss_dt_match);
1758
camss_runtime_suspend(struct device * dev)1759 static int __maybe_unused camss_runtime_suspend(struct device *dev)
1760 {
1761 struct camss *camss = dev_get_drvdata(dev);
1762 int nbr_icc_paths = 0;
1763 int i;
1764 int ret;
1765
1766 if (camss->version == CAMSS_8250)
1767 nbr_icc_paths = ICC_SM8250_COUNT;
1768
1769 for (i = 0; i < nbr_icc_paths; i++) {
1770 ret = icc_set_bw(camss->icc_path[i], 0, 0);
1771 if (ret)
1772 return ret;
1773 }
1774
1775 return 0;
1776 }
1777
camss_runtime_resume(struct device * dev)1778 static int __maybe_unused camss_runtime_resume(struct device *dev)
1779 {
1780 struct camss *camss = dev_get_drvdata(dev);
1781 int nbr_icc_paths = 0;
1782 int i;
1783 int ret;
1784
1785 if (camss->version == CAMSS_8250)
1786 nbr_icc_paths = ICC_SM8250_COUNT;
1787
1788 for (i = 0; i < nbr_icc_paths; i++) {
1789 ret = icc_set_bw(camss->icc_path[i],
1790 camss->icc_bw_tbl[i].avg,
1791 camss->icc_bw_tbl[i].peak);
1792 if (ret)
1793 return ret;
1794 }
1795
1796 return 0;
1797 }
1798
1799 static const struct dev_pm_ops camss_pm_ops = {
1800 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1801 pm_runtime_force_resume)
1802 SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL)
1803 };
1804
1805 static struct platform_driver qcom_camss_driver = {
1806 .probe = camss_probe,
1807 .remove_new = camss_remove,
1808 .driver = {
1809 .name = "qcom-camss",
1810 .of_match_table = camss_dt_match,
1811 .pm = &camss_pm_ops,
1812 },
1813 };
1814
1815 module_platform_driver(qcom_camss_driver);
1816
1817 MODULE_ALIAS("platform:qcom-camss");
1818 MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
1819 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1820 MODULE_LICENSE("GPL v2");
1821