1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ACPI support for Intel Lynxpoint LPSS.
4 *
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/pxa2xx_ssp.h>
25 #include <linux/suspend.h>
26 #include <linux/delay.h>
27
28 #include "internal.h"
29
30 #ifdef CONFIG_X86_INTEL_LPSS
31
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
35
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
37
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
40
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
60
61 #define LPSS_PRV_REG_COUNT 9
62
63 /* LPSS Flags */
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
69 /*
70 * For some devices the DSDT AML code for another device turns off the device
71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
72 * as ctx register values.
73 * Luckily these devices always use the same ctx register values, so we can
74 * work around this by saving the ctx registers once on activation.
75 */
76 #define LPSS_SAVE_CTX_ONCE BIT(5)
77 #define LPSS_NO_D3_DELAY BIT(6)
78
79 struct lpss_private_data;
80
81 struct lpss_device_desc {
82 unsigned int flags;
83 const char *clk_con_id;
84 unsigned int prv_offset;
85 size_t prv_size_override;
86 const struct property_entry *properties;
87 void (*setup)(struct lpss_private_data *pdata);
88 bool resume_from_noirq;
89 };
90
91 static const struct lpss_device_desc lpss_dma_desc = {
92 .flags = LPSS_CLK,
93 };
94
95 struct lpss_private_data {
96 struct acpi_device *adev;
97 void __iomem *mmio_base;
98 resource_size_t mmio_size;
99 unsigned int fixed_clk_rate;
100 struct clk *clk;
101 const struct lpss_device_desc *dev_desc;
102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
103 };
104
105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
107
108 /* LPSS run time quirks */
109 static unsigned int lpss_quirks;
110
111 /*
112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
113 *
114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
115 * it can be powered off automatically whenever the last LPSS device goes down.
116 * In case of no power any access to the DMA controller will hang the system.
117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
118 * well as on ASuS T100TA transformer.
119 *
120 * This quirk overrides power state of entire LPSS island to keep DMA powered
121 * on whenever we have at least one other device in use.
122 */
123 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
124
125 /* UART Component Parameter Register */
126 #define LPSS_UART_CPR 0xF4
127 #define LPSS_UART_CPR_AFCE BIT(4)
128
lpss_uart_setup(struct lpss_private_data * pdata)129 static void lpss_uart_setup(struct lpss_private_data *pdata)
130 {
131 unsigned int offset;
132 u32 val;
133
134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
135 val = readl(pdata->mmio_base + offset);
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
137
138 val = readl(pdata->mmio_base + LPSS_UART_CPR);
139 if (!(val & LPSS_UART_CPR_AFCE)) {
140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
141 val = readl(pdata->mmio_base + offset);
142 val |= LPSS_GENERAL_UART_RTS_OVRD;
143 writel(val, pdata->mmio_base + offset);
144 }
145 }
146
lpss_deassert_reset(struct lpss_private_data * pdata)147 static void lpss_deassert_reset(struct lpss_private_data *pdata)
148 {
149 unsigned int offset;
150 u32 val;
151
152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
153 val = readl(pdata->mmio_base + offset);
154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
155 writel(val, pdata->mmio_base + offset);
156 }
157
158 /*
159 * BYT PWM used for backlight control by the i915 driver on systems without
160 * the Crystal Cove PMIC.
161 */
162 static struct pwm_lookup byt_pwm_lookup[] = {
163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
165 "pwm-lpss-platform"),
166 };
167
byt_pwm_setup(struct lpss_private_data * pdata)168 static void byt_pwm_setup(struct lpss_private_data *pdata)
169 {
170 u64 uid;
171
172 /* Only call pwm_add_table for the first PWM controller */
173 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
174 return;
175
176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
177 }
178
179 #define LPSS_I2C_ENABLE 0x6c
180
byt_i2c_setup(struct lpss_private_data * pdata)181 static void byt_i2c_setup(struct lpss_private_data *pdata)
182 {
183 acpi_handle handle = pdata->adev->handle;
184 unsigned long long shared_host = 0;
185 acpi_status status;
186 u64 uid;
187
188 /* Expected to always be successfull, but better safe then sorry */
189 if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
192 if (ACPI_SUCCESS(status) && shared_host)
193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
194 }
195
196 lpss_deassert_reset(pdata);
197
198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
199 pdata->fixed_clk_rate = 133000000;
200
201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
202 }
203
204 /*
205 * BSW PWM1 is used for backlight control by the i915 driver
206 * BSW PWM2 is used for backlight control for fixed (etched into the glass)
207 * touch controls on some models. These touch-controls have specialized
208 * drivers which know they need the "pwm_soc_lpss_2" con-id.
209 */
210 static struct pwm_lookup bsw_pwm_lookup[] = {
211 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
212 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
213 "pwm-lpss-platform"),
214 PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL,
215 "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL,
216 "pwm-lpss-platform"),
217 };
218
bsw_pwm_setup(struct lpss_private_data * pdata)219 static void bsw_pwm_setup(struct lpss_private_data *pdata)
220 {
221 u64 uid;
222
223 /* Only call pwm_add_table for the first PWM controller */
224 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
225 return;
226
227 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
228 }
229
230 static const struct property_entry lpt_spi_properties[] = {
231 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
232 { }
233 };
234
235 static const struct lpss_device_desc lpt_spi_dev_desc = {
236 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
237 | LPSS_SAVE_CTX,
238 .prv_offset = 0x800,
239 .properties = lpt_spi_properties,
240 };
241
242 static const struct lpss_device_desc lpt_i2c_dev_desc = {
243 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
244 .prv_offset = 0x800,
245 };
246
247 static struct property_entry uart_properties[] = {
248 PROPERTY_ENTRY_U32("reg-io-width", 4),
249 PROPERTY_ENTRY_U32("reg-shift", 2),
250 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
251 { },
252 };
253
254 static const struct lpss_device_desc lpt_uart_dev_desc = {
255 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
256 | LPSS_SAVE_CTX,
257 .clk_con_id = "baudclk",
258 .prv_offset = 0x800,
259 .setup = lpss_uart_setup,
260 .properties = uart_properties,
261 };
262
263 static const struct lpss_device_desc lpt_sdio_dev_desc = {
264 .flags = LPSS_LTR,
265 .prv_offset = 0x1000,
266 .prv_size_override = 0x1018,
267 };
268
269 static const struct lpss_device_desc byt_pwm_dev_desc = {
270 .flags = LPSS_SAVE_CTX,
271 .prv_offset = 0x800,
272 .setup = byt_pwm_setup,
273 };
274
275 static const struct lpss_device_desc bsw_pwm_dev_desc = {
276 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
277 .prv_offset = 0x800,
278 .setup = bsw_pwm_setup,
279 .resume_from_noirq = true,
280 };
281
282 static const struct lpss_device_desc bsw_pwm2_dev_desc = {
283 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
284 .prv_offset = 0x800,
285 .resume_from_noirq = true,
286 };
287
288 static const struct lpss_device_desc byt_uart_dev_desc = {
289 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
290 .clk_con_id = "baudclk",
291 .prv_offset = 0x800,
292 .setup = lpss_uart_setup,
293 .properties = uart_properties,
294 };
295
296 static const struct lpss_device_desc bsw_uart_dev_desc = {
297 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
298 | LPSS_NO_D3_DELAY,
299 .clk_con_id = "baudclk",
300 .prv_offset = 0x800,
301 .setup = lpss_uart_setup,
302 .properties = uart_properties,
303 };
304
305 static const struct property_entry byt_spi_properties[] = {
306 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
307 { }
308 };
309
310 static const struct lpss_device_desc byt_spi_dev_desc = {
311 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
312 .prv_offset = 0x400,
313 .properties = byt_spi_properties,
314 };
315
316 static const struct lpss_device_desc byt_sdio_dev_desc = {
317 .flags = LPSS_CLK,
318 };
319
320 static const struct lpss_device_desc byt_i2c_dev_desc = {
321 .flags = LPSS_CLK | LPSS_SAVE_CTX,
322 .prv_offset = 0x800,
323 .setup = byt_i2c_setup,
324 .resume_from_noirq = true,
325 };
326
327 static const struct lpss_device_desc bsw_i2c_dev_desc = {
328 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
329 .prv_offset = 0x800,
330 .setup = byt_i2c_setup,
331 .resume_from_noirq = true,
332 };
333
334 static const struct property_entry bsw_spi_properties[] = {
335 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
336 PROPERTY_ENTRY_U32("num-cs", 2),
337 { }
338 };
339
340 static const struct lpss_device_desc bsw_spi_dev_desc = {
341 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
342 | LPSS_NO_D3_DELAY,
343 .prv_offset = 0x400,
344 .setup = lpss_deassert_reset,
345 .properties = bsw_spi_properties,
346 };
347
348 static const struct x86_cpu_id lpss_cpu_ids[] = {
349 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
350 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
351 {}
352 };
353
354 #else
355
356 #define LPSS_ADDR(desc) (0UL)
357
358 #endif /* CONFIG_X86_INTEL_LPSS */
359
360 static const struct acpi_device_id acpi_lpss_device_ids[] = {
361 /* Generic LPSS devices */
362 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
363
364 /* Lynxpoint LPSS devices */
365 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
366 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
367 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
368 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
369 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
370 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
371 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
372 { "INT33C7", },
373
374 /* BayTrail LPSS devices */
375 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
376 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
377 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
378 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
379 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
380 { "INT33B2", },
381 { "INT33FC", },
382
383 /* Braswell LPSS devices */
384 { "80862286", LPSS_ADDR(lpss_dma_desc) },
385 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
386 { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) },
387 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
388 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
389 { "808622C0", LPSS_ADDR(lpss_dma_desc) },
390 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
391
392 /* Broadwell LPSS devices */
393 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
394 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
395 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
396 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
397 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
398 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
399 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
400 { "INT3437", },
401
402 /* Wildcat Point LPSS devices */
403 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
404
405 { }
406 };
407
408 #ifdef CONFIG_X86_INTEL_LPSS
409
410 /* LPSS main clock device. */
411 static struct platform_device *lpss_clk_dev;
412
lpt_register_clock_device(void)413 static inline void lpt_register_clock_device(void)
414 {
415 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
416 PLATFORM_DEVID_NONE,
417 NULL, 0);
418 }
419
register_device_clock(struct acpi_device * adev,struct lpss_private_data * pdata)420 static int register_device_clock(struct acpi_device *adev,
421 struct lpss_private_data *pdata)
422 {
423 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
424 const char *devname = dev_name(&adev->dev);
425 struct clk *clk;
426 struct lpss_clk_data *clk_data;
427 const char *parent, *clk_name;
428 void __iomem *prv_base;
429
430 if (!lpss_clk_dev)
431 lpt_register_clock_device();
432
433 if (IS_ERR(lpss_clk_dev))
434 return PTR_ERR(lpss_clk_dev);
435
436 clk_data = platform_get_drvdata(lpss_clk_dev);
437 if (!clk_data)
438 return -ENODEV;
439 clk = clk_data->clk;
440
441 if (!pdata->mmio_base
442 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
443 return -ENODATA;
444
445 parent = clk_data->name;
446 prv_base = pdata->mmio_base + dev_desc->prv_offset;
447
448 if (pdata->fixed_clk_rate) {
449 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
450 pdata->fixed_clk_rate);
451 goto out;
452 }
453
454 if (dev_desc->flags & LPSS_CLK_GATE) {
455 clk = clk_register_gate(NULL, devname, parent, 0,
456 prv_base, 0, 0, NULL);
457 parent = devname;
458 }
459
460 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
461 /* Prevent division by zero */
462 if (!readl(prv_base))
463 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
464
465 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
466 if (!clk_name)
467 return -ENOMEM;
468 clk = clk_register_fractional_divider(NULL, clk_name, parent,
469 0, prv_base, 1, 15, 16, 15,
470 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
471 NULL);
472 parent = clk_name;
473
474 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
475 if (!clk_name) {
476 kfree(parent);
477 return -ENOMEM;
478 }
479 clk = clk_register_gate(NULL, clk_name, parent,
480 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
481 prv_base, 31, 0, NULL);
482 kfree(parent);
483 kfree(clk_name);
484 }
485 out:
486 if (IS_ERR(clk))
487 return PTR_ERR(clk);
488
489 pdata->clk = clk;
490 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
491 return 0;
492 }
493
494 struct lpss_device_links {
495 const char *supplier_hid;
496 const char *supplier_uid;
497 const char *consumer_hid;
498 const char *consumer_uid;
499 u32 flags;
500 const struct dmi_system_id *dep_missing_ids;
501 };
502
503 /* Please keep this list sorted alphabetically by vendor and model */
504 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
505 {
506 .matches = {
507 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
508 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
509 },
510 },
511 {}
512 };
513
514 /*
515 * The _DEP method is used to identify dependencies but instead of creating
516 * device links for every handle in _DEP, only links in the following list are
517 * created. That is necessary because, in the general case, _DEP can refer to
518 * devices that might not have drivers, or that are on different buses, or where
519 * the supplier is not enumerated until after the consumer is probed.
520 */
521 static const struct lpss_device_links lpss_device_links[] = {
522 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
523 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
524 /* CHT iGPU depends on PMIC I2C controller */
525 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
526 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
527 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
528 i2c1_dep_missing_dmi_ids},
529 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
530 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
531 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
532 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
533 };
534
acpi_lpss_is_supplier(struct acpi_device * adev,const struct lpss_device_links * link)535 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
536 const struct lpss_device_links *link)
537 {
538 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
539 }
540
acpi_lpss_is_consumer(struct acpi_device * adev,const struct lpss_device_links * link)541 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
542 const struct lpss_device_links *link)
543 {
544 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
545 }
546
547 struct hid_uid {
548 const char *hid;
549 const char *uid;
550 };
551
match_hid_uid(struct device * dev,const void * data)552 static int match_hid_uid(struct device *dev, const void *data)
553 {
554 struct acpi_device *adev = ACPI_COMPANION(dev);
555 const struct hid_uid *id = data;
556
557 if (!adev)
558 return 0;
559
560 return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
561 }
562
acpi_lpss_find_device(const char * hid,const char * uid)563 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
564 {
565 struct device *dev;
566
567 struct hid_uid data = {
568 .hid = hid,
569 .uid = uid,
570 };
571
572 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
573 if (dev)
574 return dev;
575
576 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
577 }
578
acpi_lpss_dep(struct acpi_device * adev,acpi_handle handle)579 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
580 {
581 struct acpi_handle_list dep_devices;
582 acpi_status status;
583 int i;
584
585 if (!acpi_has_method(adev->handle, "_DEP"))
586 return false;
587
588 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
589 &dep_devices);
590 if (ACPI_FAILURE(status)) {
591 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
592 return false;
593 }
594
595 for (i = 0; i < dep_devices.count; i++) {
596 if (dep_devices.handles[i] == handle)
597 return true;
598 }
599
600 return false;
601 }
602
acpi_lpss_link_consumer(struct device * dev1,const struct lpss_device_links * link)603 static void acpi_lpss_link_consumer(struct device *dev1,
604 const struct lpss_device_links *link)
605 {
606 struct device *dev2;
607
608 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
609 if (!dev2)
610 return;
611
612 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
613 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
614 device_link_add(dev2, dev1, link->flags);
615
616 put_device(dev2);
617 }
618
acpi_lpss_link_supplier(struct device * dev1,const struct lpss_device_links * link)619 static void acpi_lpss_link_supplier(struct device *dev1,
620 const struct lpss_device_links *link)
621 {
622 struct device *dev2;
623
624 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
625 if (!dev2)
626 return;
627
628 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
629 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
630 device_link_add(dev1, dev2, link->flags);
631
632 put_device(dev2);
633 }
634
acpi_lpss_create_device_links(struct acpi_device * adev,struct platform_device * pdev)635 static void acpi_lpss_create_device_links(struct acpi_device *adev,
636 struct platform_device *pdev)
637 {
638 int i;
639
640 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
641 const struct lpss_device_links *link = &lpss_device_links[i];
642
643 if (acpi_lpss_is_supplier(adev, link))
644 acpi_lpss_link_consumer(&pdev->dev, link);
645
646 if (acpi_lpss_is_consumer(adev, link))
647 acpi_lpss_link_supplier(&pdev->dev, link);
648 }
649 }
650
acpi_lpss_create_device(struct acpi_device * adev,const struct acpi_device_id * id)651 static int acpi_lpss_create_device(struct acpi_device *adev,
652 const struct acpi_device_id *id)
653 {
654 const struct lpss_device_desc *dev_desc;
655 struct lpss_private_data *pdata;
656 struct resource_entry *rentry;
657 struct list_head resource_list;
658 struct platform_device *pdev;
659 int ret;
660
661 dev_desc = (const struct lpss_device_desc *)id->driver_data;
662 if (!dev_desc) {
663 pdev = acpi_create_platform_device(adev, NULL);
664 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
665 }
666 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
667 if (!pdata)
668 return -ENOMEM;
669
670 INIT_LIST_HEAD(&resource_list);
671 ret = acpi_dev_get_memory_resources(adev, &resource_list);
672 if (ret < 0)
673 goto err_out;
674
675 rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
676 if (rentry) {
677 if (dev_desc->prv_size_override)
678 pdata->mmio_size = dev_desc->prv_size_override;
679 else
680 pdata->mmio_size = resource_size(rentry->res);
681 pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
682 }
683
684 acpi_dev_free_resource_list(&resource_list);
685
686 if (!pdata->mmio_base) {
687 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
688 adev->pnp.type.platform_id = 0;
689 goto out_free;
690 }
691
692 pdata->adev = adev;
693 pdata->dev_desc = dev_desc;
694
695 if (dev_desc->setup)
696 dev_desc->setup(pdata);
697
698 if (dev_desc->flags & LPSS_CLK) {
699 ret = register_device_clock(adev, pdata);
700 if (ret)
701 goto out_free;
702 }
703
704 /*
705 * This works around a known issue in ACPI tables where LPSS devices
706 * have _PS0 and _PS3 without _PSC (and no power resources), so
707 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
708 */
709 acpi_device_fix_up_power(adev);
710
711 adev->driver_data = pdata;
712 pdev = acpi_create_platform_device(adev, dev_desc->properties);
713 if (IS_ERR_OR_NULL(pdev)) {
714 adev->driver_data = NULL;
715 ret = PTR_ERR(pdev);
716 goto err_out;
717 }
718
719 acpi_lpss_create_device_links(adev, pdev);
720 return 1;
721
722 out_free:
723 /* Skip the device, but continue the namespace scan */
724 ret = 0;
725 err_out:
726 kfree(pdata);
727 return ret;
728 }
729
__lpss_reg_read(struct lpss_private_data * pdata,unsigned int reg)730 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
731 {
732 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
733 }
734
__lpss_reg_write(u32 val,struct lpss_private_data * pdata,unsigned int reg)735 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
736 unsigned int reg)
737 {
738 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
739 }
740
lpss_reg_read(struct device * dev,unsigned int reg,u32 * val)741 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
742 {
743 struct acpi_device *adev = ACPI_COMPANION(dev);
744 struct lpss_private_data *pdata;
745 unsigned long flags;
746 int ret;
747
748 if (WARN_ON(!adev))
749 return -ENODEV;
750
751 spin_lock_irqsave(&dev->power.lock, flags);
752 if (pm_runtime_suspended(dev)) {
753 ret = -EAGAIN;
754 goto out;
755 }
756 pdata = acpi_driver_data(adev);
757 if (WARN_ON(!pdata || !pdata->mmio_base)) {
758 ret = -ENODEV;
759 goto out;
760 }
761 *val = __lpss_reg_read(pdata, reg);
762 ret = 0;
763
764 out:
765 spin_unlock_irqrestore(&dev->power.lock, flags);
766 return ret;
767 }
768
lpss_ltr_show(struct device * dev,struct device_attribute * attr,char * buf)769 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
770 char *buf)
771 {
772 u32 ltr_value = 0;
773 unsigned int reg;
774 int ret;
775
776 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
777 ret = lpss_reg_read(dev, reg, <r_value);
778 if (ret)
779 return ret;
780
781 return sysfs_emit(buf, "%08x\n", ltr_value);
782 }
783
lpss_ltr_mode_show(struct device * dev,struct device_attribute * attr,char * buf)784 static ssize_t lpss_ltr_mode_show(struct device *dev,
785 struct device_attribute *attr, char *buf)
786 {
787 u32 ltr_mode = 0;
788 char *outstr;
789 int ret;
790
791 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
792 if (ret)
793 return ret;
794
795 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
796 return sprintf(buf, "%s\n", outstr);
797 }
798
799 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
800 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
801 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
802
803 static struct attribute *lpss_attrs[] = {
804 &dev_attr_auto_ltr.attr,
805 &dev_attr_sw_ltr.attr,
806 &dev_attr_ltr_mode.attr,
807 NULL,
808 };
809
810 static const struct attribute_group lpss_attr_group = {
811 .attrs = lpss_attrs,
812 .name = "lpss_ltr",
813 };
814
acpi_lpss_set_ltr(struct device * dev,s32 val)815 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
816 {
817 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
818 u32 ltr_mode, ltr_val;
819
820 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
821 if (val < 0) {
822 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
823 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
824 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
825 }
826 return;
827 }
828 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
829 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
830 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
831 val = LPSS_LTR_MAX_VAL;
832 } else if (val > LPSS_LTR_MAX_VAL) {
833 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
834 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
835 } else {
836 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
837 }
838 ltr_val |= val;
839 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
840 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
841 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
842 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
843 }
844 }
845
846 #ifdef CONFIG_PM
847 /**
848 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
849 * @dev: LPSS device
850 * @pdata: pointer to the private data of the LPSS device
851 *
852 * Most LPSS devices have private registers which may loose their context when
853 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
854 * prv_reg_ctx array.
855 */
acpi_lpss_save_ctx(struct device * dev,struct lpss_private_data * pdata)856 static void acpi_lpss_save_ctx(struct device *dev,
857 struct lpss_private_data *pdata)
858 {
859 unsigned int i;
860
861 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
862 unsigned long offset = i * sizeof(u32);
863
864 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
865 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
866 pdata->prv_reg_ctx[i], offset);
867 }
868 }
869
870 /**
871 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
872 * @dev: LPSS device
873 * @pdata: pointer to the private data of the LPSS device
874 *
875 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
876 */
acpi_lpss_restore_ctx(struct device * dev,struct lpss_private_data * pdata)877 static void acpi_lpss_restore_ctx(struct device *dev,
878 struct lpss_private_data *pdata)
879 {
880 unsigned int i;
881
882 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
883 unsigned long offset = i * sizeof(u32);
884
885 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
886 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
887 pdata->prv_reg_ctx[i], offset);
888 }
889 }
890
acpi_lpss_d3_to_d0_delay(struct lpss_private_data * pdata)891 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
892 {
893 /*
894 * The following delay is needed or the subsequent write operations may
895 * fail. The LPSS devices are actually PCI devices and the PCI spec
896 * expects 10ms delay before the device can be accessed after D3 to D0
897 * transition. However some platforms like BSW does not need this delay.
898 */
899 unsigned int delay = 10; /* default 10ms delay */
900
901 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
902 delay = 0;
903
904 msleep(delay);
905 }
906
acpi_lpss_activate(struct device * dev)907 static int acpi_lpss_activate(struct device *dev)
908 {
909 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
910 int ret;
911
912 ret = acpi_dev_resume(dev);
913 if (ret)
914 return ret;
915
916 acpi_lpss_d3_to_d0_delay(pdata);
917
918 /*
919 * This is called only on ->probe() stage where a device is either in
920 * known state defined by BIOS or most likely powered off. Due to this
921 * we have to deassert reset line to be sure that ->probe() will
922 * recognize the device.
923 */
924 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
925 lpss_deassert_reset(pdata);
926
927 #ifdef CONFIG_PM
928 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
929 acpi_lpss_save_ctx(dev, pdata);
930 #endif
931
932 return 0;
933 }
934
acpi_lpss_dismiss(struct device * dev)935 static void acpi_lpss_dismiss(struct device *dev)
936 {
937 acpi_dev_suspend(dev, false);
938 }
939
940 /* IOSF SB for LPSS island */
941 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
942 #define LPSS_IOSF_UNIT_LPIO1 0xAB
943 #define LPSS_IOSF_UNIT_LPIO2 0xAC
944
945 #define LPSS_IOSF_PMCSR 0x84
946 #define LPSS_PMCSR_D0 0
947 #define LPSS_PMCSR_D3hot 3
948 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
949
950 #define LPSS_IOSF_GPIODEF0 0x154
951 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
952 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
953 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
954 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
955
956 static DEFINE_MUTEX(lpss_iosf_mutex);
957 static bool lpss_iosf_d3_entered = true;
958
lpss_iosf_enter_d3_state(void)959 static void lpss_iosf_enter_d3_state(void)
960 {
961 u32 value1 = 0;
962 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
963 u32 value2 = LPSS_PMCSR_D3hot;
964 u32 mask2 = LPSS_PMCSR_Dx_MASK;
965 /*
966 * PMC provides an information about actual status of the LPSS devices.
967 * Here we read the values related to LPSS power island, i.e. LPSS
968 * devices, excluding both LPSS DMA controllers, along with SCC domain.
969 */
970 u32 func_dis, d3_sts_0, pmc_status;
971 int ret;
972
973 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
974 if (ret)
975 return;
976
977 mutex_lock(&lpss_iosf_mutex);
978
979 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
980 if (ret)
981 goto exit;
982
983 /*
984 * Get the status of entire LPSS power island per device basis.
985 * Shutdown both LPSS DMA controllers if and only if all other devices
986 * are already in D3hot.
987 */
988 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
989 if (pmc_status)
990 goto exit;
991
992 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
993 LPSS_IOSF_PMCSR, value2, mask2);
994
995 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
996 LPSS_IOSF_PMCSR, value2, mask2);
997
998 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
999 LPSS_IOSF_GPIODEF0, value1, mask1);
1000
1001 lpss_iosf_d3_entered = true;
1002
1003 exit:
1004 mutex_unlock(&lpss_iosf_mutex);
1005 }
1006
lpss_iosf_exit_d3_state(void)1007 static void lpss_iosf_exit_d3_state(void)
1008 {
1009 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
1010 LPSS_GPIODEF0_DMA_LLP;
1011 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
1012 u32 value2 = LPSS_PMCSR_D0;
1013 u32 mask2 = LPSS_PMCSR_Dx_MASK;
1014
1015 mutex_lock(&lpss_iosf_mutex);
1016
1017 if (!lpss_iosf_d3_entered)
1018 goto exit;
1019
1020 lpss_iosf_d3_entered = false;
1021
1022 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
1023 LPSS_IOSF_GPIODEF0, value1, mask1);
1024
1025 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1026 LPSS_IOSF_PMCSR, value2, mask2);
1027
1028 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1029 LPSS_IOSF_PMCSR, value2, mask2);
1030
1031 exit:
1032 mutex_unlock(&lpss_iosf_mutex);
1033 }
1034
acpi_lpss_suspend(struct device * dev,bool wakeup)1035 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1036 {
1037 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1038 int ret;
1039
1040 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1041 acpi_lpss_save_ctx(dev, pdata);
1042
1043 ret = acpi_dev_suspend(dev, wakeup);
1044
1045 /*
1046 * This call must be last in the sequence, otherwise PMC will return
1047 * wrong status for devices being about to be powered off. See
1048 * lpss_iosf_enter_d3_state() for further information.
1049 */
1050 if (acpi_target_system_state() == ACPI_STATE_S0 &&
1051 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1052 lpss_iosf_enter_d3_state();
1053
1054 return ret;
1055 }
1056
acpi_lpss_resume(struct device * dev)1057 static int acpi_lpss_resume(struct device *dev)
1058 {
1059 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1060 int ret;
1061
1062 /*
1063 * This call is kept first to be in symmetry with
1064 * acpi_lpss_runtime_suspend() one.
1065 */
1066 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1067 lpss_iosf_exit_d3_state();
1068
1069 ret = acpi_dev_resume(dev);
1070 if (ret)
1071 return ret;
1072
1073 acpi_lpss_d3_to_d0_delay(pdata);
1074
1075 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1076 acpi_lpss_restore_ctx(dev, pdata);
1077
1078 return 0;
1079 }
1080
1081 #ifdef CONFIG_PM_SLEEP
acpi_lpss_do_suspend_late(struct device * dev)1082 static int acpi_lpss_do_suspend_late(struct device *dev)
1083 {
1084 int ret;
1085
1086 if (dev_pm_skip_suspend(dev))
1087 return 0;
1088
1089 ret = pm_generic_suspend_late(dev);
1090 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1091 }
1092
acpi_lpss_suspend_late(struct device * dev)1093 static int acpi_lpss_suspend_late(struct device *dev)
1094 {
1095 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1096
1097 if (pdata->dev_desc->resume_from_noirq)
1098 return 0;
1099
1100 return acpi_lpss_do_suspend_late(dev);
1101 }
1102
acpi_lpss_suspend_noirq(struct device * dev)1103 static int acpi_lpss_suspend_noirq(struct device *dev)
1104 {
1105 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1106 int ret;
1107
1108 if (pdata->dev_desc->resume_from_noirq) {
1109 /*
1110 * The driver's ->suspend_late callback will be invoked by
1111 * acpi_lpss_do_suspend_late(), with the assumption that the
1112 * driver really wanted to run that code in ->suspend_noirq, but
1113 * it could not run after acpi_dev_suspend() and the driver
1114 * expected the latter to be called in the "late" phase.
1115 */
1116 ret = acpi_lpss_do_suspend_late(dev);
1117 if (ret)
1118 return ret;
1119 }
1120
1121 return acpi_subsys_suspend_noirq(dev);
1122 }
1123
acpi_lpss_do_resume_early(struct device * dev)1124 static int acpi_lpss_do_resume_early(struct device *dev)
1125 {
1126 int ret = acpi_lpss_resume(dev);
1127
1128 return ret ? ret : pm_generic_resume_early(dev);
1129 }
1130
acpi_lpss_resume_early(struct device * dev)1131 static int acpi_lpss_resume_early(struct device *dev)
1132 {
1133 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1134
1135 if (pdata->dev_desc->resume_from_noirq)
1136 return 0;
1137
1138 if (dev_pm_skip_resume(dev))
1139 return 0;
1140
1141 return acpi_lpss_do_resume_early(dev);
1142 }
1143
acpi_lpss_resume_noirq(struct device * dev)1144 static int acpi_lpss_resume_noirq(struct device *dev)
1145 {
1146 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1147 int ret;
1148
1149 /* Follow acpi_subsys_resume_noirq(). */
1150 if (dev_pm_skip_resume(dev))
1151 return 0;
1152
1153 ret = pm_generic_resume_noirq(dev);
1154 if (ret)
1155 return ret;
1156
1157 if (!pdata->dev_desc->resume_from_noirq)
1158 return 0;
1159
1160 /*
1161 * The driver's ->resume_early callback will be invoked by
1162 * acpi_lpss_do_resume_early(), with the assumption that the driver
1163 * really wanted to run that code in ->resume_noirq, but it could not
1164 * run before acpi_dev_resume() and the driver expected the latter to be
1165 * called in the "early" phase.
1166 */
1167 return acpi_lpss_do_resume_early(dev);
1168 }
1169
acpi_lpss_do_restore_early(struct device * dev)1170 static int acpi_lpss_do_restore_early(struct device *dev)
1171 {
1172 int ret = acpi_lpss_resume(dev);
1173
1174 return ret ? ret : pm_generic_restore_early(dev);
1175 }
1176
acpi_lpss_restore_early(struct device * dev)1177 static int acpi_lpss_restore_early(struct device *dev)
1178 {
1179 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1180
1181 if (pdata->dev_desc->resume_from_noirq)
1182 return 0;
1183
1184 return acpi_lpss_do_restore_early(dev);
1185 }
1186
acpi_lpss_restore_noirq(struct device * dev)1187 static int acpi_lpss_restore_noirq(struct device *dev)
1188 {
1189 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1190 int ret;
1191
1192 ret = pm_generic_restore_noirq(dev);
1193 if (ret)
1194 return ret;
1195
1196 if (!pdata->dev_desc->resume_from_noirq)
1197 return 0;
1198
1199 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1200 return acpi_lpss_do_restore_early(dev);
1201 }
1202
acpi_lpss_do_poweroff_late(struct device * dev)1203 static int acpi_lpss_do_poweroff_late(struct device *dev)
1204 {
1205 int ret = pm_generic_poweroff_late(dev);
1206
1207 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1208 }
1209
acpi_lpss_poweroff_late(struct device * dev)1210 static int acpi_lpss_poweroff_late(struct device *dev)
1211 {
1212 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1213
1214 if (dev_pm_skip_suspend(dev))
1215 return 0;
1216
1217 if (pdata->dev_desc->resume_from_noirq)
1218 return 0;
1219
1220 return acpi_lpss_do_poweroff_late(dev);
1221 }
1222
acpi_lpss_poweroff_noirq(struct device * dev)1223 static int acpi_lpss_poweroff_noirq(struct device *dev)
1224 {
1225 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1226
1227 if (dev_pm_skip_suspend(dev))
1228 return 0;
1229
1230 if (pdata->dev_desc->resume_from_noirq) {
1231 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1232 int ret = acpi_lpss_do_poweroff_late(dev);
1233
1234 if (ret)
1235 return ret;
1236 }
1237
1238 return pm_generic_poweroff_noirq(dev);
1239 }
1240 #endif /* CONFIG_PM_SLEEP */
1241
acpi_lpss_runtime_suspend(struct device * dev)1242 static int acpi_lpss_runtime_suspend(struct device *dev)
1243 {
1244 int ret = pm_generic_runtime_suspend(dev);
1245
1246 return ret ? ret : acpi_lpss_suspend(dev, true);
1247 }
1248
acpi_lpss_runtime_resume(struct device * dev)1249 static int acpi_lpss_runtime_resume(struct device *dev)
1250 {
1251 int ret = acpi_lpss_resume(dev);
1252
1253 return ret ? ret : pm_generic_runtime_resume(dev);
1254 }
1255 #endif /* CONFIG_PM */
1256
1257 static struct dev_pm_domain acpi_lpss_pm_domain = {
1258 #ifdef CONFIG_PM
1259 .activate = acpi_lpss_activate,
1260 .dismiss = acpi_lpss_dismiss,
1261 #endif
1262 .ops = {
1263 #ifdef CONFIG_PM
1264 #ifdef CONFIG_PM_SLEEP
1265 .prepare = acpi_subsys_prepare,
1266 .complete = acpi_subsys_complete,
1267 .suspend = acpi_subsys_suspend,
1268 .suspend_late = acpi_lpss_suspend_late,
1269 .suspend_noirq = acpi_lpss_suspend_noirq,
1270 .resume_noirq = acpi_lpss_resume_noirq,
1271 .resume_early = acpi_lpss_resume_early,
1272 .freeze = acpi_subsys_freeze,
1273 .poweroff = acpi_subsys_poweroff,
1274 .poweroff_late = acpi_lpss_poweroff_late,
1275 .poweroff_noirq = acpi_lpss_poweroff_noirq,
1276 .restore_noirq = acpi_lpss_restore_noirq,
1277 .restore_early = acpi_lpss_restore_early,
1278 #endif
1279 .runtime_suspend = acpi_lpss_runtime_suspend,
1280 .runtime_resume = acpi_lpss_runtime_resume,
1281 #endif
1282 },
1283 };
1284
acpi_lpss_platform_notify(struct notifier_block * nb,unsigned long action,void * data)1285 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1286 unsigned long action, void *data)
1287 {
1288 struct platform_device *pdev = to_platform_device(data);
1289 struct lpss_private_data *pdata;
1290 struct acpi_device *adev;
1291 const struct acpi_device_id *id;
1292
1293 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1294 if (!id || !id->driver_data)
1295 return 0;
1296
1297 adev = ACPI_COMPANION(&pdev->dev);
1298 if (!adev)
1299 return 0;
1300
1301 pdata = acpi_driver_data(adev);
1302 if (!pdata)
1303 return 0;
1304
1305 if (pdata->mmio_base &&
1306 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1307 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1308 return 0;
1309 }
1310
1311 switch (action) {
1312 case BUS_NOTIFY_BIND_DRIVER:
1313 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1314 break;
1315 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1316 case BUS_NOTIFY_UNBOUND_DRIVER:
1317 dev_pm_domain_set(&pdev->dev, NULL);
1318 break;
1319 case BUS_NOTIFY_ADD_DEVICE:
1320 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1321 if (pdata->dev_desc->flags & LPSS_LTR)
1322 return sysfs_create_group(&pdev->dev.kobj,
1323 &lpss_attr_group);
1324 break;
1325 case BUS_NOTIFY_DEL_DEVICE:
1326 if (pdata->dev_desc->flags & LPSS_LTR)
1327 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1328 dev_pm_domain_set(&pdev->dev, NULL);
1329 break;
1330 default:
1331 break;
1332 }
1333
1334 return 0;
1335 }
1336
1337 static struct notifier_block acpi_lpss_nb = {
1338 .notifier_call = acpi_lpss_platform_notify,
1339 };
1340
acpi_lpss_bind(struct device * dev)1341 static void acpi_lpss_bind(struct device *dev)
1342 {
1343 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1344
1345 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1346 return;
1347
1348 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1349 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1350 else
1351 dev_err(dev, "MMIO size insufficient to access LTR\n");
1352 }
1353
acpi_lpss_unbind(struct device * dev)1354 static void acpi_lpss_unbind(struct device *dev)
1355 {
1356 dev->power.set_latency_tolerance = NULL;
1357 }
1358
1359 static struct acpi_scan_handler lpss_handler = {
1360 .ids = acpi_lpss_device_ids,
1361 .attach = acpi_lpss_create_device,
1362 .bind = acpi_lpss_bind,
1363 .unbind = acpi_lpss_unbind,
1364 };
1365
acpi_lpss_init(void)1366 void __init acpi_lpss_init(void)
1367 {
1368 const struct x86_cpu_id *id;
1369 int ret;
1370
1371 ret = lpss_atom_clk_init();
1372 if (ret)
1373 return;
1374
1375 id = x86_match_cpu(lpss_cpu_ids);
1376 if (id)
1377 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1378
1379 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1380 acpi_scan_add_handler(&lpss_handler);
1381 }
1382
1383 #else
1384
1385 static struct acpi_scan_handler lpss_handler = {
1386 .ids = acpi_lpss_device_ids,
1387 };
1388
acpi_lpss_init(void)1389 void __init acpi_lpss_init(void)
1390 {
1391 acpi_scan_add_handler(&lpss_handler);
1392 }
1393
1394 #endif /* CONFIG_X86_INTEL_LPSS */
1395