1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * Thanks to the following companies for their support:
7 *
8 * - JMicron (hardware and technical support)
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/string.h>
13 #include <linux/delay.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/scatterlist.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/gpio.h>
24 #include <linux/gpio/machine.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/pm_qos.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <linux/dmi.h>
30
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #ifdef CONFIG_X86
36 #include <asm/iosf_mbi.h>
37 #endif
38
39 #include "cqhci.h"
40
41 #include "sdhci.h"
42 #include "sdhci-cqhci.h"
43 #include "sdhci-pci.h"
44
45 static void sdhci_pci_hw_reset(struct sdhci_host *host);
46
47 #ifdef CONFIG_PM_SLEEP
sdhci_pci_init_wakeup(struct sdhci_pci_chip * chip)48 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
49 {
50 mmc_pm_flag_t pm_flags = 0;
51 bool cap_cd_wake = false;
52 int i;
53
54 for (i = 0; i < chip->num_slots; i++) {
55 struct sdhci_pci_slot *slot = chip->slots[i];
56
57 if (slot) {
58 pm_flags |= slot->host->mmc->pm_flags;
59 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
60 cap_cd_wake = true;
61 }
62 }
63
64 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
65 return device_wakeup_enable(&chip->pdev->dev);
66 else if (!cap_cd_wake)
67 return device_wakeup_disable(&chip->pdev->dev);
68
69 return 0;
70 }
71
sdhci_pci_suspend_host(struct sdhci_pci_chip * chip)72 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
73 {
74 int i, ret;
75
76 sdhci_pci_init_wakeup(chip);
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80 struct sdhci_host *host;
81
82 if (!slot)
83 continue;
84
85 host = slot->host;
86
87 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
88 mmc_retune_needed(host->mmc);
89
90 ret = sdhci_suspend_host(host);
91 if (ret)
92 goto err_pci_suspend;
93
94 if (device_may_wakeup(&chip->pdev->dev))
95 mmc_gpio_set_cd_wake(host->mmc, true);
96 }
97
98 return 0;
99
100 err_pci_suspend:
101 while (--i >= 0)
102 sdhci_resume_host(chip->slots[i]->host);
103 return ret;
104 }
105
sdhci_pci_resume_host(struct sdhci_pci_chip * chip)106 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
107 {
108 struct sdhci_pci_slot *slot;
109 int i, ret;
110
111 for (i = 0; i < chip->num_slots; i++) {
112 slot = chip->slots[i];
113 if (!slot)
114 continue;
115
116 ret = sdhci_resume_host(slot->host);
117 if (ret)
118 return ret;
119
120 mmc_gpio_set_cd_wake(slot->host->mmc, false);
121 }
122
123 return 0;
124 }
125
sdhci_cqhci_suspend(struct sdhci_pci_chip * chip)126 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
127 {
128 int ret;
129
130 ret = cqhci_suspend(chip->slots[0]->host->mmc);
131 if (ret)
132 return ret;
133
134 return sdhci_pci_suspend_host(chip);
135 }
136
sdhci_cqhci_resume(struct sdhci_pci_chip * chip)137 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
138 {
139 int ret;
140
141 ret = sdhci_pci_resume_host(chip);
142 if (ret)
143 return ret;
144
145 return cqhci_resume(chip->slots[0]->host->mmc);
146 }
147 #endif
148
149 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip * chip)150 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
151 {
152 struct sdhci_pci_slot *slot;
153 struct sdhci_host *host;
154 int i, ret;
155
156 for (i = 0; i < chip->num_slots; i++) {
157 slot = chip->slots[i];
158 if (!slot)
159 continue;
160
161 host = slot->host;
162
163 ret = sdhci_runtime_suspend_host(host);
164 if (ret)
165 goto err_pci_runtime_suspend;
166
167 if (chip->rpm_retune &&
168 host->tuning_mode != SDHCI_TUNING_MODE_3)
169 mmc_retune_needed(host->mmc);
170 }
171
172 return 0;
173
174 err_pci_runtime_suspend:
175 while (--i >= 0)
176 sdhci_runtime_resume_host(chip->slots[i]->host, 0);
177 return ret;
178 }
179
sdhci_pci_runtime_resume_host(struct sdhci_pci_chip * chip)180 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
181 {
182 struct sdhci_pci_slot *slot;
183 int i, ret;
184
185 for (i = 0; i < chip->num_slots; i++) {
186 slot = chip->slots[i];
187 if (!slot)
188 continue;
189
190 ret = sdhci_runtime_resume_host(slot->host, 0);
191 if (ret)
192 return ret;
193 }
194
195 return 0;
196 }
197
sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip * chip)198 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
199 {
200 int ret;
201
202 ret = cqhci_suspend(chip->slots[0]->host->mmc);
203 if (ret)
204 return ret;
205
206 return sdhci_pci_runtime_suspend_host(chip);
207 }
208
sdhci_cqhci_runtime_resume(struct sdhci_pci_chip * chip)209 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
210 {
211 int ret;
212
213 ret = sdhci_pci_runtime_resume_host(chip);
214 if (ret)
215 return ret;
216
217 return cqhci_resume(chip->slots[0]->host->mmc);
218 }
219 #endif
220
sdhci_cqhci_irq(struct sdhci_host * host,u32 intmask)221 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
222 {
223 int cmd_error = 0;
224 int data_error = 0;
225
226 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
227 return intmask;
228
229 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
230
231 return 0;
232 }
233
sdhci_pci_dumpregs(struct mmc_host * mmc)234 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
235 {
236 sdhci_dumpregs(mmc_priv(mmc));
237 }
238
239 /*****************************************************************************\
240 * *
241 * Hardware specific quirk handling *
242 * *
243 \*****************************************************************************/
244
ricoh_probe(struct sdhci_pci_chip * chip)245 static int ricoh_probe(struct sdhci_pci_chip *chip)
246 {
247 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
248 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
249 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
250 return 0;
251 }
252
ricoh_mmc_probe_slot(struct sdhci_pci_slot * slot)253 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
254 {
255 u32 caps =
256 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) |
257 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) |
258 SDHCI_TIMEOUT_CLK_UNIT |
259 SDHCI_CAN_VDD_330 |
260 SDHCI_CAN_DO_HISPD |
261 SDHCI_CAN_DO_SDMA;
262 u32 caps1 = 0;
263
264 __sdhci_read_caps(slot->host, NULL, &caps, &caps1);
265 return 0;
266 }
267
268 #ifdef CONFIG_PM_SLEEP
ricoh_mmc_resume(struct sdhci_pci_chip * chip)269 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
270 {
271 /* Apply a delay to allow controller to settle */
272 /* Otherwise it becomes confused if card state changed
273 during suspend */
274 msleep(500);
275 return sdhci_pci_resume_host(chip);
276 }
277 #endif
278
279 static const struct sdhci_pci_fixes sdhci_ricoh = {
280 .probe = ricoh_probe,
281 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
282 SDHCI_QUIRK_FORCE_DMA |
283 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
284 };
285
286 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
287 .probe_slot = ricoh_mmc_probe_slot,
288 #ifdef CONFIG_PM_SLEEP
289 .resume = ricoh_mmc_resume,
290 #endif
291 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
292 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
293 SDHCI_QUIRK_NO_CARD_NO_RESET,
294 };
295
ene_714_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)296 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
297 {
298 struct sdhci_host *host = mmc_priv(mmc);
299
300 sdhci_set_ios(mmc, ios);
301
302 /*
303 * Some (ENE) controllers misbehave on some ios operations,
304 * signalling timeout and CRC errors even on CMD0. Resetting
305 * it on each ios seems to solve the problem.
306 */
307 if (!(host->flags & SDHCI_DEVICE_DEAD))
308 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
309 }
310
ene_714_probe_slot(struct sdhci_pci_slot * slot)311 static int ene_714_probe_slot(struct sdhci_pci_slot *slot)
312 {
313 slot->host->mmc_host_ops.set_ios = ene_714_set_ios;
314 return 0;
315 }
316
317 static const struct sdhci_pci_fixes sdhci_ene_712 = {
318 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
319 SDHCI_QUIRK_BROKEN_DMA,
320 };
321
322 static const struct sdhci_pci_fixes sdhci_ene_714 = {
323 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
324 SDHCI_QUIRK_BROKEN_DMA,
325 .probe_slot = ene_714_probe_slot,
326 };
327
328 static const struct sdhci_pci_fixes sdhci_cafe = {
329 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
330 SDHCI_QUIRK_NO_BUSY_IRQ |
331 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
332 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
333 };
334
335 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
336 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
337 };
338
mrst_hc_probe_slot(struct sdhci_pci_slot * slot)339 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
340 {
341 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
342 return 0;
343 }
344
345 /*
346 * ADMA operation is disabled for Moorestown platform due to
347 * hardware bugs.
348 */
mrst_hc_probe(struct sdhci_pci_chip * chip)349 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
350 {
351 /*
352 * slots number is fixed here for MRST as SDIO3/5 are never used and
353 * have hardware bugs.
354 */
355 chip->num_slots = 1;
356 return 0;
357 }
358
pch_hc_probe_slot(struct sdhci_pci_slot * slot)359 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
360 {
361 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
362 return 0;
363 }
364
mfd_emmc_probe_slot(struct sdhci_pci_slot * slot)365 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
366 {
367 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
368 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
369 return 0;
370 }
371
mfd_sdio_probe_slot(struct sdhci_pci_slot * slot)372 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
373 {
374 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
375 return 0;
376 }
377
378 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
379 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
380 .probe_slot = mrst_hc_probe_slot,
381 };
382
383 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
384 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
385 .probe = mrst_hc_probe,
386 };
387
388 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
389 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 };
393
394 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
396 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
397 .allow_runtime_pm = true,
398 .probe_slot = mfd_sdio_probe_slot,
399 };
400
401 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
403 .allow_runtime_pm = true,
404 .probe_slot = mfd_emmc_probe_slot,
405 };
406
407 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
408 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
409 .probe_slot = pch_hc_probe_slot,
410 };
411
412 #ifdef CONFIG_X86
413
414 #define BYT_IOSF_SCCEP 0x63
415 #define BYT_IOSF_OCP_NETCTRL0 0x1078
416 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
417
byt_ocp_setting(struct pci_dev * pdev)418 static void byt_ocp_setting(struct pci_dev *pdev)
419 {
420 u32 val = 0;
421
422 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
423 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
424 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
425 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
426 return;
427
428 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
429 &val)) {
430 dev_err(&pdev->dev, "%s read error\n", __func__);
431 return;
432 }
433
434 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
435 return;
436
437 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
438
439 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
440 val)) {
441 dev_err(&pdev->dev, "%s write error\n", __func__);
442 return;
443 }
444
445 dev_dbg(&pdev->dev, "%s completed\n", __func__);
446 }
447
448 #else
449
byt_ocp_setting(struct pci_dev * pdev)450 static inline void byt_ocp_setting(struct pci_dev *pdev)
451 {
452 }
453
454 #endif
455
456 enum {
457 INTEL_DSM_FNS = 0,
458 INTEL_DSM_V18_SWITCH = 3,
459 INTEL_DSM_V33_SWITCH = 4,
460 INTEL_DSM_DRV_STRENGTH = 9,
461 INTEL_DSM_D3_RETUNE = 10,
462 };
463
464 struct intel_host {
465 u32 dsm_fns;
466 int drv_strength;
467 bool d3_retune;
468 bool rpm_retune_ok;
469 bool needs_pwr_off;
470 u32 glk_rx_ctrl1;
471 u32 glk_tun_val;
472 u32 active_ltr;
473 u32 idle_ltr;
474 };
475
476 static const guid_t intel_dsm_guid =
477 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
478 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
479
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)480 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
481 unsigned int fn, u32 *result)
482 {
483 union acpi_object *obj;
484 int err = 0;
485 size_t len;
486
487 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
488 if (!obj)
489 return -EOPNOTSUPP;
490
491 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
492 err = -EINVAL;
493 goto out;
494 }
495
496 len = min_t(size_t, obj->buffer.length, 4);
497
498 *result = 0;
499 memcpy(result, obj->buffer.pointer, len);
500 out:
501 ACPI_FREE(obj);
502
503 return err;
504 }
505
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)506 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
507 unsigned int fn, u32 *result)
508 {
509 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
510 return -EOPNOTSUPP;
511
512 return __intel_dsm(intel_host, dev, fn, result);
513 }
514
intel_dsm_init(struct intel_host * intel_host,struct device * dev,struct mmc_host * mmc)515 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
516 struct mmc_host *mmc)
517 {
518 int err;
519 u32 val;
520
521 intel_host->d3_retune = true;
522
523 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
524 if (err) {
525 pr_debug("%s: DSM not supported, error %d\n",
526 mmc_hostname(mmc), err);
527 return;
528 }
529
530 pr_debug("%s: DSM function mask %#x\n",
531 mmc_hostname(mmc), intel_host->dsm_fns);
532
533 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
534 intel_host->drv_strength = err ? 0 : val;
535
536 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
537 intel_host->d3_retune = err ? true : !!val;
538 }
539
sdhci_pci_int_hw_reset(struct sdhci_host * host)540 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
541 {
542 u8 reg;
543
544 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
545 reg |= 0x10;
546 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
547 /* For eMMC, minimum is 1us but give it 9us for good measure */
548 udelay(9);
549 reg &= ~0x10;
550 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
551 /* For eMMC, minimum is 200us but give it 300us for good measure */
552 usleep_range(300, 1000);
553 }
554
intel_select_drive_strength(struct mmc_card * card,unsigned int max_dtr,int host_drv,int card_drv,int * drv_type)555 static int intel_select_drive_strength(struct mmc_card *card,
556 unsigned int max_dtr, int host_drv,
557 int card_drv, int *drv_type)
558 {
559 struct sdhci_host *host = mmc_priv(card->host);
560 struct sdhci_pci_slot *slot = sdhci_priv(host);
561 struct intel_host *intel_host = sdhci_pci_priv(slot);
562
563 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
564 return 0;
565
566 return intel_host->drv_strength;
567 }
568
bxt_get_cd(struct mmc_host * mmc)569 static int bxt_get_cd(struct mmc_host *mmc)
570 {
571 int gpio_cd = mmc_gpio_get_cd(mmc);
572
573 if (!gpio_cd)
574 return 0;
575
576 return sdhci_get_cd_nogpio(mmc);
577 }
578
mrfld_get_cd(struct mmc_host * mmc)579 static int mrfld_get_cd(struct mmc_host *mmc)
580 {
581 return sdhci_get_cd_nogpio(mmc);
582 }
583
584 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
585 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
586
sdhci_intel_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)587 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
588 unsigned short vdd)
589 {
590 struct sdhci_pci_slot *slot = sdhci_priv(host);
591 struct intel_host *intel_host = sdhci_pci_priv(slot);
592 int cntr;
593 u8 reg;
594
595 /*
596 * Bus power may control card power, but a full reset still may not
597 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can.
598 * That might be needed to initialize correctly, if the card was left
599 * powered on previously.
600 */
601 if (intel_host->needs_pwr_off) {
602 intel_host->needs_pwr_off = false;
603 if (mode != MMC_POWER_OFF) {
604 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
605 usleep_range(10000, 12500);
606 }
607 }
608
609 sdhci_set_power(host, mode, vdd);
610
611 if (mode == MMC_POWER_OFF) {
612 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
613 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BYT_SD)
614 usleep_range(15000, 17500);
615 return;
616 }
617
618 /*
619 * Bus power might not enable after D3 -> D0 transition due to the
620 * present state not yet having propagated. Retry for up to 2ms.
621 */
622 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
623 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
624 if (reg & SDHCI_POWER_ON)
625 break;
626 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
627 reg |= SDHCI_POWER_ON;
628 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
629 }
630 }
631
sdhci_intel_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)632 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
633 unsigned int timing)
634 {
635 /* Set UHS timing to SDR25 for High Speed mode */
636 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
637 timing = MMC_TIMING_UHS_SDR25;
638 sdhci_set_uhs_signaling(host, timing);
639 }
640
641 #define INTEL_HS400_ES_REG 0x78
642 #define INTEL_HS400_ES_BIT BIT(0)
643
intel_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)644 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
645 struct mmc_ios *ios)
646 {
647 struct sdhci_host *host = mmc_priv(mmc);
648 u32 val;
649
650 val = sdhci_readl(host, INTEL_HS400_ES_REG);
651 if (ios->enhanced_strobe)
652 val |= INTEL_HS400_ES_BIT;
653 else
654 val &= ~INTEL_HS400_ES_BIT;
655 sdhci_writel(host, val, INTEL_HS400_ES_REG);
656 }
657
intel_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)658 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
659 struct mmc_ios *ios)
660 {
661 struct device *dev = mmc_dev(mmc);
662 struct sdhci_host *host = mmc_priv(mmc);
663 struct sdhci_pci_slot *slot = sdhci_priv(host);
664 struct intel_host *intel_host = sdhci_pci_priv(slot);
665 unsigned int fn;
666 u32 result = 0;
667 int err;
668
669 err = sdhci_start_signal_voltage_switch(mmc, ios);
670 if (err)
671 return err;
672
673 switch (ios->signal_voltage) {
674 case MMC_SIGNAL_VOLTAGE_330:
675 fn = INTEL_DSM_V33_SWITCH;
676 break;
677 case MMC_SIGNAL_VOLTAGE_180:
678 fn = INTEL_DSM_V18_SWITCH;
679 break;
680 default:
681 return 0;
682 }
683
684 err = intel_dsm(intel_host, dev, fn, &result);
685 pr_debug("%s: %s DSM fn %u error %d result %u\n",
686 mmc_hostname(mmc), __func__, fn, err, result);
687
688 return 0;
689 }
690
691 static const struct sdhci_ops sdhci_intel_byt_ops = {
692 .set_clock = sdhci_set_clock,
693 .set_power = sdhci_intel_set_power,
694 .enable_dma = sdhci_pci_enable_dma,
695 .set_bus_width = sdhci_set_bus_width,
696 .reset = sdhci_reset,
697 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
698 .hw_reset = sdhci_pci_hw_reset,
699 };
700
701 static const struct sdhci_ops sdhci_intel_glk_ops = {
702 .set_clock = sdhci_set_clock,
703 .set_power = sdhci_intel_set_power,
704 .enable_dma = sdhci_pci_enable_dma,
705 .set_bus_width = sdhci_set_bus_width,
706 .reset = sdhci_and_cqhci_reset,
707 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
708 .hw_reset = sdhci_pci_hw_reset,
709 .irq = sdhci_cqhci_irq,
710 };
711
byt_read_dsm(struct sdhci_pci_slot * slot)712 static void byt_read_dsm(struct sdhci_pci_slot *slot)
713 {
714 struct intel_host *intel_host = sdhci_pci_priv(slot);
715 struct device *dev = &slot->chip->pdev->dev;
716 struct mmc_host *mmc = slot->host->mmc;
717
718 intel_dsm_init(intel_host, dev, mmc);
719 slot->chip->rpm_retune = intel_host->d3_retune;
720 }
721
intel_execute_tuning(struct mmc_host * mmc,u32 opcode)722 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
723 {
724 int err = sdhci_execute_tuning(mmc, opcode);
725 struct sdhci_host *host = mmc_priv(mmc);
726
727 if (err)
728 return err;
729
730 /*
731 * Tuning can leave the IP in an active state (Buffer Read Enable bit
732 * set) which prevents the entry to low power states (i.e. S0i3). Data
733 * reset will clear it.
734 */
735 sdhci_reset(host, SDHCI_RESET_DATA);
736
737 return 0;
738 }
739
740 #define INTEL_ACTIVELTR 0x804
741 #define INTEL_IDLELTR 0x808
742
743 #define INTEL_LTR_REQ BIT(15)
744 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
745 #define INTEL_LTR_SCALE_1US (2 << 10)
746 #define INTEL_LTR_SCALE_32US (3 << 10)
747 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
748
intel_cache_ltr(struct sdhci_pci_slot * slot)749 static void intel_cache_ltr(struct sdhci_pci_slot *slot)
750 {
751 struct intel_host *intel_host = sdhci_pci_priv(slot);
752 struct sdhci_host *host = slot->host;
753
754 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
755 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR);
756 }
757
intel_ltr_set(struct device * dev,s32 val)758 static void intel_ltr_set(struct device *dev, s32 val)
759 {
760 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
761 struct sdhci_pci_slot *slot = chip->slots[0];
762 struct intel_host *intel_host = sdhci_pci_priv(slot);
763 struct sdhci_host *host = slot->host;
764 u32 ltr;
765
766 pm_runtime_get_sync(dev);
767
768 /*
769 * Program latency tolerance (LTR) accordingly what has been asked
770 * by the PM QoS layer or disable it in case we were passed
771 * negative value or PM_QOS_LATENCY_ANY.
772 */
773 ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
774
775 if (val == PM_QOS_LATENCY_ANY || val < 0) {
776 ltr &= ~INTEL_LTR_REQ;
777 } else {
778 ltr |= INTEL_LTR_REQ;
779 ltr &= ~INTEL_LTR_SCALE_MASK;
780 ltr &= ~INTEL_LTR_VALUE_MASK;
781
782 if (val > INTEL_LTR_VALUE_MASK) {
783 val >>= 5;
784 if (val > INTEL_LTR_VALUE_MASK)
785 val = INTEL_LTR_VALUE_MASK;
786 ltr |= INTEL_LTR_SCALE_32US | val;
787 } else {
788 ltr |= INTEL_LTR_SCALE_1US | val;
789 }
790 }
791
792 if (ltr == intel_host->active_ltr)
793 goto out;
794
795 writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
796 writel(ltr, host->ioaddr + INTEL_IDLELTR);
797
798 /* Cache the values into lpss structure */
799 intel_cache_ltr(slot);
800 out:
801 pm_runtime_put_autosuspend(dev);
802 }
803
intel_use_ltr(struct sdhci_pci_chip * chip)804 static bool intel_use_ltr(struct sdhci_pci_chip *chip)
805 {
806 switch (chip->pdev->device) {
807 case PCI_DEVICE_ID_INTEL_BYT_EMMC:
808 case PCI_DEVICE_ID_INTEL_BYT_EMMC2:
809 case PCI_DEVICE_ID_INTEL_BYT_SDIO:
810 case PCI_DEVICE_ID_INTEL_BYT_SD:
811 case PCI_DEVICE_ID_INTEL_BSW_EMMC:
812 case PCI_DEVICE_ID_INTEL_BSW_SDIO:
813 case PCI_DEVICE_ID_INTEL_BSW_SD:
814 return false;
815 default:
816 return true;
817 }
818 }
819
intel_ltr_expose(struct sdhci_pci_chip * chip)820 static void intel_ltr_expose(struct sdhci_pci_chip *chip)
821 {
822 struct device *dev = &chip->pdev->dev;
823
824 if (!intel_use_ltr(chip))
825 return;
826
827 dev->power.set_latency_tolerance = intel_ltr_set;
828 dev_pm_qos_expose_latency_tolerance(dev);
829 }
830
intel_ltr_hide(struct sdhci_pci_chip * chip)831 static void intel_ltr_hide(struct sdhci_pci_chip *chip)
832 {
833 struct device *dev = &chip->pdev->dev;
834
835 if (!intel_use_ltr(chip))
836 return;
837
838 dev_pm_qos_hide_latency_tolerance(dev);
839 dev->power.set_latency_tolerance = NULL;
840 }
841
byt_probe_slot(struct sdhci_pci_slot * slot)842 static void byt_probe_slot(struct sdhci_pci_slot *slot)
843 {
844 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
845 struct device *dev = &slot->chip->pdev->dev;
846 struct mmc_host *mmc = slot->host->mmc;
847
848 byt_read_dsm(slot);
849
850 byt_ocp_setting(slot->chip->pdev);
851
852 ops->execute_tuning = intel_execute_tuning;
853 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
854
855 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
856
857 if (!mmc->slotno) {
858 slot->chip->slots[mmc->slotno] = slot;
859 intel_ltr_expose(slot->chip);
860 }
861 }
862
byt_add_debugfs(struct sdhci_pci_slot * slot)863 static void byt_add_debugfs(struct sdhci_pci_slot *slot)
864 {
865 struct intel_host *intel_host = sdhci_pci_priv(slot);
866 struct mmc_host *mmc = slot->host->mmc;
867 struct dentry *dir = mmc->debugfs_root;
868
869 if (!intel_use_ltr(slot->chip))
870 return;
871
872 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr);
873 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr);
874
875 intel_cache_ltr(slot);
876 }
877
byt_add_host(struct sdhci_pci_slot * slot)878 static int byt_add_host(struct sdhci_pci_slot *slot)
879 {
880 int ret = sdhci_add_host(slot->host);
881
882 if (!ret)
883 byt_add_debugfs(slot);
884 return ret;
885 }
886
byt_remove_slot(struct sdhci_pci_slot * slot,int dead)887 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead)
888 {
889 struct mmc_host *mmc = slot->host->mmc;
890
891 if (!mmc->slotno)
892 intel_ltr_hide(slot->chip);
893 }
894
byt_emmc_probe_slot(struct sdhci_pci_slot * slot)895 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
896 {
897 byt_probe_slot(slot);
898 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
899 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
900 MMC_CAP_CMD_DURING_TFR |
901 MMC_CAP_WAIT_WHILE_BUSY;
902 slot->hw_reset = sdhci_pci_int_hw_reset;
903 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
904 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
905 slot->host->mmc_host_ops.select_drive_strength =
906 intel_select_drive_strength;
907 return 0;
908 }
909
glk_broken_cqhci(struct sdhci_pci_slot * slot)910 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
911 {
912 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
913 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
914 dmi_match(DMI_SYS_VENDOR, "IRBIS"));
915 }
916
jsl_broken_hs400es(struct sdhci_pci_slot * slot)917 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot)
918 {
919 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC &&
920 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC.");
921 }
922
glk_emmc_probe_slot(struct sdhci_pci_slot * slot)923 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
924 {
925 int ret = byt_emmc_probe_slot(slot);
926
927 if (!glk_broken_cqhci(slot))
928 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
929
930 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
931 if (!jsl_broken_hs400es(slot)) {
932 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
933 slot->host->mmc_host_ops.hs400_enhanced_strobe =
934 intel_hs400_enhanced_strobe;
935 }
936 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
937 }
938
939 return ret;
940 }
941
942 static const struct cqhci_host_ops glk_cqhci_ops = {
943 .enable = sdhci_cqe_enable,
944 .disable = sdhci_cqe_disable,
945 .dumpregs = sdhci_pci_dumpregs,
946 };
947
glk_emmc_add_host(struct sdhci_pci_slot * slot)948 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
949 {
950 struct device *dev = &slot->chip->pdev->dev;
951 struct sdhci_host *host = slot->host;
952 struct cqhci_host *cq_host;
953 bool dma64;
954 int ret;
955
956 ret = sdhci_setup_host(host);
957 if (ret)
958 return ret;
959
960 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
961 if (!cq_host) {
962 ret = -ENOMEM;
963 goto cleanup;
964 }
965
966 cq_host->mmio = host->ioaddr + 0x200;
967 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
968 cq_host->ops = &glk_cqhci_ops;
969
970 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
971 if (dma64)
972 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
973
974 ret = cqhci_init(cq_host, host->mmc, dma64);
975 if (ret)
976 goto cleanup;
977
978 ret = __sdhci_add_host(host);
979 if (ret)
980 goto cleanup;
981
982 byt_add_debugfs(slot);
983
984 return 0;
985
986 cleanup:
987 sdhci_cleanup_host(host);
988 return ret;
989 }
990
991 #ifdef CONFIG_PM
992 #define GLK_RX_CTRL1 0x834
993 #define GLK_TUN_VAL 0x840
994 #define GLK_PATH_PLL GENMASK(13, 8)
995 #define GLK_DLY GENMASK(6, 0)
996 /* Workaround firmware failing to restore the tuning value */
glk_rpm_retune_wa(struct sdhci_pci_chip * chip,bool susp)997 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
998 {
999 struct sdhci_pci_slot *slot = chip->slots[0];
1000 struct intel_host *intel_host = sdhci_pci_priv(slot);
1001 struct sdhci_host *host = slot->host;
1002 u32 glk_rx_ctrl1;
1003 u32 glk_tun_val;
1004 u32 dly;
1005
1006 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
1007 return;
1008
1009 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
1010 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
1011
1012 if (susp) {
1013 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
1014 intel_host->glk_tun_val = glk_tun_val;
1015 return;
1016 }
1017
1018 if (!intel_host->glk_tun_val)
1019 return;
1020
1021 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
1022 intel_host->rpm_retune_ok = true;
1023 return;
1024 }
1025
1026 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
1027 (intel_host->glk_tun_val << 1));
1028 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
1029 return;
1030
1031 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
1032 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
1033
1034 intel_host->rpm_retune_ok = true;
1035 chip->rpm_retune = true;
1036 mmc_retune_needed(host->mmc);
1037 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
1038 }
1039
glk_rpm_retune_chk(struct sdhci_pci_chip * chip,bool susp)1040 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
1041 {
1042 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
1043 !chip->rpm_retune)
1044 glk_rpm_retune_wa(chip, susp);
1045 }
1046
glk_runtime_suspend(struct sdhci_pci_chip * chip)1047 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
1048 {
1049 glk_rpm_retune_chk(chip, true);
1050
1051 return sdhci_cqhci_runtime_suspend(chip);
1052 }
1053
glk_runtime_resume(struct sdhci_pci_chip * chip)1054 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
1055 {
1056 glk_rpm_retune_chk(chip, false);
1057
1058 return sdhci_cqhci_runtime_resume(chip);
1059 }
1060 #endif
1061
1062 #ifdef CONFIG_ACPI
ni_set_max_freq(struct sdhci_pci_slot * slot)1063 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
1064 {
1065 acpi_status status;
1066 unsigned long long max_freq;
1067
1068 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
1069 "MXFQ", NULL, &max_freq);
1070 if (ACPI_FAILURE(status)) {
1071 dev_err(&slot->chip->pdev->dev,
1072 "MXFQ not found in acpi table\n");
1073 return -EINVAL;
1074 }
1075
1076 slot->host->mmc->f_max = max_freq * 1000000;
1077
1078 return 0;
1079 }
1080 #else
ni_set_max_freq(struct sdhci_pci_slot * slot)1081 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
1082 {
1083 return 0;
1084 }
1085 #endif
1086
ni_byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1087 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1088 {
1089 int err;
1090
1091 byt_probe_slot(slot);
1092
1093 err = ni_set_max_freq(slot);
1094 if (err)
1095 return err;
1096
1097 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1098 MMC_CAP_WAIT_WHILE_BUSY;
1099 return 0;
1100 }
1101
byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1102 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1103 {
1104 byt_probe_slot(slot);
1105 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1106 MMC_CAP_WAIT_WHILE_BUSY;
1107 return 0;
1108 }
1109
byt_needs_pwr_off(struct sdhci_pci_slot * slot)1110 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot)
1111 {
1112 struct intel_host *intel_host = sdhci_pci_priv(slot);
1113 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL);
1114
1115 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON;
1116 }
1117
byt_sd_probe_slot(struct sdhci_pci_slot * slot)1118 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
1119 {
1120 byt_probe_slot(slot);
1121 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
1122 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
1123 slot->cd_idx = 0;
1124 slot->cd_override_level = true;
1125 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
1126 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
1127 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
1128 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
1129 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
1130
1131 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
1132 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
1133 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
1134
1135 byt_needs_pwr_off(slot);
1136
1137 return 0;
1138 }
1139
1140 #ifdef CONFIG_PM_SLEEP
1141
byt_resume(struct sdhci_pci_chip * chip)1142 static int byt_resume(struct sdhci_pci_chip *chip)
1143 {
1144 byt_ocp_setting(chip->pdev);
1145
1146 return sdhci_pci_resume_host(chip);
1147 }
1148
1149 #endif
1150
1151 #ifdef CONFIG_PM
1152
byt_runtime_resume(struct sdhci_pci_chip * chip)1153 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1154 {
1155 byt_ocp_setting(chip->pdev);
1156
1157 return sdhci_pci_runtime_resume_host(chip);
1158 }
1159
1160 #endif
1161
1162 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1163 #ifdef CONFIG_PM_SLEEP
1164 .resume = byt_resume,
1165 #endif
1166 #ifdef CONFIG_PM
1167 .runtime_resume = byt_runtime_resume,
1168 #endif
1169 .allow_runtime_pm = true,
1170 .probe_slot = byt_emmc_probe_slot,
1171 .add_host = byt_add_host,
1172 .remove_slot = byt_remove_slot,
1173 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1174 SDHCI_QUIRK_NO_LED,
1175 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1176 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1177 SDHCI_QUIRK2_STOP_WITH_TC,
1178 .ops = &sdhci_intel_byt_ops,
1179 .priv_size = sizeof(struct intel_host),
1180 };
1181
1182 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1183 .allow_runtime_pm = true,
1184 .probe_slot = glk_emmc_probe_slot,
1185 .add_host = glk_emmc_add_host,
1186 .remove_slot = byt_remove_slot,
1187 #ifdef CONFIG_PM_SLEEP
1188 .suspend = sdhci_cqhci_suspend,
1189 .resume = sdhci_cqhci_resume,
1190 #endif
1191 #ifdef CONFIG_PM
1192 .runtime_suspend = glk_runtime_suspend,
1193 .runtime_resume = glk_runtime_resume,
1194 #endif
1195 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1196 SDHCI_QUIRK_NO_LED,
1197 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1198 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1199 SDHCI_QUIRK2_STOP_WITH_TC,
1200 .ops = &sdhci_intel_glk_ops,
1201 .priv_size = sizeof(struct intel_host),
1202 };
1203
1204 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1205 #ifdef CONFIG_PM_SLEEP
1206 .resume = byt_resume,
1207 #endif
1208 #ifdef CONFIG_PM
1209 .runtime_resume = byt_runtime_resume,
1210 #endif
1211 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1212 SDHCI_QUIRK_NO_LED,
1213 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1214 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1215 .allow_runtime_pm = true,
1216 .probe_slot = ni_byt_sdio_probe_slot,
1217 .add_host = byt_add_host,
1218 .remove_slot = byt_remove_slot,
1219 .ops = &sdhci_intel_byt_ops,
1220 .priv_size = sizeof(struct intel_host),
1221 };
1222
1223 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1224 #ifdef CONFIG_PM_SLEEP
1225 .resume = byt_resume,
1226 #endif
1227 #ifdef CONFIG_PM
1228 .runtime_resume = byt_runtime_resume,
1229 #endif
1230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1231 SDHCI_QUIRK_NO_LED,
1232 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1233 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1234 .allow_runtime_pm = true,
1235 .probe_slot = byt_sdio_probe_slot,
1236 .add_host = byt_add_host,
1237 .remove_slot = byt_remove_slot,
1238 .ops = &sdhci_intel_byt_ops,
1239 .priv_size = sizeof(struct intel_host),
1240 };
1241
1242 /* DMI quirks for devices with missing or broken CD GPIO info */
1243 static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = {
1244 .dev_id = "0000:00:12.0",
1245 .table = {
1246 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH),
1247 { }
1248 },
1249 };
1250
1251 static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = {
1252 {
1253 /* Vexia Edu Atla 10 tablet 9V version */
1254 .matches = {
1255 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
1256 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
1257 /* Above strings are too generic, also match on BIOS date */
1258 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"),
1259 },
1260 .driver_data = (void *)&vexia_edu_atla10_cd_gpios,
1261 },
1262 { }
1263 };
1264
1265 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1266 #ifdef CONFIG_PM_SLEEP
1267 .resume = byt_resume,
1268 #endif
1269 #ifdef CONFIG_PM
1270 .runtime_resume = byt_runtime_resume,
1271 #endif
1272 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1273 SDHCI_QUIRK_NO_LED,
1274 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1275 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1276 SDHCI_QUIRK2_STOP_WITH_TC,
1277 .allow_runtime_pm = true,
1278 .own_cd_for_runtime_pm = true,
1279 .probe_slot = byt_sd_probe_slot,
1280 .add_host = byt_add_host,
1281 .remove_slot = byt_remove_slot,
1282 .ops = &sdhci_intel_byt_ops,
1283 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override,
1284 .priv_size = sizeof(struct intel_host),
1285 };
1286
1287 /* Define Host controllers for Intel Merrifield platform */
1288 #define INTEL_MRFLD_EMMC_0 0
1289 #define INTEL_MRFLD_EMMC_1 1
1290 #define INTEL_MRFLD_SD 2
1291 #define INTEL_MRFLD_SDIO 3
1292
1293 #ifdef CONFIG_ACPI
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1294 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1295 {
1296 struct acpi_device *device;
1297
1298 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1299 if (device)
1300 acpi_device_fix_up_power_extended(device);
1301 }
1302 #else
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1303 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1304 #endif
1305
intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot * slot)1306 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1307 {
1308 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1309
1310 switch (func) {
1311 case INTEL_MRFLD_EMMC_0:
1312 case INTEL_MRFLD_EMMC_1:
1313 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1314 MMC_CAP_8_BIT_DATA |
1315 MMC_CAP_1_8V_DDR;
1316 break;
1317 case INTEL_MRFLD_SD:
1318 slot->cd_idx = 0;
1319 slot->cd_override_level = true;
1320 /*
1321 * There are two PCB designs of SD card slot with the opposite
1322 * card detection sense. Quirk this out by ignoring GPIO state
1323 * completely in the custom ->get_cd() callback.
1324 */
1325 slot->host->mmc_host_ops.get_cd = mrfld_get_cd;
1326 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1327 break;
1328 case INTEL_MRFLD_SDIO:
1329 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1330 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1331 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1332 MMC_CAP_POWER_OFF_CARD;
1333 break;
1334 default:
1335 return -ENODEV;
1336 }
1337
1338 intel_mrfld_mmc_fix_up_power_slot(slot);
1339 return 0;
1340 }
1341
1342 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1343 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1344 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1345 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1346 .allow_runtime_pm = true,
1347 .probe_slot = intel_mrfld_mmc_probe_slot,
1348 };
1349
jmicron_pmos(struct sdhci_pci_chip * chip,int on)1350 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1351 {
1352 u8 scratch;
1353 int ret;
1354
1355 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1356 if (ret)
1357 goto fail;
1358
1359 /*
1360 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1361 * [bit 1:2] and enable over current debouncing [bit 6].
1362 */
1363 if (on)
1364 scratch |= 0x47;
1365 else
1366 scratch &= ~0x47;
1367
1368 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
1369
1370 fail:
1371 return pcibios_err_to_errno(ret);
1372 }
1373
jmicron_probe(struct sdhci_pci_chip * chip)1374 static int jmicron_probe(struct sdhci_pci_chip *chip)
1375 {
1376 int ret;
1377 u16 mmcdev = 0;
1378
1379 if (chip->pdev->revision == 0) {
1380 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1381 SDHCI_QUIRK_32BIT_DMA_SIZE |
1382 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1383 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1384 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1385 }
1386
1387 /*
1388 * JMicron chips can have two interfaces to the same hardware
1389 * in order to work around limitations in Microsoft's driver.
1390 * We need to make sure we only bind to one of them.
1391 *
1392 * This code assumes two things:
1393 *
1394 * 1. The PCI code adds subfunctions in order.
1395 *
1396 * 2. The MMC interface has a lower subfunction number
1397 * than the SD interface.
1398 */
1399 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1400 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1401 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1402 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1403
1404 if (mmcdev) {
1405 struct pci_dev *sd_dev;
1406
1407 sd_dev = NULL;
1408 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1409 mmcdev, sd_dev)) != NULL) {
1410 if ((PCI_SLOT(chip->pdev->devfn) ==
1411 PCI_SLOT(sd_dev->devfn)) &&
1412 (chip->pdev->bus == sd_dev->bus))
1413 break;
1414 }
1415
1416 if (sd_dev) {
1417 pci_dev_put(sd_dev);
1418 dev_info(&chip->pdev->dev, "Refusing to bind to "
1419 "secondary interface.\n");
1420 return -ENODEV;
1421 }
1422 }
1423
1424 /*
1425 * JMicron chips need a bit of a nudge to enable the power
1426 * output pins.
1427 */
1428 ret = jmicron_pmos(chip, 1);
1429 if (ret) {
1430 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1431 return ret;
1432 }
1433
1434 /* quirk for unsable RO-detection on JM388 chips */
1435 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1436 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1437 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1438
1439 return 0;
1440 }
1441
jmicron_enable_mmc(struct sdhci_host * host,int on)1442 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1443 {
1444 u8 scratch;
1445
1446 scratch = readb(host->ioaddr + 0xC0);
1447
1448 if (on)
1449 scratch |= 0x01;
1450 else
1451 scratch &= ~0x01;
1452
1453 writeb(scratch, host->ioaddr + 0xC0);
1454 }
1455
jmicron_probe_slot(struct sdhci_pci_slot * slot)1456 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1457 {
1458 if (slot->chip->pdev->revision == 0) {
1459 u16 version;
1460
1461 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1462 version = (version & SDHCI_VENDOR_VER_MASK) >>
1463 SDHCI_VENDOR_VER_SHIFT;
1464
1465 /*
1466 * Older versions of the chip have lots of nasty glitches
1467 * in the ADMA engine. It's best just to avoid it
1468 * completely.
1469 */
1470 if (version < 0xAC)
1471 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1472 }
1473
1474 /* JM388 MMC doesn't support 1.8V while SD supports it */
1475 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1476 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1477 MMC_VDD_29_30 | MMC_VDD_30_31 |
1478 MMC_VDD_165_195; /* allow 1.8V */
1479 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1480 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1481 }
1482
1483 /*
1484 * The secondary interface requires a bit set to get the
1485 * interrupts.
1486 */
1487 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1488 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1489 jmicron_enable_mmc(slot->host, 1);
1490
1491 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1492
1493 return 0;
1494 }
1495
jmicron_remove_slot(struct sdhci_pci_slot * slot,int dead)1496 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1497 {
1498 if (dead)
1499 return;
1500
1501 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1502 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1503 jmicron_enable_mmc(slot->host, 0);
1504 }
1505
1506 #ifdef CONFIG_PM_SLEEP
jmicron_suspend(struct sdhci_pci_chip * chip)1507 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1508 {
1509 int i, ret;
1510
1511 ret = sdhci_pci_suspend_host(chip);
1512 if (ret)
1513 return ret;
1514
1515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1517 for (i = 0; i < chip->num_slots; i++)
1518 jmicron_enable_mmc(chip->slots[i]->host, 0);
1519 }
1520
1521 return 0;
1522 }
1523
jmicron_resume(struct sdhci_pci_chip * chip)1524 static int jmicron_resume(struct sdhci_pci_chip *chip)
1525 {
1526 int ret, i;
1527
1528 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1529 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1530 for (i = 0; i < chip->num_slots; i++)
1531 jmicron_enable_mmc(chip->slots[i]->host, 1);
1532 }
1533
1534 ret = jmicron_pmos(chip, 1);
1535 if (ret) {
1536 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1537 return ret;
1538 }
1539
1540 return sdhci_pci_resume_host(chip);
1541 }
1542 #endif
1543
1544 static const struct sdhci_pci_fixes sdhci_jmicron = {
1545 .probe = jmicron_probe,
1546
1547 .probe_slot = jmicron_probe_slot,
1548 .remove_slot = jmicron_remove_slot,
1549
1550 #ifdef CONFIG_PM_SLEEP
1551 .suspend = jmicron_suspend,
1552 .resume = jmicron_resume,
1553 #endif
1554 };
1555
1556 /* SysKonnect CardBus2SDIO extra registers */
1557 #define SYSKT_CTRL 0x200
1558 #define SYSKT_RDFIFO_STAT 0x204
1559 #define SYSKT_WRFIFO_STAT 0x208
1560 #define SYSKT_POWER_DATA 0x20c
1561 #define SYSKT_POWER_330 0xef
1562 #define SYSKT_POWER_300 0xf8
1563 #define SYSKT_POWER_184 0xcc
1564 #define SYSKT_POWER_CMD 0x20d
1565 #define SYSKT_POWER_START (1 << 7)
1566 #define SYSKT_POWER_STATUS 0x20e
1567 #define SYSKT_POWER_STATUS_OK (1 << 0)
1568 #define SYSKT_BOARD_REV 0x210
1569 #define SYSKT_CHIP_REV 0x211
1570 #define SYSKT_CONF_DATA 0x212
1571 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1572 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1573 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1574
syskt_probe(struct sdhci_pci_chip * chip)1575 static int syskt_probe(struct sdhci_pci_chip *chip)
1576 {
1577 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1578 chip->pdev->class &= ~0x0000FF;
1579 chip->pdev->class |= PCI_SDHCI_IFDMA;
1580 }
1581 return 0;
1582 }
1583
syskt_probe_slot(struct sdhci_pci_slot * slot)1584 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1585 {
1586 int tm, ps;
1587
1588 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1589 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1590 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1591 "board rev %d.%d, chip rev %d.%d\n",
1592 board_rev >> 4, board_rev & 0xf,
1593 chip_rev >> 4, chip_rev & 0xf);
1594 if (chip_rev >= 0x20)
1595 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1596
1597 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1598 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1599 udelay(50);
1600 tm = 10; /* Wait max 1 ms */
1601 do {
1602 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1603 if (ps & SYSKT_POWER_STATUS_OK)
1604 break;
1605 udelay(100);
1606 } while (--tm);
1607 if (!tm) {
1608 dev_err(&slot->chip->pdev->dev,
1609 "power regulator never stabilized");
1610 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1611 return -ENODEV;
1612 }
1613
1614 return 0;
1615 }
1616
1617 static const struct sdhci_pci_fixes sdhci_syskt = {
1618 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1619 .probe = syskt_probe,
1620 .probe_slot = syskt_probe_slot,
1621 };
1622
via_probe(struct sdhci_pci_chip * chip)1623 static int via_probe(struct sdhci_pci_chip *chip)
1624 {
1625 if (chip->pdev->revision == 0x10)
1626 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1627
1628 return 0;
1629 }
1630
1631 static const struct sdhci_pci_fixes sdhci_via = {
1632 .probe = via_probe,
1633 };
1634
rtsx_probe_slot(struct sdhci_pci_slot * slot)1635 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1636 {
1637 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1638 return 0;
1639 }
1640
1641 static const struct sdhci_pci_fixes sdhci_rtsx = {
1642 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1643 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1644 SDHCI_QUIRK2_BROKEN_DDR50,
1645 .probe_slot = rtsx_probe_slot,
1646 };
1647
1648 /*AMD chipset generation*/
1649 enum amd_chipset_gen {
1650 AMD_CHIPSET_BEFORE_ML,
1651 AMD_CHIPSET_CZ,
1652 AMD_CHIPSET_NL,
1653 AMD_CHIPSET_UNKNOWN,
1654 };
1655
1656 /* AMD registers */
1657 #define AMD_SD_AUTO_PATTERN 0xB8
1658 #define AMD_MSLEEP_DURATION 4
1659 #define AMD_SD_MISC_CONTROL 0xD0
1660 #define AMD_MAX_TUNE_VALUE 0x0B
1661 #define AMD_AUTO_TUNE_SEL 0x10800
1662 #define AMD_FIFO_PTR 0x30
1663 #define AMD_BIT_MASK 0x1F
1664
amd_tuning_reset(struct sdhci_host * host)1665 static void amd_tuning_reset(struct sdhci_host *host)
1666 {
1667 unsigned int val;
1668
1669 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1670 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1671 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1672
1673 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1674 val &= ~SDHCI_CTRL_EXEC_TUNING;
1675 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1676 }
1677
amd_config_tuning_phase(struct pci_dev * pdev,u8 phase)1678 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1679 {
1680 unsigned int val;
1681
1682 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1683 val &= ~AMD_BIT_MASK;
1684 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1685 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1686 }
1687
amd_enable_manual_tuning(struct pci_dev * pdev)1688 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1689 {
1690 unsigned int val;
1691
1692 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1693 val |= AMD_FIFO_PTR;
1694 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1695 }
1696
amd_execute_tuning_hs200(struct sdhci_host * host,u32 opcode)1697 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1698 {
1699 struct sdhci_pci_slot *slot = sdhci_priv(host);
1700 struct pci_dev *pdev = slot->chip->pdev;
1701 u8 valid_win = 0;
1702 u8 valid_win_max = 0;
1703 u8 valid_win_end = 0;
1704 u8 ctrl, tune_around;
1705
1706 amd_tuning_reset(host);
1707
1708 for (tune_around = 0; tune_around < 12; tune_around++) {
1709 amd_config_tuning_phase(pdev, tune_around);
1710
1711 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1712 valid_win = 0;
1713 msleep(AMD_MSLEEP_DURATION);
1714 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1715 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1716 } else if (++valid_win > valid_win_max) {
1717 valid_win_max = valid_win;
1718 valid_win_end = tune_around;
1719 }
1720 }
1721
1722 if (!valid_win_max) {
1723 dev_err(&pdev->dev, "no tuning point found\n");
1724 return -EIO;
1725 }
1726
1727 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1728
1729 amd_enable_manual_tuning(pdev);
1730
1731 host->mmc->retune_period = 0;
1732
1733 return 0;
1734 }
1735
amd_execute_tuning(struct mmc_host * mmc,u32 opcode)1736 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1737 {
1738 struct sdhci_host *host = mmc_priv(mmc);
1739
1740 /* AMD requires custom HS200 tuning */
1741 if (host->timing == MMC_TIMING_MMC_HS200)
1742 return amd_execute_tuning_hs200(host, opcode);
1743
1744 /* Otherwise perform standard SDHCI tuning */
1745 return sdhci_execute_tuning(mmc, opcode);
1746 }
1747
amd_probe_slot(struct sdhci_pci_slot * slot)1748 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1749 {
1750 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1751
1752 ops->execute_tuning = amd_execute_tuning;
1753
1754 return 0;
1755 }
1756
amd_probe(struct sdhci_pci_chip * chip)1757 static int amd_probe(struct sdhci_pci_chip *chip)
1758 {
1759 struct pci_dev *smbus_dev;
1760 enum amd_chipset_gen gen;
1761
1762 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1763 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1764 if (smbus_dev) {
1765 gen = AMD_CHIPSET_BEFORE_ML;
1766 } else {
1767 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1768 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1769 if (smbus_dev) {
1770 if (smbus_dev->revision < 0x51)
1771 gen = AMD_CHIPSET_CZ;
1772 else
1773 gen = AMD_CHIPSET_NL;
1774 } else {
1775 gen = AMD_CHIPSET_UNKNOWN;
1776 }
1777 }
1778
1779 pci_dev_put(smbus_dev);
1780
1781 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1782 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1783
1784 return 0;
1785 }
1786
sdhci_read_present_state(struct sdhci_host * host)1787 static u32 sdhci_read_present_state(struct sdhci_host *host)
1788 {
1789 return sdhci_readl(host, SDHCI_PRESENT_STATE);
1790 }
1791
amd_sdhci_reset(struct sdhci_host * host,u8 mask)1792 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1793 {
1794 struct sdhci_pci_slot *slot = sdhci_priv(host);
1795 struct pci_dev *pdev = slot->chip->pdev;
1796 u32 present_state;
1797
1798 /*
1799 * SDHC 0x7906 requires a hard reset to clear all internal state.
1800 * Otherwise it can get into a bad state where the DATA lines are always
1801 * read as zeros.
1802 */
1803 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1804 pci_clear_master(pdev);
1805
1806 pci_save_state(pdev);
1807
1808 pci_set_power_state(pdev, PCI_D3cold);
1809 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1810 pdev->current_state);
1811 pci_set_power_state(pdev, PCI_D0);
1812
1813 pci_restore_state(pdev);
1814
1815 /*
1816 * SDHCI_RESET_ALL says the card detect logic should not be
1817 * reset, but since we need to reset the entire controller
1818 * we should wait until the card detect logic has stabilized.
1819 *
1820 * This normally takes about 40ms.
1821 */
1822 readx_poll_timeout(
1823 sdhci_read_present_state,
1824 host,
1825 present_state,
1826 present_state & SDHCI_CD_STABLE,
1827 10000,
1828 100000
1829 );
1830 }
1831
1832 return sdhci_reset(host, mask);
1833 }
1834
1835 static const struct sdhci_ops amd_sdhci_pci_ops = {
1836 .set_clock = sdhci_set_clock,
1837 .enable_dma = sdhci_pci_enable_dma,
1838 .set_bus_width = sdhci_set_bus_width,
1839 .reset = amd_sdhci_reset,
1840 .set_uhs_signaling = sdhci_set_uhs_signaling,
1841 };
1842
1843 static const struct sdhci_pci_fixes sdhci_amd = {
1844 .probe = amd_probe,
1845 .ops = &amd_sdhci_pci_ops,
1846 .probe_slot = amd_probe_slot,
1847 };
1848
1849 static const struct pci_device_id pci_ids[] = {
1850 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1851 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1852 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1853 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1854 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1855 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1856 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1857 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1858 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1859 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1860 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1861 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1862 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1863 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1864 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1865 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1866 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1867 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1868 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1869 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1870 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1871 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1872 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1873 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1874 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1875 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1876 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1877 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1878 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1879 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1880 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1881 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1882 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1883 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1884 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1885 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1886 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1887 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1888 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1889 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1890 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1891 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1892 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1893 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1894 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1895 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1896 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1897 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1898 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1899 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1900 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1901 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1902 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1903 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1904 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1905 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1906 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1907 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1908 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1909 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1910 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1911 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1912 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1913 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc),
1914 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd),
1915 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1916 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1917 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
1918 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
1919 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1920 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc),
1921 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd),
1922 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc),
1923 SDHCI_PCI_DEVICE(O2, 8120, o2),
1924 SDHCI_PCI_DEVICE(O2, 8220, o2),
1925 SDHCI_PCI_DEVICE(O2, 8221, o2),
1926 SDHCI_PCI_DEVICE(O2, 8320, o2),
1927 SDHCI_PCI_DEVICE(O2, 8321, o2),
1928 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1929 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1930 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1931 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1932 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1933 SDHCI_PCI_DEVICE(O2, GG8_9860, o2),
1934 SDHCI_PCI_DEVICE(O2, GG8_9861, o2),
1935 SDHCI_PCI_DEVICE(O2, GG8_9862, o2),
1936 SDHCI_PCI_DEVICE(O2, GG8_9863, o2),
1937 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1938 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1939 SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1940 SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1941 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
1942 SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
1943 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1944 /* Generic SD host controller */
1945 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1946 { /* end: all zeroes */ },
1947 };
1948
1949 MODULE_DEVICE_TABLE(pci, pci_ids);
1950
1951 /*****************************************************************************\
1952 * *
1953 * SDHCI core callbacks *
1954 * *
1955 \*****************************************************************************/
1956
sdhci_pci_enable_dma(struct sdhci_host * host)1957 int sdhci_pci_enable_dma(struct sdhci_host *host)
1958 {
1959 struct sdhci_pci_slot *slot;
1960 struct pci_dev *pdev;
1961
1962 slot = sdhci_priv(host);
1963 pdev = slot->chip->pdev;
1964
1965 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1966 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1967 (host->flags & SDHCI_USE_SDMA)) {
1968 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1969 "doesn't fully claim to support it.\n");
1970 }
1971
1972 pci_set_master(pdev);
1973
1974 return 0;
1975 }
1976
sdhci_pci_hw_reset(struct sdhci_host * host)1977 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1978 {
1979 struct sdhci_pci_slot *slot = sdhci_priv(host);
1980
1981 if (slot->hw_reset)
1982 slot->hw_reset(host);
1983 }
1984
1985 static const struct sdhci_ops sdhci_pci_ops = {
1986 .set_clock = sdhci_set_clock,
1987 .enable_dma = sdhci_pci_enable_dma,
1988 .set_bus_width = sdhci_set_bus_width,
1989 .reset = sdhci_reset,
1990 .set_uhs_signaling = sdhci_set_uhs_signaling,
1991 .hw_reset = sdhci_pci_hw_reset,
1992 };
1993
1994 /*****************************************************************************\
1995 * *
1996 * Suspend/resume *
1997 * *
1998 \*****************************************************************************/
1999
2000 #ifdef CONFIG_PM_SLEEP
sdhci_pci_suspend(struct device * dev)2001 static int sdhci_pci_suspend(struct device *dev)
2002 {
2003 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2004
2005 if (!chip)
2006 return 0;
2007
2008 if (chip->fixes && chip->fixes->suspend)
2009 return chip->fixes->suspend(chip);
2010
2011 return sdhci_pci_suspend_host(chip);
2012 }
2013
sdhci_pci_resume(struct device * dev)2014 static int sdhci_pci_resume(struct device *dev)
2015 {
2016 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2017
2018 if (!chip)
2019 return 0;
2020
2021 if (chip->fixes && chip->fixes->resume)
2022 return chip->fixes->resume(chip);
2023
2024 return sdhci_pci_resume_host(chip);
2025 }
2026 #endif
2027
2028 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend(struct device * dev)2029 static int sdhci_pci_runtime_suspend(struct device *dev)
2030 {
2031 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2032
2033 if (!chip)
2034 return 0;
2035
2036 if (chip->fixes && chip->fixes->runtime_suspend)
2037 return chip->fixes->runtime_suspend(chip);
2038
2039 return sdhci_pci_runtime_suspend_host(chip);
2040 }
2041
sdhci_pci_runtime_resume(struct device * dev)2042 static int sdhci_pci_runtime_resume(struct device *dev)
2043 {
2044 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2045
2046 if (!chip)
2047 return 0;
2048
2049 if (chip->fixes && chip->fixes->runtime_resume)
2050 return chip->fixes->runtime_resume(chip);
2051
2052 return sdhci_pci_runtime_resume_host(chip);
2053 }
2054 #endif
2055
2056 static const struct dev_pm_ops sdhci_pci_pm_ops = {
2057 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
2058 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
2059 sdhci_pci_runtime_resume, NULL)
2060 };
2061
2062 /*****************************************************************************\
2063 * *
2064 * Device probing/removal *
2065 * *
2066 \*****************************************************************************/
2067
sdhci_pci_add_gpio_lookup_table(struct sdhci_pci_chip * chip)2068 static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table(
2069 struct sdhci_pci_chip *chip)
2070 {
2071 struct gpiod_lookup_table *cd_gpio_lookup_table;
2072 const struct dmi_system_id *dmi_id = NULL;
2073 size_t count;
2074
2075 if (chip->fixes && chip->fixes->cd_gpio_override)
2076 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override);
2077
2078 if (!dmi_id)
2079 return NULL;
2080
2081 cd_gpio_lookup_table = dmi_id->driver_data;
2082 for (count = 0; cd_gpio_lookup_table->table[count].key; count++)
2083 ;
2084
2085 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data,
2086 /* count + 1 terminating entry */
2087 struct_size(cd_gpio_lookup_table, table, count + 1),
2088 GFP_KERNEL);
2089 if (!cd_gpio_lookup_table)
2090 return ERR_PTR(-ENOMEM);
2091
2092 gpiod_add_lookup_table(cd_gpio_lookup_table);
2093 return cd_gpio_lookup_table;
2094 }
2095
sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table * lookup_table)2096 static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table)
2097 {
2098 if (lookup_table) {
2099 gpiod_remove_lookup_table(lookup_table);
2100 kfree(lookup_table);
2101 }
2102 }
2103
sdhci_pci_probe_slot(struct pci_dev * pdev,struct sdhci_pci_chip * chip,int first_bar,int slotno)2104 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
2105 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
2106 int slotno)
2107 {
2108 struct sdhci_pci_slot *slot;
2109 struct sdhci_host *host;
2110 int ret, bar = first_bar + slotno;
2111 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
2112
2113 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
2114 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
2115 return ERR_PTR(-ENODEV);
2116 }
2117
2118 if (pci_resource_len(pdev, bar) < 0x100) {
2119 dev_err(&pdev->dev, "Invalid iomem size. You may "
2120 "experience problems.\n");
2121 }
2122
2123 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
2124 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
2125 return ERR_PTR(-ENODEV);
2126 }
2127
2128 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
2129 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
2130 return ERR_PTR(-ENODEV);
2131 }
2132
2133 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
2134 if (IS_ERR(host)) {
2135 dev_err(&pdev->dev, "cannot allocate host\n");
2136 return ERR_CAST(host);
2137 }
2138
2139 slot = sdhci_priv(host);
2140
2141 slot->chip = chip;
2142 slot->host = host;
2143 slot->cd_idx = -1;
2144
2145 host->hw_name = "PCI";
2146 host->ops = chip->fixes && chip->fixes->ops ?
2147 chip->fixes->ops :
2148 &sdhci_pci_ops;
2149 host->quirks = chip->quirks;
2150 host->quirks2 = chip->quirks2;
2151
2152 host->irq = pdev->irq;
2153
2154 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
2155 if (ret) {
2156 dev_err(&pdev->dev, "cannot request region\n");
2157 goto cleanup;
2158 }
2159
2160 host->ioaddr = pcim_iomap_table(pdev)[bar];
2161
2162 if (chip->fixes && chip->fixes->probe_slot) {
2163 ret = chip->fixes->probe_slot(slot);
2164 if (ret)
2165 goto cleanup;
2166 }
2167
2168 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
2169 host->mmc->slotno = slotno;
2170 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2171
2172 if (device_can_wakeup(&pdev->dev))
2173 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2174
2175 if (host->mmc->caps & MMC_CAP_CD_WAKE)
2176 device_init_wakeup(&pdev->dev, true);
2177
2178 if (slot->cd_idx >= 0) {
2179 struct gpiod_lookup_table *cd_gpio_lookup_table;
2180
2181 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip);
2182 if (IS_ERR(cd_gpio_lookup_table)) {
2183 ret = PTR_ERR(cd_gpio_lookup_table);
2184 goto remove;
2185 }
2186
2187 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
2188 slot->cd_override_level, 0);
2189
2190 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table);
2191
2192 if (ret && ret != -EPROBE_DEFER)
2193 ret = mmc_gpiod_request_cd(host->mmc, NULL,
2194 slot->cd_idx,
2195 slot->cd_override_level,
2196 0);
2197 if (ret == -EPROBE_DEFER)
2198 goto remove;
2199
2200 if (ret) {
2201 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2202 slot->cd_idx = -1;
2203 }
2204 }
2205
2206 if (chip->fixes && chip->fixes->add_host)
2207 ret = chip->fixes->add_host(slot);
2208 else
2209 ret = sdhci_add_host(host);
2210 if (ret)
2211 goto remove;
2212
2213 /*
2214 * Check if the chip needs a separate GPIO for card detect to wake up
2215 * from runtime suspend. If it is not there, don't allow runtime PM.
2216 */
2217 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0)
2218 chip->allow_runtime_pm = false;
2219
2220 return slot;
2221
2222 remove:
2223 if (chip->fixes && chip->fixes->remove_slot)
2224 chip->fixes->remove_slot(slot, 0);
2225
2226 cleanup:
2227 sdhci_free_host(host);
2228
2229 return ERR_PTR(ret);
2230 }
2231
sdhci_pci_remove_slot(struct sdhci_pci_slot * slot)2232 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2233 {
2234 int dead;
2235 u32 scratch;
2236
2237 dead = 0;
2238 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2239 if (scratch == (u32)-1)
2240 dead = 1;
2241
2242 sdhci_remove_host(slot->host, dead);
2243
2244 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2245 slot->chip->fixes->remove_slot(slot, dead);
2246
2247 sdhci_free_host(slot->host);
2248 }
2249
sdhci_pci_runtime_pm_allow(struct device * dev)2250 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2251 {
2252 pm_suspend_ignore_children(dev, 1);
2253 pm_runtime_set_autosuspend_delay(dev, 50);
2254 pm_runtime_use_autosuspend(dev);
2255 pm_runtime_allow(dev);
2256 /* Stay active until mmc core scans for a card */
2257 pm_runtime_put_noidle(dev);
2258 }
2259
sdhci_pci_runtime_pm_forbid(struct device * dev)2260 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2261 {
2262 pm_runtime_forbid(dev);
2263 pm_runtime_get_noresume(dev);
2264 }
2265
sdhci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2266 static int sdhci_pci_probe(struct pci_dev *pdev,
2267 const struct pci_device_id *ent)
2268 {
2269 struct sdhci_pci_chip *chip;
2270 struct sdhci_pci_slot *slot;
2271
2272 u8 slots, first_bar;
2273 int ret, i;
2274
2275 BUG_ON(pdev == NULL);
2276 BUG_ON(ent == NULL);
2277
2278 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2279 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2280
2281 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2282 if (ret)
2283 return pcibios_err_to_errno(ret);
2284
2285 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2286 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2287
2288 BUG_ON(slots > MAX_SLOTS);
2289
2290 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2291 if (ret)
2292 return pcibios_err_to_errno(ret);
2293
2294 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2295
2296 if (first_bar > 5) {
2297 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2298 return -ENODEV;
2299 }
2300
2301 ret = pcim_enable_device(pdev);
2302 if (ret)
2303 return ret;
2304
2305 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2306 if (!chip)
2307 return -ENOMEM;
2308
2309 chip->pdev = pdev;
2310 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2311 if (chip->fixes) {
2312 chip->quirks = chip->fixes->quirks;
2313 chip->quirks2 = chip->fixes->quirks2;
2314 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2315 }
2316 chip->num_slots = slots;
2317 chip->pm_retune = true;
2318 chip->rpm_retune = true;
2319
2320 pci_set_drvdata(pdev, chip);
2321
2322 if (chip->fixes && chip->fixes->probe) {
2323 ret = chip->fixes->probe(chip);
2324 if (ret)
2325 return ret;
2326 }
2327
2328 slots = chip->num_slots; /* Quirk may have changed this */
2329
2330 for (i = 0; i < slots; i++) {
2331 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2332 if (IS_ERR(slot)) {
2333 for (i--; i >= 0; i--)
2334 sdhci_pci_remove_slot(chip->slots[i]);
2335 return PTR_ERR(slot);
2336 }
2337
2338 chip->slots[i] = slot;
2339 }
2340
2341 if (chip->allow_runtime_pm)
2342 sdhci_pci_runtime_pm_allow(&pdev->dev);
2343
2344 return 0;
2345 }
2346
sdhci_pci_remove(struct pci_dev * pdev)2347 static void sdhci_pci_remove(struct pci_dev *pdev)
2348 {
2349 int i;
2350 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2351
2352 if (chip->allow_runtime_pm)
2353 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2354
2355 for (i = 0; i < chip->num_slots; i++)
2356 sdhci_pci_remove_slot(chip->slots[i]);
2357 }
2358
2359 static struct pci_driver sdhci_driver = {
2360 .name = "sdhci-pci",
2361 .id_table = pci_ids,
2362 .probe = sdhci_pci_probe,
2363 .remove = sdhci_pci_remove,
2364 .driver = {
2365 .pm = &sdhci_pci_pm_ops,
2366 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2367 },
2368 };
2369
2370 module_pci_driver(sdhci_driver);
2371
2372 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2373 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2374 MODULE_LICENSE("GPL");
2375