1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2011 The Chromium Authors
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <asm/io.h>
9 #include <asm/arch/iomap.h>
10 #include <asm/arch/pch.h>
11
broadwell_northbridge_early_init(struct udevice * dev)12 static int broadwell_northbridge_early_init(struct udevice *dev)
13 {
14 /* Move earlier? */
15 dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
16 /* 64MiB - 0-63 buses */
17 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
18
19 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
20 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
21 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
22 writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
23 writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
24
25 /* Set C0000-FFFFF to access RAM on both reads and writes */
26 dm_pci_write_config8(dev, PAM0, 0x30);
27 dm_pci_write_config8(dev, PAM1, 0x33);
28 dm_pci_write_config8(dev, PAM2, 0x33);
29 dm_pci_write_config8(dev, PAM3, 0x33);
30 dm_pci_write_config8(dev, PAM4, 0x33);
31 dm_pci_write_config8(dev, PAM5, 0x33);
32 dm_pci_write_config8(dev, PAM6, 0x33);
33
34 /* Device enable: IGD and Mini-HD */
35 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
36
37 return 0;
38 }
39
broadwell_northbridge_probe(struct udevice * dev)40 static int broadwell_northbridge_probe(struct udevice *dev)
41 {
42 if (!(gd->flags & GD_FLG_RELOC))
43 return broadwell_northbridge_early_init(dev);
44
45 return 0;
46 }
47
48 static const struct udevice_id broadwell_northbridge_ids[] = {
49 { .compatible = "intel,broadwell-northbridge" },
50 { }
51 };
52
53 U_BOOT_DRIVER(broadwell_northbridge_drv) = {
54 .name = "broadwell_northbridge",
55 .id = UCLASS_NORTHBRIDGE,
56 .of_match = broadwell_northbridge_ids,
57 .probe = broadwell_northbridge_probe,
58 };
59