xref: /openbmc/linux/drivers/memory/brcmstb_dpfe.c (revision 0b483871)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
4  *
5  * Copyright (c) 2017 Broadcom
6  */
7 
8 /*
9  * This driver provides access to the DPFE interface of Broadcom STB SoCs.
10  * The firmware running on the DCPU inside the DDR PHY can provide current
11  * information about the system's RAM, for instance the DRAM refresh rate.
12  * This can be used as an indirect indicator for the DRAM's temperature.
13  * Slower refresh rate means cooler RAM, higher refresh rate means hotter
14  * RAM.
15  *
16  * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
17  * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
18  *
19  * Note regarding the loading of the firmware image: we use be32_to_cpu()
20  * and le_32_to_cpu(), so we can support the following four cases:
21  *     - LE kernel + LE firmware image (the most common case)
22  *     - LE kernel + BE firmware image
23  *     - BE kernel + LE firmware image
24  *     - BE kernel + BE firmware image
25  *
26  * The DPCU always runs in big endian mode. The firmware image, however, can
27  * be in either format. Also, communication between host CPU and DCPU is
28  * always in little endian.
29  */
30 
31 #include <linux/delay.h>
32 #include <linux/firmware.h>
33 #include <linux/io.h>
34 #include <linux/module.h>
35 #include <linux/of.h>
36 #include <linux/platform_device.h>
37 
38 #define DRVNAME			"brcmstb-dpfe"
39 
40 /* DCPU register offsets */
41 #define REG_DCPU_RESET		0x0
42 #define REG_TO_DCPU_MBOX	0x10
43 #define REG_TO_HOST_MBOX	0x14
44 
45 /* Macros to process offsets returned by the DCPU */
46 #define DRAM_MSG_ADDR_OFFSET	0x0
47 #define DRAM_MSG_TYPE_OFFSET	0x1c
48 #define DRAM_MSG_ADDR_MASK	((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
49 #define DRAM_MSG_TYPE_MASK	((1UL << \
50 				 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
51 
52 /* Message RAM */
53 #define DCPU_MSG_RAM_START	0x100
54 #define DCPU_MSG_RAM(x)		(DCPU_MSG_RAM_START + (x) * sizeof(u32))
55 
56 /* DRAM Info Offsets & Masks */
57 #define DRAM_INFO_INTERVAL	0x0
58 #define DRAM_INFO_MR4		0x4
59 #define DRAM_INFO_ERROR		0x8
60 #define DRAM_INFO_MR4_MASK	0xff
61 #define DRAM_INFO_MR4_SHIFT	24	/* We need to look at byte 3 */
62 
63 /* DRAM MR4 Offsets & Masks */
64 #define DRAM_MR4_REFRESH	0x0	/* Refresh rate */
65 #define DRAM_MR4_SR_ABORT	0x3	/* Self Refresh Abort */
66 #define DRAM_MR4_PPRE		0x4	/* Post-package repair entry/exit */
67 #define DRAM_MR4_TH_OFFS	0x5	/* Thermal Offset; vendor specific */
68 #define DRAM_MR4_TUF		0x7	/* Temperature Update Flag */
69 
70 #define DRAM_MR4_REFRESH_MASK	0x7
71 #define DRAM_MR4_SR_ABORT_MASK	0x1
72 #define DRAM_MR4_PPRE_MASK	0x1
73 #define DRAM_MR4_TH_OFFS_MASK	0x3
74 #define DRAM_MR4_TUF_MASK	0x1
75 
76 /* DRAM Vendor Offsets & Masks (API v2) */
77 #define DRAM_VENDOR_MR5		0x0
78 #define DRAM_VENDOR_MR6		0x4
79 #define DRAM_VENDOR_MR7		0x8
80 #define DRAM_VENDOR_MR8		0xc
81 #define DRAM_VENDOR_ERROR	0x10
82 #define DRAM_VENDOR_MASK	0xff
83 #define DRAM_VENDOR_SHIFT	24	/* We need to look at byte 3 */
84 
85 /* DRAM Information Offsets & Masks (API v3) */
86 #define DRAM_DDR_INFO_MR4	0x0
87 #define DRAM_DDR_INFO_MR5	0x4
88 #define DRAM_DDR_INFO_MR6	0x8
89 #define DRAM_DDR_INFO_MR7	0xc
90 #define DRAM_DDR_INFO_MR8	0x10
91 #define DRAM_DDR_INFO_ERROR	0x14
92 #define DRAM_DDR_INFO_MASK	0xff
93 
94 /* Reset register bits & masks */
95 #define DCPU_RESET_SHIFT	0x0
96 #define DCPU_RESET_MASK		0x1
97 #define DCPU_CLK_DISABLE_SHIFT	0x2
98 
99 /* DCPU return codes */
100 #define DCPU_RET_ERROR_BIT	BIT(31)
101 #define DCPU_RET_SUCCESS	0x1
102 #define DCPU_RET_ERR_HEADER	(DCPU_RET_ERROR_BIT | BIT(0))
103 #define DCPU_RET_ERR_INVAL	(DCPU_RET_ERROR_BIT | BIT(1))
104 #define DCPU_RET_ERR_CHKSUM	(DCPU_RET_ERROR_BIT | BIT(2))
105 #define DCPU_RET_ERR_COMMAND	(DCPU_RET_ERROR_BIT | BIT(3))
106 /* This error code is not firmware defined and only used in the driver. */
107 #define DCPU_RET_ERR_TIMEDOUT	(DCPU_RET_ERROR_BIT | BIT(4))
108 
109 /* Firmware magic */
110 #define DPFE_BE_MAGIC		0xfe1010fe
111 #define DPFE_LE_MAGIC		0xfe0101fe
112 
113 /* Error codes */
114 #define ERR_INVALID_MAGIC	-1
115 #define ERR_INVALID_SIZE	-2
116 #define ERR_INVALID_CHKSUM	-3
117 
118 /* Message types */
119 #define DPFE_MSG_TYPE_COMMAND	1
120 #define DPFE_MSG_TYPE_RESPONSE	2
121 
122 #define DELAY_LOOP_MAX		1000
123 
124 enum dpfe_msg_fields {
125 	MSG_HEADER,
126 	MSG_COMMAND,
127 	MSG_ARG_COUNT,
128 	MSG_ARG0,
129 	MSG_FIELD_MAX	= 16 /* Max number of arguments */
130 };
131 
132 enum dpfe_commands {
133 	DPFE_CMD_GET_INFO,
134 	DPFE_CMD_GET_REFRESH,
135 	DPFE_CMD_GET_VENDOR,
136 	DPFE_CMD_MAX /* Last entry */
137 };
138 
139 /*
140  * Format of the binary firmware file:
141  *
142  *   entry
143  *      0    header
144  *              value:  0xfe0101fe  <== little endian
145  *                      0xfe1010fe  <== big endian
146  *      1    sequence:
147  *              [31:16] total segments on this build
148  *              [15:0]  this segment sequence.
149  *      2    FW version
150  *      3    IMEM byte size
151  *      4    DMEM byte size
152  *           IMEM
153  *           DMEM
154  *      last checksum ==> sum of everything
155  */
156 struct dpfe_firmware_header {
157 	u32 magic;
158 	u32 sequence;
159 	u32 version;
160 	u32 imem_size;
161 	u32 dmem_size;
162 };
163 
164 /* Things we only need during initialization. */
165 struct init_data {
166 	unsigned int dmem_len;
167 	unsigned int imem_len;
168 	unsigned int chksum;
169 	bool is_big_endian;
170 };
171 
172 /* API version and corresponding commands */
173 struct dpfe_api {
174 	int version;
175 	const char *fw_name;
176 	const struct attribute_group **sysfs_attrs;
177 	u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
178 };
179 
180 /* Things we need for as long as we are active. */
181 struct brcmstb_dpfe_priv {
182 	void __iomem *regs;
183 	void __iomem *dmem;
184 	void __iomem *imem;
185 	struct device *dev;
186 	const struct dpfe_api *dpfe_api;
187 	struct mutex lock;
188 };
189 
190 /*
191  * Forward declaration of our sysfs attribute functions, so we can declare the
192  * attribute data structures early.
193  */
194 static ssize_t show_info(struct device *, struct device_attribute *, char *);
195 static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
196 static ssize_t store_refresh(struct device *, struct device_attribute *,
197 			  const char *, size_t);
198 static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
199 static ssize_t show_dram(struct device *, struct device_attribute *, char *);
200 
201 /*
202  * Declare our attributes early, so they can be referenced in the API data
203  * structure. We need to do this, because the attributes depend on the API
204  * version.
205  */
206 static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
207 static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
208 static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
209 static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
210 
211 /* API v2 sysfs attributes */
212 static struct attribute *dpfe_v2_attrs[] = {
213 	&dev_attr_dpfe_info.attr,
214 	&dev_attr_dpfe_refresh.attr,
215 	&dev_attr_dpfe_vendor.attr,
216 	NULL
217 };
218 ATTRIBUTE_GROUPS(dpfe_v2);
219 
220 /* API v3 sysfs attributes */
221 static struct attribute *dpfe_v3_attrs[] = {
222 	&dev_attr_dpfe_info.attr,
223 	&dev_attr_dpfe_dram.attr,
224 	NULL
225 };
226 ATTRIBUTE_GROUPS(dpfe_v3);
227 
228 /*
229  * Old API v2 firmware commands, as defined in the rev 0.61 specification, we
230  * use a version set to 1 to denote that it is not compatible with the new API
231  * v2 and onwards.
232  */
233 static const struct dpfe_api dpfe_api_old_v2 = {
234 	.version = 1,
235 	.fw_name = "dpfe.bin",
236 	.sysfs_attrs = dpfe_v2_groups,
237 	.command = {
238 		[DPFE_CMD_GET_INFO] = {
239 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
240 			[MSG_COMMAND] = 1,
241 			[MSG_ARG_COUNT] = 1,
242 			[MSG_ARG0] = 1,
243 		},
244 		[DPFE_CMD_GET_REFRESH] = {
245 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
246 			[MSG_COMMAND] = 2,
247 			[MSG_ARG_COUNT] = 1,
248 			[MSG_ARG0] = 1,
249 		},
250 		[DPFE_CMD_GET_VENDOR] = {
251 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
252 			[MSG_COMMAND] = 2,
253 			[MSG_ARG_COUNT] = 1,
254 			[MSG_ARG0] = 2,
255 		},
256 	}
257 };
258 
259 /*
260  * API v2 firmware commands, as defined in the rev 0.8 specification, named new
261  * v2 here
262  */
263 static const struct dpfe_api dpfe_api_new_v2 = {
264 	.version = 2,
265 	.fw_name = NULL, /* We expect the firmware to have been downloaded! */
266 	.sysfs_attrs = dpfe_v2_groups,
267 	.command = {
268 		[DPFE_CMD_GET_INFO] = {
269 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
270 			[MSG_COMMAND] = 0x101,
271 		},
272 		[DPFE_CMD_GET_REFRESH] = {
273 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
274 			[MSG_COMMAND] = 0x201,
275 		},
276 		[DPFE_CMD_GET_VENDOR] = {
277 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
278 			[MSG_COMMAND] = 0x202,
279 		},
280 	}
281 };
282 
283 /* API v3 firmware commands */
284 static const struct dpfe_api dpfe_api_v3 = {
285 	.version = 3,
286 	.fw_name = NULL, /* We expect the firmware to have been downloaded! */
287 	.sysfs_attrs = dpfe_v3_groups,
288 	.command = {
289 		[DPFE_CMD_GET_INFO] = {
290 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
291 			[MSG_COMMAND] = 0x0101,
292 			[MSG_ARG_COUNT] = 1,
293 			[MSG_ARG0] = 1,
294 		},
295 		[DPFE_CMD_GET_REFRESH] = {
296 			[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
297 			[MSG_COMMAND] = 0x0202,
298 			[MSG_ARG_COUNT] = 0,
299 		},
300 		/* There's no GET_VENDOR command in API v3. */
301 	},
302 };
303 
get_error_text(unsigned int i)304 static const char *get_error_text(unsigned int i)
305 {
306 	static const char * const error_text[] = {
307 		"Success", "Header code incorrect",
308 		"Unknown command or argument", "Incorrect checksum",
309 		"Malformed command", "Timed out", "Unknown error",
310 	};
311 
312 	if (unlikely(i >= ARRAY_SIZE(error_text)))
313 		i = ARRAY_SIZE(error_text) - 1;
314 
315 	return error_text[i];
316 }
317 
is_dcpu_enabled(struct brcmstb_dpfe_priv * priv)318 static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
319 {
320 	u32 val;
321 
322 	mutex_lock(&priv->lock);
323 	val = readl_relaxed(priv->regs + REG_DCPU_RESET);
324 	mutex_unlock(&priv->lock);
325 
326 	return !(val & DCPU_RESET_MASK);
327 }
328 
__disable_dcpu(struct brcmstb_dpfe_priv * priv)329 static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
330 {
331 	u32 val;
332 
333 	if (!is_dcpu_enabled(priv))
334 		return;
335 
336 	mutex_lock(&priv->lock);
337 
338 	/* Put DCPU in reset if it's running. */
339 	val = readl_relaxed(priv->regs + REG_DCPU_RESET);
340 	val |= (1 << DCPU_RESET_SHIFT);
341 	writel_relaxed(val, priv->regs + REG_DCPU_RESET);
342 
343 	mutex_unlock(&priv->lock);
344 }
345 
__enable_dcpu(struct brcmstb_dpfe_priv * priv)346 static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
347 {
348 	void __iomem *regs = priv->regs;
349 	u32 val;
350 
351 	mutex_lock(&priv->lock);
352 
353 	/* Clear mailbox registers. */
354 	writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
355 	writel_relaxed(0, regs + REG_TO_HOST_MBOX);
356 
357 	/* Disable DCPU clock gating */
358 	val = readl_relaxed(regs + REG_DCPU_RESET);
359 	val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
360 	writel_relaxed(val, regs + REG_DCPU_RESET);
361 
362 	/* Take DCPU out of reset */
363 	val = readl_relaxed(regs + REG_DCPU_RESET);
364 	val &= ~(1 << DCPU_RESET_SHIFT);
365 	writel_relaxed(val, regs + REG_DCPU_RESET);
366 
367 	mutex_unlock(&priv->lock);
368 }
369 
get_msg_chksum(const u32 msg[],unsigned int max)370 static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
371 {
372 	unsigned int sum = 0;
373 	unsigned int i;
374 
375 	/* Don't include the last field in the checksum. */
376 	for (i = 0; i < max; i++)
377 		sum += msg[i];
378 
379 	return sum;
380 }
381 
get_msg_ptr(struct brcmstb_dpfe_priv * priv,u32 response,char * buf,ssize_t * size)382 static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
383 				 char *buf, ssize_t *size)
384 {
385 	unsigned int msg_type;
386 	unsigned int offset;
387 	void __iomem *ptr = NULL;
388 
389 	/* There is no need to use this function for API v3 or later. */
390 	if (unlikely(priv->dpfe_api->version >= 3))
391 		return NULL;
392 
393 	msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
394 	offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
395 
396 	/*
397 	 * msg_type == 1: the offset is relative to the message RAM
398 	 * msg_type == 0: the offset is relative to the data RAM (this is the
399 	 *                previous way of passing data)
400 	 * msg_type is anything else: there's critical hardware problem
401 	 */
402 	switch (msg_type) {
403 	case 1:
404 		ptr = priv->regs + DCPU_MSG_RAM_START + offset;
405 		break;
406 	case 0:
407 		ptr = priv->dmem + offset;
408 		break;
409 	default:
410 		dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
411 			response);
412 		if (buf && size)
413 			*size = sprintf(buf,
414 				"FATAL: communication error with DCPU\n");
415 	}
416 
417 	return ptr;
418 }
419 
__finalize_command(struct brcmstb_dpfe_priv * priv)420 static void __finalize_command(struct brcmstb_dpfe_priv *priv)
421 {
422 	unsigned int release_mbox;
423 
424 	/*
425 	 * It depends on the API version which MBOX register we have to write to
426 	 * signal we are done.
427 	 */
428 	release_mbox = (priv->dpfe_api->version < 2)
429 			? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
430 	writel_relaxed(0, priv->regs + release_mbox);
431 }
432 
__send_command(struct brcmstb_dpfe_priv * priv,unsigned int cmd,u32 result[])433 static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
434 			  u32 result[])
435 {
436 	void __iomem *regs = priv->regs;
437 	unsigned int i, chksum, chksum_idx;
438 	const u32 *msg;
439 	int ret = 0;
440 	u32 resp;
441 
442 	if (cmd >= DPFE_CMD_MAX)
443 		return -1;
444 
445 	msg = priv->dpfe_api->command[cmd];
446 
447 	mutex_lock(&priv->lock);
448 
449 	/* Wait for DCPU to become ready */
450 	for (i = 0; i < DELAY_LOOP_MAX; i++) {
451 		resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
452 		if (resp == 0)
453 			break;
454 		msleep(1);
455 	}
456 	if (resp != 0) {
457 		mutex_unlock(&priv->lock);
458 		return -ffs(DCPU_RET_ERR_TIMEDOUT);
459 	}
460 
461 	/* Compute checksum over the message */
462 	chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
463 	chksum = get_msg_chksum(msg, chksum_idx);
464 
465 	/* Write command and arguments to message area */
466 	for (i = 0; i < MSG_FIELD_MAX; i++) {
467 		if (i == chksum_idx)
468 			writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
469 		else
470 			writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
471 	}
472 
473 	/* Tell DCPU there is a command waiting */
474 	writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
475 
476 	/* Wait for DCPU to process the command */
477 	for (i = 0; i < DELAY_LOOP_MAX; i++) {
478 		/* Read response code */
479 		resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
480 		if (resp > 0)
481 			break;
482 		msleep(1);
483 	}
484 
485 	if (i == DELAY_LOOP_MAX) {
486 		resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
487 		ret = -ffs(resp);
488 	} else {
489 		/* Read response data */
490 		for (i = 0; i < MSG_FIELD_MAX; i++)
491 			result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
492 		chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
493 	}
494 
495 	/* Tell DCPU we are done */
496 	__finalize_command(priv);
497 
498 	mutex_unlock(&priv->lock);
499 
500 	if (ret)
501 		return ret;
502 
503 	/* Verify response */
504 	chksum = get_msg_chksum(result, chksum_idx);
505 	if (chksum != result[chksum_idx])
506 		resp = DCPU_RET_ERR_CHKSUM;
507 
508 	if (resp != DCPU_RET_SUCCESS) {
509 		resp &= ~DCPU_RET_ERROR_BIT;
510 		ret = -ffs(resp);
511 	}
512 
513 	return ret;
514 }
515 
516 /* Ensure that the firmware file loaded meets all the requirements. */
__verify_firmware(struct init_data * init,const struct firmware * fw)517 static int __verify_firmware(struct init_data *init,
518 			     const struct firmware *fw)
519 {
520 	const struct dpfe_firmware_header *header = (void *)fw->data;
521 	unsigned int dmem_size, imem_size, total_size;
522 	bool is_big_endian = false;
523 	const u32 *chksum_ptr;
524 
525 	if (header->magic == DPFE_BE_MAGIC)
526 		is_big_endian = true;
527 	else if (header->magic != DPFE_LE_MAGIC)
528 		return ERR_INVALID_MAGIC;
529 
530 	if (is_big_endian) {
531 		dmem_size = be32_to_cpu(header->dmem_size);
532 		imem_size = be32_to_cpu(header->imem_size);
533 	} else {
534 		dmem_size = le32_to_cpu(header->dmem_size);
535 		imem_size = le32_to_cpu(header->imem_size);
536 	}
537 
538 	/* Data and instruction sections are 32 bit words. */
539 	if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
540 		return ERR_INVALID_SIZE;
541 
542 	/*
543 	 * The header + the data section + the instruction section + the
544 	 * checksum must be equal to the total firmware size.
545 	 */
546 	total_size = dmem_size + imem_size + sizeof(*header) +
547 		sizeof(*chksum_ptr);
548 	if (total_size != fw->size)
549 		return ERR_INVALID_SIZE;
550 
551 	/* The checksum comes at the very end. */
552 	chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
553 
554 	init->is_big_endian = is_big_endian;
555 	init->dmem_len = dmem_size;
556 	init->imem_len = imem_size;
557 	init->chksum = (is_big_endian)
558 		? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
559 
560 	return 0;
561 }
562 
563 /* Verify checksum by reading back the firmware from co-processor RAM. */
__verify_fw_checksum(struct init_data * init,struct brcmstb_dpfe_priv * priv,const struct dpfe_firmware_header * header,u32 checksum)564 static int __verify_fw_checksum(struct init_data *init,
565 				struct brcmstb_dpfe_priv *priv,
566 				const struct dpfe_firmware_header *header,
567 				u32 checksum)
568 {
569 	u32 magic, sequence, version, sum;
570 	u32 __iomem *dmem = priv->dmem;
571 	u32 __iomem *imem = priv->imem;
572 	unsigned int i;
573 
574 	if (init->is_big_endian) {
575 		magic = be32_to_cpu(header->magic);
576 		sequence = be32_to_cpu(header->sequence);
577 		version = be32_to_cpu(header->version);
578 	} else {
579 		magic = le32_to_cpu(header->magic);
580 		sequence = le32_to_cpu(header->sequence);
581 		version = le32_to_cpu(header->version);
582 	}
583 
584 	sum = magic + sequence + version + init->dmem_len + init->imem_len;
585 
586 	for (i = 0; i < init->dmem_len / sizeof(u32); i++)
587 		sum += readl_relaxed(dmem + i);
588 
589 	for (i = 0; i < init->imem_len / sizeof(u32); i++)
590 		sum += readl_relaxed(imem + i);
591 
592 	return (sum == checksum) ? 0 : -1;
593 }
594 
__write_firmware(u32 __iomem * mem,const u32 * fw,unsigned int size,bool is_big_endian)595 static int __write_firmware(u32 __iomem *mem, const u32 *fw,
596 			    unsigned int size, bool is_big_endian)
597 {
598 	unsigned int i;
599 
600 	/* Convert size to 32-bit words. */
601 	size /= sizeof(u32);
602 
603 	/* It is recommended to clear the firmware area first. */
604 	for (i = 0; i < size; i++)
605 		writel_relaxed(0, mem + i);
606 
607 	/* Now copy it. */
608 	if (is_big_endian) {
609 		for (i = 0; i < size; i++)
610 			writel_relaxed(be32_to_cpu(fw[i]), mem + i);
611 	} else {
612 		for (i = 0; i < size; i++)
613 			writel_relaxed(le32_to_cpu(fw[i]), mem + i);
614 	}
615 
616 	return 0;
617 }
618 
brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv * priv)619 static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
620 {
621 	const struct dpfe_firmware_header *header;
622 	unsigned int dmem_size, imem_size;
623 	struct device *dev = priv->dev;
624 	bool is_big_endian = false;
625 	const struct firmware *fw;
626 	const u32 *dmem, *imem;
627 	struct init_data init;
628 	const void *fw_blob;
629 	int ret;
630 
631 	/*
632 	 * Skip downloading the firmware if the DCPU is already running and
633 	 * responding to commands.
634 	 */
635 	if (is_dcpu_enabled(priv)) {
636 		u32 response[MSG_FIELD_MAX];
637 
638 		ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
639 		if (!ret)
640 			return 0;
641 	}
642 
643 	/*
644 	 * If the firmware filename is NULL it means the boot firmware has to
645 	 * download the DCPU firmware for us. If that didn't work, we have to
646 	 * bail, since downloading it ourselves wouldn't work either.
647 	 */
648 	if (!priv->dpfe_api->fw_name)
649 		return -ENODEV;
650 
651 	ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
652 	/*
653 	 * Defer the firmware download if the firmware file couldn't be found.
654 	 * The root file system may not be available yet.
655 	 */
656 	if (ret)
657 		return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
658 
659 	ret = __verify_firmware(&init, fw);
660 	if (ret) {
661 		ret = -EFAULT;
662 		goto release_fw;
663 	}
664 
665 	__disable_dcpu(priv);
666 
667 	is_big_endian = init.is_big_endian;
668 	dmem_size = init.dmem_len;
669 	imem_size = init.imem_len;
670 
671 	/* At the beginning of the firmware blob is a header. */
672 	header = (struct dpfe_firmware_header *)fw->data;
673 	/* Void pointer to the beginning of the actual firmware. */
674 	fw_blob = fw->data + sizeof(*header);
675 	/* IMEM comes right after the header. */
676 	imem = fw_blob;
677 	/* DMEM follows after IMEM. */
678 	dmem = fw_blob + imem_size;
679 
680 	ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
681 	if (ret)
682 		goto release_fw;
683 	ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
684 	if (ret)
685 		goto release_fw;
686 
687 	ret = __verify_fw_checksum(&init, priv, header, init.chksum);
688 	if (ret)
689 		goto release_fw;
690 
691 	__enable_dcpu(priv);
692 
693 release_fw:
694 	release_firmware(fw);
695 	return ret;
696 }
697 
generic_show(unsigned int command,u32 response[],struct brcmstb_dpfe_priv * priv,char * buf)698 static ssize_t generic_show(unsigned int command, u32 response[],
699 			    struct brcmstb_dpfe_priv *priv, char *buf)
700 {
701 	int ret;
702 
703 	if (!priv)
704 		return sprintf(buf, "ERROR: driver private data not set\n");
705 
706 	ret = __send_command(priv, command, response);
707 	if (ret < 0)
708 		return sprintf(buf, "ERROR: %s\n", get_error_text(-ret));
709 
710 	return 0;
711 }
712 
show_info(struct device * dev,struct device_attribute * devattr,char * buf)713 static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
714 			 char *buf)
715 {
716 	u32 response[MSG_FIELD_MAX];
717 	struct brcmstb_dpfe_priv *priv;
718 	unsigned int info;
719 	ssize_t ret;
720 
721 	priv = dev_get_drvdata(dev);
722 	ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
723 	if (ret)
724 		return ret;
725 
726 	info = response[MSG_ARG0];
727 
728 	return sprintf(buf, "%u.%u.%u.%u\n",
729 		       (info >> 24) & 0xff,
730 		       (info >> 16) & 0xff,
731 		       (info >> 8) & 0xff,
732 		       info & 0xff);
733 }
734 
show_refresh(struct device * dev,struct device_attribute * devattr,char * buf)735 static ssize_t show_refresh(struct device *dev,
736 			    struct device_attribute *devattr, char *buf)
737 {
738 	u32 response[MSG_FIELD_MAX];
739 	void __iomem *info;
740 	struct brcmstb_dpfe_priv *priv;
741 	u8 refresh, sr_abort, ppre, thermal_offs, tuf;
742 	u32 mr4;
743 	ssize_t ret;
744 
745 	priv = dev_get_drvdata(dev);
746 	ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
747 	if (ret)
748 		return ret;
749 
750 	info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
751 	if (!info)
752 		return ret;
753 
754 	mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
755 	       DRAM_INFO_MR4_MASK;
756 
757 	refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
758 	sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
759 	ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
760 	thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
761 	tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
762 
763 	return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
764 		       readl_relaxed(info + DRAM_INFO_INTERVAL),
765 		       refresh, sr_abort, ppre, thermal_offs, tuf,
766 		       readl_relaxed(info + DRAM_INFO_ERROR));
767 }
768 
store_refresh(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)769 static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
770 			  const char *buf, size_t count)
771 {
772 	u32 response[MSG_FIELD_MAX];
773 	struct brcmstb_dpfe_priv *priv;
774 	void __iomem *info;
775 	unsigned long val;
776 	int ret;
777 
778 	if (kstrtoul(buf, 0, &val) < 0)
779 		return -EINVAL;
780 
781 	priv = dev_get_drvdata(dev);
782 	ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
783 	if (ret)
784 		return ret;
785 
786 	info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
787 	if (!info)
788 		return -EIO;
789 
790 	writel_relaxed(val, info + DRAM_INFO_INTERVAL);
791 
792 	return count;
793 }
794 
show_vendor(struct device * dev,struct device_attribute * devattr,char * buf)795 static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
796 			   char *buf)
797 {
798 	u32 response[MSG_FIELD_MAX];
799 	struct brcmstb_dpfe_priv *priv;
800 	void __iomem *info;
801 	ssize_t ret;
802 	u32 mr5, mr6, mr7, mr8, err;
803 
804 	priv = dev_get_drvdata(dev);
805 	ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
806 	if (ret)
807 		return ret;
808 
809 	info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
810 	if (!info)
811 		return ret;
812 
813 	mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
814 		DRAM_VENDOR_MASK;
815 	mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
816 		DRAM_VENDOR_MASK;
817 	mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
818 		DRAM_VENDOR_MASK;
819 	mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
820 		DRAM_VENDOR_MASK;
821 	err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
822 
823 	return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
824 }
825 
show_dram(struct device * dev,struct device_attribute * devattr,char * buf)826 static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
827 			 char *buf)
828 {
829 	u32 response[MSG_FIELD_MAX];
830 	struct brcmstb_dpfe_priv *priv;
831 	ssize_t ret;
832 	u32 mr4, mr5, mr6, mr7, mr8, err;
833 
834 	priv = dev_get_drvdata(dev);
835 	ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
836 	if (ret)
837 		return ret;
838 
839 	mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
840 	mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
841 	mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
842 	mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
843 	mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
844 	err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
845 
846 	return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
847 			mr8, err);
848 }
849 
brcmstb_dpfe_resume(struct platform_device * pdev)850 static int brcmstb_dpfe_resume(struct platform_device *pdev)
851 {
852 	struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
853 
854 	return brcmstb_dpfe_download_firmware(priv);
855 }
856 
brcmstb_dpfe_probe(struct platform_device * pdev)857 static int brcmstb_dpfe_probe(struct platform_device *pdev)
858 {
859 	struct device *dev = &pdev->dev;
860 	struct brcmstb_dpfe_priv *priv;
861 	int ret;
862 
863 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
864 	if (!priv)
865 		return -ENOMEM;
866 
867 	priv->dev = dev;
868 
869 	mutex_init(&priv->lock);
870 	platform_set_drvdata(pdev, priv);
871 
872 	priv->regs = devm_platform_ioremap_resource_byname(pdev, "dpfe-cpu");
873 	if (IS_ERR(priv->regs)) {
874 		dev_err(dev, "couldn't map DCPU registers\n");
875 		return -ENODEV;
876 	}
877 
878 	priv->dmem = devm_platform_ioremap_resource_byname(pdev, "dpfe-dmem");
879 	if (IS_ERR(priv->dmem)) {
880 		dev_err(dev, "Couldn't map DCPU data memory\n");
881 		return -ENOENT;
882 	}
883 
884 	priv->imem = devm_platform_ioremap_resource_byname(pdev, "dpfe-imem");
885 	if (IS_ERR(priv->imem)) {
886 		dev_err(dev, "Couldn't map DCPU instruction memory\n");
887 		return -ENOENT;
888 	}
889 
890 	priv->dpfe_api = of_device_get_match_data(dev);
891 	if (unlikely(!priv->dpfe_api)) {
892 		/*
893 		 * It should be impossible to end up here, but to be safe we
894 		 * check anyway.
895 		 */
896 		dev_err(dev, "Couldn't determine API\n");
897 		return -ENOENT;
898 	}
899 
900 	ret = brcmstb_dpfe_download_firmware(priv);
901 	if (ret)
902 		return dev_err_probe(dev, ret, "Couldn't download firmware\n");
903 
904 	ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
905 	if (!ret)
906 		dev_info(dev, "registered with API v%d.\n",
907 			 priv->dpfe_api->version);
908 
909 	return ret;
910 }
911 
brcmstb_dpfe_remove(struct platform_device * pdev)912 static int brcmstb_dpfe_remove(struct platform_device *pdev)
913 {
914 	struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
915 
916 	sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
917 
918 	return 0;
919 }
920 
921 static const struct of_device_id brcmstb_dpfe_of_match[] = {
922 	/* Use legacy API v2 for a select number of chips */
923 	{ .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
924 	{ .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
925 	{ .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
926 	{ .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
927 	/* API v3 is the default going forward */
928 	{ .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
929 	{}
930 };
931 MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
932 
933 static struct platform_driver brcmstb_dpfe_driver = {
934 	.driver	= {
935 		.name = DRVNAME,
936 		.of_match_table = brcmstb_dpfe_of_match,
937 	},
938 	.probe = brcmstb_dpfe_probe,
939 	.remove	= brcmstb_dpfe_remove,
940 	.resume = brcmstb_dpfe_resume,
941 };
942 
943 module_platform_driver(brcmstb_dpfe_driver);
944 
945 MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
946 MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
947 MODULE_LICENSE("GPL");
948