xref: /openbmc/linux/sound/soc/codecs/max98095.c (revision 9abcd240)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * max98095.c -- MAX98095 ALSA SoC Audio driver
4  *
5  * Copyright 2011 Maxim Integrated Products
6  */
7 
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/clk.h>
16 #include <linux/mutex.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
23 #include <linux/slab.h>
24 #include <asm/div64.h>
25 #include <sound/max98095.h>
26 #include <sound/jack.h>
27 #include "max98095.h"
28 
29 enum max98095_type {
30 	MAX98095,
31 };
32 
33 struct max98095_cdata {
34 	unsigned int rate;
35 	unsigned int fmt;
36 	int eq_sel;
37 	int bq_sel;
38 };
39 
40 struct max98095_priv {
41 	struct regmap *regmap;
42 	enum max98095_type devtype;
43 	struct max98095_pdata *pdata;
44 	struct clk *mclk;
45 	unsigned int sysclk;
46 	struct max98095_cdata dai[3];
47 	const char **eq_texts;
48 	const char **bq_texts;
49 	struct soc_enum eq_enum;
50 	struct soc_enum bq_enum;
51 	int eq_textcnt;
52 	int bq_textcnt;
53 	u8 lin_state;
54 	unsigned int mic1pre;
55 	unsigned int mic2pre;
56 	struct snd_soc_jack *headphone_jack;
57 	struct snd_soc_jack *mic_jack;
58 	struct mutex lock;
59 };
60 
61 static const struct reg_default max98095_reg_def[] = {
62 	{  0xf, 0x00 }, /* 0F */
63 	{ 0x10, 0x00 }, /* 10 */
64 	{ 0x11, 0x00 }, /* 11 */
65 	{ 0x12, 0x00 }, /* 12 */
66 	{ 0x13, 0x00 }, /* 13 */
67 	{ 0x14, 0x00 }, /* 14 */
68 	{ 0x15, 0x00 }, /* 15 */
69 	{ 0x16, 0x00 }, /* 16 */
70 	{ 0x17, 0x00 }, /* 17 */
71 	{ 0x18, 0x00 }, /* 18 */
72 	{ 0x19, 0x00 }, /* 19 */
73 	{ 0x1a, 0x00 }, /* 1A */
74 	{ 0x1b, 0x00 }, /* 1B */
75 	{ 0x1c, 0x00 }, /* 1C */
76 	{ 0x1d, 0x00 }, /* 1D */
77 	{ 0x1e, 0x00 }, /* 1E */
78 	{ 0x1f, 0x00 }, /* 1F */
79 	{ 0x20, 0x00 }, /* 20 */
80 	{ 0x21, 0x00 }, /* 21 */
81 	{ 0x22, 0x00 }, /* 22 */
82 	{ 0x23, 0x00 }, /* 23 */
83 	{ 0x24, 0x00 }, /* 24 */
84 	{ 0x25, 0x00 }, /* 25 */
85 	{ 0x26, 0x00 }, /* 26 */
86 	{ 0x27, 0x00 }, /* 27 */
87 	{ 0x28, 0x00 }, /* 28 */
88 	{ 0x29, 0x00 }, /* 29 */
89 	{ 0x2a, 0x00 }, /* 2A */
90 	{ 0x2b, 0x00 }, /* 2B */
91 	{ 0x2c, 0x00 }, /* 2C */
92 	{ 0x2d, 0x00 }, /* 2D */
93 	{ 0x2e, 0x00 }, /* 2E */
94 	{ 0x2f, 0x00 }, /* 2F */
95 	{ 0x30, 0x00 }, /* 30 */
96 	{ 0x31, 0x00 }, /* 31 */
97 	{ 0x32, 0x00 }, /* 32 */
98 	{ 0x33, 0x00 }, /* 33 */
99 	{ 0x34, 0x00 }, /* 34 */
100 	{ 0x35, 0x00 }, /* 35 */
101 	{ 0x36, 0x00 }, /* 36 */
102 	{ 0x37, 0x00 }, /* 37 */
103 	{ 0x38, 0x00 }, /* 38 */
104 	{ 0x39, 0x00 }, /* 39 */
105 	{ 0x3a, 0x00 }, /* 3A */
106 	{ 0x3b, 0x00 }, /* 3B */
107 	{ 0x3c, 0x00 }, /* 3C */
108 	{ 0x3d, 0x00 }, /* 3D */
109 	{ 0x3e, 0x00 }, /* 3E */
110 	{ 0x3f, 0x00 }, /* 3F */
111 	{ 0x40, 0x00 }, /* 40 */
112 	{ 0x41, 0x00 }, /* 41 */
113 	{ 0x42, 0x00 }, /* 42 */
114 	{ 0x43, 0x00 }, /* 43 */
115 	{ 0x44, 0x00 }, /* 44 */
116 	{ 0x45, 0x00 }, /* 45 */
117 	{ 0x46, 0x00 }, /* 46 */
118 	{ 0x47, 0x00 }, /* 47 */
119 	{ 0x48, 0x00 }, /* 48 */
120 	{ 0x49, 0x00 }, /* 49 */
121 	{ 0x4a, 0x00 }, /* 4A */
122 	{ 0x4b, 0x00 }, /* 4B */
123 	{ 0x4c, 0x00 }, /* 4C */
124 	{ 0x4d, 0x00 }, /* 4D */
125 	{ 0x4e, 0x00 }, /* 4E */
126 	{ 0x4f, 0x00 }, /* 4F */
127 	{ 0x50, 0x00 }, /* 50 */
128 	{ 0x51, 0x00 }, /* 51 */
129 	{ 0x52, 0x00 }, /* 52 */
130 	{ 0x53, 0x00 }, /* 53 */
131 	{ 0x54, 0x00 }, /* 54 */
132 	{ 0x55, 0x00 }, /* 55 */
133 	{ 0x56, 0x00 }, /* 56 */
134 	{ 0x57, 0x00 }, /* 57 */
135 	{ 0x58, 0x00 }, /* 58 */
136 	{ 0x59, 0x00 }, /* 59 */
137 	{ 0x5a, 0x00 }, /* 5A */
138 	{ 0x5b, 0x00 }, /* 5B */
139 	{ 0x5c, 0x00 }, /* 5C */
140 	{ 0x5d, 0x00 }, /* 5D */
141 	{ 0x5e, 0x00 }, /* 5E */
142 	{ 0x5f, 0x00 }, /* 5F */
143 	{ 0x60, 0x00 }, /* 60 */
144 	{ 0x61, 0x00 }, /* 61 */
145 	{ 0x62, 0x00 }, /* 62 */
146 	{ 0x63, 0x00 }, /* 63 */
147 	{ 0x64, 0x00 }, /* 64 */
148 	{ 0x65, 0x00 }, /* 65 */
149 	{ 0x66, 0x00 }, /* 66 */
150 	{ 0x67, 0x00 }, /* 67 */
151 	{ 0x68, 0x00 }, /* 68 */
152 	{ 0x69, 0x00 }, /* 69 */
153 	{ 0x6a, 0x00 }, /* 6A */
154 	{ 0x6b, 0x00 }, /* 6B */
155 	{ 0x6c, 0x00 }, /* 6C */
156 	{ 0x6d, 0x00 }, /* 6D */
157 	{ 0x6e, 0x00 }, /* 6E */
158 	{ 0x6f, 0x00 }, /* 6F */
159 	{ 0x70, 0x00 }, /* 70 */
160 	{ 0x71, 0x00 }, /* 71 */
161 	{ 0x72, 0x00 }, /* 72 */
162 	{ 0x73, 0x00 }, /* 73 */
163 	{ 0x74, 0x00 }, /* 74 */
164 	{ 0x75, 0x00 }, /* 75 */
165 	{ 0x76, 0x00 }, /* 76 */
166 	{ 0x77, 0x00 }, /* 77 */
167 	{ 0x78, 0x00 }, /* 78 */
168 	{ 0x79, 0x00 }, /* 79 */
169 	{ 0x7a, 0x00 }, /* 7A */
170 	{ 0x7b, 0x00 }, /* 7B */
171 	{ 0x7c, 0x00 }, /* 7C */
172 	{ 0x7d, 0x00 }, /* 7D */
173 	{ 0x7e, 0x00 }, /* 7E */
174 	{ 0x7f, 0x00 }, /* 7F */
175 	{ 0x80, 0x00 }, /* 80 */
176 	{ 0x81, 0x00 }, /* 81 */
177 	{ 0x82, 0x00 }, /* 82 */
178 	{ 0x83, 0x00 }, /* 83 */
179 	{ 0x84, 0x00 }, /* 84 */
180 	{ 0x85, 0x00 }, /* 85 */
181 	{ 0x86, 0x00 }, /* 86 */
182 	{ 0x87, 0x00 }, /* 87 */
183 	{ 0x88, 0x00 }, /* 88 */
184 	{ 0x89, 0x00 }, /* 89 */
185 	{ 0x8a, 0x00 }, /* 8A */
186 	{ 0x8b, 0x00 }, /* 8B */
187 	{ 0x8c, 0x00 }, /* 8C */
188 	{ 0x8d, 0x00 }, /* 8D */
189 	{ 0x8e, 0x00 }, /* 8E */
190 	{ 0x8f, 0x00 }, /* 8F */
191 	{ 0x90, 0x00 }, /* 90 */
192 	{ 0x91, 0x00 }, /* 91 */
193 	{ 0x92, 0x30 }, /* 92 */
194 	{ 0x93, 0xF0 }, /* 93 */
195 	{ 0x94, 0x00 }, /* 94 */
196 	{ 0x95, 0x00 }, /* 95 */
197 	{ 0x96, 0x3F }, /* 96 */
198 	{ 0x97, 0x00 }, /* 97 */
199 	{ 0xff, 0x00 }, /* FF */
200 };
201 
max98095_readable(struct device * dev,unsigned int reg)202 static bool max98095_readable(struct device *dev, unsigned int reg)
203 {
204 	switch (reg) {
205 	case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
206 	case M98095_0FF_REV_ID:
207 		return true;
208 	default:
209 		return false;
210 	}
211 }
212 
max98095_writeable(struct device * dev,unsigned int reg)213 static bool max98095_writeable(struct device *dev, unsigned int reg)
214 {
215 	switch (reg) {
216 	case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
217 		return true;
218 	default:
219 		return false;
220 	}
221 }
222 
max98095_volatile(struct device * dev,unsigned int reg)223 static bool max98095_volatile(struct device *dev, unsigned int reg)
224 {
225 	switch (reg) {
226 	case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
227 	case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
228 		return true;
229 	default:
230 		return false;
231 	}
232 }
233 
234 static const struct regmap_config max98095_regmap = {
235 	.reg_bits = 8,
236 	.val_bits = 8,
237 
238 	.reg_defaults = max98095_reg_def,
239 	.num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
240 	.max_register = M98095_0FF_REV_ID,
241 	.cache_type = REGCACHE_RBTREE,
242 
243 	.readable_reg = max98095_readable,
244 	.writeable_reg = max98095_writeable,
245 	.volatile_reg = max98095_volatile,
246 };
247 
248 /*
249  * Load equalizer DSP coefficient configurations registers
250  */
m98095_eq_band(struct snd_soc_component * component,unsigned int dai,unsigned int band,u16 * coefs)251 static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
252 		    unsigned int band, u16 *coefs)
253 {
254 	unsigned int eq_reg;
255 	unsigned int i;
256 
257 	if (WARN_ON(band > 4) ||
258 	    WARN_ON(dai > 1))
259 		return;
260 
261 	/* Load the base register address */
262 	eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
263 
264 	/* Add the band address offset, note adjustment for word address */
265 	eq_reg += band * (M98095_COEFS_PER_BAND << 1);
266 
267 	/* Step through the registers and coefs */
268 	for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
269 		snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
270 		snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
271 	}
272 }
273 
274 /*
275  * Load biquad filter coefficient configurations registers
276  */
m98095_biquad_band(struct snd_soc_component * component,unsigned int dai,unsigned int band,u16 * coefs)277 static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
278 		    unsigned int band, u16 *coefs)
279 {
280 	unsigned int bq_reg;
281 	unsigned int i;
282 
283 	if (WARN_ON(band > 1) ||
284 	    WARN_ON(dai > 1))
285 		return;
286 
287 	/* Load the base register address */
288 	bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
289 
290 	/* Add the band address offset, note adjustment for word address */
291 	bq_reg += band * (M98095_COEFS_PER_BAND << 1);
292 
293 	/* Step through the registers and coefs */
294 	for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
295 		snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
296 		snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
297 	}
298 }
299 
300 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
301 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
302 			    M98095_02E_DAI1_FILTERS, 7,
303 			    max98095_fltr_mode);
304 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
305 			    M98095_038_DAI2_FILTERS, 7,
306 			    max98095_fltr_mode);
307 
308 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
309 
310 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
311 			    M98095_087_CFG_MIC, 0,
312 			    max98095_extmic_text);
313 
314 static const struct snd_kcontrol_new max98095_extmic_mux =
315 	SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
316 
317 static const char * const max98095_linein_text[] = { "INA", "INB" };
318 
319 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
320 			    M98095_086_CFG_LINE, 6,
321 			    max98095_linein_text);
322 
323 static const struct snd_kcontrol_new max98095_linein_mux =
324 	SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
325 
326 static const char * const max98095_line_mode_text[] = {
327 	"Stereo", "Differential"};
328 
329 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
330 			    M98095_086_CFG_LINE, 7,
331 			    max98095_line_mode_text);
332 
333 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
334 			    M98095_086_CFG_LINE, 4,
335 			    max98095_line_mode_text);
336 
337 static const char * const max98095_dai_fltr[] = {
338 	"Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
339 	"Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
340 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
341 			    M98095_02E_DAI1_FILTERS, 0,
342 			    max98095_dai_fltr);
343 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
344 			    M98095_038_DAI2_FILTERS, 0,
345 			    max98095_dai_fltr);
346 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
347 			    M98095_042_DAI3_FILTERS, 0,
348 			    max98095_dai_fltr);
349 
max98095_mic1pre_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)350 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
351 				struct snd_ctl_elem_value *ucontrol)
352 {
353 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
354 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
355 	unsigned int sel = ucontrol->value.integer.value[0];
356 
357 	max98095->mic1pre = sel;
358 	snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
359 		(1+sel)<<M98095_MICPRE_SHIFT);
360 
361 	return 0;
362 }
363 
max98095_mic1pre_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)364 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
365 				struct snd_ctl_elem_value *ucontrol)
366 {
367 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
368 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
369 
370 	ucontrol->value.integer.value[0] = max98095->mic1pre;
371 	return 0;
372 }
373 
max98095_mic2pre_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)374 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
375 				struct snd_ctl_elem_value *ucontrol)
376 {
377 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
378 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
379 	unsigned int sel = ucontrol->value.integer.value[0];
380 
381 	max98095->mic2pre = sel;
382 	snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
383 		(1+sel)<<M98095_MICPRE_SHIFT);
384 
385 	return 0;
386 }
387 
max98095_mic2pre_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)388 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
389 				struct snd_ctl_elem_value *ucontrol)
390 {
391 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
392 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
393 
394 	ucontrol->value.integer.value[0] = max98095->mic2pre;
395 	return 0;
396 }
397 
398 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
399 	0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
400 	2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
401 );
402 
403 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
404 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
405 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
406 
407 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
408 	0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
409 	7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
410 	15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
411 	22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
412 	28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
413 );
414 
415 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
416 	0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
417 	11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
418 	19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
419 	28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
420 );
421 
422 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
423 	0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
424 	7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
425 	15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
426 	22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
427 	28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
428 );
429 
430 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
431 	0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
432 	3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
433 	4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
434 );
435 
436 static const struct snd_kcontrol_new max98095_snd_controls[] = {
437 
438 	SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
439 		M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
440 
441 	SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
442 		M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
443 
444 	SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
445 		0, 31, 0, max98095_rcv_lout_tlv),
446 
447 	SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
448 		M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
449 
450 	SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
451 		M98095_065_LVL_HP_R, 7, 1, 1),
452 
453 	SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
454 		M98095_068_LVL_SPK_R, 7, 1, 1),
455 
456 	SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
457 
458 	SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
459 		M98095_063_LVL_LINEOUT2, 7, 1, 1),
460 
461 	SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
462 		max98095_mic_tlv),
463 
464 	SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
465 		max98095_mic_tlv),
466 
467 	SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
468 			M98095_05F_LVL_MIC1, 5, 2, 0,
469 			max98095_mic1pre_get, max98095_mic1pre_set,
470 			max98095_micboost_tlv),
471 	SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
472 			M98095_060_LVL_MIC2, 5, 2, 0,
473 			max98095_mic2pre_get, max98095_mic2pre_set,
474 			max98095_micboost_tlv),
475 
476 	SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
477 		max98095_lin_tlv),
478 
479 	SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
480 		max98095_adc_tlv),
481 	SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
482 		max98095_adc_tlv),
483 
484 	SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
485 		max98095_adcboost_tlv),
486 	SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
487 		max98095_adcboost_tlv),
488 
489 	SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
490 	SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
491 
492 	SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
493 	SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
494 
495 	SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
496 	SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
497 	SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
498 	SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
499 	SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
500 
501 	SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
502 	SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
503 };
504 
505 /* Left speaker mixer switch */
506 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
507 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
508 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
509 	SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
510 	SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
511 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
512 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
513 	SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
514 	SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
515 };
516 
517 /* Right speaker mixer switch */
518 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
519 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
520 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
521 	SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
522 	SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
523 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
524 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
525 	SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
526 	SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
527 };
528 
529 /* Left headphone mixer switch */
530 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
531 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
532 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
533 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
534 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
535 	SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
536 	SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
537 };
538 
539 /* Right headphone mixer switch */
540 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
541 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
542 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
543 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
544 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
545 	SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
546 	SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
547 };
548 
549 /* Receiver earpiece mixer switch */
550 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
551 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
552 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
553 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
554 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
555 	SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
556 	SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
557 };
558 
559 /* Left lineout mixer switch */
560 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
561 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
562 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
563 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
564 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
565 	SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
566 	SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
567 };
568 
569 /* Right lineout mixer switch */
570 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
571 	SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
572 	SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
573 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
574 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
575 	SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
576 	SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
577 };
578 
579 /* Left ADC mixer switch */
580 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
581 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
582 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
583 	SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
584 	SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
585 };
586 
587 /* Right ADC mixer switch */
588 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
589 	SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
590 	SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
591 	SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
592 	SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
593 };
594 
max98095_mic_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)595 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
596 			     struct snd_kcontrol *kcontrol, int event)
597 {
598 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
599 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
600 
601 	switch (event) {
602 	case SND_SOC_DAPM_POST_PMU:
603 		if (w->reg == M98095_05F_LVL_MIC1) {
604 			snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
605 				(1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
606 		} else {
607 			snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
608 				(1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
609 		}
610 		break;
611 	case SND_SOC_DAPM_POST_PMD:
612 		snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
613 		break;
614 	default:
615 		return -EINVAL;
616 	}
617 
618 	return 0;
619 }
620 
621 /*
622  * The line inputs are stereo inputs with the left and right
623  * channels sharing a common PGA power control signal.
624  */
max98095_line_pga(struct snd_soc_dapm_widget * w,int event,u8 channel)625 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
626 			     int event, u8 channel)
627 {
628 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
629 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
630 	u8 *state;
631 
632 	if (WARN_ON(!(channel == 1 || channel == 2)))
633 		return -EINVAL;
634 
635 	state = &max98095->lin_state;
636 
637 	switch (event) {
638 	case SND_SOC_DAPM_POST_PMU:
639 		*state |= channel;
640 		snd_soc_component_update_bits(component, w->reg,
641 			(1 << w->shift), (1 << w->shift));
642 		break;
643 	case SND_SOC_DAPM_POST_PMD:
644 		*state &= ~channel;
645 		if (*state == 0) {
646 			snd_soc_component_update_bits(component, w->reg,
647 				(1 << w->shift), 0);
648 		}
649 		break;
650 	default:
651 		return -EINVAL;
652 	}
653 
654 	return 0;
655 }
656 
max98095_pga_in1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)657 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
658 				   struct snd_kcontrol *k, int event)
659 {
660 	return max98095_line_pga(w, event, 1);
661 }
662 
max98095_pga_in2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)663 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
664 				   struct snd_kcontrol *k, int event)
665 {
666 	return max98095_line_pga(w, event, 2);
667 }
668 
669 /*
670  * The stereo line out mixer outputs to two stereo line outs.
671  * The 2nd pair has a separate set of enables.
672  */
max98095_lineout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)673 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
674 			     struct snd_kcontrol *kcontrol, int event)
675 {
676 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
677 
678 	switch (event) {
679 	case SND_SOC_DAPM_POST_PMU:
680 		snd_soc_component_update_bits(component, w->reg,
681 			(1 << (w->shift+2)), (1 << (w->shift+2)));
682 		break;
683 	case SND_SOC_DAPM_POST_PMD:
684 		snd_soc_component_update_bits(component, w->reg,
685 			(1 << (w->shift+2)), 0);
686 		break;
687 	default:
688 		return -EINVAL;
689 	}
690 
691 	return 0;
692 }
693 
694 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
695 
696 	SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
697 	SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
698 
699 	SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
700 		M98095_091_PWR_EN_OUT, 0, 0),
701 	SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
702 		M98095_091_PWR_EN_OUT, 1, 0),
703 	SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
704 		M98095_091_PWR_EN_OUT, 2, 0),
705 	SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
706 		M98095_091_PWR_EN_OUT, 2, 0),
707 
708 	SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
709 		6, 0, NULL, 0),
710 	SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
711 		7, 0, NULL, 0),
712 
713 	SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
714 		4, 0, NULL, 0),
715 	SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
716 		5, 0, NULL, 0),
717 
718 	SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
719 		3, 0, NULL, 0),
720 
721 	SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
722 		0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
723 	SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
724 		1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
725 
726 	SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
727 		&max98095_extmic_mux),
728 
729 	SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
730 		&max98095_linein_mux),
731 
732 	SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
733 		&max98095_left_hp_mixer_controls[0],
734 		ARRAY_SIZE(max98095_left_hp_mixer_controls)),
735 
736 	SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
737 		&max98095_right_hp_mixer_controls[0],
738 		ARRAY_SIZE(max98095_right_hp_mixer_controls)),
739 
740 	SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
741 		&max98095_left_speaker_mixer_controls[0],
742 		ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
743 
744 	SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
745 		&max98095_right_speaker_mixer_controls[0],
746 		ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
747 
748 	SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
749 	  &max98095_mono_rcv_mixer_controls[0],
750 		ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
751 
752 	SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
753 		&max98095_left_lineout_mixer_controls[0],
754 		ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
755 
756 	SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
757 		&max98095_right_lineout_mixer_controls[0],
758 		ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
759 
760 	SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
761 		&max98095_left_ADC_mixer_controls[0],
762 		ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
763 
764 	SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
765 		&max98095_right_ADC_mixer_controls[0],
766 		ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
767 
768 	SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
769 		5, 0, NULL, 0, max98095_mic_event,
770 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
771 
772 	SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
773 		5, 0, NULL, 0, max98095_mic_event,
774 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
775 
776 	SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
777 		7, 0, NULL, 0, max98095_pga_in1_event,
778 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
779 
780 	SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
781 		7, 0, NULL, 0, max98095_pga_in2_event,
782 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
783 
784 	SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
785 	SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
786 
787 	SND_SOC_DAPM_OUTPUT("HPL"),
788 	SND_SOC_DAPM_OUTPUT("HPR"),
789 	SND_SOC_DAPM_OUTPUT("SPKL"),
790 	SND_SOC_DAPM_OUTPUT("SPKR"),
791 	SND_SOC_DAPM_OUTPUT("RCV"),
792 	SND_SOC_DAPM_OUTPUT("OUT1"),
793 	SND_SOC_DAPM_OUTPUT("OUT2"),
794 	SND_SOC_DAPM_OUTPUT("OUT3"),
795 	SND_SOC_DAPM_OUTPUT("OUT4"),
796 
797 	SND_SOC_DAPM_INPUT("MIC1"),
798 	SND_SOC_DAPM_INPUT("MIC2"),
799 	SND_SOC_DAPM_INPUT("INA1"),
800 	SND_SOC_DAPM_INPUT("INA2"),
801 	SND_SOC_DAPM_INPUT("INB1"),
802 	SND_SOC_DAPM_INPUT("INB2"),
803 };
804 
805 static const struct snd_soc_dapm_route max98095_audio_map[] = {
806 	/* Left headphone output mixer */
807 	{"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
808 	{"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
809 	{"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
810 	{"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
811 	{"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
812 	{"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
813 
814 	/* Right headphone output mixer */
815 	{"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
816 	{"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
817 	{"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
818 	{"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
819 	{"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
820 	{"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
821 
822 	/* Left speaker output mixer */
823 	{"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
824 	{"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
825 	{"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
826 	{"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
827 	{"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
828 	{"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
829 	{"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
830 	{"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
831 
832 	/* Right speaker output mixer */
833 	{"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
834 	{"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
835 	{"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
836 	{"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
837 	{"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
838 	{"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
839 	{"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
840 	{"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
841 
842 	/* Earpiece/Receiver output mixer */
843 	{"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
844 	{"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
845 	{"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
846 	{"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
847 	{"Receiver Mixer", "IN1 Switch", "IN1 Input"},
848 	{"Receiver Mixer", "IN2 Switch", "IN2 Input"},
849 
850 	/* Left Lineout output mixer */
851 	{"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
852 	{"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
853 	{"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
854 	{"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
855 	{"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
856 	{"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
857 
858 	/* Right lineout output mixer */
859 	{"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
860 	{"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
861 	{"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
862 	{"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
863 	{"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
864 	{"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
865 
866 	{"HP Left Out", NULL, "Left Headphone Mixer"},
867 	{"HP Right Out", NULL, "Right Headphone Mixer"},
868 	{"SPK Left Out", NULL, "Left Speaker Mixer"},
869 	{"SPK Right Out", NULL, "Right Speaker Mixer"},
870 	{"RCV Mono Out", NULL, "Receiver Mixer"},
871 	{"LINE Left Out", NULL, "Left Lineout Mixer"},
872 	{"LINE Right Out", NULL, "Right Lineout Mixer"},
873 
874 	{"HPL", NULL, "HP Left Out"},
875 	{"HPR", NULL, "HP Right Out"},
876 	{"SPKL", NULL, "SPK Left Out"},
877 	{"SPKR", NULL, "SPK Right Out"},
878 	{"RCV", NULL, "RCV Mono Out"},
879 	{"OUT1", NULL, "LINE Left Out"},
880 	{"OUT2", NULL, "LINE Right Out"},
881 	{"OUT3", NULL, "LINE Left Out"},
882 	{"OUT4", NULL, "LINE Right Out"},
883 
884 	/* Left ADC input mixer */
885 	{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
886 	{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
887 	{"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
888 	{"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
889 
890 	/* Right ADC input mixer */
891 	{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
892 	{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
893 	{"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
894 	{"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
895 
896 	/* Inputs */
897 	{"ADCL", NULL, "Left ADC Mixer"},
898 	{"ADCR", NULL, "Right ADC Mixer"},
899 
900 	{"IN1 Input", NULL, "INA1"},
901 	{"IN2 Input", NULL, "INA2"},
902 
903 	{"MIC1 Input", NULL, "MIC1"},
904 	{"MIC2 Input", NULL, "MIC2"},
905 };
906 
907 /* codec mclk clock divider coefficients */
908 static const struct {
909 	u32 rate;
910 	u8  sr;
911 } rate_table[] = {
912 	{8000,  0x01},
913 	{11025, 0x02},
914 	{16000, 0x03},
915 	{22050, 0x04},
916 	{24000, 0x05},
917 	{32000, 0x06},
918 	{44100, 0x07},
919 	{48000, 0x08},
920 	{88200, 0x09},
921 	{96000, 0x0A},
922 };
923 
rate_value(int rate,u8 * value)924 static int rate_value(int rate, u8 *value)
925 {
926 	int i;
927 
928 	for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
929 		if (rate_table[i].rate >= rate) {
930 			*value = rate_table[i].sr;
931 			return 0;
932 		}
933 	}
934 	*value = rate_table[0].sr;
935 	return -EINVAL;
936 }
937 
max98095_dai1_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)938 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
939 				   struct snd_pcm_hw_params *params,
940 				   struct snd_soc_dai *dai)
941 {
942 	struct snd_soc_component *component = dai->component;
943 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
944 	struct max98095_cdata *cdata;
945 	unsigned long long ni;
946 	unsigned int rate;
947 	u8 regval;
948 
949 	cdata = &max98095->dai[0];
950 
951 	rate = params_rate(params);
952 
953 	switch (params_width(params)) {
954 	case 16:
955 		snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
956 			M98095_DAI_WS, 0);
957 		break;
958 	case 24:
959 		snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
960 			M98095_DAI_WS, M98095_DAI_WS);
961 		break;
962 	default:
963 		return -EINVAL;
964 	}
965 
966 	if (rate_value(rate, &regval))
967 		return -EINVAL;
968 
969 	snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
970 		M98095_CLKMODE_MASK, regval);
971 	cdata->rate = rate;
972 
973 	/* Configure NI when operating as master */
974 	if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
975 		if (max98095->sysclk == 0) {
976 			dev_err(component->dev, "Invalid system clock frequency\n");
977 			return -EINVAL;
978 		}
979 		ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
980 				* (unsigned long long int)rate;
981 		do_div(ni, (unsigned long long int)max98095->sysclk);
982 		snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
983 			(ni >> 8) & 0x7F);
984 		snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
985 			ni & 0xFF);
986 	}
987 
988 	/* Update sample rate mode */
989 	if (rate < 50000)
990 		snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
991 			M98095_DAI_DHF, 0);
992 	else
993 		snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
994 			M98095_DAI_DHF, M98095_DAI_DHF);
995 
996 	return 0;
997 }
998 
max98095_dai2_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)999 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1000 				   struct snd_pcm_hw_params *params,
1001 				   struct snd_soc_dai *dai)
1002 {
1003 	struct snd_soc_component *component = dai->component;
1004 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1005 	struct max98095_cdata *cdata;
1006 	unsigned long long ni;
1007 	unsigned int rate;
1008 	u8 regval;
1009 
1010 	cdata = &max98095->dai[1];
1011 
1012 	rate = params_rate(params);
1013 
1014 	switch (params_width(params)) {
1015 	case 16:
1016 		snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1017 			M98095_DAI_WS, 0);
1018 		break;
1019 	case 24:
1020 		snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1021 			M98095_DAI_WS, M98095_DAI_WS);
1022 		break;
1023 	default:
1024 		return -EINVAL;
1025 	}
1026 
1027 	if (rate_value(rate, &regval))
1028 		return -EINVAL;
1029 
1030 	snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
1031 		M98095_CLKMODE_MASK, regval);
1032 	cdata->rate = rate;
1033 
1034 	/* Configure NI when operating as master */
1035 	if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1036 		if (max98095->sysclk == 0) {
1037 			dev_err(component->dev, "Invalid system clock frequency\n");
1038 			return -EINVAL;
1039 		}
1040 		ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1041 				* (unsigned long long int)rate;
1042 		do_div(ni, (unsigned long long int)max98095->sysclk);
1043 		snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1044 			(ni >> 8) & 0x7F);
1045 		snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1046 			ni & 0xFF);
1047 	}
1048 
1049 	/* Update sample rate mode */
1050 	if (rate < 50000)
1051 		snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1052 			M98095_DAI_DHF, 0);
1053 	else
1054 		snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1055 			M98095_DAI_DHF, M98095_DAI_DHF);
1056 
1057 	return 0;
1058 }
1059 
max98095_dai3_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1060 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1061 				   struct snd_pcm_hw_params *params,
1062 				   struct snd_soc_dai *dai)
1063 {
1064 	struct snd_soc_component *component = dai->component;
1065 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1066 	struct max98095_cdata *cdata;
1067 	unsigned long long ni;
1068 	unsigned int rate;
1069 	u8 regval;
1070 
1071 	cdata = &max98095->dai[2];
1072 
1073 	rate = params_rate(params);
1074 
1075 	switch (params_width(params)) {
1076 	case 16:
1077 		snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1078 			M98095_DAI_WS, 0);
1079 		break;
1080 	case 24:
1081 		snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1082 			M98095_DAI_WS, M98095_DAI_WS);
1083 		break;
1084 	default:
1085 		return -EINVAL;
1086 	}
1087 
1088 	if (rate_value(rate, &regval))
1089 		return -EINVAL;
1090 
1091 	snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
1092 		M98095_CLKMODE_MASK, regval);
1093 	cdata->rate = rate;
1094 
1095 	/* Configure NI when operating as master */
1096 	if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1097 		if (max98095->sysclk == 0) {
1098 			dev_err(component->dev, "Invalid system clock frequency\n");
1099 			return -EINVAL;
1100 		}
1101 		ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1102 				* (unsigned long long int)rate;
1103 		do_div(ni, (unsigned long long int)max98095->sysclk);
1104 		snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1105 			(ni >> 8) & 0x7F);
1106 		snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1107 			ni & 0xFF);
1108 	}
1109 
1110 	/* Update sample rate mode */
1111 	if (rate < 50000)
1112 		snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1113 			M98095_DAI_DHF, 0);
1114 	else
1115 		snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1116 			M98095_DAI_DHF, M98095_DAI_DHF);
1117 
1118 	return 0;
1119 }
1120 
max98095_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1121 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1122 				   int clk_id, unsigned int freq, int dir)
1123 {
1124 	struct snd_soc_component *component = dai->component;
1125 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1126 
1127 	/* Requested clock frequency is already setup */
1128 	if (freq == max98095->sysclk)
1129 		return 0;
1130 
1131 	if (!IS_ERR(max98095->mclk)) {
1132 		freq = clk_round_rate(max98095->mclk, freq);
1133 		clk_set_rate(max98095->mclk, freq);
1134 	}
1135 
1136 	/* Setup clocks for slave mode, and using the PLL
1137 	 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1138 	 *         0x02 (when master clk is 20MHz to 40MHz)..
1139 	 *         0x03 (when master clk is 40MHz to 60MHz)..
1140 	 */
1141 	if ((freq >= 10000000) && (freq < 20000000)) {
1142 		snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
1143 	} else if ((freq >= 20000000) && (freq < 40000000)) {
1144 		snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
1145 	} else if ((freq >= 40000000) && (freq < 60000000)) {
1146 		snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
1147 	} else {
1148 		dev_err(component->dev, "Invalid master clock frequency\n");
1149 		return -EINVAL;
1150 	}
1151 
1152 	dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1153 
1154 	max98095->sysclk = freq;
1155 	return 0;
1156 }
1157 
max98095_dai1_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1158 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1159 				 unsigned int fmt)
1160 {
1161 	struct snd_soc_component *component = codec_dai->component;
1162 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1163 	struct max98095_cdata *cdata;
1164 	u8 regval = 0;
1165 
1166 	cdata = &max98095->dai[0];
1167 
1168 	if (fmt != cdata->fmt) {
1169 		cdata->fmt = fmt;
1170 
1171 		switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1172 		case SND_SOC_DAIFMT_CBC_CFC:
1173 			/* Consumer mode PLL */
1174 			snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
1175 				0x80);
1176 			snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
1177 				0x00);
1178 			break;
1179 		case SND_SOC_DAIFMT_CBP_CFP:
1180 			/* Set to provider mode */
1181 			regval |= M98095_DAI_MAS;
1182 			break;
1183 		default:
1184 			dev_err(component->dev, "Clock mode unsupported");
1185 			return -EINVAL;
1186 		}
1187 
1188 		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1189 		case SND_SOC_DAIFMT_I2S:
1190 			regval |= M98095_DAI_DLY;
1191 			break;
1192 		case SND_SOC_DAIFMT_LEFT_J:
1193 			break;
1194 		default:
1195 			return -EINVAL;
1196 		}
1197 
1198 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1199 		case SND_SOC_DAIFMT_NB_NF:
1200 			break;
1201 		case SND_SOC_DAIFMT_NB_IF:
1202 			regval |= M98095_DAI_WCI;
1203 			break;
1204 		case SND_SOC_DAIFMT_IB_NF:
1205 			regval |= M98095_DAI_BCI;
1206 			break;
1207 		case SND_SOC_DAIFMT_IB_IF:
1208 			regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1209 			break;
1210 		default:
1211 			return -EINVAL;
1212 		}
1213 
1214 		snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
1215 			M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1216 			M98095_DAI_WCI, regval);
1217 
1218 		snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1219 	}
1220 
1221 	return 0;
1222 }
1223 
max98095_dai2_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1224 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1225 				 unsigned int fmt)
1226 {
1227 	struct snd_soc_component *component = codec_dai->component;
1228 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1229 	struct max98095_cdata *cdata;
1230 	u8 regval = 0;
1231 
1232 	cdata = &max98095->dai[1];
1233 
1234 	if (fmt != cdata->fmt) {
1235 		cdata->fmt = fmt;
1236 
1237 		switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1238 		case SND_SOC_DAIFMT_CBC_CFC:
1239 			/* Consumer mode PLL */
1240 			snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1241 				0x80);
1242 			snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1243 				0x00);
1244 			break;
1245 		case SND_SOC_DAIFMT_CBP_CFP:
1246 			/* Set to provider mode */
1247 			regval |= M98095_DAI_MAS;
1248 			break;
1249 		default:
1250 			dev_err(component->dev, "Clock mode unsupported");
1251 			return -EINVAL;
1252 		}
1253 
1254 		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1255 		case SND_SOC_DAIFMT_I2S:
1256 			regval |= M98095_DAI_DLY;
1257 			break;
1258 		case SND_SOC_DAIFMT_LEFT_J:
1259 			break;
1260 		default:
1261 			return -EINVAL;
1262 		}
1263 
1264 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1265 		case SND_SOC_DAIFMT_NB_NF:
1266 			break;
1267 		case SND_SOC_DAIFMT_NB_IF:
1268 			regval |= M98095_DAI_WCI;
1269 			break;
1270 		case SND_SOC_DAIFMT_IB_NF:
1271 			regval |= M98095_DAI_BCI;
1272 			break;
1273 		case SND_SOC_DAIFMT_IB_IF:
1274 			regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1275 			break;
1276 		default:
1277 			return -EINVAL;
1278 		}
1279 
1280 		snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1281 			M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1282 			M98095_DAI_WCI, regval);
1283 
1284 		snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
1285 			M98095_DAI_BSEL64);
1286 	}
1287 
1288 	return 0;
1289 }
1290 
max98095_dai3_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1291 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1292 				 unsigned int fmt)
1293 {
1294 	struct snd_soc_component *component = codec_dai->component;
1295 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1296 	struct max98095_cdata *cdata;
1297 	u8 regval = 0;
1298 
1299 	cdata = &max98095->dai[2];
1300 
1301 	if (fmt != cdata->fmt) {
1302 		cdata->fmt = fmt;
1303 
1304 		switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1305 		case SND_SOC_DAIFMT_CBC_CFC:
1306 			/* Consumer mode PLL */
1307 			snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1308 				0x80);
1309 			snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1310 				0x00);
1311 			break;
1312 		case SND_SOC_DAIFMT_CBP_CFP:
1313 			/* Set to provider mode */
1314 			regval |= M98095_DAI_MAS;
1315 			break;
1316 		default:
1317 			dev_err(component->dev, "Clock mode unsupported");
1318 			return -EINVAL;
1319 		}
1320 
1321 		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1322 		case SND_SOC_DAIFMT_I2S:
1323 			regval |= M98095_DAI_DLY;
1324 			break;
1325 		case SND_SOC_DAIFMT_LEFT_J:
1326 			break;
1327 		default:
1328 			return -EINVAL;
1329 		}
1330 
1331 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1332 		case SND_SOC_DAIFMT_NB_NF:
1333 			break;
1334 		case SND_SOC_DAIFMT_NB_IF:
1335 			regval |= M98095_DAI_WCI;
1336 			break;
1337 		case SND_SOC_DAIFMT_IB_NF:
1338 			regval |= M98095_DAI_BCI;
1339 			break;
1340 		case SND_SOC_DAIFMT_IB_IF:
1341 			regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1342 			break;
1343 		default:
1344 			return -EINVAL;
1345 		}
1346 
1347 		snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1348 			M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1349 			M98095_DAI_WCI, regval);
1350 
1351 		snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
1352 			M98095_DAI_BSEL64);
1353 	}
1354 
1355 	return 0;
1356 }
1357 
max98095_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1358 static int max98095_set_bias_level(struct snd_soc_component *component,
1359 				   enum snd_soc_bias_level level)
1360 {
1361 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1362 	int ret;
1363 
1364 	switch (level) {
1365 	case SND_SOC_BIAS_ON:
1366 		break;
1367 
1368 	case SND_SOC_BIAS_PREPARE:
1369 		/*
1370 		 * SND_SOC_BIAS_PREPARE is called while preparing for a
1371 		 * transition to ON or away from ON. If current bias_level
1372 		 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1373 		 * away from ON. Disable the clock in that case, otherwise
1374 		 * enable it.
1375 		 */
1376 		if (IS_ERR(max98095->mclk))
1377 			break;
1378 
1379 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1380 			clk_disable_unprepare(max98095->mclk);
1381 		} else {
1382 			ret = clk_prepare_enable(max98095->mclk);
1383 			if (ret)
1384 				return ret;
1385 		}
1386 		break;
1387 
1388 	case SND_SOC_BIAS_STANDBY:
1389 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1390 			ret = regcache_sync(max98095->regmap);
1391 
1392 			if (ret != 0) {
1393 				dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1394 				return ret;
1395 			}
1396 		}
1397 
1398 		snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1399 				M98095_MBEN, M98095_MBEN);
1400 		break;
1401 
1402 	case SND_SOC_BIAS_OFF:
1403 		snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1404 				M98095_MBEN, 0);
1405 		regcache_mark_dirty(max98095->regmap);
1406 		break;
1407 	}
1408 	return 0;
1409 }
1410 
1411 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1412 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1413 
1414 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1415 	.set_sysclk = max98095_dai_set_sysclk,
1416 	.set_fmt = max98095_dai1_set_fmt,
1417 	.hw_params = max98095_dai1_hw_params,
1418 };
1419 
1420 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1421 	.set_sysclk = max98095_dai_set_sysclk,
1422 	.set_fmt = max98095_dai2_set_fmt,
1423 	.hw_params = max98095_dai2_hw_params,
1424 };
1425 
1426 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1427 	.set_sysclk = max98095_dai_set_sysclk,
1428 	.set_fmt = max98095_dai3_set_fmt,
1429 	.hw_params = max98095_dai3_hw_params,
1430 };
1431 
1432 static struct snd_soc_dai_driver max98095_dai[] = {
1433 {
1434 	.name = "HiFi",
1435 	.playback = {
1436 		.stream_name = "HiFi Playback",
1437 		.channels_min = 1,
1438 		.channels_max = 2,
1439 		.rates = MAX98095_RATES,
1440 		.formats = MAX98095_FORMATS,
1441 	},
1442 	.capture = {
1443 		.stream_name = "HiFi Capture",
1444 		.channels_min = 1,
1445 		.channels_max = 2,
1446 		.rates = MAX98095_RATES,
1447 		.formats = MAX98095_FORMATS,
1448 	},
1449 	 .ops = &max98095_dai1_ops,
1450 },
1451 {
1452 	.name = "Aux",
1453 	.playback = {
1454 		.stream_name = "Aux Playback",
1455 		.channels_min = 1,
1456 		.channels_max = 1,
1457 		.rates = MAX98095_RATES,
1458 		.formats = MAX98095_FORMATS,
1459 	},
1460 	.ops = &max98095_dai2_ops,
1461 },
1462 {
1463 	.name = "Voice",
1464 	.playback = {
1465 		.stream_name = "Voice Playback",
1466 		.channels_min = 1,
1467 		.channels_max = 1,
1468 		.rates = MAX98095_RATES,
1469 		.formats = MAX98095_FORMATS,
1470 	},
1471 	.ops = &max98095_dai3_ops,
1472 }
1473 
1474 };
1475 
max98095_get_eq_channel(const char * name)1476 static int max98095_get_eq_channel(const char *name)
1477 {
1478 	if (strcmp(name, "EQ1 Mode") == 0)
1479 		return 0;
1480 	if (strcmp(name, "EQ2 Mode") == 0)
1481 		return 1;
1482 	return -EINVAL;
1483 }
1484 
max98095_put_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1485 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1486 				 struct snd_ctl_elem_value *ucontrol)
1487 {
1488 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1489 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1490 	struct max98095_pdata *pdata = max98095->pdata;
1491 	int channel = max98095_get_eq_channel(kcontrol->id.name);
1492 	struct max98095_cdata *cdata;
1493 	unsigned int sel = ucontrol->value.enumerated.item[0];
1494 	struct max98095_eq_cfg *coef_set;
1495 	int fs, best, best_val, i;
1496 	int regmask, regsave;
1497 
1498 	if (WARN_ON(channel > 1))
1499 		return -EINVAL;
1500 
1501 	if (!pdata || !max98095->eq_textcnt)
1502 		return 0;
1503 
1504 	if (sel >= pdata->eq_cfgcnt)
1505 		return -EINVAL;
1506 
1507 	cdata = &max98095->dai[channel];
1508 	cdata->eq_sel = sel;
1509 	fs = cdata->rate;
1510 
1511 	/* Find the selected configuration with nearest sample rate */
1512 	best = 0;
1513 	best_val = INT_MAX;
1514 	for (i = 0; i < pdata->eq_cfgcnt; i++) {
1515 		if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1516 			abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1517 			best = i;
1518 			best_val = abs(pdata->eq_cfg[i].rate - fs);
1519 		}
1520 	}
1521 
1522 	dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1523 		pdata->eq_cfg[best].name,
1524 		pdata->eq_cfg[best].rate, fs);
1525 
1526 	coef_set = &pdata->eq_cfg[best];
1527 
1528 	regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1529 
1530 	/* Disable filter while configuring, and save current on/off state */
1531 	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1532 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1533 
1534 	mutex_lock(&max98095->lock);
1535 	snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1536 	m98095_eq_band(component, channel, 0, coef_set->band1);
1537 	m98095_eq_band(component, channel, 1, coef_set->band2);
1538 	m98095_eq_band(component, channel, 2, coef_set->band3);
1539 	m98095_eq_band(component, channel, 3, coef_set->band4);
1540 	m98095_eq_band(component, channel, 4, coef_set->band5);
1541 	snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1542 	mutex_unlock(&max98095->lock);
1543 
1544 	/* Restore the original on/off state */
1545 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1546 	return 0;
1547 }
1548 
max98095_get_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1549 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1550 				 struct snd_ctl_elem_value *ucontrol)
1551 {
1552 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1553 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1554 	int channel = max98095_get_eq_channel(kcontrol->id.name);
1555 	struct max98095_cdata *cdata;
1556 
1557 	cdata = &max98095->dai[channel];
1558 	ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1559 
1560 	return 0;
1561 }
1562 
max98095_handle_eq_pdata(struct snd_soc_component * component)1563 static void max98095_handle_eq_pdata(struct snd_soc_component *component)
1564 {
1565 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1566 	struct max98095_pdata *pdata = max98095->pdata;
1567 	struct max98095_eq_cfg *cfg;
1568 	unsigned int cfgcnt;
1569 	int i, j;
1570 	const char **t;
1571 	int ret;
1572 
1573 	struct snd_kcontrol_new controls[] = {
1574 		SOC_ENUM_EXT("EQ1 Mode",
1575 			max98095->eq_enum,
1576 			max98095_get_eq_enum,
1577 			max98095_put_eq_enum),
1578 		SOC_ENUM_EXT("EQ2 Mode",
1579 			max98095->eq_enum,
1580 			max98095_get_eq_enum,
1581 			max98095_put_eq_enum),
1582 	};
1583 
1584 	cfg = pdata->eq_cfg;
1585 	cfgcnt = pdata->eq_cfgcnt;
1586 
1587 	/* Setup an array of texts for the equalizer enum.
1588 	 * This is based on Mark Brown's equalizer driver code.
1589 	 */
1590 	max98095->eq_textcnt = 0;
1591 	max98095->eq_texts = NULL;
1592 	for (i = 0; i < cfgcnt; i++) {
1593 		for (j = 0; j < max98095->eq_textcnt; j++) {
1594 			if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1595 				break;
1596 		}
1597 
1598 		if (j != max98095->eq_textcnt)
1599 			continue;
1600 
1601 		/* Expand the array */
1602 		t = krealloc(max98095->eq_texts,
1603 			     sizeof(char *) * (max98095->eq_textcnt + 1),
1604 			     GFP_KERNEL);
1605 		if (t == NULL)
1606 			continue;
1607 
1608 		/* Store the new entry */
1609 		t[max98095->eq_textcnt] = cfg[i].name;
1610 		max98095->eq_textcnt++;
1611 		max98095->eq_texts = t;
1612 	}
1613 
1614 	/* Now point the soc_enum to .texts array items */
1615 	max98095->eq_enum.texts = max98095->eq_texts;
1616 	max98095->eq_enum.items = max98095->eq_textcnt;
1617 
1618 	ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1619 	if (ret != 0)
1620 		dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1621 }
1622 
1623 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1624 
max98095_get_bq_channel(struct snd_soc_component * component,const char * name)1625 static int max98095_get_bq_channel(struct snd_soc_component *component,
1626 				   const char *name)
1627 {
1628 	int ret;
1629 
1630 	ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
1631 	if (ret < 0)
1632 		dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
1633 	return ret;
1634 }
1635 
max98095_put_bq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1636 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1637 				 struct snd_ctl_elem_value *ucontrol)
1638 {
1639 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1640 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1641 	struct max98095_pdata *pdata = max98095->pdata;
1642 	int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1643 	struct max98095_cdata *cdata;
1644 	unsigned int sel = ucontrol->value.enumerated.item[0];
1645 	struct max98095_biquad_cfg *coef_set;
1646 	int fs, best, best_val, i;
1647 	int regmask, regsave;
1648 
1649 	if (channel < 0)
1650 		return channel;
1651 
1652 	if (!pdata || !max98095->bq_textcnt)
1653 		return 0;
1654 
1655 	if (sel >= pdata->bq_cfgcnt)
1656 		return -EINVAL;
1657 
1658 	cdata = &max98095->dai[channel];
1659 	cdata->bq_sel = sel;
1660 	fs = cdata->rate;
1661 
1662 	/* Find the selected configuration with nearest sample rate */
1663 	best = 0;
1664 	best_val = INT_MAX;
1665 	for (i = 0; i < pdata->bq_cfgcnt; i++) {
1666 		if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1667 			abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1668 			best = i;
1669 			best_val = abs(pdata->bq_cfg[i].rate - fs);
1670 		}
1671 	}
1672 
1673 	dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1674 		pdata->bq_cfg[best].name,
1675 		pdata->bq_cfg[best].rate, fs);
1676 
1677 	coef_set = &pdata->bq_cfg[best];
1678 
1679 	regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1680 
1681 	/* Disable filter while configuring, and save current on/off state */
1682 	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1683 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1684 
1685 	mutex_lock(&max98095->lock);
1686 	snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1687 	m98095_biquad_band(component, channel, 0, coef_set->band1);
1688 	m98095_biquad_band(component, channel, 1, coef_set->band2);
1689 	snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1690 	mutex_unlock(&max98095->lock);
1691 
1692 	/* Restore the original on/off state */
1693 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1694 	return 0;
1695 }
1696 
max98095_get_bq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1697 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1698 				 struct snd_ctl_elem_value *ucontrol)
1699 {
1700 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1701 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1702 	int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1703 	struct max98095_cdata *cdata;
1704 
1705 	if (channel < 0)
1706 		return channel;
1707 
1708 	cdata = &max98095->dai[channel];
1709 	ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1710 
1711 	return 0;
1712 }
1713 
max98095_handle_bq_pdata(struct snd_soc_component * component)1714 static void max98095_handle_bq_pdata(struct snd_soc_component *component)
1715 {
1716 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1717 	struct max98095_pdata *pdata = max98095->pdata;
1718 	struct max98095_biquad_cfg *cfg;
1719 	unsigned int cfgcnt;
1720 	int i, j;
1721 	const char **t;
1722 	int ret;
1723 
1724 	struct snd_kcontrol_new controls[] = {
1725 		SOC_ENUM_EXT((char *)bq_mode_name[0],
1726 			max98095->bq_enum,
1727 			max98095_get_bq_enum,
1728 			max98095_put_bq_enum),
1729 		SOC_ENUM_EXT((char *)bq_mode_name[1],
1730 			max98095->bq_enum,
1731 			max98095_get_bq_enum,
1732 			max98095_put_bq_enum),
1733 	};
1734 	BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
1735 
1736 	cfg = pdata->bq_cfg;
1737 	cfgcnt = pdata->bq_cfgcnt;
1738 
1739 	/* Setup an array of texts for the biquad enum.
1740 	 * This is based on Mark Brown's equalizer driver code.
1741 	 */
1742 	max98095->bq_textcnt = 0;
1743 	max98095->bq_texts = NULL;
1744 	for (i = 0; i < cfgcnt; i++) {
1745 		for (j = 0; j < max98095->bq_textcnt; j++) {
1746 			if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1747 				break;
1748 		}
1749 
1750 		if (j != max98095->bq_textcnt)
1751 			continue;
1752 
1753 		/* Expand the array */
1754 		t = krealloc(max98095->bq_texts,
1755 			     sizeof(char *) * (max98095->bq_textcnt + 1),
1756 			     GFP_KERNEL);
1757 		if (t == NULL)
1758 			continue;
1759 
1760 		/* Store the new entry */
1761 		t[max98095->bq_textcnt] = cfg[i].name;
1762 		max98095->bq_textcnt++;
1763 		max98095->bq_texts = t;
1764 	}
1765 
1766 	/* Now point the soc_enum to .texts array items */
1767 	max98095->bq_enum.texts = max98095->bq_texts;
1768 	max98095->bq_enum.items = max98095->bq_textcnt;
1769 
1770 	ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1771 	if (ret != 0)
1772 		dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
1773 }
1774 
max98095_handle_pdata(struct snd_soc_component * component)1775 static void max98095_handle_pdata(struct snd_soc_component *component)
1776 {
1777 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1778 	struct max98095_pdata *pdata = max98095->pdata;
1779 	u8 regval = 0;
1780 
1781 	if (!pdata) {
1782 		dev_dbg(component->dev, "No platform data\n");
1783 		return;
1784 	}
1785 
1786 	/* Configure mic for analog/digital mic mode */
1787 	if (pdata->digmic_left_mode)
1788 		regval |= M98095_DIGMIC_L;
1789 
1790 	if (pdata->digmic_right_mode)
1791 		regval |= M98095_DIGMIC_R;
1792 
1793 	snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
1794 
1795 	/* Configure equalizers */
1796 	if (pdata->eq_cfgcnt)
1797 		max98095_handle_eq_pdata(component);
1798 
1799 	/* Configure bi-quad filters */
1800 	if (pdata->bq_cfgcnt)
1801 		max98095_handle_bq_pdata(component);
1802 }
1803 
max98095_report_jack(int irq,void * data)1804 static irqreturn_t max98095_report_jack(int irq, void *data)
1805 {
1806 	struct snd_soc_component *component = data;
1807 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1808 	unsigned int value;
1809 	int hp_report = 0;
1810 	int mic_report = 0;
1811 
1812 	/* Read the Jack Status Register */
1813 	value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
1814 
1815 	/* If ddone is not set, then detection isn't finished yet */
1816 	if ((value & M98095_DDONE) == 0)
1817 		return IRQ_NONE;
1818 
1819 	/* if hp, check its bit, and if set, clear it */
1820 	if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
1821 		max98095->headphone_jack)
1822 		hp_report |= SND_JACK_HEADPHONE;
1823 
1824 	/* if mic, check its bit, and if set, clear it */
1825 	if ((value & M98095_MIC_IN) && max98095->mic_jack)
1826 		mic_report |= SND_JACK_MICROPHONE;
1827 
1828 	if (max98095->headphone_jack == max98095->mic_jack) {
1829 		snd_soc_jack_report(max98095->headphone_jack,
1830 					hp_report | mic_report,
1831 					SND_JACK_HEADSET);
1832 	} else {
1833 		if (max98095->headphone_jack)
1834 			snd_soc_jack_report(max98095->headphone_jack,
1835 					hp_report, SND_JACK_HEADPHONE);
1836 		if (max98095->mic_jack)
1837 			snd_soc_jack_report(max98095->mic_jack,
1838 					mic_report, SND_JACK_MICROPHONE);
1839 	}
1840 
1841 	return IRQ_HANDLED;
1842 }
1843 
max98095_jack_detect_enable(struct snd_soc_component * component)1844 static int max98095_jack_detect_enable(struct snd_soc_component *component)
1845 {
1846 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1847 	int ret = 0;
1848 	int detect_enable = M98095_JDEN;
1849 	unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
1850 
1851 	if (max98095->pdata->jack_detect_pin5en)
1852 		detect_enable |= M98095_PIN5EN;
1853 
1854 	if (max98095->pdata->jack_detect_delay)
1855 		slew = max98095->pdata->jack_detect_delay;
1856 
1857 	ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
1858 	if (ret < 0) {
1859 		dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1860 		return ret;
1861 	}
1862 
1863 	/* configure auto detection to be enabled */
1864 	ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
1865 	if (ret < 0) {
1866 		dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1867 		return ret;
1868 	}
1869 
1870 	return ret;
1871 }
1872 
max98095_jack_detect_disable(struct snd_soc_component * component)1873 static int max98095_jack_detect_disable(struct snd_soc_component *component)
1874 {
1875 	int ret = 0;
1876 
1877 	/* configure auto detection to be disabled */
1878 	ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
1879 	if (ret < 0) {
1880 		dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1881 		return ret;
1882 	}
1883 
1884 	return ret;
1885 }
1886 
max98095_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack)1887 int max98095_jack_detect(struct snd_soc_component *component,
1888 	struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
1889 {
1890 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1891 	struct i2c_client *client = to_i2c_client(component->dev);
1892 	int ret = 0;
1893 
1894 	max98095->headphone_jack = hp_jack;
1895 	max98095->mic_jack = mic_jack;
1896 
1897 	/* only progress if we have at least 1 jack pointer */
1898 	if (!hp_jack && !mic_jack)
1899 		return -EINVAL;
1900 
1901 	max98095_jack_detect_enable(component);
1902 
1903 	/* enable interrupts for headphone jack detection */
1904 	ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
1905 		M98095_IDDONE, M98095_IDDONE);
1906 	if (ret < 0) {
1907 		dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
1908 		return ret;
1909 	}
1910 
1911 	max98095_report_jack(client->irq, component);
1912 	return 0;
1913 }
1914 EXPORT_SYMBOL_GPL(max98095_jack_detect);
1915 
1916 #ifdef CONFIG_PM
max98095_suspend(struct snd_soc_component * component)1917 static int max98095_suspend(struct snd_soc_component *component)
1918 {
1919 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1920 
1921 	if (max98095->headphone_jack || max98095->mic_jack)
1922 		max98095_jack_detect_disable(component);
1923 
1924 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1925 
1926 	return 0;
1927 }
1928 
max98095_resume(struct snd_soc_component * component)1929 static int max98095_resume(struct snd_soc_component *component)
1930 {
1931 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1932 	struct i2c_client *client = to_i2c_client(component->dev);
1933 
1934 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1935 
1936 	if (max98095->headphone_jack || max98095->mic_jack) {
1937 		max98095_jack_detect_enable(component);
1938 		max98095_report_jack(client->irq, component);
1939 	}
1940 
1941 	return 0;
1942 }
1943 #else
1944 #define max98095_suspend NULL
1945 #define max98095_resume NULL
1946 #endif
1947 
max98095_reset(struct snd_soc_component * component)1948 static int max98095_reset(struct snd_soc_component *component)
1949 {
1950 	int i, ret;
1951 
1952 	/* Gracefully reset the DSP core and the codec hardware
1953 	 * in a proper sequence */
1954 	ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
1955 	if (ret < 0) {
1956 		dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
1957 		return ret;
1958 	}
1959 
1960 	ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
1961 	if (ret < 0) {
1962 		dev_err(component->dev, "Failed to reset component: %d\n", ret);
1963 		return ret;
1964 	}
1965 
1966 	/* Reset to hardware default for registers, as there is not
1967 	 * a soft reset hardware control register */
1968 	for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1969 		ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
1970 		if (ret < 0) {
1971 			dev_err(component->dev, "Failed to reset: %d\n", ret);
1972 			return ret;
1973 		}
1974 	}
1975 
1976 	return ret;
1977 }
1978 
max98095_probe(struct snd_soc_component * component)1979 static int max98095_probe(struct snd_soc_component *component)
1980 {
1981 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1982 	struct max98095_cdata *cdata;
1983 	struct i2c_client *client;
1984 	int ret = 0;
1985 
1986 	max98095->mclk = devm_clk_get(component->dev, "mclk");
1987 	if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
1988 		return -EPROBE_DEFER;
1989 
1990 	/* reset the codec, the DSP core, and disable all interrupts */
1991 	max98095_reset(component);
1992 
1993 	client = to_i2c_client(component->dev);
1994 
1995 	/* initialize private data */
1996 
1997 	max98095->sysclk = (unsigned)-1;
1998 	max98095->eq_textcnt = 0;
1999 	max98095->bq_textcnt = 0;
2000 
2001 	cdata = &max98095->dai[0];
2002 	cdata->rate = (unsigned)-1;
2003 	cdata->fmt  = (unsigned)-1;
2004 	cdata->eq_sel = 0;
2005 	cdata->bq_sel = 0;
2006 
2007 	cdata = &max98095->dai[1];
2008 	cdata->rate = (unsigned)-1;
2009 	cdata->fmt  = (unsigned)-1;
2010 	cdata->eq_sel = 0;
2011 	cdata->bq_sel = 0;
2012 
2013 	cdata = &max98095->dai[2];
2014 	cdata->rate = (unsigned)-1;
2015 	cdata->fmt  = (unsigned)-1;
2016 	cdata->eq_sel = 0;
2017 	cdata->bq_sel = 0;
2018 
2019 	max98095->lin_state = 0;
2020 	max98095->mic1pre = 0;
2021 	max98095->mic2pre = 0;
2022 
2023 	if (client->irq) {
2024 		/* register an audio interrupt */
2025 		ret = request_threaded_irq(client->irq, NULL,
2026 			max98095_report_jack,
2027 			IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
2028 			IRQF_ONESHOT, "max98095", component);
2029 		if (ret) {
2030 			dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
2031 			goto err_access;
2032 		}
2033 	}
2034 
2035 	ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
2036 	if (ret < 0) {
2037 		dev_err(component->dev, "Failure reading hardware revision: %d\n",
2038 			ret);
2039 		goto err_irq;
2040 	}
2041 	dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2042 
2043 	snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
2044 
2045 	snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
2046 		M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2047 
2048 	snd_soc_component_write(component, M98095_049_MIX_DAC_M,
2049 		M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2050 
2051 	snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2052 	snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2053 	snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
2054 
2055 	snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
2056 		M98095_S1NORMAL|M98095_SDATA);
2057 
2058 	snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
2059 		M98095_S2NORMAL|M98095_SDATA);
2060 
2061 	snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
2062 		M98095_S3NORMAL|M98095_SDATA);
2063 
2064 	max98095_handle_pdata(component);
2065 
2066 	/* take the codec out of the shut down */
2067 	snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
2068 		M98095_SHDNRUN);
2069 
2070 	return 0;
2071 
2072 err_irq:
2073 	if (client->irq)
2074 		free_irq(client->irq, component);
2075 err_access:
2076 	return ret;
2077 }
2078 
max98095_remove(struct snd_soc_component * component)2079 static void max98095_remove(struct snd_soc_component *component)
2080 {
2081 	struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
2082 	struct i2c_client *client = to_i2c_client(component->dev);
2083 
2084 	if (max98095->headphone_jack || max98095->mic_jack)
2085 		max98095_jack_detect_disable(component);
2086 
2087 	if (client->irq)
2088 		free_irq(client->irq, component);
2089 }
2090 
2091 static const struct snd_soc_component_driver soc_component_dev_max98095 = {
2092 	.probe			= max98095_probe,
2093 	.remove			= max98095_remove,
2094 	.suspend		= max98095_suspend,
2095 	.resume			= max98095_resume,
2096 	.set_bias_level		= max98095_set_bias_level,
2097 	.controls		= max98095_snd_controls,
2098 	.num_controls		= ARRAY_SIZE(max98095_snd_controls),
2099 	.dapm_widgets		= max98095_dapm_widgets,
2100 	.num_dapm_widgets	= ARRAY_SIZE(max98095_dapm_widgets),
2101 	.dapm_routes		= max98095_audio_map,
2102 	.num_dapm_routes	= ARRAY_SIZE(max98095_audio_map),
2103 	.idle_bias_on		= 1,
2104 	.use_pmdown_time	= 1,
2105 	.endianness		= 1,
2106 };
2107 
2108 static const struct i2c_device_id max98095_i2c_id[] = {
2109 	{ "max98095", MAX98095 },
2110 	{ }
2111 };
2112 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2113 
max98095_i2c_probe(struct i2c_client * i2c)2114 static int max98095_i2c_probe(struct i2c_client *i2c)
2115 {
2116 	struct max98095_priv *max98095;
2117 	int ret;
2118 	const struct i2c_device_id *id;
2119 
2120 	max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2121 				GFP_KERNEL);
2122 	if (max98095 == NULL)
2123 		return -ENOMEM;
2124 
2125 	mutex_init(&max98095->lock);
2126 
2127 	max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2128 	if (IS_ERR(max98095->regmap)) {
2129 		ret = PTR_ERR(max98095->regmap);
2130 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2131 		return ret;
2132 	}
2133 
2134 	id = i2c_match_id(max98095_i2c_id, i2c);
2135 	max98095->devtype = id->driver_data;
2136 	i2c_set_clientdata(i2c, max98095);
2137 	max98095->pdata = i2c->dev.platform_data;
2138 
2139 	ret = devm_snd_soc_register_component(&i2c->dev,
2140 				     &soc_component_dev_max98095,
2141 				     max98095_dai, ARRAY_SIZE(max98095_dai));
2142 	return ret;
2143 }
2144 
2145 #ifdef CONFIG_OF
2146 static const struct of_device_id max98095_of_match[] = {
2147 	{ .compatible = "maxim,max98095", },
2148 	{ }
2149 };
2150 MODULE_DEVICE_TABLE(of, max98095_of_match);
2151 #endif
2152 
2153 static struct i2c_driver max98095_i2c_driver = {
2154 	.driver = {
2155 		.name = "max98095",
2156 		.of_match_table = of_match_ptr(max98095_of_match),
2157 	},
2158 	.probe = max98095_i2c_probe,
2159 	.id_table = max98095_i2c_id,
2160 };
2161 
2162 module_i2c_driver(max98095_i2c_driver);
2163 
2164 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2165 MODULE_AUTHOR("Peter Hsiang");
2166 MODULE_LICENSE("GPL");
2167