1 /****************************************************************************\
2 *
3 *  File Name      atomfirmware.h
4 *  Project        This is an interface header file between atombios and OS GPU drivers for SoC15 products
5 *
6 *  Description    header file of general definitions for OS and pre-OS video drivers
7 *
8 *  Copyright 2014 Advanced Micro Devices, Inc.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 \****************************************************************************/
28 
29 /*IMPORTANT NOTES
30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33 */
34 
35 #ifndef _ATOMFIRMWARE_H_
36 #define _ATOMFIRMWARE_H_
37 
38 enum  atom_bios_header_version_def{
39   ATOM_MAJOR_VERSION        =0x0003,
40   ATOM_MINOR_VERSION        =0x0003,
41 };
42 
43 #ifdef _H2INC
44   #ifndef uint32_t
45     typedef unsigned long uint32_t;
46   #endif
47 
48   #ifndef uint16_t
49     typedef unsigned short uint16_t;
50   #endif
51 
52   #ifndef uint8_t
53     typedef unsigned char uint8_t;
54   #endif
55 #endif
56 
57 enum atom_crtc_def{
58   ATOM_CRTC1      =0,
59   ATOM_CRTC2      =1,
60   ATOM_CRTC3      =2,
61   ATOM_CRTC4      =3,
62   ATOM_CRTC5      =4,
63   ATOM_CRTC6      =5,
64   ATOM_CRTC_INVALID  =0xff,
65 };
66 
67 enum atom_ppll_def{
68   ATOM_PPLL0          =2,
69   ATOM_GCK_DFS        =8,
70   ATOM_FCH_CLK        =9,
71   ATOM_DP_DTO         =11,
72   ATOM_COMBOPHY_PLL0  =20,
73   ATOM_COMBOPHY_PLL1  =21,
74   ATOM_COMBOPHY_PLL2  =22,
75   ATOM_COMBOPHY_PLL3  =23,
76   ATOM_COMBOPHY_PLL4  =24,
77   ATOM_COMBOPHY_PLL5  =25,
78   ATOM_PPLL_INVALID   =0xff,
79 };
80 
81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82 enum atom_dig_def{
83   ASIC_INT_DIG1_ENCODER_ID  =0x03,
84   ASIC_INT_DIG2_ENCODER_ID  =0x09,
85   ASIC_INT_DIG3_ENCODER_ID  =0x0a,
86   ASIC_INT_DIG4_ENCODER_ID  =0x0b,
87   ASIC_INT_DIG5_ENCODER_ID  =0x0c,
88   ASIC_INT_DIG6_ENCODER_ID  =0x0d,
89   ASIC_INT_DIG7_ENCODER_ID  =0x0e,
90 };
91 
92 //ucEncoderMode
93 enum atom_encode_mode_def
94 {
95   ATOM_ENCODER_MODE_DP          =0,
96   ATOM_ENCODER_MODE_DP_SST      =0,
97   ATOM_ENCODER_MODE_LVDS        =1,
98   ATOM_ENCODER_MODE_DVI         =2,
99   ATOM_ENCODER_MODE_HDMI        =3,
100   ATOM_ENCODER_MODE_DP_AUDIO    =5,
101   ATOM_ENCODER_MODE_DP_MST      =5,
102   ATOM_ENCODER_MODE_CRT         =15,
103   ATOM_ENCODER_MODE_DVO         =16,
104 };
105 
106 enum atom_encoder_refclk_src_def{
107   ENCODER_REFCLK_SRC_P1PLL      =0,
108   ENCODER_REFCLK_SRC_P2PLL      =1,
109   ENCODER_REFCLK_SRC_P3PLL      =2,
110   ENCODER_REFCLK_SRC_EXTCLK     =3,
111   ENCODER_REFCLK_SRC_INVALID    =0xff,
112 };
113 
114 enum atom_scaler_def{
115   ATOM_SCALER_DISABLE          =0,  /*scaler bypass mode, auto-center & no replication*/
116   ATOM_SCALER_CENTER           =1,  //For Fudo, it's bypass and auto-center & auto replication
117   ATOM_SCALER_EXPANSION        =2,  /*scaler expansion by 2 tap alpha blending mode*/
118 };
119 
120 enum atom_operation_def{
121   ATOM_DISABLE             = 0,
122   ATOM_ENABLE              = 1,
123   ATOM_INIT                = 7,
124   ATOM_GET_STATUS          = 8,
125 };
126 
127 enum atom_embedded_display_op_def{
128   ATOM_LCD_BL_OFF                = 2,
129   ATOM_LCD_BL_OM                 = 3,
130   ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131   ATOM_LCD_SELFTEST_START        = 5,
132   ATOM_LCD_SELFTEST_STOP         = 6,
133 };
134 
135 enum atom_spread_spectrum_mode{
136   ATOM_SS_CENTER_OR_DOWN_MODE_MASK  = 0x01,
137   ATOM_SS_DOWN_SPREAD_MODE          = 0x00,
138   ATOM_SS_CENTRE_SPREAD_MODE        = 0x01,
139   ATOM_INT_OR_EXT_SS_MASK           = 0x02,
140   ATOM_INTERNAL_SS_MASK             = 0x00,
141   ATOM_EXTERNAL_SS_MASK             = 0x02,
142 };
143 
144 /* define panel bit per color  */
145 enum atom_panel_bit_per_color{
146   PANEL_BPC_UNDEFINE     =0x00,
147   PANEL_6BIT_PER_COLOR   =0x01,
148   PANEL_8BIT_PER_COLOR   =0x02,
149   PANEL_10BIT_PER_COLOR  =0x03,
150   PANEL_12BIT_PER_COLOR  =0x04,
151   PANEL_16BIT_PER_COLOR  =0x05,
152 };
153 
154 //ucVoltageType
155 enum atom_voltage_type
156 {
157   VOLTAGE_TYPE_VDDC = 1,
158   VOLTAGE_TYPE_MVDDC = 2,
159   VOLTAGE_TYPE_MVDDQ = 3,
160   VOLTAGE_TYPE_VDDCI = 4,
161   VOLTAGE_TYPE_VDDGFX = 5,
162   VOLTAGE_TYPE_PCC = 6,
163   VOLTAGE_TYPE_MVPP = 7,
164   VOLTAGE_TYPE_LEDDPM = 8,
165   VOLTAGE_TYPE_PCC_MVDD = 9,
166   VOLTAGE_TYPE_PCIE_VDDC = 10,
167   VOLTAGE_TYPE_PCIE_VDDR = 11,
168   VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169   VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170   VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171   VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172   VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173   VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174   VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175   VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176   VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177   VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178 };
179 
180 enum atom_dgpu_vram_type {
181   ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182   ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
183   ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184   ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185   ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80,
186 };
187 
188 enum atom_dp_vs_preemph_def{
189   DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
190   DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
191   DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
192   DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
193   DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
194   DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
195   DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
196   DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
197   DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
198   DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
199 };
200 
201 #define BIOS_ATOM_PREFIX   "ATOMBIOS"
202 #define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
203 #define BIOS_STRING_LENGTH 43
204 
205 /*
206 enum atom_string_def{
207 asic_bus_type_pcie_string = "PCI_EXPRESS",
208 atom_fire_gl_string       = "FGL",
209 atom_bios_string          = "ATOM"
210 };
211 */
212 
213 #pragma pack(1)                          /* BIOS data must use byte aligment*/
214 
215 enum atombios_image_offset{
216   OFFSET_TO_ATOM_ROM_HEADER_POINTER          = 0x00000048,
217   OFFSET_TO_ATOM_ROM_IMAGE_SIZE              = 0x00000002,
218   OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       = 0x94,
219   MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      = 20,  /*including the terminator 0x0!*/
220   OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   = 0x2f,
221   OFFSET_TO_GET_ATOMBIOS_STRING_START        = 0x6e,
222   OFFSET_TO_VBIOS_PART_NUMBER                = 0x80,
223   OFFSET_TO_VBIOS_DATE                       = 0x50,
224 };
225 
226 /****************************************************************************
227 * Common header for all tables (Data table, Command function).
228 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
229 * And the pointer actually points to this header.
230 ****************************************************************************/
231 
232 struct atom_common_table_header
233 {
234   uint16_t structuresize;
235   uint8_t  format_revision;   //mainly used for a hw function, when the parser is not backward compatible
236   uint8_t  content_revision;  //change it when a data table has a structure change, or a hw function has a input/output parameter change
237 };
238 
239 /****************************************************************************
240 * Structure stores the ROM header.
241 ****************************************************************************/
242 struct atom_rom_header_v2_2
243 {
244   struct atom_common_table_header table_header;
245   uint8_t  atom_bios_string[4];        //enum atom_string_def atom_bios_string;     //Signature to distinguish between Atombios and non-atombios,
246   uint16_t bios_segment_address;
247   uint16_t protectedmodeoffset;
248   uint16_t configfilenameoffset;
249   uint16_t crc_block_offset;
250   uint16_t vbios_bootupmessageoffset;
251   uint16_t int10_offset;
252   uint16_t pcibusdevinitcode;
253   uint16_t iobaseaddress;
254   uint16_t subsystem_vendor_id;
255   uint16_t subsystem_id;
256   uint16_t pci_info_offset;
257   uint16_t masterhwfunction_offset;      //Offest for SW to get all command function offsets, Don't change the position
258   uint16_t masterdatatable_offset;       //Offest for SW to get all data table offsets, Don't change the position
259   uint16_t reserved;
260   uint32_t pspdirtableoffset;
261 };
262 
263 /*==============================hw function portion======================================================================*/
264 
265 
266 /****************************************************************************
267 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time
268 * The real functionality of each function is associated with the parameter structure version when defined
269 * For all internal cmd function definitions, please reference to atomstruct.h
270 ****************************************************************************/
271 struct atom_master_list_of_command_functions_v2_1{
272   uint16_t asic_init;                   //Function
273   uint16_t cmd_function1;               //used as an internal one
274   uint16_t cmd_function2;               //used as an internal one
275   uint16_t cmd_function3;               //used as an internal one
276   uint16_t digxencodercontrol;          //Function
277   uint16_t cmd_function5;               //used as an internal one
278   uint16_t cmd_function6;               //used as an internal one
279   uint16_t cmd_function7;               //used as an internal one
280   uint16_t cmd_function8;               //used as an internal one
281   uint16_t cmd_function9;               //used as an internal one
282   uint16_t setengineclock;              //Function
283   uint16_t setmemoryclock;              //Function
284   uint16_t setpixelclock;               //Function
285   uint16_t enabledisppowergating;       //Function
286   uint16_t cmd_function14;              //used as an internal one
287   uint16_t cmd_function15;              //used as an internal one
288   uint16_t cmd_function16;              //used as an internal one
289   uint16_t cmd_function17;              //used as an internal one
290   uint16_t cmd_function18;              //used as an internal one
291   uint16_t cmd_function19;              //used as an internal one
292   uint16_t cmd_function20;              //used as an internal one
293   uint16_t cmd_function21;              //used as an internal one
294   uint16_t cmd_function22;              //used as an internal one
295   uint16_t cmd_function23;              //used as an internal one
296   uint16_t cmd_function24;              //used as an internal one
297   uint16_t cmd_function25;              //used as an internal one
298   uint16_t cmd_function26;              //used as an internal one
299   uint16_t cmd_function27;              //used as an internal one
300   uint16_t cmd_function28;              //used as an internal one
301   uint16_t cmd_function29;              //used as an internal one
302   uint16_t cmd_function30;              //used as an internal one
303   uint16_t cmd_function31;              //used as an internal one
304   uint16_t cmd_function32;              //used as an internal one
305   uint16_t cmd_function33;              //used as an internal one
306   uint16_t blankcrtc;                   //Function
307   uint16_t enablecrtc;                  //Function
308   uint16_t cmd_function36;              //used as an internal one
309   uint16_t cmd_function37;              //used as an internal one
310   uint16_t cmd_function38;              //used as an internal one
311   uint16_t cmd_function39;              //used as an internal one
312   uint16_t cmd_function40;              //used as an internal one
313   uint16_t getsmuclockinfo;             //Function
314   uint16_t selectcrtc_source;           //Function
315   uint16_t cmd_function43;              //used as an internal one
316   uint16_t cmd_function44;              //used as an internal one
317   uint16_t cmd_function45;              //used as an internal one
318   uint16_t setdceclock;                 //Function
319   uint16_t getmemoryclock;              //Function
320   uint16_t getengineclock;              //Function
321   uint16_t setcrtc_usingdtdtiming;      //Function
322   uint16_t externalencodercontrol;      //Function
323   uint16_t cmd_function51;              //used as an internal one
324   uint16_t cmd_function52;              //used as an internal one
325   uint16_t cmd_function53;              //used as an internal one
326   uint16_t processi2cchanneltransaction;//Function
327   uint16_t cmd_function55;              //used as an internal one
328   uint16_t cmd_function56;              //used as an internal one
329   uint16_t cmd_function57;              //used as an internal one
330   uint16_t cmd_function58;              //used as an internal one
331   uint16_t cmd_function59;              //used as an internal one
332   uint16_t computegpuclockparam;        //Function
333   uint16_t cmd_function61;              //used as an internal one
334   uint16_t cmd_function62;              //used as an internal one
335   uint16_t dynamicmemorysettings;       //Function function
336   uint16_t memorytraining;              //Function function
337   uint16_t cmd_function65;              //used as an internal one
338   uint16_t cmd_function66;              //used as an internal one
339   uint16_t setvoltage;                  //Function
340   uint16_t cmd_function68;              //used as an internal one
341   uint16_t readefusevalue;              //Function
342   uint16_t cmd_function70;              //used as an internal one
343   uint16_t cmd_function71;              //used as an internal one
344   uint16_t cmd_function72;              //used as an internal one
345   uint16_t cmd_function73;              //used as an internal one
346   uint16_t cmd_function74;              //used as an internal one
347   uint16_t cmd_function75;              //used as an internal one
348   uint16_t dig1transmittercontrol;      //Function
349   uint16_t cmd_function77;              //used as an internal one
350   uint16_t processauxchanneltransaction;//Function
351   uint16_t cmd_function79;              //used as an internal one
352   uint16_t getvoltageinfo;              //Function
353 };
354 
355 struct atom_master_command_function_v2_1
356 {
357   struct atom_common_table_header  table_header;
358   struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
359 };
360 
361 /****************************************************************************
362 * Structures used in every command function
363 ****************************************************************************/
364 struct atom_function_attribute
365 {
366   uint16_t  ws_in_bytes:8;            //[7:0]=Size of workspace in Bytes (in multiple of a dword),
367   uint16_t  ps_in_bytes:7;            //[14:8]=Size of parameter space in Bytes (multiple of a dword),
368   uint16_t  updated_by_util:1;        //[15]=flag to indicate the function is updated by util
369 };
370 
371 
372 /****************************************************************************
373 * Common header for all hw functions.
374 * Every function pointed by _master_list_of_hw_function has this common header.
375 * And the pointer actually points to this header.
376 ****************************************************************************/
377 struct atom_rom_hw_function_header
378 {
379   struct atom_common_table_header func_header;
380   struct atom_function_attribute func_attrib;
381 };
382 
383 
384 /*==============================sw data table portion======================================================================*/
385 /****************************************************************************
386 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
387 * The real name of each table is given when its data structure version is defined
388 ****************************************************************************/
389 struct atom_master_list_of_data_tables_v2_1{
390   uint16_t utilitypipeline;               /* Offest for the utility to get parser info,Don't change this position!*/
391   uint16_t multimedia_info;
392   uint16_t smc_dpm_info;
393   uint16_t sw_datatable3;
394   uint16_t firmwareinfo;                  /* Shared by various SW components */
395   uint16_t sw_datatable5;
396   uint16_t lcd_info;                      /* Shared by various SW components */
397   uint16_t sw_datatable7;
398   uint16_t smu_info;
399   uint16_t sw_datatable9;
400   uint16_t sw_datatable10;
401   uint16_t vram_usagebyfirmware;          /* Shared by various SW components */
402   uint16_t gpio_pin_lut;                  /* Shared by various SW components */
403   uint16_t sw_datatable13;
404   uint16_t gfx_info;
405   uint16_t powerplayinfo;                 /* Shared by various SW components */
406   uint16_t sw_datatable16;
407   uint16_t sw_datatable17;
408   uint16_t sw_datatable18;
409   uint16_t sw_datatable19;
410   uint16_t sw_datatable20;
411   uint16_t sw_datatable21;
412   uint16_t displayobjectinfo;             /* Shared by various SW components */
413   uint16_t indirectioaccess;			  /* used as an internal one */
414   uint16_t umc_info;                      /* Shared by various SW components */
415   uint16_t sw_datatable25;
416   uint16_t sw_datatable26;
417   uint16_t dce_info;                      /* Shared by various SW components */
418   uint16_t vram_info;                     /* Shared by various SW components */
419   uint16_t sw_datatable29;
420   uint16_t integratedsysteminfo;          /* Shared by various SW components */
421   uint16_t asic_profiling_info;           /* Shared by various SW components */
422   uint16_t voltageobject_info;            /* shared by various SW components */
423   uint16_t sw_datatable33;
424   uint16_t sw_datatable34;
425 };
426 
427 
428 struct atom_master_data_table_v2_1
429 {
430   struct atom_common_table_header table_header;
431   struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
432 };
433 
434 
435 struct atom_dtd_format
436 {
437   uint16_t  pixclk;
438   uint16_t  h_active;
439   uint16_t  h_blanking_time;
440   uint16_t  v_active;
441   uint16_t  v_blanking_time;
442   uint16_t  h_sync_offset;
443   uint16_t  h_sync_width;
444   uint16_t  v_sync_offset;
445   uint16_t  v_syncwidth;
446   uint16_t  reserved;
447   uint16_t  reserved0;
448   uint8_t   h_border;
449   uint8_t   v_border;
450   uint16_t  miscinfo;
451   uint8_t   atom_mode_id;
452   uint8_t   refreshrate;
453 };
454 
455 /* atom_dtd_format.modemiscinfo defintion */
456 enum atom_dtd_format_modemiscinfo{
457   ATOM_HSYNC_POLARITY    = 0x0002,
458   ATOM_VSYNC_POLARITY    = 0x0004,
459   ATOM_H_REPLICATIONBY2  = 0x0010,
460   ATOM_V_REPLICATIONBY2  = 0x0020,
461   ATOM_INTERLACE         = 0x0080,
462   ATOM_COMPOSITESYNC     = 0x0040,
463 };
464 
465 
466 /* utilitypipeline
467  * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
468  * the location of it can't change
469 */
470 
471 
472 /*
473   ***************************************************************************
474     Data Table firmwareinfo  structure
475   ***************************************************************************
476 */
477 
478 struct atom_firmware_info_v3_1
479 {
480   struct atom_common_table_header table_header;
481   uint32_t firmware_revision;
482   uint32_t bootup_sclk_in10khz;
483   uint32_t bootup_mclk_in10khz;
484   uint32_t firmware_capability;             // enum atombios_firmware_capability
485   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
486   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
487   uint16_t bootup_vddc_mv;
488   uint16_t bootup_vddci_mv;
489   uint16_t bootup_mvddc_mv;
490   uint16_t bootup_vddgfx_mv;
491   uint8_t  mem_module_id;
492   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
493   uint8_t  reserved1[2];
494   uint32_t mc_baseaddr_high;
495   uint32_t mc_baseaddr_low;
496   uint32_t reserved2[6];
497 };
498 
499 /* Total 32bit cap indication */
500 enum atombios_firmware_capability
501 {
502 	ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
503 	ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
504 	ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
505 	ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
506 	ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
507 	ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
508 	ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
509 	ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
510 	ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
511 };
512 
513 enum atom_cooling_solution_id{
514   AIR_COOLING    = 0x00,
515   LIQUID_COOLING = 0x01
516 };
517 
518 struct atom_firmware_info_v3_2 {
519   struct atom_common_table_header table_header;
520   uint32_t firmware_revision;
521   uint32_t bootup_sclk_in10khz;
522   uint32_t bootup_mclk_in10khz;
523   uint32_t firmware_capability;             // enum atombios_firmware_capability
524   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
525   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
526   uint16_t bootup_vddc_mv;
527   uint16_t bootup_vddci_mv;
528   uint16_t bootup_mvddc_mv;
529   uint16_t bootup_vddgfx_mv;
530   uint8_t  mem_module_id;
531   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
532   uint8_t  reserved1[2];
533   uint32_t mc_baseaddr_high;
534   uint32_t mc_baseaddr_low;
535   uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
536   uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
537   uint8_t  board_i2c_feature_slave_addr;
538   uint8_t  reserved3;
539   uint16_t bootup_mvddq_mv;
540   uint16_t bootup_mvpp_mv;
541   uint32_t zfbstartaddrin16mb;
542   uint32_t reserved2[3];
543 };
544 
545 struct atom_firmware_info_v3_3
546 {
547   struct atom_common_table_header table_header;
548   uint32_t firmware_revision;
549   uint32_t bootup_sclk_in10khz;
550   uint32_t bootup_mclk_in10khz;
551   uint32_t firmware_capability;             // enum atombios_firmware_capability
552   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
553   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
554   uint16_t bootup_vddc_mv;
555   uint16_t bootup_vddci_mv;
556   uint16_t bootup_mvddc_mv;
557   uint16_t bootup_vddgfx_mv;
558   uint8_t  mem_module_id;
559   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
560   uint8_t  reserved1[2];
561   uint32_t mc_baseaddr_high;
562   uint32_t mc_baseaddr_low;
563   uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
564   uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
565   uint8_t  board_i2c_feature_slave_addr;
566   uint8_t  reserved3;
567   uint16_t bootup_mvddq_mv;
568   uint16_t bootup_mvpp_mv;
569   uint32_t zfbstartaddrin16mb;
570   uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
571   uint32_t reserved2[2];
572 };
573 
574 struct atom_firmware_info_v3_4 {
575 	struct atom_common_table_header table_header;
576 	uint32_t firmware_revision;
577 	uint32_t bootup_sclk_in10khz;
578 	uint32_t bootup_mclk_in10khz;
579 	uint32_t firmware_capability;             // enum atombios_firmware_capability
580 	uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
581 	uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
582 	uint16_t bootup_vddc_mv;
583 	uint16_t bootup_vddci_mv;
584 	uint16_t bootup_mvddc_mv;
585 	uint16_t bootup_vddgfx_mv;
586 	uint8_t  mem_module_id;
587 	uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
588 	uint8_t  reserved1[2];
589 	uint32_t mc_baseaddr_high;
590 	uint32_t mc_baseaddr_low;
591 	uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
592 	uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
593 	uint8_t  board_i2c_feature_slave_addr;
594 	uint8_t  ras_rom_i2c_slave_addr;
595 	uint16_t bootup_mvddq_mv;
596 	uint16_t bootup_mvpp_mv;
597 	uint32_t zfbstartaddrin16mb;
598 	uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
599 	uint32_t mvdd_ratio;                      // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
600 	uint16_t hw_bootup_vddgfx_mv;             // hw default vddgfx voltage level decide by board strap
601 	uint16_t hw_bootup_vddc_mv;               // hw default vddc voltage level decide by board strap
602 	uint16_t hw_bootup_mvddc_mv;              // hw default mvddc voltage level decide by board strap
603 	uint16_t hw_bootup_vddci_mv;              // hw default vddci voltage level decide by board strap
604 	uint32_t maco_pwrlimit_mw;                // bomaco mode power limit in unit of m-watt
605 	uint32_t usb_pwrlimit_mw;                 // power limit when USB is enable in unit of m-watt
606 	uint32_t fw_reserved_size_in_kb;          // VBIOS reserved extra fw size in unit of kb.
607         uint32_t pspbl_init_done_reg_addr;
608         uint32_t pspbl_init_done_value;
609         uint32_t pspbl_init_done_check_timeout;   // time out in unit of us when polling pspbl init done
610         uint32_t reserved[2];
611 };
612 
613 /*
614   ***************************************************************************
615     Data Table lcd_info  structure
616   ***************************************************************************
617 */
618 
619 struct lcd_info_v2_1
620 {
621   struct  atom_common_table_header table_header;
622   struct  atom_dtd_format  lcd_timing;
623   uint16_t backlight_pwm;
624   uint16_t special_handle_cap;
625   uint16_t panel_misc;
626   uint16_t lvds_max_slink_pclk;
627   uint16_t lvds_ss_percentage;
628   uint16_t lvds_ss_rate_10hz;
629   uint8_t  pwr_on_digon_to_de;          /*all pwr sequence numbers below are in uint of 4ms*/
630   uint8_t  pwr_on_de_to_vary_bl;
631   uint8_t  pwr_down_vary_bloff_to_de;
632   uint8_t  pwr_down_de_to_digoff;
633   uint8_t  pwr_off_delay;
634   uint8_t  pwr_on_vary_bl_to_blon;
635   uint8_t  pwr_down_bloff_to_vary_bloff;
636   uint8_t  panel_bpc;
637   uint8_t  dpcd_edp_config_cap;
638   uint8_t  dpcd_max_link_rate;
639   uint8_t  dpcd_max_lane_count;
640   uint8_t  dpcd_max_downspread;
641   uint8_t  min_allowed_bl_level;
642   uint8_t  max_allowed_bl_level;
643   uint8_t  bootup_bl_level;
644   uint8_t  dplvdsrxid;
645   uint32_t reserved1[8];
646 };
647 
648 /* lcd_info_v2_1.panel_misc defintion */
649 enum atom_lcd_info_panel_misc{
650   ATOM_PANEL_MISC_FPDI            =0x0002,
651 };
652 
653 //uceDPToLVDSRxId
654 enum atom_lcd_info_dptolvds_rx_id
655 {
656   eDP_TO_LVDS_RX_DISABLE                 = 0x00,       // no eDP->LVDS translator chip
657   eDP_TO_LVDS_COMMON_ID                  = 0x01,       // common eDP->LVDS translator chip without AMD SW init
658   eDP_TO_LVDS_REALTEK_ID                 = 0x02,       // Realtek tansaltor which require AMD SW init
659 };
660 
661 
662 /*
663   ***************************************************************************
664     Data Table gpio_pin_lut  structure
665   ***************************************************************************
666 */
667 
668 struct atom_gpio_pin_assignment
669 {
670   uint32_t data_a_reg_index;
671   uint8_t  gpio_bitshift;
672   uint8_t  gpio_mask_bitshift;
673   uint8_t  gpio_id;
674   uint8_t  reserved;
675 };
676 
677 /* atom_gpio_pin_assignment.gpio_id definition */
678 enum atom_gpio_pin_assignment_gpio_id {
679   I2C_HW_LANE_MUX        =0x0f, /* only valid when bit7=1 */
680   I2C_HW_ENGINE_ID_MASK  =0x70, /* only valid when bit7=1 */
681   I2C_HW_CAP             =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
682 
683   /* gpio_id pre-define id for multiple usage */
684   /* GPIO use to control PCIE_VDDC in certain SLT board */
685   PCIE_VDDC_CONTROL_GPIO_PINID = 56,
686   /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
687   PP_AC_DC_SWITCH_GPIO_PINID = 60,
688   /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
689   VDDC_VRHOT_GPIO_PINID = 61,
690   /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
691   VDDC_PCC_GPIO_PINID = 62,
692   /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
693   EFUSE_CUT_ENABLE_GPIO_PINID = 63,
694   /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
695   DRAM_SELF_REFRESH_GPIO_PINID = 64,
696   /* Thermal interrupt output->system thermal chip GPIO pin */
697   THERMAL_INT_OUTPUT_GPIO_PINID =65,
698 };
699 
700 
701 struct atom_gpio_pin_lut_v2_1
702 {
703   struct  atom_common_table_header  table_header;
704   /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut  */
705   struct  atom_gpio_pin_assignment  gpio_pin[8];
706 };
707 
708 
709 /*
710  * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write
711  * access that region. driver can allocate their own reservation region as long as it does not
712  * overlap firwmare's reservation region.
713  * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3:
714  * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1
715  *   if VBIOS/UEFI GOP is posted:
716  *     VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS
717  *     update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
718  *     ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10)
719  *     driver can allocate driver reservation region under firmware reservation,
720  *     used_by_driver_in_kb = driver reservation size
721  *     driver reservation start address =  (start_address_in_kb - used_by_driver_in_kb)
722  *     Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by
723  *     host driver. Host driver would overwrite the table with the following
724  *     used_by_firmware_in_kb = total reserved size for pf-vf info exchange and
725  *     set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0
726  *   else there is no VBIOS reservation region:
727  *     driver must allocate driver reservation region at top of FB.
728  *     driver set used_by_driver_in_kb = driver reservation size
729  *     driver reservation start address =  (total_mem_size_in_kb - used_by_driver_in_kb)
730  *     same as Comment1
731  * else (NV1X and after):
732  *   if VBIOS/UEFI GOP is posted:
733  *     VBIOS/UEFIGOP update:
734  *       used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb;
735  *       start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
736  *       (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10)
737  *   if vram_usagebyfirmwareTable version <= 2.1:
738  *     driver can allocate driver reservation region under firmware reservation,
739  *     driver set used_by_driver_in_kb = driver reservation size
740  *     driver reservation start address = start_address_in_kb - used_by_driver_in_kb
741  *     same as Comment1
742  *   else driver can:
743  *     allocate it reservation any place as long as it does overlap pre-OS FW reservation area
744  *     set used_by_driver_region0_in_kb = driver reservation size
745  *     set driver_region0_start_address_in_kb =  driver reservation region start address
746  *     Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to
747  *     zero as the reservation for VF as it doesn’t exist.  And Host driver should also
748  *     update atom_firmware_Info table to remove the same VBIOS reservation as well.
749  */
750 
751 struct vram_usagebyfirmware_v2_1
752 {
753 	struct  atom_common_table_header  table_header;
754 	uint32_t  start_address_in_kb;
755 	uint16_t  used_by_firmware_in_kb;
756 	uint16_t  used_by_driver_in_kb;
757 };
758 
759 struct vram_usagebyfirmware_v2_2 {
760 	struct  atom_common_table_header  table_header;
761 	uint32_t  fw_region_start_address_in_kb;
762 	uint16_t  used_by_firmware_in_kb;
763 	uint16_t  reserved;
764 	uint32_t  driver_region0_start_address_in_kb;
765 	uint32_t  used_by_driver_region0_in_kb;
766 	uint32_t  reserved32[7];
767 };
768 
769 /*
770   ***************************************************************************
771     Data Table displayobjectinfo  structure
772   ***************************************************************************
773 */
774 
775 enum atom_object_record_type_id {
776 	ATOM_I2C_RECORD_TYPE = 1,
777 	ATOM_HPD_INT_RECORD_TYPE = 2,
778 	ATOM_CONNECTOR_CAP_RECORD_TYPE = 3,
779 	ATOM_CONNECTOR_SPEED_UPTO = 4,
780 	ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9,
781 	ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16,
782 	ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17,
783 	ATOM_ENCODER_CAP_RECORD_TYPE = 20,
784 	ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21,
785 	ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22,
786 	ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23,
787 	ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25,
788 	ATOM_RECORD_END_TYPE = 0xFF,
789 };
790 
791 struct atom_common_record_header
792 {
793   uint8_t record_type;                      //An emun to indicate the record type
794   uint8_t record_size;                      //The size of the whole record in byte
795 };
796 
797 struct atom_i2c_record
798 {
799   struct atom_common_record_header record_header;   //record_type = ATOM_I2C_RECORD_TYPE
800   uint8_t i2c_id;
801   uint8_t i2c_slave_addr;                   //The slave address, it's 0 when the record is attached to connector for DDC
802 };
803 
804 struct atom_hpd_int_record
805 {
806   struct atom_common_record_header record_header;  //record_type = ATOM_HPD_INT_RECORD_TYPE
807   uint8_t  pin_id;              //Corresponding block in GPIO_PIN_INFO table gives the pin info
808   uint8_t  plugin_pin_state;
809 };
810 
811 struct atom_connector_caps_record {
812 	struct atom_common_record_header
813 		record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE
814 	uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not
815 };
816 
817 struct atom_connector_speed_record {
818 	struct atom_common_record_header
819 		record_header; //record_type = ATOM_CONN_SPEED_UPTO
820 	uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.
821 	uint16_t reserved;
822 };
823 
824 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
825 enum atom_encoder_caps_def
826 {
827   ATOM_ENCODER_CAP_RECORD_HBR2                  =0x01,         // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
828   ATOM_ENCODER_CAP_RECORD_MST_EN                =0x01,         // from SI, this bit means DP MST is enable or not.
829   ATOM_ENCODER_CAP_RECORD_HBR2_EN               =0x02,         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
830   ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          =0x04,         // HDMI2.0 6Gbps enable or not.
831   ATOM_ENCODER_CAP_RECORD_HBR3_EN               =0x08,         // DP1.3 HBR3 is supported by board.
832   ATOM_ENCODER_CAP_RECORD_DP2                   =0x10,         // DP2 is supported by ASIC/board.
833   ATOM_ENCODER_CAP_RECORD_UHBR10_EN             =0x20,         // DP2.0 UHBR10 settings is supported by board
834   ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN           =0x40,         // DP2.0 UHBR13.5 settings is supported by board
835   ATOM_ENCODER_CAP_RECORD_UHBR20_EN             =0x80,         // DP2.0 UHBR20 settings is supported by board
836   ATOM_ENCODER_CAP_RECORD_USB_C_TYPE            =0x100,        // the DP connector is a USB-C type.
837 };
838 
839 struct  atom_encoder_caps_record
840 {
841   struct atom_common_record_header record_header;  //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
842   uint32_t  encodercaps;
843 };
844 
845 enum atom_connector_caps_def
846 {
847   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY         = 0x01,        //a cap bit to indicate that this non-embedded display connector is an internal display
848   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL      = 0x02,        //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
849 };
850 
851 struct atom_disp_connector_caps_record
852 {
853   struct atom_common_record_header record_header;
854   uint32_t connectcaps;
855 };
856 
857 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
858 struct atom_gpio_pin_control_pair
859 {
860   uint8_t gpio_id;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
861   uint8_t gpio_pinstate;         // Pin state showing how to set-up the pin
862 };
863 
864 struct atom_object_gpio_cntl_record
865 {
866   struct atom_common_record_header record_header;
867   uint8_t flag;                   // Future expnadibility
868   uint8_t number_of_pins;         // Number of GPIO pins used to control the object
869   struct atom_gpio_pin_control_pair gpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
870 };
871 
872 //Definitions for GPIO pin state
873 enum atom_gpio_pin_control_pinstate_def
874 {
875   GPIO_PIN_TYPE_INPUT             = 0x00,
876   GPIO_PIN_TYPE_OUTPUT            = 0x10,
877   GPIO_PIN_TYPE_HW_CONTROL        = 0x20,
878 
879 //For GPIO_PIN_TYPE_OUTPUT the following is defined
880   GPIO_PIN_OUTPUT_STATE_MASK      = 0x01,
881   GPIO_PIN_OUTPUT_STATE_SHIFT     = 0,
882   GPIO_PIN_STATE_ACTIVE_LOW       = 0x0,
883   GPIO_PIN_STATE_ACTIVE_HIGH      = 0x1,
884 };
885 
886 // Indexes to GPIO array in GLSync record
887 // GLSync record is for Frame Lock/Gen Lock feature.
888 enum atom_glsync_record_gpio_index_def
889 {
890   ATOM_GPIO_INDEX_GLSYNC_REFCLK    = 0,
891   ATOM_GPIO_INDEX_GLSYNC_HSYNC     = 1,
892   ATOM_GPIO_INDEX_GLSYNC_VSYNC     = 2,
893   ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  = 3,
894   ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  = 4,
895   ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
896   ATOM_GPIO_INDEX_GLSYNC_V_RESET   = 6,
897   ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
898   ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  = 8,
899   ATOM_GPIO_INDEX_GLSYNC_MAX       = 9,
900 };
901 
902 
903 struct atom_connector_hpdpin_lut_record     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
904 {
905   struct atom_common_record_header record_header;
906   uint8_t hpd_pin_map[8];
907 };
908 
909 struct atom_connector_auxddc_lut_record     //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
910 {
911   struct atom_common_record_header record_header;
912   uint8_t aux_ddc_map[8];
913 };
914 
915 struct atom_connector_forced_tmds_cap_record
916 {
917   struct atom_common_record_header record_header;
918   // override TMDS capability on this connector when it operate in TMDS mode.  usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
919   uint8_t  maxtmdsclkrate_in2_5mhz;
920   uint8_t  reserved;
921 };
922 
923 struct atom_connector_layout_info
924 {
925   uint16_t connectorobjid;
926   uint8_t  connector_type;
927   uint8_t  position;
928 };
929 
930 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
931 enum atom_connector_layout_info_connector_type_def
932 {
933   CONNECTOR_TYPE_DVI_D                 = 1,
934 
935   CONNECTOR_TYPE_HDMI                  = 4,
936   CONNECTOR_TYPE_DISPLAY_PORT          = 5,
937   CONNECTOR_TYPE_MINI_DISPLAY_PORT     = 6,
938 };
939 
940 struct  atom_bracket_layout_record
941 {
942   struct atom_common_record_header record_header;
943   uint8_t bracketlen;
944   uint8_t bracketwidth;
945   uint8_t conn_num;
946   uint8_t reserved;
947   struct atom_connector_layout_info  conn_info[1];
948 };
949 struct atom_bracket_layout_record_v2 {
950 	struct atom_common_record_header
951 		record_header; //record_type =  ATOM_BRACKET_LAYOUT_RECORD_TYPE
952 	uint8_t bracketlen; //Bracket Length in mm
953 	uint8_t bracketwidth; //Bracket Width in mm
954 	uint8_t conn_num; //Connector numbering
955 	uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
956 	uint8_t reserved1;
957 	uint8_t reserved2;
958 };
959 
960 enum atom_connector_layout_info_mini_type_def {
961 	MINI_TYPE_NORMAL = 0,
962 	MINI_TYPE_MINI = 1,
963 };
964 
965 enum atom_display_device_tag_def{
966   ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
967   ATOM_DISPLAY_LCD2_SUPPORT			       = 0x0020, //second edp device tag 0x0020 for backward compability
968   ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
969   ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
970   ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
971   ATOM_DISPLAY_DFP4_SUPPORT            = 0x0400,
972   ATOM_DISPLAY_DFP5_SUPPORT            = 0x0800,
973   ATOM_DISPLAY_DFP6_SUPPORT            = 0x0040,
974   ATOM_DISPLAY_DFPx_SUPPORT            = 0x0ec8,
975 };
976 
977 struct atom_display_object_path_v2
978 {
979   uint16_t display_objid;                  //Connector Object ID or Misc Object ID
980   uint16_t disp_recordoffset;
981   uint16_t encoderobjid;                   //first encoder closer to the connector, could be either an external or intenal encoder
982   uint16_t extencoderobjid;                //2nd encoder after the first encoder, from the connector point of view;
983   uint16_t encoder_recordoffset;
984   uint16_t extencoder_recordoffset;
985   uint16_t device_tag;                     //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
986   uint8_t  priority_id;
987   uint8_t  reserved;
988 };
989 
990 struct atom_display_object_path_v3 {
991 	uint16_t display_objid; //Connector Object ID or Misc Object ID
992 	uint16_t disp_recordoffset;
993 	uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
994 	uint16_t reserved1; //only on USBC case, otherwise always = 0
995 	uint16_t reserved2; //reserved and always = 0
996 	uint16_t reserved3; //reserved and always = 0
997 	//a supported device vector, each display path starts with this.the paths are enumerated in the way of priority,
998 	//a path appears first
999 	uint16_t device_tag;
1000 	uint16_t reserved4; //reserved and always = 0
1001 };
1002 
1003 struct display_object_info_table_v1_4
1004 {
1005   struct    atom_common_table_header  table_header;
1006   uint16_t  supporteddevices;
1007   uint8_t   number_of_path;
1008   uint8_t   reserved;
1009   struct    atom_display_object_path_v2 display_path[8];   //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1010 };
1011 
1012 struct display_object_info_table_v1_5 {
1013 	struct atom_common_table_header table_header;
1014 	uint16_t supporteddevices;
1015 	uint8_t number_of_path;
1016 	uint8_t reserved;
1017 	// the real number of this included in the structure is calculated by using the
1018 	// (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1019 	struct atom_display_object_path_v3 display_path[8];
1020 };
1021 
1022 /*
1023   ***************************************************************************
1024     Data Table dce_info  structure
1025   ***************************************************************************
1026 */
1027 struct atom_display_controller_info_v4_1
1028 {
1029   struct  atom_common_table_header  table_header;
1030   uint32_t display_caps;
1031   uint32_t bootup_dispclk_10khz;
1032   uint16_t dce_refclk_10khz;
1033   uint16_t i2c_engine_refclk_10khz;
1034   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1035   uint16_t dvi_ss_rate_10hz;
1036   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1037   uint16_t hdmi_ss_rate_10hz;
1038   uint16_t dp_ss_percentage;        // in unit of 0.001%
1039   uint16_t dp_ss_rate_10hz;
1040   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1041   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1042   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1043   uint8_t  ss_reserved;
1044   uint8_t  hardcode_mode_num;       // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
1045   uint8_t  reserved1[3];
1046   uint16_t dpphy_refclk_10khz;
1047   uint16_t reserved2;
1048   uint8_t  dceip_min_ver;
1049   uint8_t  dceip_max_ver;
1050   uint8_t  max_disp_pipe_num;
1051   uint8_t  max_vbios_active_disp_pipe_num;
1052   uint8_t  max_ppll_num;
1053   uint8_t  max_disp_phy_num;
1054   uint8_t  max_aux_pairs;
1055   uint8_t  remotedisplayconfig;
1056   uint8_t  reserved3[8];
1057 };
1058 
1059 struct atom_display_controller_info_v4_2
1060 {
1061   struct  atom_common_table_header  table_header;
1062   uint32_t display_caps;
1063   uint32_t bootup_dispclk_10khz;
1064   uint16_t dce_refclk_10khz;
1065   uint16_t i2c_engine_refclk_10khz;
1066   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1067   uint16_t dvi_ss_rate_10hz;
1068   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1069   uint16_t hdmi_ss_rate_10hz;
1070   uint16_t dp_ss_percentage;        // in unit of 0.001%
1071   uint16_t dp_ss_rate_10hz;
1072   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1073   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1074   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1075   uint8_t  ss_reserved;
1076   uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1077   uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1078   uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1079   uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1080   uint16_t dpphy_refclk_10khz;
1081   uint16_t reserved2;
1082   uint8_t  dcnip_min_ver;
1083   uint8_t  dcnip_max_ver;
1084   uint8_t  max_disp_pipe_num;
1085   uint8_t  max_vbios_active_disp_pipe_num;
1086   uint8_t  max_ppll_num;
1087   uint8_t  max_disp_phy_num;
1088   uint8_t  max_aux_pairs;
1089   uint8_t  remotedisplayconfig;
1090   uint8_t  reserved3[8];
1091 };
1092 
1093 struct atom_display_controller_info_v4_3
1094 {
1095   struct  atom_common_table_header  table_header;
1096   uint32_t display_caps;
1097   uint32_t bootup_dispclk_10khz;
1098   uint16_t dce_refclk_10khz;
1099   uint16_t i2c_engine_refclk_10khz;
1100   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1101   uint16_t dvi_ss_rate_10hz;
1102   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1103   uint16_t hdmi_ss_rate_10hz;
1104   uint16_t dp_ss_percentage;        // in unit of 0.001%
1105   uint16_t dp_ss_rate_10hz;
1106   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1107   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1108   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1109   uint8_t  ss_reserved;
1110   uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1111   uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1112   uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1113   uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1114   uint16_t dpphy_refclk_10khz;
1115   uint16_t reserved2;
1116   uint8_t  dcnip_min_ver;
1117   uint8_t  dcnip_max_ver;
1118   uint8_t  max_disp_pipe_num;
1119   uint8_t  max_vbios_active_disp_pipe_num;
1120   uint8_t  max_ppll_num;
1121   uint8_t  max_disp_phy_num;
1122   uint8_t  max_aux_pairs;
1123   uint8_t  remotedisplayconfig;
1124   uint8_t  reserved3[8];
1125 };
1126 
1127 struct atom_display_controller_info_v4_4 {
1128 	struct atom_common_table_header table_header;
1129 	uint32_t display_caps;
1130 	uint32_t bootup_dispclk_10khz;
1131 	uint16_t dce_refclk_10khz;
1132 	uint16_t i2c_engine_refclk_10khz;
1133 	uint16_t dvi_ss_percentage;	 // in unit of 0.001%
1134 	uint16_t dvi_ss_rate_10hz;
1135 	uint16_t hdmi_ss_percentage;	 // in unit of 0.001%
1136 	uint16_t hdmi_ss_rate_10hz;
1137 	uint16_t dp_ss_percentage;	 // in unit of 0.001%
1138 	uint16_t dp_ss_rate_10hz;
1139 	uint8_t dvi_ss_mode;		 // enum of atom_spread_spectrum_mode
1140 	uint8_t hdmi_ss_mode;		 // enum of atom_spread_spectrum_mode
1141 	uint8_t dp_ss_mode;		 // enum of atom_spread_spectrum_mode
1142 	uint8_t ss_reserved;
1143 	uint8_t dfp_hardcode_mode_num;	 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1144 	uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1145 	uint8_t vga_hardcode_mode_num;	 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1146 	uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1147 	uint16_t dpphy_refclk_10khz;
1148 	uint16_t hw_chip_id;
1149 	uint8_t dcnip_min_ver;
1150 	uint8_t dcnip_max_ver;
1151 	uint8_t max_disp_pipe_num;
1152 	uint8_t max_vbios_active_disp_pipum;
1153 	uint8_t max_ppll_num;
1154 	uint8_t max_disp_phy_num;
1155 	uint8_t max_aux_pairs;
1156 	uint8_t remotedisplayconfig;
1157 	uint32_t dispclk_pll_vco_freq;
1158 	uint32_t dp_ref_clk_freq;
1159 	uint32_t max_mclk_chg_lat;	 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1160 	uint32_t max_sr_exit_lat;	 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1161 	uint32_t max_sr_enter_exit_lat;	 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1162 	uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1163 	uint16_t dc_golden_table_ver;
1164 	uint32_t reserved3[3];
1165 };
1166 
1167 struct atom_dc_golden_table_v1
1168 {
1169 	uint32_t aux_dphy_rx_control0_val;
1170 	uint32_t aux_dphy_tx_control_val;
1171 	uint32_t aux_dphy_rx_control1_val;
1172 	uint32_t dc_gpio_aux_ctrl_0_val;
1173 	uint32_t dc_gpio_aux_ctrl_1_val;
1174 	uint32_t dc_gpio_aux_ctrl_2_val;
1175 	uint32_t dc_gpio_aux_ctrl_3_val;
1176 	uint32_t dc_gpio_aux_ctrl_4_val;
1177 	uint32_t dc_gpio_aux_ctrl_5_val;
1178 	uint32_t reserved[23];
1179 };
1180 
1181 enum dce_info_caps_def {
1182 	// only for VBIOS
1183 	DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
1184 	// only for VBIOS
1185 	DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
1186 	// only for VBIOS
1187 	DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
1188 	// only for VBIOS
1189 	DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
1190 	DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1191 };
1192 
1193 struct atom_display_controller_info_v4_5
1194 {
1195   struct  atom_common_table_header  table_header;
1196   uint32_t display_caps;
1197   uint32_t bootup_dispclk_10khz;
1198   uint16_t dce_refclk_10khz;
1199   uint16_t i2c_engine_refclk_10khz;
1200   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1201   uint16_t dvi_ss_rate_10hz;
1202   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1203   uint16_t hdmi_ss_rate_10hz;
1204   uint16_t dp_ss_percentage;        // in unit of 0.001%
1205   uint16_t dp_ss_rate_10hz;
1206   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1207   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1208   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1209   uint8_t  ss_reserved;
1210   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1211   uint8_t  dfp_hardcode_mode_num;
1212   // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1213   uint8_t  dfp_hardcode_refreshrate;
1214   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1215   uint8_t  vga_hardcode_mode_num;
1216   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1217   uint8_t  vga_hardcode_refreshrate;
1218   uint16_t dpphy_refclk_10khz;
1219   uint16_t hw_chip_id;
1220   uint8_t  dcnip_min_ver;
1221   uint8_t  dcnip_max_ver;
1222   uint8_t  max_disp_pipe_num;
1223   uint8_t  max_vbios_active_disp_pipe_num;
1224   uint8_t  max_ppll_num;
1225   uint8_t  max_disp_phy_num;
1226   uint8_t  max_aux_pairs;
1227   uint8_t  remotedisplayconfig;
1228   uint32_t dispclk_pll_vco_freq;
1229   uint32_t dp_ref_clk_freq;
1230   // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1231   uint32_t max_mclk_chg_lat;
1232   // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1233   uint32_t max_sr_exit_lat;
1234   // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1235   uint32_t max_sr_enter_exit_lat;
1236   uint16_t dc_golden_table_offset;  // point of struct of atom_dc_golden_table_vxx
1237   uint16_t dc_golden_table_ver;
1238   uint32_t aux_dphy_rx_control0_val;
1239   uint32_t aux_dphy_tx_control_val;
1240   uint32_t aux_dphy_rx_control1_val;
1241   uint32_t dc_gpio_aux_ctrl_0_val;
1242   uint32_t dc_gpio_aux_ctrl_1_val;
1243   uint32_t dc_gpio_aux_ctrl_2_val;
1244   uint32_t dc_gpio_aux_ctrl_3_val;
1245   uint32_t dc_gpio_aux_ctrl_4_val;
1246   uint32_t dc_gpio_aux_ctrl_5_val;
1247   uint32_t reserved[26];
1248 };
1249 
1250 /*
1251   ***************************************************************************
1252     Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO  structure
1253   ***************************************************************************
1254 */
1255 struct atom_ext_display_path
1256 {
1257   uint16_t  device_tag;                      //A bit vector to show what devices are supported
1258   uint16_t  device_acpi_enum;                //16bit device ACPI id.
1259   uint16_t  connectorobjid;                  //A physical connector for displays to plug in, using object connector definitions
1260   uint8_t   auxddclut_index;                 //An index into external AUX/DDC channel LUT
1261   uint8_t   hpdlut_index;                    //An index into external HPD pin LUT
1262   uint16_t  ext_encoder_objid;               //external encoder object id
1263   uint8_t   channelmapping;                  // if ucChannelMapping=0, using default one to one mapping
1264   uint8_t   chpninvert;                      // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1265   uint16_t  caps;
1266   uint16_t  reserved;
1267 };
1268 
1269 //usCaps
1270 enum ext_display_path_cap_def {
1271 	EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =           0x0001,
1272 	EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =         0x0002,
1273 	EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =          0x007C,
1274 	EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 =      (0x01 << 2), //PI redriver chip
1275 	EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1276 	EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 =    (0x03 << 2)  //Parade DP->HDMI recoverter chip
1277 };
1278 
1279 struct atom_external_display_connection_info
1280 {
1281   struct  atom_common_table_header  table_header;
1282   uint8_t                  guid[16];                                  // a GUID is a 16 byte long string
1283   struct atom_ext_display_path path[7];                               // total of fixed 7 entries.
1284   uint8_t                  checksum;                                  // a simple Checksum of the sum of whole structure equal to 0x0.
1285   uint8_t                  stereopinid;                               // use for eDP panel
1286   uint8_t                  remotedisplayconfig;
1287   uint8_t                  edptolvdsrxid;
1288   uint8_t                  fixdpvoltageswing;                         // usCaps[1]=1, this indicate DP_LANE_SET value
1289   uint8_t                  reserved[3];                               // for potential expansion
1290 };
1291 
1292 /*
1293   ***************************************************************************
1294     Data Table integratedsysteminfo  structure
1295   ***************************************************************************
1296 */
1297 
1298 struct atom_camera_dphy_timing_param
1299 {
1300   uint8_t  profile_id;       // SENSOR_PROFILES
1301   uint32_t param;
1302 };
1303 
1304 struct atom_camera_dphy_elec_param
1305 {
1306   uint16_t param[3];
1307 };
1308 
1309 struct atom_camera_module_info
1310 {
1311   uint8_t module_id;                    // 0: Rear, 1: Front right of user, 2: Front left of user
1312   uint8_t module_name[8];
1313   struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1314 };
1315 
1316 struct atom_camera_flashlight_info
1317 {
1318   uint8_t flashlight_id;                // 0: Rear, 1: Front
1319   uint8_t name[8];
1320 };
1321 
1322 struct atom_camera_data
1323 {
1324   uint32_t versionCode;
1325   struct atom_camera_module_info cameraInfo[3];      // Assuming 3 camera sensors max
1326   struct atom_camera_flashlight_info flashInfo;      // Assuming 1 flashlight max
1327   struct atom_camera_dphy_elec_param dphy_param;
1328   uint32_t crc_val;         // CRC
1329 };
1330 
1331 
1332 struct atom_14nm_dpphy_dvihdmi_tuningset
1333 {
1334   uint32_t max_symclk_in10khz;
1335   uint8_t encoder_mode;            //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1336   uint8_t phy_sel;                 //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1337   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1338   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1339   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1340   uint8_t tx_driver_fifty_ohms;    //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1341   uint8_t deemph_sel;              //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1342 };
1343 
1344 struct atom_14nm_dpphy_dp_setting{
1345   uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1346   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1347   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1348   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1349 };
1350 
1351 struct atom_14nm_dpphy_dp_tuningset{
1352   uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1353   uint8_t version;
1354   uint16_t table_size;             // size of atom_14nm_dpphy_dp_tuningset
1355   uint16_t reserved;
1356   struct atom_14nm_dpphy_dp_setting dptuning[10];
1357 };
1358 
1359 struct atom_14nm_dig_transmitter_info_header_v4_0{
1360   struct  atom_common_table_header  table_header;
1361   uint16_t pcie_phy_tmds_hdmi_macro_settings_offset;     // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1362   uint16_t uniphy_vs_emph_lookup_table_offset;           // offset of UniphyVSEmphLookUpTbl
1363   uint16_t uniphy_xbar_settings_table_offset;            // offset of UniphyXbarSettingsTbl
1364 };
1365 
1366 struct atom_14nm_combphy_tmds_vs_set
1367 {
1368   uint8_t sym_clk;
1369   uint8_t dig_mode;
1370   uint8_t phy_sel;
1371   uint16_t common_mar_deemph_nom__margin_deemph_val;
1372   uint8_t common_seldeemph60__deemph_6db_4_val;
1373   uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1374   uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1375   uint8_t margin_deemph_lane0__deemph_sel_val;
1376 };
1377 
1378 struct atom_DCN_dpphy_dvihdmi_tuningset
1379 {
1380   uint32_t max_symclk_in10khz;
1381   uint8_t  encoder_mode;           //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1382   uint8_t  phy_sel;                //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1383   uint8_t  tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1384   uint8_t  tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1385   uint8_t  tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1386   uint8_t  reserved1;
1387   uint8_t  tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1388   uint8_t  reserved2;
1389 };
1390 
1391 struct atom_DCN_dpphy_dp_setting{
1392   uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1393   uint8_t tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1394   uint8_t tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1395   uint8_t tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1396   uint8_t tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1397 };
1398 
1399 struct atom_DCN_dpphy_dp_tuningset{
1400   uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1401   uint8_t version;
1402   uint16_t table_size;             // size of atom_14nm_dpphy_dp_setting
1403   uint16_t reserved;
1404   struct atom_DCN_dpphy_dp_setting dptunings[10];
1405 };
1406 
1407 struct atom_i2c_reg_info {
1408   uint8_t ucI2cRegIndex;
1409   uint8_t ucI2cRegVal;
1410 };
1411 
1412 struct atom_hdmi_retimer_redriver_set {
1413   uint8_t HdmiSlvAddr;
1414   uint8_t HdmiRegNum;
1415   uint8_t Hdmi6GRegNum;
1416   struct atom_i2c_reg_info HdmiRegSetting[9];        //For non 6G Hz use
1417   struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];    //For 6G Hz use.
1418 };
1419 
1420 struct atom_integrated_system_info_v1_11
1421 {
1422   struct  atom_common_table_header  table_header;
1423   uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1424   uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1425   uint32_t  system_config;
1426   uint32_t  cpucapinfo;
1427   uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1428   uint16_t  gpuclk_ss_type;
1429   uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1430   uint16_t  lvds_ss_rate_10hz;
1431   uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1432   uint16_t  hdmi_ss_rate_10hz;
1433   uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1434   uint16_t  dvi_ss_rate_10hz;
1435   uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1436   uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1437   uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1438   uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1439   uint8_t   umachannelnumber;                 // number of memory channels
1440   uint8_t   pwr_on_digon_to_de;               /* all pwr sequence numbers below are in uint of 4ms */
1441   uint8_t   pwr_on_de_to_vary_bl;
1442   uint8_t   pwr_down_vary_bloff_to_de;
1443   uint8_t   pwr_down_de_to_digoff;
1444   uint8_t   pwr_off_delay;
1445   uint8_t   pwr_on_vary_bl_to_blon;
1446   uint8_t   pwr_down_bloff_to_vary_bloff;
1447   uint8_t   min_allowed_bl_level;
1448   uint8_t   htc_hyst_limit;
1449   uint8_t   htc_tmp_limit;
1450   uint8_t   reserved1;
1451   uint8_t   reserved2;
1452   struct atom_external_display_connection_info extdispconninfo;
1453   struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1454   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1455   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1456   struct atom_14nm_dpphy_dp_tuningset dp_tuningset;        // rbr 1.62G dp tuning set
1457   struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;   // HBR3 dp tuning set
1458   struct atom_camera_data  camera_info;
1459   struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1460   struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1461   struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1462   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1463   struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset;    //hbr 2.7G dp tuning set
1464   struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset;   //hbr2 5.4G dp turnig set
1465   struct atom_14nm_dpphy_dp_tuningset edp_tuningset;       //edp tuning set
1466   uint32_t  reserved[66];
1467 };
1468 
1469 struct atom_integrated_system_info_v1_12
1470 {
1471   struct  atom_common_table_header  table_header;
1472   uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1473   uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1474   uint32_t  system_config;
1475   uint32_t  cpucapinfo;
1476   uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1477   uint16_t  gpuclk_ss_type;
1478   uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1479   uint16_t  lvds_ss_rate_10hz;
1480   uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1481   uint16_t  hdmi_ss_rate_10hz;
1482   uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1483   uint16_t  dvi_ss_rate_10hz;
1484   uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1485   uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1486   uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1487   uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1488   uint8_t   umachannelnumber;                 // number of memory channels
1489   uint8_t   pwr_on_digon_to_de;               // all pwr sequence numbers below are in uint of 4ms //
1490   uint8_t   pwr_on_de_to_vary_bl;
1491   uint8_t   pwr_down_vary_bloff_to_de;
1492   uint8_t   pwr_down_de_to_digoff;
1493   uint8_t   pwr_off_delay;
1494   uint8_t   pwr_on_vary_bl_to_blon;
1495   uint8_t   pwr_down_bloff_to_vary_bloff;
1496   uint8_t   min_allowed_bl_level;
1497   uint8_t   htc_hyst_limit;
1498   uint8_t   htc_tmp_limit;
1499   uint8_t   reserved1;
1500   uint8_t   reserved2;
1501   struct atom_external_display_connection_info extdispconninfo;
1502   struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1503   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset;
1504   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1505   struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1506   struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
1507   struct atom_camera_data  camera_info;
1508   struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1509   struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1510   struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1511   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1512   struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1513   struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1514   struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1515   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1516   uint32_t  reserved[63];
1517 };
1518 
1519 struct edp_info_table
1520 {
1521         uint16_t edp_backlight_pwm_hz;
1522         uint16_t edp_ss_percentage;
1523         uint16_t edp_ss_rate_10hz;
1524         uint16_t reserved1;
1525         uint32_t reserved2;
1526         uint8_t  edp_pwr_on_off_delay;
1527         uint8_t  edp_pwr_on_vary_bl_to_blon;
1528         uint8_t  edp_pwr_down_bloff_to_vary_bloff;
1529         uint8_t  edp_panel_bpc;
1530         uint8_t  edp_bootup_bl_level;
1531         uint8_t  reserved3[3];
1532         uint32_t reserved4[3];
1533 };
1534 
1535 struct atom_integrated_system_info_v2_1
1536 {
1537         struct  atom_common_table_header  table_header;
1538         uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1539         uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1540         uint32_t  system_config;
1541         uint32_t  cpucapinfo;
1542         uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1543         uint16_t  gpuclk_ss_type;
1544         uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1545         uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1546         uint8_t   umachannelnumber;                 // number of memory channels
1547         uint8_t   htc_hyst_limit;
1548         uint8_t   htc_tmp_limit;
1549         uint8_t   reserved1;
1550         uint8_t   reserved2;
1551         struct edp_info_table edp1_info;
1552         struct edp_info_table edp2_info;
1553         uint32_t  reserved3[8];
1554         struct atom_external_display_connection_info extdispconninfo;
1555         struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1556         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset; //add clk6
1557         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1558         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1559         uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1560         struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1561         struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1562         struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1563         struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
1564         struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1565         uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1566         struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1567         struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1568         struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1569         struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1570         uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1571         uint32_t reserved7[32];
1572 
1573 };
1574 
1575 struct atom_n6_display_phy_tuning_set {
1576 	uint8_t display_signal_type;
1577 	uint8_t phy_sel;
1578 	uint8_t preset_level;
1579 	uint8_t reserved1;
1580 	uint32_t reserved2;
1581 	uint32_t speed_upto;
1582 	uint8_t tx_vboost_level;
1583 	uint8_t tx_vreg_v2i;
1584 	uint8_t tx_vregdrv_byp;
1585 	uint8_t tx_term_cntl;
1586 	uint8_t tx_peak_level;
1587 	uint8_t tx_slew_en;
1588 	uint8_t tx_eq_pre;
1589 	uint8_t tx_eq_main;
1590 	uint8_t tx_eq_post;
1591 	uint8_t tx_en_inv_pre;
1592 	uint8_t tx_en_inv_post;
1593 	uint8_t reserved3;
1594 	uint32_t reserved4;
1595 	uint32_t reserved5;
1596 	uint32_t reserved6;
1597 };
1598 
1599 struct atom_display_phy_tuning_info {
1600 	struct atom_common_table_header table_header;
1601 	struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
1602 };
1603 
1604 struct atom_integrated_system_info_v2_2
1605 {
1606 	struct  atom_common_table_header  table_header;
1607 	uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1608 	uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1609 	uint32_t  system_config;
1610 	uint32_t  cpucapinfo;
1611 	uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1612 	uint16_t  gpuclk_ss_type;
1613 	uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1614 	uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1615 	uint8_t   umachannelnumber;                 // number of memory channels
1616 	uint8_t   htc_hyst_limit;
1617 	uint8_t   htc_tmp_limit;
1618 	uint8_t   reserved1;
1619 	uint8_t   reserved2;
1620 	struct edp_info_table edp1_info;
1621 	struct edp_info_table edp2_info;
1622 	uint32_t  reserved3[8];
1623 	struct atom_external_display_connection_info extdispconninfo;
1624 
1625 	uint32_t  reserved4[189];
1626 };
1627 
1628 struct uma_carveout_option {
1629   char       optionName[29];        //max length of string is 28chars + '\0'. Current design is for "minimum", "Medium", "High". This makes entire struct size 64bits
1630   uint8_t    memoryCarvedGb;        //memory carved out with setting
1631   uint8_t    memoryRemainingGb;     //memory remaining on system
1632   union {
1633     struct _flags {
1634       uint8_t Auto     : 1;
1635       uint8_t Custom   : 1;
1636       uint8_t Reserved : 6;
1637     } flags;
1638     uint8_t all8;
1639   } uma_carveout_option_flags;
1640 };
1641 
1642 struct atom_integrated_system_info_v2_3 {
1643   struct  atom_common_table_header table_header;
1644   uint32_t  vbios_misc; // enum of atom_system_vbiosmisc_def
1645   uint32_t  gpucapinfo; // enum of atom_system_gpucapinf_def
1646   uint32_t  system_config;
1647   uint32_t  cpucapinfo;
1648   uint16_t  gpuclk_ss_percentage; // unit of 0.001%,   1000 mean 1%
1649   uint16_t  gpuclk_ss_type;
1650   uint16_t  dpphy_override;  // bit vector, enum of atom_sysinfo_dpphy_override_def
1651   uint8_t memorytype;       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1652   uint8_t umachannelnumber; // number of memory channels
1653   uint8_t htc_hyst_limit;
1654   uint8_t htc_tmp_limit;
1655   uint8_t reserved1; // dp_ss_control
1656   uint8_t gpu_package_id;
1657   struct  edp_info_table  edp1_info;
1658   struct  edp_info_table  edp2_info;
1659   uint32_t  reserved2[8];
1660   struct  atom_external_display_connection_info extdispconninfo;
1661   uint8_t UMACarveoutVersion;
1662   uint8_t UMACarveoutIndexMax;
1663   uint8_t UMACarveoutTypeDefault;
1664   uint8_t UMACarveoutIndexDefault;
1665   uint8_t UMACarveoutType;           //Auto or Custom
1666   uint8_t UMACarveoutIndex;
1667   struct  uma_carveout_option UMASizeControlOption[20];
1668   uint8_t reserved3[110];
1669 };
1670 
1671 // system_config
1672 enum atom_system_vbiosmisc_def{
1673   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1674 };
1675 
1676 
1677 // gpucapinfo
1678 enum atom_system_gpucapinf_def{
1679   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
1680 };
1681 
1682 //dpphy_override
1683 enum atom_sysinfo_dpphy_override_def{
1684   ATOM_ENABLE_DVI_TUNINGSET   = 0x01,
1685   ATOM_ENABLE_HDMI_TUNINGSET  = 0x02,
1686   ATOM_ENABLE_HDMI6G_TUNINGSET  = 0x04,
1687   ATOM_ENABLE_DP_TUNINGSET  = 0x08,
1688   ATOM_ENABLE_DP_HBR3_TUNINGSET  = 0x10,
1689 };
1690 
1691 //lvds_misc
1692 enum atom_sys_info_lvds_misc_def
1693 {
1694   SYS_INFO_LVDS_MISC_888_FPDI_MODE                 =0x01,
1695   SYS_INFO_LVDS_MISC_888_BPC_MODE                  =0x04,
1696   SYS_INFO_LVDS_MISC_OVERRIDE_EN                   =0x08,
1697 };
1698 
1699 
1700 //memorytype  DMI Type 17 offset 12h - Memory Type
1701 enum atom_dmi_t17_mem_type_def{
1702   OtherMemType = 0x01,                                  ///< Assign 01 to Other
1703   UnknownMemType,                                       ///< Assign 02 to Unknown
1704   DramMemType,                                          ///< Assign 03 to DRAM
1705   EdramMemType,                                         ///< Assign 04 to EDRAM
1706   VramMemType,                                          ///< Assign 05 to VRAM
1707   SramMemType,                                          ///< Assign 06 to SRAM
1708   RamMemType,                                           ///< Assign 07 to RAM
1709   RomMemType,                                           ///< Assign 08 to ROM
1710   FlashMemType,                                         ///< Assign 09 to Flash
1711   EepromMemType,                                        ///< Assign 10 to EEPROM
1712   FepromMemType,                                        ///< Assign 11 to FEPROM
1713   EpromMemType,                                         ///< Assign 12 to EPROM
1714   CdramMemType,                                         ///< Assign 13 to CDRAM
1715   ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
1716   SdramMemType,                                         ///< Assign 15 to SDRAM
1717   SgramMemType,                                         ///< Assign 16 to SGRAM
1718   RdramMemType,                                         ///< Assign 17 to RDRAM
1719   DdrMemType,                                           ///< Assign 18 to DDR
1720   Ddr2MemType,                                          ///< Assign 19 to DDR2
1721   Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
1722   Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
1723   Fbd2MemType,                                          ///< Assign 25 to FBD2
1724   Ddr4MemType,                                          ///< Assign 26 to DDR4
1725   LpDdrMemType,                                         ///< Assign 27 to LPDDR
1726   LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
1727   LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
1728   LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
1729   GDdr6MemType,                                         ///< Assign 31 to GDDR6
1730   HbmMemType,                                           ///< Assign 32 to HBM
1731   Hbm2MemType,                                          ///< Assign 33 to HBM2
1732   Ddr5MemType,                                          ///< Assign 34 to DDR5
1733   LpDdr5MemType,                                        ///< Assign 35 to LPDDR5
1734 };
1735 
1736 
1737 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1738 struct atom_fusion_system_info_v4
1739 {
1740   struct atom_integrated_system_info_v1_11   sysinfo;           // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1741   uint32_t   powerplayinfo[256];                                // Reserve 1024 bytes space for PowerPlayInfoTable
1742 };
1743 
1744 
1745 /*
1746   ***************************************************************************
1747     Data Table gfx_info  structure
1748   ***************************************************************************
1749 */
1750 
1751 struct  atom_gfx_info_v2_2
1752 {
1753   struct  atom_common_table_header  table_header;
1754   uint8_t gfxip_min_ver;
1755   uint8_t gfxip_max_ver;
1756   uint8_t max_shader_engines;
1757   uint8_t max_tile_pipes;
1758   uint8_t max_cu_per_sh;
1759   uint8_t max_sh_per_se;
1760   uint8_t max_backends_per_se;
1761   uint8_t max_texture_channel_caches;
1762   uint32_t regaddr_cp_dma_src_addr;
1763   uint32_t regaddr_cp_dma_src_addr_hi;
1764   uint32_t regaddr_cp_dma_dst_addr;
1765   uint32_t regaddr_cp_dma_dst_addr_hi;
1766   uint32_t regaddr_cp_dma_command;
1767   uint32_t regaddr_cp_status;
1768   uint32_t regaddr_rlc_gpu_clock_32;
1769   uint32_t rlc_gpu_timer_refclk;
1770 };
1771 
1772 struct  atom_gfx_info_v2_3 {
1773   struct  atom_common_table_header  table_header;
1774   uint8_t gfxip_min_ver;
1775   uint8_t gfxip_max_ver;
1776   uint8_t max_shader_engines;
1777   uint8_t max_tile_pipes;
1778   uint8_t max_cu_per_sh;
1779   uint8_t max_sh_per_se;
1780   uint8_t max_backends_per_se;
1781   uint8_t max_texture_channel_caches;
1782   uint32_t regaddr_cp_dma_src_addr;
1783   uint32_t regaddr_cp_dma_src_addr_hi;
1784   uint32_t regaddr_cp_dma_dst_addr;
1785   uint32_t regaddr_cp_dma_dst_addr_hi;
1786   uint32_t regaddr_cp_dma_command;
1787   uint32_t regaddr_cp_status;
1788   uint32_t regaddr_rlc_gpu_clock_32;
1789   uint32_t rlc_gpu_timer_refclk;
1790   uint8_t active_cu_per_sh;
1791   uint8_t active_rb_per_se;
1792   uint16_t gcgoldenoffset;
1793   uint32_t rm21_sram_vmin_value;
1794 };
1795 
1796 struct  atom_gfx_info_v2_4
1797 {
1798   struct  atom_common_table_header  table_header;
1799   uint8_t gfxip_min_ver;
1800   uint8_t gfxip_max_ver;
1801   uint8_t max_shader_engines;
1802   uint8_t reserved;
1803   uint8_t max_cu_per_sh;
1804   uint8_t max_sh_per_se;
1805   uint8_t max_backends_per_se;
1806   uint8_t max_texture_channel_caches;
1807   uint32_t regaddr_cp_dma_src_addr;
1808   uint32_t regaddr_cp_dma_src_addr_hi;
1809   uint32_t regaddr_cp_dma_dst_addr;
1810   uint32_t regaddr_cp_dma_dst_addr_hi;
1811   uint32_t regaddr_cp_dma_command;
1812   uint32_t regaddr_cp_status;
1813   uint32_t regaddr_rlc_gpu_clock_32;
1814   uint32_t rlc_gpu_timer_refclk;
1815   uint8_t active_cu_per_sh;
1816   uint8_t active_rb_per_se;
1817   uint16_t gcgoldenoffset;
1818   uint16_t gc_num_gprs;
1819   uint16_t gc_gsprim_buff_depth;
1820   uint16_t gc_parameter_cache_depth;
1821   uint16_t gc_wave_size;
1822   uint16_t gc_max_waves_per_simd;
1823   uint16_t gc_lds_size;
1824   uint8_t gc_num_max_gs_thds;
1825   uint8_t gc_gs_table_depth;
1826   uint8_t gc_double_offchip_lds_buffer;
1827   uint8_t gc_max_scratch_slots_per_cu;
1828   uint32_t sram_rm_fuses_val;
1829   uint32_t sram_custom_rm_fuses_val;
1830 };
1831 
1832 struct atom_gfx_info_v2_7 {
1833 	struct atom_common_table_header table_header;
1834 	uint8_t gfxip_min_ver;
1835 	uint8_t gfxip_max_ver;
1836 	uint8_t max_shader_engines;
1837 	uint8_t reserved;
1838 	uint8_t max_cu_per_sh;
1839 	uint8_t max_sh_per_se;
1840 	uint8_t max_backends_per_se;
1841 	uint8_t max_texture_channel_caches;
1842 	uint32_t regaddr_cp_dma_src_addr;
1843 	uint32_t regaddr_cp_dma_src_addr_hi;
1844 	uint32_t regaddr_cp_dma_dst_addr;
1845 	uint32_t regaddr_cp_dma_dst_addr_hi;
1846 	uint32_t regaddr_cp_dma_command;
1847 	uint32_t regaddr_cp_status;
1848 	uint32_t regaddr_rlc_gpu_clock_32;
1849 	uint32_t rlc_gpu_timer_refclk;
1850 	uint8_t active_cu_per_sh;
1851 	uint8_t active_rb_per_se;
1852 	uint16_t gcgoldenoffset;
1853 	uint16_t gc_num_gprs;
1854 	uint16_t gc_gsprim_buff_depth;
1855 	uint16_t gc_parameter_cache_depth;
1856 	uint16_t gc_wave_size;
1857 	uint16_t gc_max_waves_per_simd;
1858 	uint16_t gc_lds_size;
1859 	uint8_t gc_num_max_gs_thds;
1860 	uint8_t gc_gs_table_depth;
1861 	uint8_t gc_double_offchip_lds_buffer;
1862 	uint8_t gc_max_scratch_slots_per_cu;
1863 	uint32_t sram_rm_fuses_val;
1864 	uint32_t sram_custom_rm_fuses_val;
1865 	uint8_t cut_cu;
1866 	uint8_t active_cu_total;
1867 	uint8_t cu_reserved[2];
1868 	uint32_t gc_config;
1869 	uint8_t inactive_cu_per_se[8];
1870 	uint32_t reserved2[6];
1871 };
1872 
1873 struct atom_gfx_info_v3_0 {
1874 	struct atom_common_table_header table_header;
1875 	uint8_t gfxip_min_ver;
1876 	uint8_t gfxip_max_ver;
1877 	uint8_t max_shader_engines;
1878 	uint8_t max_tile_pipes;
1879 	uint8_t max_cu_per_sh;
1880 	uint8_t max_sh_per_se;
1881 	uint8_t max_backends_per_se;
1882 	uint8_t max_texture_channel_caches;
1883 	uint32_t regaddr_lsdma_queue0_rb_rptr;
1884 	uint32_t regaddr_lsdma_queue0_rb_rptr_hi;
1885 	uint32_t regaddr_lsdma_queue0_rb_wptr;
1886 	uint32_t regaddr_lsdma_queue0_rb_wptr_hi;
1887 	uint32_t regaddr_lsdma_command;
1888 	uint32_t regaddr_lsdma_status;
1889 	uint32_t regaddr_golden_tsc_count_lower;
1890 	uint32_t golden_tsc_count_lower_refclk;
1891 	uint8_t active_wgp_per_se;
1892 	uint8_t active_rb_per_se;
1893 	uint8_t active_se;
1894 	uint8_t reserved1;
1895 	uint32_t sram_rm_fuses_val;
1896 	uint32_t sram_custom_rm_fuses_val;
1897 	uint32_t inactive_sa_mask;
1898 	uint32_t gc_config;
1899 	uint8_t inactive_wgp[16];
1900 	uint8_t inactive_rb[16];
1901 	uint32_t gdfll_as_wait_ctrl_val;
1902 	uint32_t gdfll_as_step_ctrl_val;
1903 	uint32_t reserved[8];
1904 };
1905 
1906 /*
1907   ***************************************************************************
1908     Data Table smu_info  structure
1909   ***************************************************************************
1910 */
1911 struct atom_smu_info_v3_1
1912 {
1913   struct  atom_common_table_header  table_header;
1914   uint8_t smuip_min_ver;
1915   uint8_t smuip_max_ver;
1916   uint8_t smu_rsd1;
1917   uint8_t gpuclk_ss_mode;           // enum of atom_spread_spectrum_mode
1918   uint16_t sclk_ss_percentage;
1919   uint16_t sclk_ss_rate_10hz;
1920   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1921   uint16_t gpuclk_ss_rate_10hz;
1922   uint32_t core_refclk_10khz;
1923   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1924   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1925   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1926   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1927   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1928   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1929   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1930   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1931 };
1932 
1933 struct atom_smu_info_v3_2 {
1934   struct   atom_common_table_header  table_header;
1935   uint8_t  smuip_min_ver;
1936   uint8_t  smuip_max_ver;
1937   uint8_t  smu_rsd1;
1938   uint8_t  gpuclk_ss_mode;
1939   uint16_t sclk_ss_percentage;
1940   uint16_t sclk_ss_rate_10hz;
1941   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1942   uint16_t gpuclk_ss_rate_10hz;
1943   uint32_t core_refclk_10khz;
1944   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1945   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1946   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1947   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1948   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1949   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1950   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1951   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1952   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1953   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1954   uint16_t smugoldenoffset;
1955   uint32_t gpupll_vco_freq_10khz;
1956   uint32_t bootup_smnclk_10khz;
1957   uint32_t bootup_socclk_10khz;
1958   uint32_t bootup_mp0clk_10khz;
1959   uint32_t bootup_mp1clk_10khz;
1960   uint32_t bootup_lclk_10khz;
1961   uint32_t bootup_dcefclk_10khz;
1962   uint32_t ctf_threshold_override_value;
1963   uint32_t reserved[5];
1964 };
1965 
1966 struct atom_smu_info_v3_3 {
1967   struct   atom_common_table_header  table_header;
1968   uint8_t  smuip_min_ver;
1969   uint8_t  smuip_max_ver;
1970   uint8_t  waflclk_ss_mode;
1971   uint8_t  gpuclk_ss_mode;
1972   uint16_t sclk_ss_percentage;
1973   uint16_t sclk_ss_rate_10hz;
1974   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1975   uint16_t gpuclk_ss_rate_10hz;
1976   uint32_t core_refclk_10khz;
1977   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1978   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1979   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1980   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1981   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1982   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1983   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1984   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1985   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1986   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1987   uint16_t smugoldenoffset;
1988   uint32_t gpupll_vco_freq_10khz;
1989   uint32_t bootup_smnclk_10khz;
1990   uint32_t bootup_socclk_10khz;
1991   uint32_t bootup_mp0clk_10khz;
1992   uint32_t bootup_mp1clk_10khz;
1993   uint32_t bootup_lclk_10khz;
1994   uint32_t bootup_dcefclk_10khz;
1995   uint32_t ctf_threshold_override_value;
1996   uint32_t syspll3_0_vco_freq_10khz;
1997   uint32_t syspll3_1_vco_freq_10khz;
1998   uint32_t bootup_fclk_10khz;
1999   uint32_t bootup_waflclk_10khz;
2000   uint32_t smu_info_caps;
2001   uint16_t waflclk_ss_percentage;    // in unit of 0.001%
2002   uint16_t smuinitoffset;
2003   uint32_t reserved;
2004 };
2005 
2006 struct atom_smu_info_v3_5
2007 {
2008   struct   atom_common_table_header  table_header;
2009   uint8_t  smuip_min_ver;
2010   uint8_t  smuip_max_ver;
2011   uint8_t  waflclk_ss_mode;
2012   uint8_t  gpuclk_ss_mode;
2013   uint16_t sclk_ss_percentage;
2014   uint16_t sclk_ss_rate_10hz;
2015   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
2016   uint16_t gpuclk_ss_rate_10hz;
2017   uint32_t core_refclk_10khz;
2018   uint32_t syspll0_1_vco_freq_10khz;
2019   uint32_t syspll0_2_vco_freq_10khz;
2020   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2021   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
2022   uint16_t smugoldenoffset;
2023   uint32_t syspll0_0_vco_freq_10khz;
2024   uint32_t bootup_smnclk_10khz;
2025   uint32_t bootup_socclk_10khz;
2026   uint32_t bootup_mp0clk_10khz;
2027   uint32_t bootup_mp1clk_10khz;
2028   uint32_t bootup_lclk_10khz;
2029   uint32_t bootup_dcefclk_10khz;
2030   uint32_t ctf_threshold_override_value;
2031   uint32_t syspll3_0_vco_freq_10khz;
2032   uint32_t syspll3_1_vco_freq_10khz;
2033   uint32_t bootup_fclk_10khz;
2034   uint32_t bootup_waflclk_10khz;
2035   uint32_t smu_info_caps;
2036   uint16_t waflclk_ss_percentage;    // in unit of 0.001%
2037   uint16_t smuinitoffset;
2038   uint32_t bootup_dprefclk_10khz;
2039   uint32_t bootup_usbclk_10khz;
2040   uint32_t smb_slave_address;
2041   uint32_t cg_fdo_ctrl0_val;
2042   uint32_t cg_fdo_ctrl1_val;
2043   uint32_t cg_fdo_ctrl2_val;
2044   uint32_t gdfll_as_wait_ctrl_val;
2045   uint32_t gdfll_as_step_ctrl_val;
2046   uint32_t bootup_dtbclk_10khz;
2047   uint32_t fclk_syspll_refclk_10khz;
2048   uint32_t smusvi_svc0_val;
2049   uint32_t smusvi_svc1_val;
2050   uint32_t smusvi_svd0_val;
2051   uint32_t smusvi_svd1_val;
2052   uint32_t smusvi_svt0_val;
2053   uint32_t smusvi_svt1_val;
2054   uint32_t cg_tach_ctrl_val;
2055   uint32_t cg_pump_ctrl1_val;
2056   uint32_t cg_pump_tach_ctrl_val;
2057   uint32_t thm_ctf_delay_val;
2058   uint32_t thm_thermal_int_ctrl_val;
2059   uint32_t thm_tmon_config_val;
2060   uint32_t reserved[16];
2061 };
2062 
2063 struct atom_smu_info_v3_6
2064 {
2065 	struct   atom_common_table_header  table_header;
2066 	uint8_t  smuip_min_ver;
2067 	uint8_t  smuip_max_ver;
2068 	uint8_t  waflclk_ss_mode;
2069 	uint8_t  gpuclk_ss_mode;
2070 	uint16_t sclk_ss_percentage;
2071 	uint16_t sclk_ss_rate_10hz;
2072 	uint16_t gpuclk_ss_percentage;
2073 	uint16_t gpuclk_ss_rate_10hz;
2074 	uint32_t core_refclk_10khz;
2075 	uint32_t syspll0_1_vco_freq_10khz;
2076 	uint32_t syspll0_2_vco_freq_10khz;
2077 	uint8_t  pcc_gpio_bit;
2078 	uint8_t  pcc_gpio_polarity;
2079 	uint16_t smugoldenoffset;
2080 	uint32_t syspll0_0_vco_freq_10khz;
2081 	uint32_t bootup_smnclk_10khz;
2082 	uint32_t bootup_socclk_10khz;
2083 	uint32_t bootup_mp0clk_10khz;
2084 	uint32_t bootup_mp1clk_10khz;
2085 	uint32_t bootup_lclk_10khz;
2086 	uint32_t bootup_dxioclk_10khz;
2087 	uint32_t ctf_threshold_override_value;
2088 	uint32_t syspll3_0_vco_freq_10khz;
2089 	uint32_t syspll3_1_vco_freq_10khz;
2090 	uint32_t bootup_fclk_10khz;
2091 	uint32_t bootup_waflclk_10khz;
2092 	uint32_t smu_info_caps;
2093 	uint16_t waflclk_ss_percentage;
2094 	uint16_t smuinitoffset;
2095 	uint32_t bootup_gfxavsclk_10khz;
2096 	uint32_t bootup_mpioclk_10khz;
2097 	uint32_t smb_slave_address;
2098 	uint32_t cg_fdo_ctrl0_val;
2099 	uint32_t cg_fdo_ctrl1_val;
2100 	uint32_t cg_fdo_ctrl2_val;
2101 	uint32_t gdfll_as_wait_ctrl_val;
2102 	uint32_t gdfll_as_step_ctrl_val;
2103 	uint32_t reserved_clk;
2104 	uint32_t fclk_syspll_refclk_10khz;
2105 	uint32_t smusvi_svc0_val;
2106 	uint32_t smusvi_svc1_val;
2107 	uint32_t smusvi_svd0_val;
2108 	uint32_t smusvi_svd1_val;
2109 	uint32_t smusvi_svt0_val;
2110 	uint32_t smusvi_svt1_val;
2111 	uint32_t cg_tach_ctrl_val;
2112 	uint32_t cg_pump_ctrl1_val;
2113 	uint32_t cg_pump_tach_ctrl_val;
2114 	uint32_t thm_ctf_delay_val;
2115 	uint32_t thm_thermal_int_ctrl_val;
2116 	uint32_t thm_tmon_config_val;
2117 	uint32_t bootup_vclk_10khz;
2118 	uint32_t bootup_dclk_10khz;
2119 	uint32_t smu_gpiopad_pu_en_val;
2120 	uint32_t smu_gpiopad_pd_en_val;
2121 	uint32_t reserved[12];
2122 };
2123 
2124 struct atom_smu_info_v4_0 {
2125 	struct atom_common_table_header table_header;
2126 	uint32_t bootup_gfxclk_bypass_10khz;
2127 	uint32_t bootup_usrclk_10khz;
2128 	uint32_t bootup_csrclk_10khz;
2129 	uint32_t core_refclk_10khz;
2130 	uint32_t syspll1_vco_freq_10khz;
2131 	uint32_t syspll2_vco_freq_10khz;
2132 	uint8_t pcc_gpio_bit;
2133 	uint8_t pcc_gpio_polarity;
2134 	uint16_t bootup_vddusr_mv;
2135 	uint32_t syspll0_vco_freq_10khz;
2136 	uint32_t bootup_smnclk_10khz;
2137 	uint32_t bootup_socclk_10khz;
2138 	uint32_t bootup_mp0clk_10khz;
2139 	uint32_t bootup_mp1clk_10khz;
2140 	uint32_t bootup_lclk_10khz;
2141 	uint32_t bootup_dcefclk_10khz;
2142 	uint32_t ctf_threshold_override_value;
2143 	uint32_t syspll3_vco_freq_10khz;
2144 	uint32_t mm_syspll_vco_freq_10khz;
2145 	uint32_t bootup_fclk_10khz;
2146 	uint32_t bootup_waflclk_10khz;
2147 	uint32_t smu_info_caps;
2148 	uint16_t waflclk_ss_percentage;
2149 	uint16_t smuinitoffset;
2150 	uint32_t bootup_dprefclk_10khz;
2151 	uint32_t bootup_usbclk_10khz;
2152 	uint32_t smb_slave_address;
2153 	uint32_t cg_fdo_ctrl0_val;
2154 	uint32_t cg_fdo_ctrl1_val;
2155 	uint32_t cg_fdo_ctrl2_val;
2156 	uint32_t gdfll_as_wait_ctrl_val;
2157 	uint32_t gdfll_as_step_ctrl_val;
2158 	uint32_t bootup_dtbclk_10khz;
2159 	uint32_t fclk_syspll_refclk_10khz;
2160 	uint32_t smusvi_svc0_val;
2161 	uint32_t smusvi_svc1_val;
2162 	uint32_t smusvi_svd0_val;
2163 	uint32_t smusvi_svd1_val;
2164 	uint32_t smusvi_svt0_val;
2165 	uint32_t smusvi_svt1_val;
2166 	uint32_t cg_tach_ctrl_val;
2167 	uint32_t cg_pump_ctrl1_val;
2168 	uint32_t cg_pump_tach_ctrl_val;
2169 	uint32_t thm_ctf_delay_val;
2170 	uint32_t thm_thermal_int_ctrl_val;
2171 	uint32_t thm_tmon_config_val;
2172 	uint32_t smbus_timing_cntrl0_val;
2173 	uint32_t smbus_timing_cntrl1_val;
2174 	uint32_t smbus_timing_cntrl2_val;
2175 	uint32_t pwr_disp_timer_global_control_val;
2176 	uint32_t bootup_mpioclk_10khz;
2177 	uint32_t bootup_dclk0_10khz;
2178 	uint32_t bootup_vclk0_10khz;
2179 	uint32_t bootup_dclk1_10khz;
2180 	uint32_t bootup_vclk1_10khz;
2181 	uint32_t bootup_baco400clk_10khz;
2182 	uint32_t bootup_baco1200clk_bypass_10khz;
2183 	uint32_t bootup_baco700clk_bypass_10khz;
2184 	uint32_t reserved[16];
2185 };
2186 
2187 /*
2188  ***************************************************************************
2189    Data Table smc_dpm_info  structure
2190  ***************************************************************************
2191  */
2192 struct atom_smc_dpm_info_v4_1
2193 {
2194   struct   atom_common_table_header  table_header;
2195   uint8_t  liquid1_i2c_address;
2196   uint8_t  liquid2_i2c_address;
2197   uint8_t  vr_i2c_address;
2198   uint8_t  plx_i2c_address;
2199 
2200   uint8_t  liquid_i2c_linescl;
2201   uint8_t  liquid_i2c_linesda;
2202   uint8_t  vr_i2c_linescl;
2203   uint8_t  vr_i2c_linesda;
2204 
2205   uint8_t  plx_i2c_linescl;
2206   uint8_t  plx_i2c_linesda;
2207   uint8_t  vrsensorpresent;
2208   uint8_t  liquidsensorpresent;
2209 
2210   uint16_t maxvoltagestepgfx;
2211   uint16_t maxvoltagestepsoc;
2212 
2213   uint8_t  vddgfxvrmapping;
2214   uint8_t  vddsocvrmapping;
2215   uint8_t  vddmem0vrmapping;
2216   uint8_t  vddmem1vrmapping;
2217 
2218   uint8_t  gfxulvphasesheddingmask;
2219   uint8_t  soculvphasesheddingmask;
2220   uint8_t  padding8_v[2];
2221 
2222   uint16_t gfxmaxcurrent;
2223   uint8_t  gfxoffset;
2224   uint8_t  padding_telemetrygfx;
2225 
2226   uint16_t socmaxcurrent;
2227   uint8_t  socoffset;
2228   uint8_t  padding_telemetrysoc;
2229 
2230   uint16_t mem0maxcurrent;
2231   uint8_t  mem0offset;
2232   uint8_t  padding_telemetrymem0;
2233 
2234   uint16_t mem1maxcurrent;
2235   uint8_t  mem1offset;
2236   uint8_t  padding_telemetrymem1;
2237 
2238   uint8_t  acdcgpio;
2239   uint8_t  acdcpolarity;
2240   uint8_t  vr0hotgpio;
2241   uint8_t  vr0hotpolarity;
2242 
2243   uint8_t  vr1hotgpio;
2244   uint8_t  vr1hotpolarity;
2245   uint8_t  padding1;
2246   uint8_t  padding2;
2247 
2248   uint8_t  ledpin0;
2249   uint8_t  ledpin1;
2250   uint8_t  ledpin2;
2251   uint8_t  padding8_4;
2252 
2253 	uint8_t  pllgfxclkspreadenabled;
2254 	uint8_t  pllgfxclkspreadpercent;
2255 	uint16_t pllgfxclkspreadfreq;
2256 
2257   uint8_t uclkspreadenabled;
2258   uint8_t uclkspreadpercent;
2259   uint16_t uclkspreadfreq;
2260 
2261   uint8_t socclkspreadenabled;
2262   uint8_t socclkspreadpercent;
2263   uint16_t socclkspreadfreq;
2264 
2265 	uint8_t  acggfxclkspreadenabled;
2266 	uint8_t  acggfxclkspreadpercent;
2267 	uint16_t acggfxclkspreadfreq;
2268 
2269 	uint8_t Vr2_I2C_address;
2270 	uint8_t padding_vr2[3];
2271 
2272 	uint32_t boardreserved[9];
2273 };
2274 
2275 /*
2276  ***************************************************************************
2277    Data Table smc_dpm_info  structure
2278  ***************************************************************************
2279  */
2280 struct atom_smc_dpm_info_v4_3
2281 {
2282   struct   atom_common_table_header  table_header;
2283   uint8_t  liquid1_i2c_address;
2284   uint8_t  liquid2_i2c_address;
2285   uint8_t  vr_i2c_address;
2286   uint8_t  plx_i2c_address;
2287 
2288   uint8_t  liquid_i2c_linescl;
2289   uint8_t  liquid_i2c_linesda;
2290   uint8_t  vr_i2c_linescl;
2291   uint8_t  vr_i2c_linesda;
2292 
2293   uint8_t  plx_i2c_linescl;
2294   uint8_t  plx_i2c_linesda;
2295   uint8_t  vrsensorpresent;
2296   uint8_t  liquidsensorpresent;
2297 
2298   uint16_t maxvoltagestepgfx;
2299   uint16_t maxvoltagestepsoc;
2300 
2301   uint8_t  vddgfxvrmapping;
2302   uint8_t  vddsocvrmapping;
2303   uint8_t  vddmem0vrmapping;
2304   uint8_t  vddmem1vrmapping;
2305 
2306   uint8_t  gfxulvphasesheddingmask;
2307   uint8_t  soculvphasesheddingmask;
2308   uint8_t  externalsensorpresent;
2309   uint8_t  padding8_v;
2310 
2311   uint16_t gfxmaxcurrent;
2312   uint8_t  gfxoffset;
2313   uint8_t  padding_telemetrygfx;
2314 
2315   uint16_t socmaxcurrent;
2316   uint8_t  socoffset;
2317   uint8_t  padding_telemetrysoc;
2318 
2319   uint16_t mem0maxcurrent;
2320   uint8_t  mem0offset;
2321   uint8_t  padding_telemetrymem0;
2322 
2323   uint16_t mem1maxcurrent;
2324   uint8_t  mem1offset;
2325   uint8_t  padding_telemetrymem1;
2326 
2327   uint8_t  acdcgpio;
2328   uint8_t  acdcpolarity;
2329   uint8_t  vr0hotgpio;
2330   uint8_t  vr0hotpolarity;
2331 
2332   uint8_t  vr1hotgpio;
2333   uint8_t  vr1hotpolarity;
2334   uint8_t  padding1;
2335   uint8_t  padding2;
2336 
2337   uint8_t  ledpin0;
2338   uint8_t  ledpin1;
2339   uint8_t  ledpin2;
2340   uint8_t  padding8_4;
2341 
2342   uint8_t  pllgfxclkspreadenabled;
2343   uint8_t  pllgfxclkspreadpercent;
2344   uint16_t pllgfxclkspreadfreq;
2345 
2346   uint8_t uclkspreadenabled;
2347   uint8_t uclkspreadpercent;
2348   uint16_t uclkspreadfreq;
2349 
2350   uint8_t fclkspreadenabled;
2351   uint8_t fclkspreadpercent;
2352   uint16_t fclkspreadfreq;
2353 
2354   uint8_t fllgfxclkspreadenabled;
2355   uint8_t fllgfxclkspreadpercent;
2356   uint16_t fllgfxclkspreadfreq;
2357 
2358   uint32_t boardreserved[10];
2359 };
2360 
2361 struct smudpm_i2ccontrollerconfig_t {
2362   uint32_t  enabled;
2363   uint32_t  slaveaddress;
2364   uint32_t  controllerport;
2365   uint32_t  controllername;
2366   uint32_t  thermalthrottler;
2367   uint32_t  i2cprotocol;
2368   uint32_t  i2cspeed;
2369 };
2370 
2371 struct atom_smc_dpm_info_v4_4
2372 {
2373   struct   atom_common_table_header  table_header;
2374   uint32_t  i2c_padding[3];
2375 
2376   uint16_t maxvoltagestepgfx;
2377   uint16_t maxvoltagestepsoc;
2378 
2379   uint8_t  vddgfxvrmapping;
2380   uint8_t  vddsocvrmapping;
2381   uint8_t  vddmem0vrmapping;
2382   uint8_t  vddmem1vrmapping;
2383 
2384   uint8_t  gfxulvphasesheddingmask;
2385   uint8_t  soculvphasesheddingmask;
2386   uint8_t  externalsensorpresent;
2387   uint8_t  padding8_v;
2388 
2389   uint16_t gfxmaxcurrent;
2390   uint8_t  gfxoffset;
2391   uint8_t  padding_telemetrygfx;
2392 
2393   uint16_t socmaxcurrent;
2394   uint8_t  socoffset;
2395   uint8_t  padding_telemetrysoc;
2396 
2397   uint16_t mem0maxcurrent;
2398   uint8_t  mem0offset;
2399   uint8_t  padding_telemetrymem0;
2400 
2401   uint16_t mem1maxcurrent;
2402   uint8_t  mem1offset;
2403   uint8_t  padding_telemetrymem1;
2404 
2405 
2406   uint8_t  acdcgpio;
2407   uint8_t  acdcpolarity;
2408   uint8_t  vr0hotgpio;
2409   uint8_t  vr0hotpolarity;
2410 
2411   uint8_t  vr1hotgpio;
2412   uint8_t  vr1hotpolarity;
2413   uint8_t  padding1;
2414   uint8_t  padding2;
2415 
2416 
2417   uint8_t  ledpin0;
2418   uint8_t  ledpin1;
2419   uint8_t  ledpin2;
2420   uint8_t  padding8_4;
2421 
2422 
2423   uint8_t  pllgfxclkspreadenabled;
2424   uint8_t  pllgfxclkspreadpercent;
2425   uint16_t pllgfxclkspreadfreq;
2426 
2427 
2428   uint8_t  uclkspreadenabled;
2429   uint8_t  uclkspreadpercent;
2430   uint16_t uclkspreadfreq;
2431 
2432 
2433   uint8_t  fclkspreadenabled;
2434   uint8_t  fclkspreadpercent;
2435   uint16_t fclkspreadfreq;
2436 
2437 
2438   uint8_t  fllgfxclkspreadenabled;
2439   uint8_t  fllgfxclkspreadpercent;
2440   uint16_t fllgfxclkspreadfreq;
2441 
2442 
2443   struct smudpm_i2ccontrollerconfig_t  i2ccontrollers[7];
2444 
2445 
2446   uint32_t boardreserved[10];
2447 };
2448 
2449 enum smudpm_v4_5_i2ccontrollername_e{
2450     SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2451     SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
2452     SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
2453     SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
2454     SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
2455     SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
2456     SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
2457     SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
2458     SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
2459 };
2460 
2461 enum smudpm_v4_5_i2ccontrollerthrottler_e{
2462     SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2463     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
2464     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
2465     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
2466     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
2467     SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
2468     SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
2469     SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
2470     SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
2471 };
2472 
2473 enum smudpm_v4_5_i2ccontrollerprotocol_e{
2474     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
2475     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
2476     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
2477     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
2478     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
2479     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
2480     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
2481 };
2482 
2483 struct smudpm_i2c_controller_config_v2
2484 {
2485     uint8_t   Enabled;
2486     uint8_t   Speed;
2487     uint8_t   Padding[2];
2488     uint32_t  SlaveAddress;
2489     uint8_t   ControllerPort;
2490     uint8_t   ControllerName;
2491     uint8_t   ThermalThrotter;
2492     uint8_t   I2cProtocol;
2493 };
2494 
2495 struct atom_smc_dpm_info_v4_5
2496 {
2497   struct   atom_common_table_header  table_header;
2498     // SECTION: BOARD PARAMETERS
2499     // I2C Control
2500   struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2501 
2502   // SVI2 Board Parameters
2503   uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2504   uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2505 
2506   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2507   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2508   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2509   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2510 
2511   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2512   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2513   uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2514   uint8_t      Padding8_V;
2515 
2516   // Telemetry Settings
2517   uint16_t     GfxMaxCurrent;   // in Amps
2518   uint8_t      GfxOffset;       // in Amps
2519   uint8_t      Padding_TelemetryGfx;
2520   uint16_t     SocMaxCurrent;   // in Amps
2521   uint8_t      SocOffset;       // in Amps
2522   uint8_t      Padding_TelemetrySoc;
2523 
2524   uint16_t     Mem0MaxCurrent;   // in Amps
2525   uint8_t      Mem0Offset;       // in Amps
2526   uint8_t      Padding_TelemetryMem0;
2527 
2528   uint16_t     Mem1MaxCurrent;   // in Amps
2529   uint8_t      Mem1Offset;       // in Amps
2530   uint8_t      Padding_TelemetryMem1;
2531 
2532   // GPIO Settings
2533   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2534   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2535   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2536   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2537 
2538   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2539   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2540   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2541   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2542 
2543   // LED Display Settings
2544   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2545   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2546   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2547   uint8_t      padding8_4;
2548 
2549   // GFXCLK PLL Spread Spectrum
2550   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2551   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2552   uint16_t     PllGfxclkSpreadFreq;      // kHz
2553 
2554   // GFXCLK DFLL Spread Spectrum
2555   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2556   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2557   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2558 
2559   // UCLK Spread Spectrum
2560   uint8_t      UclkSpreadEnabled;   // on or off
2561   uint8_t      UclkSpreadPercent;   // Q4.4
2562   uint16_t     UclkSpreadFreq;      // kHz
2563 
2564   // SOCCLK Spread Spectrum
2565   uint8_t      SoclkSpreadEnabled;   // on or off
2566   uint8_t      SocclkSpreadPercent;   // Q4.4
2567   uint16_t     SocclkSpreadFreq;      // kHz
2568 
2569   // Total board power
2570   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2571   uint16_t     BoardPadding;
2572 
2573   // Mvdd Svi2 Div Ratio Setting
2574   uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2575 
2576   uint32_t     BoardReserved[9];
2577 
2578 };
2579 
2580 struct atom_smc_dpm_info_v4_6
2581 {
2582   struct   atom_common_table_header  table_header;
2583   // section: board parameters
2584   uint32_t     i2c_padding[3];   // old i2c control are moved to new area
2585 
2586   uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2587   uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2588 
2589   uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
2590   uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
2591   uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
2592   uint8_t      boardvrmapping;      // use vr_mapping* bitfields
2593 
2594   uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2595   uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
2596   uint8_t      padding8_v[2];
2597 
2598   // telemetry settings
2599   uint16_t     gfxmaxcurrent;   // in amps
2600   uint8_t      gfxoffset;       // in amps
2601   uint8_t      padding_telemetrygfx;
2602 
2603   uint16_t     socmaxcurrent;   // in amps
2604   uint8_t      socoffset;       // in amps
2605   uint8_t      padding_telemetrysoc;
2606 
2607   uint16_t     memmaxcurrent;   // in amps
2608   uint8_t      memoffset;       // in amps
2609   uint8_t      padding_telemetrymem;
2610 
2611   uint16_t     boardmaxcurrent;   // in amps
2612   uint8_t      boardoffset;       // in amps
2613   uint8_t      padding_telemetryboardinput;
2614 
2615   // gpio settings
2616   uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
2617   uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
2618   uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
2619   uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
2620 
2621  // gfxclk pll spread spectrum
2622   uint8_t	   pllgfxclkspreadenabled;	// on or off
2623   uint8_t	   pllgfxclkspreadpercent;	// q4.4
2624   uint16_t	   pllgfxclkspreadfreq;		// khz
2625 
2626  // uclk spread spectrum
2627   uint8_t	   uclkspreadenabled;   // on or off
2628   uint8_t	   uclkspreadpercent;   // q4.4
2629   uint16_t	   uclkspreadfreq;	   // khz
2630 
2631  // fclk spread spectrum
2632   uint8_t	   fclkspreadenabled;   // on or off
2633   uint8_t	   fclkspreadpercent;   // q4.4
2634   uint16_t	   fclkspreadfreq;	   // khz
2635 
2636 
2637   // gfxclk fll spread spectrum
2638   uint8_t      fllgfxclkspreadenabled;   // on or off
2639   uint8_t      fllgfxclkspreadpercent;   // q4.4
2640   uint16_t     fllgfxclkspreadfreq;      // khz
2641 
2642   // i2c controller structure
2643   struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2644 
2645   // memory section
2646   uint32_t	 memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2647 
2648   uint8_t 	 drambitwidth; // for dram use only.  see dram bit width type defines
2649   uint8_t 	 paddingmem[3];
2650 
2651 	// total board power
2652   uint16_t	 totalboardpower;	  //only needed for tcp estimated case, where tcp = tgp+total board power
2653   uint16_t	 boardpadding;
2654 
2655 	// section: xgmi training
2656   uint8_t 	 xgmilinkspeed[4];
2657   uint8_t 	 xgmilinkwidth[4];
2658 
2659   uint16_t	 xgmifclkfreq[4];
2660   uint16_t	 xgmisocvoltage[4];
2661 
2662   // reserved
2663   uint32_t   boardreserved[10];
2664 };
2665 
2666 struct atom_smc_dpm_info_v4_7
2667 {
2668   struct   atom_common_table_header  table_header;
2669     // SECTION: BOARD PARAMETERS
2670     // I2C Control
2671   struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2672 
2673   // SVI2 Board Parameters
2674   uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2675   uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2676 
2677   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2678   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2679   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2680   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2681 
2682   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2683   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2684   uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2685   uint8_t      Padding8_V;
2686 
2687   // Telemetry Settings
2688   uint16_t     GfxMaxCurrent;   // in Amps
2689   uint8_t      GfxOffset;       // in Amps
2690   uint8_t      Padding_TelemetryGfx;
2691   uint16_t     SocMaxCurrent;   // in Amps
2692   uint8_t      SocOffset;       // in Amps
2693   uint8_t      Padding_TelemetrySoc;
2694 
2695   uint16_t     Mem0MaxCurrent;   // in Amps
2696   uint8_t      Mem0Offset;       // in Amps
2697   uint8_t      Padding_TelemetryMem0;
2698 
2699   uint16_t     Mem1MaxCurrent;   // in Amps
2700   uint8_t      Mem1Offset;       // in Amps
2701   uint8_t      Padding_TelemetryMem1;
2702 
2703   // GPIO Settings
2704   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2705   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2706   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2707   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2708 
2709   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2710   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2711   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2712   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2713 
2714   // LED Display Settings
2715   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2716   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2717   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2718   uint8_t      padding8_4;
2719 
2720   // GFXCLK PLL Spread Spectrum
2721   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2722   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2723   uint16_t     PllGfxclkSpreadFreq;      // kHz
2724 
2725   // GFXCLK DFLL Spread Spectrum
2726   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2727   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2728   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2729 
2730   // UCLK Spread Spectrum
2731   uint8_t      UclkSpreadEnabled;   // on or off
2732   uint8_t      UclkSpreadPercent;   // Q4.4
2733   uint16_t     UclkSpreadFreq;      // kHz
2734 
2735   // SOCCLK Spread Spectrum
2736   uint8_t      SoclkSpreadEnabled;   // on or off
2737   uint8_t      SocclkSpreadPercent;   // Q4.4
2738   uint16_t     SocclkSpreadFreq;      // kHz
2739 
2740   // Total board power
2741   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2742   uint16_t     BoardPadding;
2743 
2744   // Mvdd Svi2 Div Ratio Setting
2745   uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2746 
2747   // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2748   uint8_t      GpioI2cScl;          // Serial Clock
2749   uint8_t      GpioI2cSda;          // Serial Data
2750   uint16_t     GpioPadding;
2751 
2752   // Additional LED Display Settings
2753   uint8_t      LedPin3;         // GPIO number for LedPin[3] - PCIE GEN Speed
2754   uint8_t      LedPin4;         // GPIO number for LedPin[4] - PMFW Error Status
2755   uint16_t     LedEnableMask;
2756 
2757   // Power Limit Scalars
2758   uint8_t      PowerLimitScalar[4];    //[PPT_THROTTLER_COUNT]
2759 
2760   uint8_t      MvddUlvPhaseSheddingMask;
2761   uint8_t      VddciUlvPhaseSheddingMask;
2762   uint8_t      Padding8_Psi1;
2763   uint8_t      Padding8_Psi2;
2764 
2765   uint32_t     BoardReserved[5];
2766 };
2767 
2768 struct smudpm_i2c_controller_config_v3
2769 {
2770   uint8_t   Enabled;
2771   uint8_t   Speed;
2772   uint8_t   SlaveAddress;
2773   uint8_t   ControllerPort;
2774   uint8_t   ControllerName;
2775   uint8_t   ThermalThrotter;
2776   uint8_t   I2cProtocol;
2777   uint8_t   PaddingConfig;
2778 };
2779 
2780 struct atom_smc_dpm_info_v4_9
2781 {
2782   struct   atom_common_table_header  table_header;
2783 
2784   //SECTION: Gaming Clocks
2785   //uint32_t     GamingClk[6];
2786 
2787   // SECTION: I2C Control
2788   struct smudpm_i2c_controller_config_v3  I2cControllers[16];
2789 
2790   uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1
2791   uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1
2792   uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2793   uint8_t      I2cSpare;
2794 
2795   // SECTION: SVI2 Board Parameters
2796   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2797   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2798   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2799   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2800 
2801   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2802   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2803   uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2804   uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2805 
2806   // SECTION: Telemetry Settings
2807   uint16_t     GfxMaxCurrent;   // in Amps
2808   uint8_t      GfxOffset;       // in Amps
2809   uint8_t      Padding_TelemetryGfx;
2810 
2811   uint16_t     SocMaxCurrent;   // in Amps
2812   uint8_t      SocOffset;       // in Amps
2813   uint8_t      Padding_TelemetrySoc;
2814 
2815   uint16_t     Mem0MaxCurrent;   // in Amps
2816   uint8_t      Mem0Offset;       // in Amps
2817   uint8_t      Padding_TelemetryMem0;
2818 
2819   uint16_t     Mem1MaxCurrent;   // in Amps
2820   uint8_t      Mem1Offset;       // in Amps
2821   uint8_t      Padding_TelemetryMem1;
2822 
2823   uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2824 
2825   // SECTION: GPIO Settings
2826   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2827   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2828   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2829   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2830 
2831   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2832   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2833   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2834   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2835 
2836   // LED Display Settings
2837   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2838   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2839   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2840   uint8_t      LedEnableMask;
2841 
2842   uint8_t      LedPcie;        // GPIO number for PCIE results
2843   uint8_t      LedError;       // GPIO number for Error Cases
2844   uint8_t      LedSpare1[2];
2845 
2846   // SECTION: Clock Spread Spectrum
2847 
2848   // GFXCLK PLL Spread Spectrum
2849   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2850   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2851   uint16_t     PllGfxclkSpreadFreq;      // kHz
2852 
2853   // GFXCLK DFLL Spread Spectrum
2854   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2855   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2856   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2857 
2858   // UCLK Spread Spectrum
2859   uint8_t      UclkSpreadEnabled;   // on or off
2860   uint8_t      UclkSpreadPercent;   // Q4.4
2861   uint16_t     UclkSpreadFreq;      // kHz
2862 
2863   // FCLK Spread Spectrum
2864   uint8_t      FclkSpreadEnabled;   // on or off
2865   uint8_t      FclkSpreadPercent;   // Q4.4
2866   uint16_t     FclkSpreadFreq;      // kHz
2867 
2868   // Section: Memory Config
2869   uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2870 
2871   uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
2872   uint8_t      PaddingMem1[3];
2873 
2874   // Section: Total Board Power
2875   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2876   uint16_t     BoardPowerPadding;
2877 
2878   // SECTION: XGMI Training
2879   uint8_t      XgmiLinkSpeed   [4];
2880   uint8_t      XgmiLinkWidth   [4];
2881 
2882   uint16_t     XgmiFclkFreq    [4];
2883   uint16_t     XgmiSocVoltage  [4];
2884 
2885   // SECTION: Board Reserved
2886 
2887   uint32_t     BoardReserved[16];
2888 
2889 };
2890 
2891 struct atom_smc_dpm_info_v4_10
2892 {
2893   struct   atom_common_table_header  table_header;
2894 
2895   // SECTION: BOARD PARAMETERS
2896   // Telemetry Settings
2897   uint16_t GfxMaxCurrent; // in Amps
2898   uint8_t   GfxOffset;     // in Amps
2899   uint8_t  Padding_TelemetryGfx;
2900 
2901   uint16_t SocMaxCurrent; // in Amps
2902   uint8_t   SocOffset;     // in Amps
2903   uint8_t  Padding_TelemetrySoc;
2904 
2905   uint16_t MemMaxCurrent; // in Amps
2906   uint8_t   MemOffset;     // in Amps
2907   uint8_t  Padding_TelemetryMem;
2908 
2909   uint16_t BoardMaxCurrent; // in Amps
2910   uint8_t   BoardOffset;     // in Amps
2911   uint8_t  Padding_TelemetryBoardInput;
2912 
2913   // Platform input telemetry voltage coefficient
2914   uint32_t BoardVoltageCoeffA; // decode by /1000
2915   uint32_t BoardVoltageCoeffB; // decode by /1000
2916 
2917   // GPIO Settings
2918   uint8_t  VR0HotGpio;     // GPIO pin configured for VR0 HOT event
2919   uint8_t  VR0HotPolarity; // GPIO polarity for VR0 HOT event
2920   uint8_t  VR1HotGpio;     // GPIO pin configured for VR1 HOT event
2921   uint8_t  VR1HotPolarity; // GPIO polarity for VR1 HOT event
2922 
2923   // UCLK Spread Spectrum
2924   uint8_t  UclkSpreadEnabled; // on or off
2925   uint8_t  UclkSpreadPercent; // Q4.4
2926   uint16_t UclkSpreadFreq;    // kHz
2927 
2928   // FCLK Spread Spectrum
2929   uint8_t  FclkSpreadEnabled; // on or off
2930   uint8_t  FclkSpreadPercent; // Q4.4
2931   uint16_t FclkSpreadFreq;    // kHz
2932 
2933   // I2C Controller Structure
2934   struct smudpm_i2c_controller_config_v3  I2cControllers[8];
2935 
2936   // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2937   uint8_t  GpioI2cScl; // Serial Clock
2938   uint8_t  GpioI2cSda; // Serial Data
2939   uint16_t spare5;
2940 
2941   uint32_t reserved[16];
2942 };
2943 
2944 /*
2945   ***************************************************************************
2946     Data Table asic_profiling_info  structure
2947   ***************************************************************************
2948 */
2949 struct  atom_asic_profiling_info_v4_1
2950 {
2951   struct  atom_common_table_header  table_header;
2952   uint32_t  maxvddc;
2953   uint32_t  minvddc;
2954   uint32_t  avfs_meannsigma_acontant0;
2955   uint32_t  avfs_meannsigma_acontant1;
2956   uint32_t  avfs_meannsigma_acontant2;
2957   uint16_t  avfs_meannsigma_dc_tol_sigma;
2958   uint16_t  avfs_meannsigma_platform_mean;
2959   uint16_t  avfs_meannsigma_platform_sigma;
2960   uint32_t  gb_vdroop_table_cksoff_a0;
2961   uint32_t  gb_vdroop_table_cksoff_a1;
2962   uint32_t  gb_vdroop_table_cksoff_a2;
2963   uint32_t  gb_vdroop_table_ckson_a0;
2964   uint32_t  gb_vdroop_table_ckson_a1;
2965   uint32_t  gb_vdroop_table_ckson_a2;
2966   uint32_t  avfsgb_fuse_table_cksoff_m1;
2967   uint32_t  avfsgb_fuse_table_cksoff_m2;
2968   uint32_t  avfsgb_fuse_table_cksoff_b;
2969   uint32_t  avfsgb_fuse_table_ckson_m1;
2970   uint32_t  avfsgb_fuse_table_ckson_m2;
2971   uint32_t  avfsgb_fuse_table_ckson_b;
2972   uint16_t  max_voltage_0_25mv;
2973   uint8_t   enable_gb_vdroop_table_cksoff;
2974   uint8_t   enable_gb_vdroop_table_ckson;
2975   uint8_t   enable_gb_fuse_table_cksoff;
2976   uint8_t   enable_gb_fuse_table_ckson;
2977   uint16_t  psm_age_comfactor;
2978   uint8_t   enable_apply_avfs_cksoff_voltage;
2979   uint8_t   reserved;
2980   uint32_t  dispclk2gfxclk_a;
2981   uint32_t  dispclk2gfxclk_b;
2982   uint32_t  dispclk2gfxclk_c;
2983   uint32_t  pixclk2gfxclk_a;
2984   uint32_t  pixclk2gfxclk_b;
2985   uint32_t  pixclk2gfxclk_c;
2986   uint32_t  dcefclk2gfxclk_a;
2987   uint32_t  dcefclk2gfxclk_b;
2988   uint32_t  dcefclk2gfxclk_c;
2989   uint32_t  phyclk2gfxclk_a;
2990   uint32_t  phyclk2gfxclk_b;
2991   uint32_t  phyclk2gfxclk_c;
2992 };
2993 
2994 struct  atom_asic_profiling_info_v4_2 {
2995 	struct  atom_common_table_header  table_header;
2996 	uint32_t  maxvddc;
2997 	uint32_t  minvddc;
2998 	uint32_t  avfs_meannsigma_acontant0;
2999 	uint32_t  avfs_meannsigma_acontant1;
3000 	uint32_t  avfs_meannsigma_acontant2;
3001 	uint16_t  avfs_meannsigma_dc_tol_sigma;
3002 	uint16_t  avfs_meannsigma_platform_mean;
3003 	uint16_t  avfs_meannsigma_platform_sigma;
3004 	uint32_t  gb_vdroop_table_cksoff_a0;
3005 	uint32_t  gb_vdroop_table_cksoff_a1;
3006 	uint32_t  gb_vdroop_table_cksoff_a2;
3007 	uint32_t  gb_vdroop_table_ckson_a0;
3008 	uint32_t  gb_vdroop_table_ckson_a1;
3009 	uint32_t  gb_vdroop_table_ckson_a2;
3010 	uint32_t  avfsgb_fuse_table_cksoff_m1;
3011 	uint32_t  avfsgb_fuse_table_cksoff_m2;
3012 	uint32_t  avfsgb_fuse_table_cksoff_b;
3013 	uint32_t  avfsgb_fuse_table_ckson_m1;
3014 	uint32_t  avfsgb_fuse_table_ckson_m2;
3015 	uint32_t  avfsgb_fuse_table_ckson_b;
3016 	uint16_t  max_voltage_0_25mv;
3017 	uint8_t   enable_gb_vdroop_table_cksoff;
3018 	uint8_t   enable_gb_vdroop_table_ckson;
3019 	uint8_t   enable_gb_fuse_table_cksoff;
3020 	uint8_t   enable_gb_fuse_table_ckson;
3021 	uint16_t  psm_age_comfactor;
3022 	uint8_t   enable_apply_avfs_cksoff_voltage;
3023 	uint8_t   reserved;
3024 	uint32_t  dispclk2gfxclk_a;
3025 	uint32_t  dispclk2gfxclk_b;
3026 	uint32_t  dispclk2gfxclk_c;
3027 	uint32_t  pixclk2gfxclk_a;
3028 	uint32_t  pixclk2gfxclk_b;
3029 	uint32_t  pixclk2gfxclk_c;
3030 	uint32_t  dcefclk2gfxclk_a;
3031 	uint32_t  dcefclk2gfxclk_b;
3032 	uint32_t  dcefclk2gfxclk_c;
3033 	uint32_t  phyclk2gfxclk_a;
3034 	uint32_t  phyclk2gfxclk_b;
3035 	uint32_t  phyclk2gfxclk_c;
3036 	uint32_t  acg_gb_vdroop_table_a0;
3037 	uint32_t  acg_gb_vdroop_table_a1;
3038 	uint32_t  acg_gb_vdroop_table_a2;
3039 	uint32_t  acg_avfsgb_fuse_table_m1;
3040 	uint32_t  acg_avfsgb_fuse_table_m2;
3041 	uint32_t  acg_avfsgb_fuse_table_b;
3042 	uint8_t   enable_acg_gb_vdroop_table;
3043 	uint8_t   enable_acg_gb_fuse_table;
3044 	uint32_t  acg_dispclk2gfxclk_a;
3045 	uint32_t  acg_dispclk2gfxclk_b;
3046 	uint32_t  acg_dispclk2gfxclk_c;
3047 	uint32_t  acg_pixclk2gfxclk_a;
3048 	uint32_t  acg_pixclk2gfxclk_b;
3049 	uint32_t  acg_pixclk2gfxclk_c;
3050 	uint32_t  acg_dcefclk2gfxclk_a;
3051 	uint32_t  acg_dcefclk2gfxclk_b;
3052 	uint32_t  acg_dcefclk2gfxclk_c;
3053 	uint32_t  acg_phyclk2gfxclk_a;
3054 	uint32_t  acg_phyclk2gfxclk_b;
3055 	uint32_t  acg_phyclk2gfxclk_c;
3056 };
3057 
3058 /*
3059   ***************************************************************************
3060     Data Table multimedia_info  structure
3061   ***************************************************************************
3062 */
3063 struct atom_multimedia_info_v2_1
3064 {
3065   struct  atom_common_table_header  table_header;
3066   uint8_t uvdip_min_ver;
3067   uint8_t uvdip_max_ver;
3068   uint8_t vceip_min_ver;
3069   uint8_t vceip_max_ver;
3070   uint16_t uvd_enc_max_input_width_pixels;
3071   uint16_t uvd_enc_max_input_height_pixels;
3072   uint16_t vce_enc_max_input_width_pixels;
3073   uint16_t vce_enc_max_input_height_pixels;
3074   uint32_t uvd_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
3075   uint32_t vce_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
3076 };
3077 
3078 
3079 /*
3080   ***************************************************************************
3081     Data Table umc_info  structure
3082   ***************************************************************************
3083 */
3084 struct atom_umc_info_v3_1
3085 {
3086   struct  atom_common_table_header  table_header;
3087   uint32_t ucode_version;
3088   uint32_t ucode_rom_startaddr;
3089   uint32_t ucode_length;
3090   uint16_t umc_reg_init_offset;
3091   uint16_t customer_ucode_name_offset;
3092   uint16_t mclk_ss_percentage;
3093   uint16_t mclk_ss_rate_10hz;
3094   uint8_t umcip_min_ver;
3095   uint8_t umcip_max_ver;
3096   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3097   uint8_t umc_config;
3098   uint32_t mem_refclk_10khz;
3099 };
3100 
3101 // umc_info.umc_config
3102 enum atom_umc_config_def {
3103   UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE  =   0x00000001,
3104   UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE      =   0x00000002,
3105   UMC_CONFIG__ENABLE_HBM_LANE_REPAIR      =   0x00000004,
3106   UMC_CONFIG__ENABLE_BANK_HARVESTING      =   0x00000008,
3107   UMC_CONFIG__ENABLE_PHY_REINIT           =   0x00000010,
3108   UMC_CONFIG__DISABLE_UCODE_CHKSTATUS     =   0x00000020,
3109 };
3110 
3111 struct atom_umc_info_v3_2
3112 {
3113   struct  atom_common_table_header  table_header;
3114   uint32_t ucode_version;
3115   uint32_t ucode_rom_startaddr;
3116   uint32_t ucode_length;
3117   uint16_t umc_reg_init_offset;
3118   uint16_t customer_ucode_name_offset;
3119   uint16_t mclk_ss_percentage;
3120   uint16_t mclk_ss_rate_10hz;
3121   uint8_t umcip_min_ver;
3122   uint8_t umcip_max_ver;
3123   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3124   uint8_t umc_config;
3125   uint32_t mem_refclk_10khz;
3126   uint32_t pstate_uclk_10khz[4];
3127   uint16_t umcgoldenoffset;
3128   uint16_t densitygoldenoffset;
3129 };
3130 
3131 struct atom_umc_info_v3_3
3132 {
3133   struct  atom_common_table_header  table_header;
3134   uint32_t ucode_reserved;
3135   uint32_t ucode_rom_startaddr;
3136   uint32_t ucode_length;
3137   uint16_t umc_reg_init_offset;
3138   uint16_t customer_ucode_name_offset;
3139   uint16_t mclk_ss_percentage;
3140   uint16_t mclk_ss_rate_10hz;
3141   uint8_t umcip_min_ver;
3142   uint8_t umcip_max_ver;
3143   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3144   uint8_t umc_config;
3145   uint32_t mem_refclk_10khz;
3146   uint32_t pstate_uclk_10khz[4];
3147   uint16_t umcgoldenoffset;
3148   uint16_t densitygoldenoffset;
3149   uint32_t umc_config1;
3150   uint32_t bist_data_startaddr;
3151   uint32_t reserved[2];
3152 };
3153 
3154 enum atom_umc_config1_def {
3155 	UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
3156 	UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
3157 	UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
3158 	UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
3159 	UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
3160 	UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
3161 };
3162 
3163 struct atom_umc_info_v4_0 {
3164 	struct atom_common_table_header table_header;
3165 	uint32_t ucode_reserved[5];
3166 	uint8_t umcip_min_ver;
3167 	uint8_t umcip_max_ver;
3168 	uint8_t vram_type;
3169 	uint8_t umc_config;
3170 	uint32_t mem_refclk_10khz;
3171 	uint32_t clk_reserved[4];
3172 	uint32_t golden_reserved;
3173 	uint32_t umc_config1;
3174 	uint32_t reserved[2];
3175 	uint8_t channel_num;
3176 	uint8_t channel_width;
3177 	uint8_t channel_reserve[2];
3178 	uint8_t umc_info_reserved[16];
3179 };
3180 
3181 /*
3182   ***************************************************************************
3183     Data Table vram_info  structure
3184   ***************************************************************************
3185 */
3186 struct atom_vram_module_v9 {
3187   // Design Specific Values
3188   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3189   uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3190   uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3191   uint16_t  reserved[3];
3192   uint16_t  mem_voltage;                   // mem_voltage
3193   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3194   uint8_t   ext_memory_id;                 // Current memory module ID
3195   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3196   uint8_t   channel_num;                   // Number of mem. channels supported in this module
3197   uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3198   uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3199   uint8_t   tunningset_id;                 // MC phy registers set per.
3200   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3201   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3202   uint8_t   hbm_ven_rev_id;		   // hbm_ven_rev_id
3203   uint8_t   vram_rsd2;			   // reserved
3204   char    dram_pnstring[20];               // part number end with '0'.
3205 };
3206 
3207 struct atom_vram_info_header_v2_3 {
3208   struct   atom_common_table_header table_header;
3209   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3210   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3211   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3212   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3213   uint16_t dram_data_remap_tbloffset;                    // reserved for now
3214   uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
3215   uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3216   uint16_t vram_rsd2;
3217   uint8_t  vram_module_num;                              // indicate number of VRAM module
3218   uint8_t  umcip_min_ver;
3219   uint8_t  umcip_max_ver;
3220   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3221   struct   atom_vram_module_v9  vram_module[16];         // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3222 };
3223 
3224 /*
3225   ***************************************************************************
3226     Data Table vram_info v3.0  structure
3227   ***************************************************************************
3228 */
3229 struct atom_vram_module_v3_0 {
3230 	uint8_t density;
3231 	uint8_t tunningset_id;
3232 	uint8_t ext_memory_id;
3233 	uint8_t dram_vendor_id;
3234 	uint16_t dram_info_offset;
3235 	uint16_t mem_tuning_offset;
3236 	uint16_t tmrs_seq_offset;
3237 	uint16_t reserved1;
3238 	uint32_t dram_size_per_ch;
3239 	uint32_t reserved[3];
3240 	char dram_pnstring[40];
3241 };
3242 
3243 struct atom_vram_info_header_v3_0 {
3244 	struct atom_common_table_header table_header;
3245 	uint16_t mem_tuning_table_offset;
3246 	uint16_t dram_info_table_offset;
3247 	uint16_t tmrs_table_offset;
3248 	uint16_t mc_init_table_offset;
3249 	uint16_t dram_data_remap_table_offset;
3250 	uint16_t umc_emuinittable_offset;
3251 	uint16_t reserved_sub_table_offset[2];
3252 	uint8_t vram_module_num;
3253 	uint8_t umcip_min_ver;
3254 	uint8_t umcip_max_ver;
3255 	uint8_t mc_phy_tile_num;
3256 	uint8_t memory_type;
3257 	uint8_t channel_num;
3258 	uint8_t channel_width;
3259 	uint8_t reserved1;
3260 	uint32_t channel_enable;
3261 	uint32_t channel1_enable;
3262 	uint32_t feature_enable;
3263 	uint32_t feature1_enable;
3264 	uint32_t hardcode_mem_size;
3265 	uint32_t reserved4[4];
3266 	struct atom_vram_module_v3_0 vram_module[8];
3267 };
3268 
3269 struct atom_umc_register_addr_info{
3270   uint32_t  umc_register_addr:24;
3271   uint32_t  umc_reg_type_ind:1;
3272   uint32_t  umc_reg_rsvd:7;
3273 };
3274 
3275 //atom_umc_register_addr_info.
3276 enum atom_umc_register_addr_info_flag{
3277   b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS  =0x01,
3278 };
3279 
3280 union atom_umc_register_addr_info_access
3281 {
3282   struct atom_umc_register_addr_info umc_reg_addr;
3283   uint32_t u32umc_reg_addr;
3284 };
3285 
3286 struct atom_umc_reg_setting_id_config{
3287   uint32_t memclockrange:24;
3288   uint32_t mem_blk_id:8;
3289 };
3290 
3291 union atom_umc_reg_setting_id_config_access
3292 {
3293   struct atom_umc_reg_setting_id_config umc_id_access;
3294   uint32_t  u32umc_id_access;
3295 };
3296 
3297 struct atom_umc_reg_setting_data_block{
3298   union atom_umc_reg_setting_id_config_access  block_id;
3299   uint32_t u32umc_reg_data[1];
3300 };
3301 
3302 struct atom_umc_init_reg_block{
3303   uint16_t umc_reg_num;
3304   uint16_t reserved;
3305   union atom_umc_register_addr_info_access umc_reg_list[1];     //for allocation purpose, the real number come from umc_reg_num;
3306   struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
3307 };
3308 
3309 struct atom_vram_module_v10 {
3310   // Design Specific Values
3311   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3312   uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3313   uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3314   uint16_t  reserved[3];
3315   uint16_t  mem_voltage;                   // mem_voltage
3316   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3317   uint8_t   ext_memory_id;                 // Current memory module ID
3318   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3319   uint8_t   channel_num;                   // Number of mem. channels supported in this module
3320   uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3321   uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3322   uint8_t   tunningset_id;                 // MC phy registers set per
3323   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3324   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3325   uint8_t   vram_flags;			   // bit0= bankgroup enable
3326   uint8_t   vram_rsd2;			   // reserved
3327   uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
3328   uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
3329   uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
3330   uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
3331   char    dram_pnstring[20];               // part number end with '0'
3332 };
3333 
3334 struct atom_vram_info_header_v2_4 {
3335   struct   atom_common_table_header table_header;
3336   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3337   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3338   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3339   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3340   uint16_t dram_data_remap_tbloffset;                    // reserved for now
3341   uint16_t reserved;                                     // offset of reserved
3342   uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3343   uint16_t vram_rsd2;
3344   uint8_t  vram_module_num;                              // indicate number of VRAM module
3345   uint8_t  umcip_min_ver;
3346   uint8_t  umcip_max_ver;
3347   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3348   struct   atom_vram_module_v10  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3349 };
3350 
3351 struct atom_vram_module_v11 {
3352 	// Design Specific Values
3353 	uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3354 	uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3355 	uint16_t  mem_voltage;                   // mem_voltage
3356 	uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3357 	uint8_t   ext_memory_id;                 // Current memory module ID
3358 	uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3359 	uint8_t   channel_num;                   // Number of mem. channels supported in this module
3360 	uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3361 	uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3362 	uint8_t   tunningset_id;                 // MC phy registers set per.
3363 	uint16_t  reserved[4];                   // reserved
3364 	uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3365 	uint8_t   refreshrate;			 // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3366 	uint8_t   vram_flags;			 // bit0= bankgroup enable
3367 	uint8_t   vram_rsd2;			 // reserved
3368 	uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
3369 	uint16_t  gddr6_mr0;                     // gddr6 mode register0 value
3370 	uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
3371 	uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
3372 	uint16_t  gddr6_mr4;                     // gddr6 mode register4 value
3373 	uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
3374 	uint16_t  gddr6_mr8;                     // gddr6 mode register8 value
3375 	char    dram_pnstring[40];               // part number end with '0'.
3376 };
3377 
3378 struct atom_gddr6_ac_timing_v2_5 {
3379 	uint32_t  u32umc_id_access;
3380 	uint8_t  RL;
3381 	uint8_t  WL;
3382 	uint8_t  tRAS;
3383 	uint8_t  tRC;
3384 
3385 	uint16_t  tREFI;
3386 	uint8_t  tRFC;
3387 	uint8_t  tRFCpb;
3388 
3389 	uint8_t  tRREFD;
3390 	uint8_t  tRCDRD;
3391 	uint8_t  tRCDWR;
3392 	uint8_t  tRP;
3393 
3394 	uint8_t  tRRDS;
3395 	uint8_t  tRRDL;
3396 	uint8_t  tWR;
3397 	uint8_t  tWTRS;
3398 
3399 	uint8_t  tWTRL;
3400 	uint8_t  tFAW;
3401 	uint8_t  tCCDS;
3402 	uint8_t  tCCDL;
3403 
3404 	uint8_t  tCRCRL;
3405 	uint8_t  tCRCWL;
3406 	uint8_t  tCKE;
3407 	uint8_t  tCKSRE;
3408 
3409 	uint8_t  tCKSRX;
3410 	uint8_t  tRTPS;
3411 	uint8_t  tRTPL;
3412 	uint8_t  tMRD;
3413 
3414 	uint8_t  tMOD;
3415 	uint8_t  tXS;
3416 	uint8_t  tXHP;
3417 	uint8_t  tXSMRS;
3418 
3419 	uint32_t  tXSH;
3420 
3421 	uint8_t  tPD;
3422 	uint8_t  tXP;
3423 	uint8_t  tCPDED;
3424 	uint8_t  tACTPDE;
3425 
3426 	uint8_t  tPREPDE;
3427 	uint8_t  tREFPDE;
3428 	uint8_t  tMRSPDEN;
3429 	uint8_t  tRDSRE;
3430 
3431 	uint8_t  tWRSRE;
3432 	uint8_t  tPPD;
3433 	uint8_t  tCCDMW;
3434 	uint8_t  tWTRTR;
3435 
3436 	uint8_t  tLTLTR;
3437 	uint8_t  tREFTR;
3438 	uint8_t  VNDR;
3439 	uint8_t  reserved[9];
3440 };
3441 
3442 struct atom_gddr6_bit_byte_remap {
3443 	uint32_t dphy_byteremap;    //mmUMC_DPHY_ByteRemap
3444 	uint32_t dphy_bitremap0;    //mmUMC_DPHY_BitRemap0
3445 	uint32_t dphy_bitremap1;    //mmUMC_DPHY_BitRemap1
3446 	uint32_t dphy_bitremap2;    //mmUMC_DPHY_BitRemap2
3447 	uint32_t aphy_bitremap0;    //mmUMC_APHY_BitRemap0
3448 	uint32_t aphy_bitremap1;    //mmUMC_APHY_BitRemap1
3449 	uint32_t phy_dram;          //mmUMC_PHY_DRAM
3450 };
3451 
3452 struct atom_gddr6_dram_data_remap {
3453 	uint32_t table_size;
3454 	uint8_t phyintf_ck_inverted[8];     //UMC_PHY_PHYINTF_CNTL.INV_CK
3455 	struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
3456 };
3457 
3458 struct atom_vram_info_header_v2_5 {
3459 	struct   atom_common_table_header table_header;
3460 	uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
3461 	uint16_t gddr6_ac_timing_offset;                     // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
3462 	uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3463 	uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3464 	uint16_t dram_data_remap_tbloffset;                    // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
3465 	uint16_t reserved;                                     // offset of reserved
3466 	uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3467 	uint16_t strobe_mode_patch_tbloffset;                  // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
3468 	uint8_t  vram_module_num;                              // indicate number of VRAM module
3469 	uint8_t  umcip_min_ver;
3470 	uint8_t  umcip_max_ver;
3471 	uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3472 	struct   atom_vram_module_v11  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3473 };
3474 
3475 struct atom_vram_info_header_v2_6 {
3476 	struct atom_common_table_header table_header;
3477 	uint16_t mem_adjust_tbloffset;
3478 	uint16_t mem_clk_patch_tbloffset;
3479 	uint16_t mc_adjust_pertile_tbloffset;
3480 	uint16_t mc_phyinit_tbloffset;
3481 	uint16_t dram_data_remap_tbloffset;
3482 	uint16_t tmrs_seq_offset;
3483 	uint16_t post_ucode_init_offset;
3484 	uint16_t vram_rsd2;
3485 	uint8_t  vram_module_num;
3486 	uint8_t  umcip_min_ver;
3487 	uint8_t  umcip_max_ver;
3488 	uint8_t  mc_phy_tile_num;
3489 	struct atom_vram_module_v9 vram_module[16];
3490 };
3491 /*
3492   ***************************************************************************
3493     Data Table voltageobject_info  structure
3494   ***************************************************************************
3495 */
3496 struct  atom_i2c_data_entry
3497 {
3498   uint16_t  i2c_reg_index;               // i2c register address, can be up to 16bit
3499   uint16_t  i2c_reg_data;                // i2c register data, can be up to 16bit
3500 };
3501 
3502 struct atom_voltage_object_header_v4{
3503   uint8_t    voltage_type;                           //enum atom_voltage_type
3504   uint8_t    voltage_mode;                           //enum atom_voltage_object_mode
3505   uint16_t   object_size;                            //Size of Object
3506 };
3507 
3508 // atom_voltage_object_header_v4.voltage_mode
3509 enum atom_voltage_object_mode
3510 {
3511    VOLTAGE_OBJ_GPIO_LUT              =  0,        //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
3512    VOLTAGE_OBJ_VR_I2C_INIT_SEQ       =  3,        //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
3513    VOLTAGE_OBJ_PHASE_LUT             =  4,        //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
3514    VOLTAGE_OBJ_SVID2                 =  7,        //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
3515    VOLTAGE_OBJ_EVV                   =  8,
3516    VOLTAGE_OBJ_MERGED_POWER          =  9,
3517 };
3518 
3519 struct  atom_i2c_voltage_object_v4
3520 {
3521    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
3522    uint8_t  regulator_id;                        //Indicate Voltage Regulator Id
3523    uint8_t  i2c_id;
3524    uint8_t  i2c_slave_addr;
3525    uint8_t  i2c_control_offset;
3526    uint8_t  i2c_flag;                            // Bit0: 0 - One byte data; 1 - Two byte data
3527    uint8_t  i2c_speed;                           // =0, use default i2c speed, otherwise use it in unit of kHz.
3528    uint8_t  reserved[2];
3529    struct atom_i2c_data_entry i2cdatalut[1];     // end with 0xff
3530 };
3531 
3532 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
3533 enum atom_i2c_voltage_control_flag
3534 {
3535    VOLTAGE_DATA_ONE_BYTE = 0,
3536    VOLTAGE_DATA_TWO_BYTE = 1,
3537 };
3538 
3539 
3540 struct atom_voltage_gpio_map_lut
3541 {
3542   uint32_t  voltage_gpio_reg_val;              // The Voltage ID which is used to program GPIO register
3543   uint16_t  voltage_level_mv;                  // The corresponding Voltage Value, in mV
3544 };
3545 
3546 struct atom_gpio_voltage_object_v4
3547 {
3548    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
3549    uint8_t  gpio_control_id;                     // default is 0 which indicate control through CG VID mode
3550    uint8_t  gpio_entry_num;                      // indiate the entry numbers of Votlage/Gpio value Look up table
3551    uint8_t  phase_delay_us;                      // phase delay in unit of micro second
3552    uint8_t  reserved;
3553    uint32_t gpio_mask_val;                         // GPIO Mask value
3554    struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
3555 };
3556 
3557 struct  atom_svid2_voltage_object_v4
3558 {
3559    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_SVID2
3560    uint8_t loadline_psi1;                        // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3561    uint8_t psi0_l_vid_thresd;                    // VR PSI0_L VID threshold
3562    uint8_t psi0_enable;                          //
3563    uint8_t maxvstep;
3564    uint8_t telemetry_offset;
3565    uint8_t telemetry_gain;
3566    uint16_t reserved1;
3567 };
3568 
3569 struct atom_merged_voltage_object_v4
3570 {
3571   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_MERGED_POWER
3572   uint8_t  merged_powerrail_type;               //enum atom_voltage_type
3573   uint8_t  reserved[3];
3574 };
3575 
3576 union atom_voltage_object_v4{
3577   struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
3578   struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
3579   struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
3580   struct atom_merged_voltage_object_v4 merged_voltage_obj;
3581 };
3582 
3583 struct  atom_voltage_objects_info_v4_1
3584 {
3585   struct atom_common_table_header table_header;
3586   union atom_voltage_object_v4 voltage_object[1];   //Info for Voltage control
3587 };
3588 
3589 
3590 /*
3591   ***************************************************************************
3592               All Command Function structure definition
3593   ***************************************************************************
3594 */
3595 
3596 /*
3597   ***************************************************************************
3598               Structures used by asic_init
3599   ***************************************************************************
3600 */
3601 
3602 struct asic_init_engine_parameters
3603 {
3604   uint32_t sclkfreqin10khz:24;
3605   uint32_t engineflag:8;              /* enum atom_asic_init_engine_flag  */
3606 };
3607 
3608 struct asic_init_mem_parameters
3609 {
3610   uint32_t mclkfreqin10khz:24;
3611   uint32_t memflag:8;                 /* enum atom_asic_init_mem_flag  */
3612 };
3613 
3614 struct asic_init_parameters_v2_1
3615 {
3616   struct asic_init_engine_parameters engineparam;
3617   struct asic_init_mem_parameters memparam;
3618 };
3619 
3620 struct asic_init_ps_allocation_v2_1
3621 {
3622   struct asic_init_parameters_v2_1 param;
3623   uint32_t reserved[16];
3624 };
3625 
3626 
3627 enum atom_asic_init_engine_flag
3628 {
3629   b3NORMAL_ENGINE_INIT = 0,
3630   b3SRIOV_SKIP_ASIC_INIT = 0x02,
3631   b3SRIOV_LOAD_UCODE = 0x40,
3632 };
3633 
3634 enum atom_asic_init_mem_flag
3635 {
3636   b3NORMAL_MEM_INIT = 0,
3637   b3DRAM_SELF_REFRESH_EXIT =0x20,
3638 };
3639 
3640 /*
3641   ***************************************************************************
3642               Structures used by setengineclock
3643   ***************************************************************************
3644 */
3645 
3646 struct set_engine_clock_parameters_v2_1
3647 {
3648   uint32_t sclkfreqin10khz:24;
3649   uint32_t sclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3650   uint32_t reserved[10];
3651 };
3652 
3653 struct set_engine_clock_ps_allocation_v2_1
3654 {
3655   struct set_engine_clock_parameters_v2_1 clockinfo;
3656   uint32_t reserved[10];
3657 };
3658 
3659 
3660 enum atom_set_engine_mem_clock_flag
3661 {
3662   b3NORMAL_CHANGE_CLOCK = 0,
3663   b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3664   b3STORE_DPM_TRAINGING = 0x40,         //Applicable to memory clock change,when set, it store specific DPM mode training result
3665 };
3666 
3667 /*
3668   ***************************************************************************
3669               Structures used by getengineclock
3670   ***************************************************************************
3671 */
3672 struct get_engine_clock_parameter
3673 {
3674   uint32_t sclk_10khz;          // current engine speed in 10KHz unit
3675   uint32_t reserved;
3676 };
3677 
3678 /*
3679   ***************************************************************************
3680               Structures used by setmemoryclock
3681   ***************************************************************************
3682 */
3683 struct set_memory_clock_parameters_v2_1
3684 {
3685   uint32_t mclkfreqin10khz:24;
3686   uint32_t mclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3687   uint32_t reserved[10];
3688 };
3689 
3690 struct set_memory_clock_ps_allocation_v2_1
3691 {
3692   struct set_memory_clock_parameters_v2_1 clockinfo;
3693   uint32_t reserved[10];
3694 };
3695 
3696 
3697 /*
3698   ***************************************************************************
3699               Structures used by getmemoryclock
3700   ***************************************************************************
3701 */
3702 struct get_memory_clock_parameter
3703 {
3704   uint32_t mclk_10khz;          // current engine speed in 10KHz unit
3705   uint32_t reserved;
3706 };
3707 
3708 
3709 
3710 /*
3711   ***************************************************************************
3712               Structures used by setvoltage
3713   ***************************************************************************
3714 */
3715 
3716 struct set_voltage_parameters_v1_4
3717 {
3718   uint8_t  voltagetype;                /* enum atom_voltage_type */
3719   uint8_t  command;                    /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3720   uint16_t vlevel_mv;                  /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
3721 };
3722 
3723 //set_voltage_parameters_v2_1.voltagemode
3724 enum atom_set_voltage_command{
3725   ATOM_SET_VOLTAGE  = 0,
3726   ATOM_INIT_VOLTAGE_REGULATOR = 3,
3727   ATOM_SET_VOLTAGE_PHASE = 4,
3728   ATOM_GET_LEAKAGE_ID    = 8,
3729 };
3730 
3731 struct set_voltage_ps_allocation_v1_4
3732 {
3733   struct set_voltage_parameters_v1_4 setvoltageparam;
3734   uint32_t reserved[10];
3735 };
3736 
3737 
3738 /*
3739   ***************************************************************************
3740               Structures used by computegpuclockparam
3741   ***************************************************************************
3742 */
3743 
3744 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
3745 enum atom_gpu_clock_type
3746 {
3747   COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3748   COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3749   COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3750 };
3751 
3752 struct compute_gpu_clock_input_parameter_v1_8
3753 {
3754   uint32_t  gpuclock_10khz:24;         //Input= target clock, output = actual clock
3755   uint32_t  gpu_clock_type:8;          //Input indicate clock type: enum atom_gpu_clock_type
3756   uint32_t  reserved[5];
3757 };
3758 
3759 
3760 struct compute_gpu_clock_output_parameter_v1_8
3761 {
3762   uint32_t  gpuclock_10khz:24;              //Input= target clock, output = actual clock
3763   uint32_t  dfs_did:8;                      //return parameter: DFS divider which is used to program to register directly
3764   uint32_t  pll_fb_mult;                    //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3765   uint32_t  pll_ss_fbsmult;                 // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3766   uint16_t  pll_ss_slew_frac;
3767   uint8_t   pll_ss_enable;
3768   uint8_t   reserved;
3769   uint32_t  reserved1[2];
3770 };
3771 
3772 
3773 
3774 /*
3775   ***************************************************************************
3776               Structures used by ReadEfuseValue
3777   ***************************************************************************
3778 */
3779 
3780 struct read_efuse_input_parameters_v3_1
3781 {
3782   uint16_t efuse_start_index;
3783   uint8_t  reserved;
3784   uint8_t  bitslen;
3785 };
3786 
3787 // ReadEfuseValue input/output parameter
3788 union read_efuse_value_parameters_v3_1
3789 {
3790   struct read_efuse_input_parameters_v3_1 efuse_info;
3791   uint32_t efusevalue;
3792 };
3793 
3794 
3795 /*
3796   ***************************************************************************
3797               Structures used by getsmuclockinfo
3798   ***************************************************************************
3799 */
3800 struct atom_get_smu_clock_info_parameters_v3_1
3801 {
3802   uint8_t syspll_id;          // 0= syspll0, 1=syspll1, 2=syspll2
3803   uint8_t clk_id;             // atom_smu9_syspll0_clock_id  (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3804   uint8_t command;            // enum of atom_get_smu_clock_info_command
3805   uint8_t dfsdid;             // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3806 };
3807 
3808 enum atom_get_smu_clock_info_command
3809 {
3810   GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ       = 0,
3811   GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ      = 1,
3812   GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ   = 2,
3813 };
3814 
3815 enum atom_smu9_syspll0_clock_id
3816 {
3817   SMU9_SYSPLL0_SMNCLK_ID   = 0,       //  SMNCLK
3818   SMU9_SYSPLL0_SOCCLK_ID   = 1,       //	SOCCLK (FCLK)
3819   SMU9_SYSPLL0_MP0CLK_ID   = 2,       //	MP0CLK
3820   SMU9_SYSPLL0_MP1CLK_ID   = 3,       //	MP1CLK
3821   SMU9_SYSPLL0_LCLK_ID     = 4,       //	LCLK
3822   SMU9_SYSPLL0_DCLK_ID     = 5,       //	DCLK
3823   SMU9_SYSPLL0_VCLK_ID     = 6,       //	VCLK
3824   SMU9_SYSPLL0_ECLK_ID     = 7,       //	ECLK
3825   SMU9_SYSPLL0_DCEFCLK_ID  = 8,       //	DCEFCLK
3826   SMU9_SYSPLL0_DPREFCLK_ID = 10,      //	DPREFCLK
3827   SMU9_SYSPLL0_DISPCLK_ID  = 11,      //	DISPCLK
3828 };
3829 
3830 enum atom_smu11_syspll_id {
3831   SMU11_SYSPLL0_ID            = 0,
3832   SMU11_SYSPLL1_0_ID          = 1,
3833   SMU11_SYSPLL1_1_ID          = 2,
3834   SMU11_SYSPLL1_2_ID          = 3,
3835   SMU11_SYSPLL2_ID            = 4,
3836   SMU11_SYSPLL3_0_ID          = 5,
3837   SMU11_SYSPLL3_1_ID          = 6,
3838 };
3839 
3840 enum atom_smu11_syspll0_clock_id {
3841   SMU11_SYSPLL0_ECLK_ID     = 0,       //	ECLK
3842   SMU11_SYSPLL0_SOCCLK_ID   = 1,       //	SOCCLK
3843   SMU11_SYSPLL0_MP0CLK_ID   = 2,       //	MP0CLK
3844   SMU11_SYSPLL0_DCLK_ID     = 3,       //	DCLK
3845   SMU11_SYSPLL0_VCLK_ID     = 4,       //	VCLK
3846   SMU11_SYSPLL0_DCEFCLK_ID  = 5,       //	DCEFCLK
3847 };
3848 
3849 enum atom_smu11_syspll1_0_clock_id {
3850   SMU11_SYSPLL1_0_UCLKA_ID   = 0,       // UCLK_a
3851 };
3852 
3853 enum atom_smu11_syspll1_1_clock_id {
3854   SMU11_SYSPLL1_0_UCLKB_ID   = 0,       // UCLK_b
3855 };
3856 
3857 enum atom_smu11_syspll1_2_clock_id {
3858   SMU11_SYSPLL1_0_FCLK_ID   = 0,        // FCLK
3859 };
3860 
3861 enum atom_smu11_syspll2_clock_id {
3862   SMU11_SYSPLL2_GFXCLK_ID   = 0,        // GFXCLK
3863 };
3864 
3865 enum atom_smu11_syspll3_0_clock_id {
3866   SMU11_SYSPLL3_0_WAFCLK_ID = 0,       //	WAFCLK
3867   SMU11_SYSPLL3_0_DISPCLK_ID = 1,      //	DISPCLK
3868   SMU11_SYSPLL3_0_DPREFCLK_ID = 2,     //	DPREFCLK
3869 };
3870 
3871 enum atom_smu11_syspll3_1_clock_id {
3872   SMU11_SYSPLL3_1_MP1CLK_ID = 0,       //	MP1CLK
3873   SMU11_SYSPLL3_1_SMNCLK_ID = 1,       //	SMNCLK
3874   SMU11_SYSPLL3_1_LCLK_ID = 2,         //	LCLK
3875 };
3876 
3877 enum atom_smu12_syspll_id {
3878   SMU12_SYSPLL0_ID          = 0,
3879   SMU12_SYSPLL1_ID          = 1,
3880   SMU12_SYSPLL2_ID          = 2,
3881   SMU12_SYSPLL3_0_ID        = 3,
3882   SMU12_SYSPLL3_1_ID        = 4,
3883 };
3884 
3885 enum atom_smu12_syspll0_clock_id {
3886   SMU12_SYSPLL0_SMNCLK_ID   = 0,			//	SOCCLK
3887   SMU12_SYSPLL0_SOCCLK_ID   = 1,			//	SOCCLK
3888   SMU12_SYSPLL0_MP0CLK_ID   = 2,			//	MP0CLK
3889   SMU12_SYSPLL0_MP1CLK_ID   = 3,			//	MP1CLK
3890   SMU12_SYSPLL0_MP2CLK_ID   = 4,			//	MP2CLK
3891   SMU12_SYSPLL0_VCLK_ID     = 5,			//	VCLK
3892   SMU12_SYSPLL0_LCLK_ID     = 6,			//	LCLK
3893   SMU12_SYSPLL0_DCLK_ID     = 7,			//	DCLK
3894   SMU12_SYSPLL0_ACLK_ID     = 8,			//	ACLK
3895   SMU12_SYSPLL0_ISPCLK_ID   = 9,			//	ISPCLK
3896   SMU12_SYSPLL0_SHUBCLK_ID  = 10,			//	SHUBCLK
3897 };
3898 
3899 enum atom_smu12_syspll1_clock_id {
3900   SMU12_SYSPLL1_DISPCLK_ID  = 0,      //	DISPCLK
3901   SMU12_SYSPLL1_DPPCLK_ID   = 1,      //	DPPCLK
3902   SMU12_SYSPLL1_DPREFCLK_ID = 2,      //	DPREFCLK
3903   SMU12_SYSPLL1_DCFCLK_ID   = 3,      //	DCFCLK
3904 };
3905 
3906 enum atom_smu12_syspll2_clock_id {
3907   SMU12_SYSPLL2_Pre_GFXCLK_ID = 0,   // Pre_GFXCLK
3908 };
3909 
3910 enum atom_smu12_syspll3_0_clock_id {
3911   SMU12_SYSPLL3_0_FCLK_ID = 0,      //	FCLK
3912 };
3913 
3914 enum atom_smu12_syspll3_1_clock_id {
3915   SMU12_SYSPLL3_1_UMCCLK_ID = 0,    //	UMCCLK
3916 };
3917 
3918 struct  atom_get_smu_clock_info_output_parameters_v3_1
3919 {
3920   union {
3921     uint32_t smu_clock_freq_hz;
3922     uint32_t syspllvcofreq_10khz;
3923     uint32_t sysspllrefclk_10khz;
3924   }atom_smu_outputclkfreq;
3925 };
3926 
3927 
3928 
3929 /*
3930   ***************************************************************************
3931               Structures used by dynamicmemorysettings
3932   ***************************************************************************
3933 */
3934 
3935 enum atom_dynamic_memory_setting_command
3936 {
3937   COMPUTE_MEMORY_PLL_PARAM = 1,
3938   COMPUTE_ENGINE_PLL_PARAM = 2,
3939   ADJUST_MC_SETTING_PARAM = 3,
3940 };
3941 
3942 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3943 struct dynamic_mclk_settings_parameters_v2_1
3944 {
3945   uint32_t  mclk_10khz:24;         //Input= target mclk
3946   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3947   uint32_t  reserved;
3948 };
3949 
3950 /* when command = COMPUTE_ENGINE_PLL_PARAM */
3951 struct dynamic_sclk_settings_parameters_v2_1
3952 {
3953   uint32_t  sclk_10khz:24;         //Input= target mclk
3954   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3955   uint32_t  mclk_10khz;
3956   uint32_t  reserved;
3957 };
3958 
3959 union dynamic_memory_settings_parameters_v2_1
3960 {
3961   struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3962   struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3963 };
3964 
3965 
3966 
3967 /*
3968   ***************************************************************************
3969               Structures used by memorytraining
3970   ***************************************************************************
3971 */
3972 
3973 enum atom_umc6_0_ucode_function_call_enum_id
3974 {
3975   UMC60_UCODE_FUNC_ID_REINIT                 = 0,
3976   UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH      = 1,
3977   UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH       = 2,
3978 };
3979 
3980 
3981 struct memory_training_parameters_v2_1
3982 {
3983   uint8_t ucode_func_id;
3984   uint8_t ucode_reserved[3];
3985   uint32_t reserved[5];
3986 };
3987 
3988 
3989 /*
3990   ***************************************************************************
3991               Structures used by setpixelclock
3992   ***************************************************************************
3993 */
3994 
3995 struct set_pixel_clock_parameter_v1_7
3996 {
3997     uint32_t pixclk_100hz;               // target the pixel clock to drive the CRTC timing in unit of 100Hz.
3998 
3999     uint8_t  pll_id;                     // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
4000     uint8_t  encoderobjid;               // ASIC encoder id defined in objectId.h,
4001                                          // indicate which graphic encoder will be used.
4002     uint8_t  encoder_mode;               // Encoder mode:
4003     uint8_t  miscinfo;                   // enum atom_set_pixel_clock_v1_7_misc_info
4004     uint8_t  crtc_id;                    // enum of atom_crtc_def
4005     uint8_t  deep_color_ratio;           // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4006     uint8_t  reserved1[2];
4007     uint32_t reserved2;
4008 };
4009 
4010 //ucMiscInfo
4011 enum atom_set_pixel_clock_v1_7_misc_info
4012 {
4013   PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL         = 0x01,
4014   PIXEL_CLOCK_V7_MISC_PROG_PHYPLL             = 0x02,
4015   PIXEL_CLOCK_V7_MISC_YUV420_MODE             = 0x04,
4016   PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN         = 0x08,
4017   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC             = 0x30,
4018   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN      = 0x00,
4019   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE        = 0x10,
4020   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK       = 0x20,
4021   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD      = 0x30,
4022   PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE           = 0x40,
4023   PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS            = 0x80,
4024 };
4025 
4026 /* deep_color_ratio */
4027 enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4028 {
4029   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS          = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
4030   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4          = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
4031   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2          = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
4032   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1          = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
4033 };
4034 
4035 /*
4036   ***************************************************************************
4037               Structures used by setdceclock
4038   ***************************************************************************
4039 */
4040 
4041 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
4042 struct set_dce_clock_parameters_v2_1
4043 {
4044   uint32_t dceclk_10khz;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
4045   uint8_t  dceclktype;                                 // =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK
4046   uint8_t  dceclksrc;                                  // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
4047   uint8_t  dceclkflag;                                 // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
4048   uint8_t  crtc_id;                                    // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
4049 };
4050 
4051 //ucDCEClkType
4052 enum atom_set_dce_clock_clock_type
4053 {
4054   DCE_CLOCK_TYPE_DISPCLK                      = 0,
4055   DCE_CLOCK_TYPE_DPREFCLK                     = 1,
4056   DCE_CLOCK_TYPE_PIXELCLK                     = 2,        // used by VBIOS internally, called by SetPixelClock
4057 };
4058 
4059 //ucDCEClkFlag when ucDCEClkType == DPREFCLK
4060 enum atom_set_dce_clock_dprefclk_flag
4061 {
4062   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK          = 0x03,
4063   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA      = 0x00,
4064   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK         = 0x01,
4065   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE          = 0x02,
4066   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN        = 0x03,
4067 };
4068 
4069 //ucDCEClkFlag when ucDCEClkType == PIXCLK
4070 enum atom_set_dce_clock_pixclk_flag
4071 {
4072   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK    = 0x03,
4073   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS     = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
4074   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4     = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
4075   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2     = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
4076   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1     = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
4077   DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE           = 0x04,
4078 };
4079 
4080 struct set_dce_clock_ps_allocation_v2_1
4081 {
4082   struct set_dce_clock_parameters_v2_1 param;
4083   uint32_t ulReserved[2];
4084 };
4085 
4086 
4087 /****************************************************************************/
4088 // Structures used by BlankCRTC
4089 /****************************************************************************/
4090 struct blank_crtc_parameters
4091 {
4092   uint8_t  crtc_id;                   // enum atom_crtc_def
4093   uint8_t  blanking;                  // enum atom_blank_crtc_command
4094   uint16_t reserved;
4095   uint32_t reserved1;
4096 };
4097 
4098 enum atom_blank_crtc_command
4099 {
4100   ATOM_BLANKING         = 1,
4101   ATOM_BLANKING_OFF     = 0,
4102 };
4103 
4104 /****************************************************************************/
4105 // Structures used by enablecrtc
4106 /****************************************************************************/
4107 struct enable_crtc_parameters
4108 {
4109   uint8_t crtc_id;                    // enum atom_crtc_def
4110   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
4111   uint8_t padding[2];
4112 };
4113 
4114 
4115 /****************************************************************************/
4116 // Structure used by EnableDispPowerGating
4117 /****************************************************************************/
4118 struct enable_disp_power_gating_parameters_v2_1
4119 {
4120   uint8_t disp_pipe_id;                // ATOM_CRTC1, ATOM_CRTC2, ...
4121   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
4122   uint8_t padding[2];
4123 };
4124 
4125 struct enable_disp_power_gating_ps_allocation
4126 {
4127   struct enable_disp_power_gating_parameters_v2_1 param;
4128   uint32_t ulReserved[4];
4129 };
4130 
4131 /****************************************************************************/
4132 // Structure used in setcrtc_usingdtdtiming
4133 /****************************************************************************/
4134 struct set_crtc_using_dtd_timing_parameters
4135 {
4136   uint16_t  h_size;
4137   uint16_t  h_blanking_time;
4138   uint16_t  v_size;
4139   uint16_t  v_blanking_time;
4140   uint16_t  h_syncoffset;
4141   uint16_t  h_syncwidth;
4142   uint16_t  v_syncoffset;
4143   uint16_t  v_syncwidth;
4144   uint16_t  modemiscinfo;
4145   uint8_t   h_border;
4146   uint8_t   v_border;
4147   uint8_t   crtc_id;                   // enum atom_crtc_def
4148   uint8_t   encoder_mode;			   // atom_encode_mode_def
4149   uint8_t   padding[2];
4150 };
4151 
4152 
4153 /****************************************************************************/
4154 // Structures used by processi2cchanneltransaction
4155 /****************************************************************************/
4156 struct process_i2c_channel_transaction_parameters
4157 {
4158   uint8_t i2cspeed_khz;
4159   union {
4160     uint8_t regindex;
4161     uint8_t status;                  /* enum atom_process_i2c_flag */
4162   } regind_status;
4163   uint16_t  i2c_data_out;
4164   uint8_t   flag;                    /* enum atom_process_i2c_status */
4165   uint8_t   trans_bytes;
4166   uint8_t   slave_addr;
4167   uint8_t   i2c_id;
4168 };
4169 
4170 //ucFlag
4171 enum atom_process_i2c_flag
4172 {
4173   HW_I2C_WRITE          = 1,
4174   HW_I2C_READ           = 0,
4175   I2C_2BYTE_ADDR        = 0x02,
4176   HW_I2C_SMBUS_BYTE_WR  = 0x04,
4177 };
4178 
4179 //status
4180 enum atom_process_i2c_status
4181 {
4182   HW_ASSISTED_I2C_STATUS_FAILURE     =2,
4183   HW_ASSISTED_I2C_STATUS_SUCCESS     =1,
4184 };
4185 
4186 
4187 /****************************************************************************/
4188 // Structures used by processauxchanneltransaction
4189 /****************************************************************************/
4190 
4191 struct process_aux_channel_transaction_parameters_v1_2
4192 {
4193   uint16_t aux_request;
4194   uint16_t dataout;
4195   uint8_t  channelid;
4196   union {
4197     uint8_t   reply_status;
4198     uint8_t   aux_delay;
4199   } aux_status_delay;
4200   uint8_t   dataout_len;
4201   uint8_t   hpd_id;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
4202 };
4203 
4204 
4205 /****************************************************************************/
4206 // Structures used by selectcrtc_source
4207 /****************************************************************************/
4208 
4209 struct select_crtc_source_parameters_v2_3
4210 {
4211   uint8_t crtc_id;                        // enum atom_crtc_def
4212   uint8_t encoder_id;                     // enum atom_dig_def
4213   uint8_t encode_mode;                    // enum atom_encode_mode_def
4214   uint8_t dst_bpc;                        // enum atom_panel_bit_per_color
4215 };
4216 
4217 
4218 /****************************************************************************/
4219 // Structures used by digxencodercontrol
4220 /****************************************************************************/
4221 
4222 // ucAction:
4223 enum atom_dig_encoder_control_action
4224 {
4225   ATOM_ENCODER_CMD_DISABLE_DIG                  = 0,
4226   ATOM_ENCODER_CMD_ENABLE_DIG                   = 1,
4227   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       = 0x08,
4228   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    = 0x09,
4229   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    = 0x0a,
4230   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    = 0x13,
4231   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    = 0x0b,
4232   ATOM_ENCODER_CMD_DP_VIDEO_OFF                 = 0x0c,
4233   ATOM_ENCODER_CMD_DP_VIDEO_ON                  = 0x0d,
4234   ATOM_ENCODER_CMD_SETUP_PANEL_MODE             = 0x10,
4235   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4    = 0x14,
4236   ATOM_ENCODER_CMD_STREAM_SETUP                 = 0x0F,
4237   ATOM_ENCODER_CMD_LINK_SETUP                   = 0x11,
4238   ATOM_ENCODER_CMD_ENCODER_BLANK                = 0x12,
4239 };
4240 
4241 //define ucPanelMode
4242 enum atom_dig_encoder_control_panelmode
4243 {
4244   DP_PANEL_MODE_DISABLE                        = 0x00,
4245   DP_PANEL_MODE_ENABLE_eDP_MODE                = 0x01,
4246   DP_PANEL_MODE_ENABLE_LVLINK_MODE             = 0x11,
4247 };
4248 
4249 //ucDigId
4250 enum atom_dig_encoder_control_v5_digid
4251 {
4252   ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER           = 0x00,
4253   ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER           = 0x01,
4254   ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER           = 0x02,
4255   ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER           = 0x03,
4256   ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER           = 0x04,
4257   ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER           = 0x05,
4258   ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER           = 0x06,
4259   ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER           = 0x07,
4260 };
4261 
4262 struct dig_encoder_stream_setup_parameters_v1_5
4263 {
4264   uint8_t digid;            // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4265   uint8_t action;           // =  ATOM_ENOCODER_CMD_STREAM_SETUP
4266   uint8_t digmode;          // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4267   uint8_t lanenum;          // Lane number
4268   uint32_t pclk_10khz;      // Pixel Clock in 10Khz
4269   uint8_t bitpercolor;
4270   uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G  = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
4271   uint8_t reserved[2];
4272 };
4273 
4274 struct dig_encoder_link_setup_parameters_v1_5
4275 {
4276   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4277   uint8_t action;          // =  ATOM_ENOCODER_CMD_LINK_SETUP
4278   uint8_t digmode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4279   uint8_t lanenum;         // Lane number
4280   uint8_t symclk_10khz;    // Symbol Clock in 10Khz
4281   uint8_t hpd_sel;
4282   uint8_t digfe_sel;       // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4283   uint8_t reserved[2];
4284 };
4285 
4286 struct dp_panel_mode_set_parameters_v1_5
4287 {
4288   uint8_t digid;              // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4289   uint8_t action;             // = ATOM_ENCODER_CMD_DPLINK_SETUP
4290   uint8_t panelmode;      // enum atom_dig_encoder_control_panelmode
4291   uint8_t reserved1;
4292   uint32_t reserved2[2];
4293 };
4294 
4295 struct dig_encoder_generic_cmd_parameters_v1_5
4296 {
4297   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4298   uint8_t action;          // = rest of generic encoder command which does not carry any parameters
4299   uint8_t reserved1[2];
4300   uint32_t reserved2[2];
4301 };
4302 
4303 union dig_encoder_control_parameters_v1_5
4304 {
4305   struct dig_encoder_generic_cmd_parameters_v1_5  cmd_param;
4306   struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
4307   struct dig_encoder_link_setup_parameters_v1_5   link_param;
4308   struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
4309 };
4310 
4311 /*
4312   ***************************************************************************
4313               Structures used by dig1transmittercontrol
4314   ***************************************************************************
4315 */
4316 struct dig_transmitter_control_parameters_v1_6
4317 {
4318   uint8_t phyid;           // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4319   uint8_t action;          // define as ATOM_TRANSMITER_ACTION_xxx
4320   union {
4321     uint8_t digmode;        // enum atom_encode_mode_def
4322     uint8_t dplaneset;      // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
4323   } mode_laneset;
4324   uint8_t  lanenum;        // Lane number 1, 2, 4, 8
4325   uint32_t symclk_10khz;   // Symbol Clock in 10Khz
4326   uint8_t  hpdsel;         // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4327   uint8_t  digfe_sel;      // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4328   uint8_t  connobj_id;     // Connector Object Id defined in ObjectId.h
4329   uint8_t  reserved;
4330   uint32_t reserved1;
4331 };
4332 
4333 struct dig_transmitter_control_ps_allocation_v1_6
4334 {
4335   struct dig_transmitter_control_parameters_v1_6 param;
4336   uint32_t reserved[4];
4337 };
4338 
4339 //ucAction
4340 enum atom_dig_transmitter_control_action
4341 {
4342   ATOM_TRANSMITTER_ACTION_DISABLE                 = 0,
4343   ATOM_TRANSMITTER_ACTION_ENABLE                  = 1,
4344   ATOM_TRANSMITTER_ACTION_LCD_BLOFF               = 2,
4345   ATOM_TRANSMITTER_ACTION_LCD_BLON                = 3,
4346   ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL   = 4,
4347   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START      = 5,
4348   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP       = 6,
4349   ATOM_TRANSMITTER_ACTION_INIT                    = 7,
4350   ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          = 8,
4351   ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT           = 9,
4352   ATOM_TRANSMITTER_ACTION_SETUP                   = 10,
4353   ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH            = 11,
4354   ATOM_TRANSMITTER_ACTION_POWER_ON                = 12,
4355   ATOM_TRANSMITTER_ACTION_POWER_OFF               = 13,
4356 };
4357 
4358 // digfe_sel
4359 enum atom_dig_transmitter_control_digfe_sel
4360 {
4361   ATOM_TRANMSITTER_V6__DIGA_SEL                   = 0x01,
4362   ATOM_TRANMSITTER_V6__DIGB_SEL                   = 0x02,
4363   ATOM_TRANMSITTER_V6__DIGC_SEL                   = 0x04,
4364   ATOM_TRANMSITTER_V6__DIGD_SEL                   = 0x08,
4365   ATOM_TRANMSITTER_V6__DIGE_SEL                   = 0x10,
4366   ATOM_TRANMSITTER_V6__DIGF_SEL                   = 0x20,
4367   ATOM_TRANMSITTER_V6__DIGG_SEL                   = 0x40,
4368 };
4369 
4370 
4371 //ucHPDSel
4372 enum atom_dig_transmitter_control_hpd_sel
4373 {
4374   ATOM_TRANSMITTER_V6_NO_HPD_SEL                  = 0x00,
4375   ATOM_TRANSMITTER_V6_HPD1_SEL                    = 0x01,
4376   ATOM_TRANSMITTER_V6_HPD2_SEL                    = 0x02,
4377   ATOM_TRANSMITTER_V6_HPD3_SEL                    = 0x03,
4378   ATOM_TRANSMITTER_V6_HPD4_SEL                    = 0x04,
4379   ATOM_TRANSMITTER_V6_HPD5_SEL                    = 0x05,
4380   ATOM_TRANSMITTER_V6_HPD6_SEL                    = 0x06,
4381 };
4382 
4383 // ucDPLaneSet
4384 enum atom_dig_transmitter_control_dplaneset
4385 {
4386   DP_LANE_SET__0DB_0_4V                           = 0x00,
4387   DP_LANE_SET__0DB_0_6V                           = 0x01,
4388   DP_LANE_SET__0DB_0_8V                           = 0x02,
4389   DP_LANE_SET__0DB_1_2V                           = 0x03,
4390   DP_LANE_SET__3_5DB_0_4V                         = 0x08,
4391   DP_LANE_SET__3_5DB_0_6V                         = 0x09,
4392   DP_LANE_SET__3_5DB_0_8V                         = 0x0a,
4393   DP_LANE_SET__6DB_0_4V                           = 0x10,
4394   DP_LANE_SET__6DB_0_6V                           = 0x11,
4395   DP_LANE_SET__9_5DB_0_4V                         = 0x18,
4396 };
4397 
4398 
4399 
4400 /****************************************************************************/
4401 // Structures used by ExternalEncoderControl V2.4
4402 /****************************************************************************/
4403 
4404 struct external_encoder_control_parameters_v2_4
4405 {
4406   uint16_t pixelclock_10khz;  // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
4407   uint8_t  config;            // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
4408   uint8_t  action;            //
4409   uint8_t  encodermode;       // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4410   uint8_t  lanenum;           // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4411   uint8_t  bitpercolor;       // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
4412   uint8_t  hpd_id;
4413 };
4414 
4415 
4416 // ucAction
4417 enum external_encoder_control_action_def
4418 {
4419   EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT           = 0x00,
4420   EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT            = 0x01,
4421   EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT             = 0x07,
4422   EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP            = 0x0f,
4423   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF     = 0x10,
4424   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING         = 0x11,
4425   EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION        = 0x12,
4426   EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP                = 0x14,
4427 };
4428 
4429 // ucConfig
4430 enum external_encoder_control_v2_4_config_def
4431 {
4432   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK          = 0x03,
4433   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ       = 0x00,
4434   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ       = 0x01,
4435   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ       = 0x02,
4436   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ       = 0x03,
4437   EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS         = 0x70,
4438   EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                 = 0x00,
4439   EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                 = 0x10,
4440   EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                 = 0x20,
4441 };
4442 
4443 struct external_encoder_control_ps_allocation_v2_4
4444 {
4445   struct external_encoder_control_parameters_v2_4 sExtEncoder;
4446   uint32_t reserved[2];
4447 };
4448 
4449 
4450 /*
4451   ***************************************************************************
4452                            AMD ACPI Table
4453 
4454   ***************************************************************************
4455 */
4456 
4457 struct amd_acpi_description_header{
4458   uint32_t signature;
4459   uint32_t tableLength;      //Length
4460   uint8_t  revision;
4461   uint8_t  checksum;
4462   uint8_t  oemId[6];
4463   uint8_t  oemTableId[8];    //UINT64  OemTableId;
4464   uint32_t oemRevision;
4465   uint32_t creatorId;
4466   uint32_t creatorRevision;
4467 };
4468 
4469 struct uefi_acpi_vfct{
4470   struct   amd_acpi_description_header sheader;
4471   uint8_t  tableUUID[16];    //0x24
4472   uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
4473   uint32_t lib1Imageoffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
4474   uint32_t reserved[4];      //0x3C
4475 };
4476 
4477 struct vfct_image_header{
4478   uint32_t  pcibus;          //0x4C
4479   uint32_t  pcidevice;       //0x50
4480   uint32_t  pcifunction;     //0x54
4481   uint16_t  vendorid;        //0x58
4482   uint16_t  deviceid;        //0x5A
4483   uint16_t  ssvid;           //0x5C
4484   uint16_t  ssid;            //0x5E
4485   uint32_t  revision;        //0x60
4486   uint32_t  imagelength;     //0x64
4487 };
4488 
4489 
4490 struct gop_vbios_content {
4491   struct vfct_image_header vbiosheader;
4492   uint8_t                  vbioscontent[1];
4493 };
4494 
4495 struct gop_lib1_content {
4496   struct vfct_image_header lib1header;
4497   uint8_t                  lib1content[1];
4498 };
4499 
4500 
4501 
4502 /*
4503   ***************************************************************************
4504                    Scratch Register definitions
4505   Each number below indicates which scratch regiser request, Active and
4506   Connect all share the same definitions as display_device_tag defines
4507   ***************************************************************************
4508 */
4509 
4510 enum scratch_register_def{
4511   ATOM_DEVICE_CONNECT_INFO_DEF      = 0,
4512   ATOM_BL_BRI_LEVEL_INFO_DEF        = 2,
4513   ATOM_ACTIVE_INFO_DEF              = 3,
4514   ATOM_LCD_INFO_DEF                 = 4,
4515   ATOM_DEVICE_REQ_INFO_DEF          = 5,
4516   ATOM_ACC_CHANGE_INFO_DEF          = 6,
4517   ATOM_PRE_OS_MODE_INFO_DEF         = 7,
4518   ATOM_PRE_OS_ASSERTION_DEF      = 8,    //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
4519   ATOM_INTERNAL_TIMER_INFO_DEF      = 10,
4520 };
4521 
4522 enum scratch_device_connect_info_bit_def{
4523   ATOM_DISPLAY_LCD1_CONNECT           =0x0002,
4524   ATOM_DISPLAY_DFP1_CONNECT           =0x0008,
4525   ATOM_DISPLAY_DFP2_CONNECT           =0x0080,
4526   ATOM_DISPLAY_DFP3_CONNECT           =0x0200,
4527   ATOM_DISPLAY_DFP4_CONNECT           =0x0400,
4528   ATOM_DISPLAY_DFP5_CONNECT           =0x0800,
4529   ATOM_DISPLAY_DFP6_CONNECT           =0x0040,
4530   ATOM_DISPLAY_DFPx_CONNECT           =0x0ec8,
4531   ATOM_CONNECT_INFO_DEVICE_MASK       =0x0fff,
4532 };
4533 
4534 enum scratch_bl_bri_level_info_bit_def{
4535   ATOM_CURRENT_BL_LEVEL_SHIFT         =0x8,
4536 #ifndef _H2INC
4537   ATOM_CURRENT_BL_LEVEL_MASK          =0x0000ff00,
4538   ATOM_DEVICE_DPMS_STATE              =0x00010000,
4539 #endif
4540 };
4541 
4542 enum scratch_active_info_bits_def{
4543   ATOM_DISPLAY_LCD1_ACTIVE            =0x0002,
4544   ATOM_DISPLAY_DFP1_ACTIVE            =0x0008,
4545   ATOM_DISPLAY_DFP2_ACTIVE            =0x0080,
4546   ATOM_DISPLAY_DFP3_ACTIVE            =0x0200,
4547   ATOM_DISPLAY_DFP4_ACTIVE            =0x0400,
4548   ATOM_DISPLAY_DFP5_ACTIVE            =0x0800,
4549   ATOM_DISPLAY_DFP6_ACTIVE            =0x0040,
4550   ATOM_ACTIVE_INFO_DEVICE_MASK        =0x0fff,
4551 };
4552 
4553 enum scratch_device_req_info_bits_def{
4554   ATOM_DISPLAY_LCD1_REQ               =0x0002,
4555   ATOM_DISPLAY_DFP1_REQ               =0x0008,
4556   ATOM_DISPLAY_DFP2_REQ               =0x0080,
4557   ATOM_DISPLAY_DFP3_REQ               =0x0200,
4558   ATOM_DISPLAY_DFP4_REQ               =0x0400,
4559   ATOM_DISPLAY_DFP5_REQ               =0x0800,
4560   ATOM_DISPLAY_DFP6_REQ               =0x0040,
4561   ATOM_REQ_INFO_DEVICE_MASK           =0x0fff,
4562 };
4563 
4564 enum scratch_acc_change_info_bitshift_def{
4565   ATOM_ACC_CHANGE_ACC_MODE_SHIFT    =4,
4566   ATOM_ACC_CHANGE_LID_STATUS_SHIFT  =6,
4567 };
4568 
4569 enum scratch_acc_change_info_bits_def{
4570   ATOM_ACC_CHANGE_ACC_MODE          =0x00000010,
4571   ATOM_ACC_CHANGE_LID_STATUS        =0x00000040,
4572 };
4573 
4574 enum scratch_pre_os_mode_info_bits_def{
4575   ATOM_PRE_OS_MODE_MASK             =0x00000003,
4576   ATOM_PRE_OS_MODE_VGA              =0x00000000,
4577   ATOM_PRE_OS_MODE_VESA             =0x00000001,
4578   ATOM_PRE_OS_MODE_GOP              =0x00000002,
4579   ATOM_PRE_OS_MODE_PIXEL_DEPTH      =0x0000000C,
4580   ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4581   ATOM_PRE_OS_MODE_8BIT_PAL_EN      =0x00000100,
4582   ATOM_ASIC_INIT_COMPLETE           =0x00000200,
4583 #ifndef _H2INC
4584   ATOM_PRE_OS_MODE_NUMBER_MASK      =0xFFFF0000,
4585 #endif
4586 };
4587 
4588 
4589 
4590 /*
4591   ***************************************************************************
4592                        ATOM firmware ID header file
4593               !! Please keep it at end of the atomfirmware.h !!
4594   ***************************************************************************
4595 */
4596 #include "atomfirmwareid.h"
4597 #pragma pack()
4598 
4599 #endif
4600 
4601