1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010 Extreme Engineering Solutions, Inc.
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <i2c.h>
9
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12
get_spd(ddr3_spd_eeprom_t * spd,u8 i2c_address)13 void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
14 {
15 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
16 sizeof(ddr3_spd_eeprom_t));
17 }
18
19 /*
20 * There are traditionally three board-specific SDRAM timing parameters
21 * which must be calculated based on the particular PCB artwork. These are:
22 * 1.) CPO (Read Capture Delay)
23 * - TIMING_CFG_2 register
24 * Source: Calculation based on board trace lengths and
25 * chip-specific internal delays.
26 * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
27 * - DDR_SDRAM_CLK_CNTL register
28 * Source: Signal Integrity Simulations
29 * 3.) 2T Timing on Addr/Ctl
30 * - TIMING_CFG_2 register
31 * Source: Signal Integrity Simulations
32 * Usually only needed with heavy load/very high speed (>DDR2-800)
33 *
34 * ====== XPedite550x DDR3-800 read delay calculations ======
35 *
36 * The P2020 processor provides an autoleveling option. Setting CPO to
37 * 0x1f enables this auto configuration.
38 */
39
40 typedef struct {
41 unsigned short datarate_mhz_low;
42 unsigned short datarate_mhz_high;
43 unsigned char clk_adjust;
44 unsigned char cpo;
45 } board_specific_parameters_t;
46
47 const board_specific_parameters_t board_specific_parameters[][20] = {
48 {
49 /* Controller 0 */
50 {
51 /* DDR3-600/667 */
52 .datarate_mhz_low = 500,
53 .datarate_mhz_high = 750,
54 .clk_adjust = 5,
55 .cpo = 31,
56 },
57 {
58 /* DDR3-800 */
59 .datarate_mhz_low = 750,
60 .datarate_mhz_high = 850,
61 .clk_adjust = 5,
62 .cpo = 31,
63 },
64 },
65 };
66
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)67 void fsl_ddr_board_options(memctl_options_t *popts,
68 dimm_params_t *pdimm,
69 unsigned int ctrl_num)
70 {
71 const board_specific_parameters_t *pbsp =
72 &(board_specific_parameters[ctrl_num][0]);
73 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
74 sizeof(board_specific_parameters[0][0]);
75 u32 i;
76 ulong ddr_freq;
77
78 /*
79 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
80 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
81 * there are two dimms in the controller, set odt_rd_cfg to 3 and
82 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
83 */
84 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
85 if (i&1) { /* odd CS */
86 popts->cs_local_opts[i].odt_rd_cfg = 0;
87 popts->cs_local_opts[i].odt_wr_cfg = 0;
88 } else { /* even CS */
89 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
90 popts->cs_local_opts[i].odt_rd_cfg = 0;
91 popts->cs_local_opts[i].odt_wr_cfg = 4;
92 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
93 popts->cs_local_opts[i].odt_rd_cfg = 3;
94 popts->cs_local_opts[i].odt_wr_cfg = 3;
95 }
96 }
97 }
98
99 /*
100 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
101 * freqency and n_banks specified in board_specific_parameters table.
102 */
103 ddr_freq = get_ddr_freq(0) / 1000000;
104
105 for (i = 0; i < num_params; i++) {
106 if (ddr_freq >= pbsp->datarate_mhz_low &&
107 ddr_freq <= pbsp->datarate_mhz_high) {
108 popts->clk_adjust = pbsp->clk_adjust;
109 popts->cpo_override = pbsp->cpo;
110 popts->twot_en = 0;
111 break;
112 }
113 pbsp++;
114 }
115
116 if (i == num_params) {
117 printf("Warning: board specific timing not found "
118 "for data rate %lu MT/s!\n", ddr_freq);
119 }
120
121 /*
122 * Factors to consider for half-strength driver enable:
123 * - number of DIMMs installed
124 */
125 popts->half_strength_driver_enable = 0;
126
127 /*
128 * Enable on-die termination.
129 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
130 * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
131 * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
132 */
133 popts->rtt_override = 1;
134 popts->rtt_override_value = 3;
135 }
136