1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60 /* board IDs for specific chipsets in alphabetical order */
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /*
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
74 */
75 board_ahci_pcs7,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_runtime_suspend(struct device *dev);
98 static int ahci_pci_device_runtime_resume(struct device *dev);
99 #ifdef CONFIG_PM_SLEEP
100 static int ahci_pci_device_suspend(struct device *dev);
101 static int ahci_pci_device_resume(struct device *dev);
102 #endif
103 #endif /* CONFIG_PM */
104
105 static const struct scsi_host_template ahci_sht = {
106 AHCI_SHT("ahci"),
107 };
108
109 static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
112 };
113
114 static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
117 };
118
119 static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
122 };
123
124 static const struct ata_port_info ahci_port_info[] = {
125 /* by features */
126 [board_ahci] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_43bit_dma] = {
133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_ign_iferr] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_low_power] = {
147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_no_debounce_delay] = {
154 .flags = AHCI_FLAG_COMMON,
155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_nomsi] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_noncq] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_nosntf] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 [board_ahci_yes_fbs] = {
182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 /* by chipsets */
189 [board_ahci_al] = {
190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
191 .flags = AHCI_FLAG_COMMON,
192 .pio_mask = ATA_PIO4,
193 .udma_mask = ATA_UDMA6,
194 .port_ops = &ahci_ops,
195 },
196 [board_ahci_avn] = {
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_avn_ops,
201 },
202 [board_ahci_mcp65] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
204 AHCI_HFLAG_YES_NCQ),
205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
209 },
210 [board_ahci_mcp77] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_mcp89] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_mv] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_ops,
231 },
232 [board_ahci_sb600] = {
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
235 AHCI_HFLAG_32BIT_ONLY),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
240 },
241 [board_ahci_sb700] = { /* for SB700 and SB800 */
242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_pmp_retry_srst_ops,
247 },
248 [board_ahci_vt8251] = {
249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
250 .flags = AHCI_FLAG_COMMON,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_vt8251_ops,
254 },
255 [board_ahci_pcs7] = {
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_ops,
260 },
261 };
262
263 static const struct pci_device_id ahci_pci_tbl[] = {
264 /* Intel */
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
434
435 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
436 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
438 /* JMicron 362B and 362C have an AHCI function with IDE class code */
439 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
440 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
441 /* May need to update quirk_jmicron_async_suspend() for additions */
442
443 /* ATI */
444 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
445 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
451
452 /* Amazon's Annapurna Labs support */
453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
454 .class = PCI_CLASS_STORAGE_SATA_AHCI,
455 .class_mask = 0xffffff,
456 board_ahci_al },
457 /* AMD */
458 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
459 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
460 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
461 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
462 /* AMD is using RAID class only for ahci controllers */
463 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
465
466 /* Dell S140/S150 */
467 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
468 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
469
470 /* VIA */
471 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
472 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
473
474 /* NVIDIA */
475 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
559
560 /* SiS */
561 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
562 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
563 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
564
565 /* ST Microelectronics */
566 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
567
568 /* Marvell */
569 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
570 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
572 .class = PCI_CLASS_STORAGE_SATA_AHCI,
573 .class_mask = 0xffffff,
574 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
576 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
577 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
578 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
587 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
595 .driver_data = board_ahci_yes_fbs },
596 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
597 .driver_data = board_ahci_no_debounce_delay },
598 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
599 .driver_data = board_ahci_yes_fbs },
600 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
601 .driver_data = board_ahci_yes_fbs },
602
603 /* Promise */
604 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
605 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
606
607 /* ASMedia */
608 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
609 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
610 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
611 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
612 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
613 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
614 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
615 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
616 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
617 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
618 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
619 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
620
621 /*
622 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
623 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
624 */
625 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
626 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
627
628 /* Enmotus */
629 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
630
631 /* Loongson */
632 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
633
634 /* Generic, PCI class code for AHCI */
635 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
636 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
637
638 { } /* terminate list */
639 };
640
641 static const struct dev_pm_ops ahci_pci_pm_ops = {
642 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
643 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
644 ahci_pci_device_runtime_resume, NULL)
645 };
646
647 static struct pci_driver ahci_pci_driver = {
648 .name = DRV_NAME,
649 .id_table = ahci_pci_tbl,
650 .probe = ahci_init_one,
651 .remove = ahci_remove_one,
652 .shutdown = ahci_shutdown_one,
653 .driver = {
654 .pm = &ahci_pci_pm_ops,
655 },
656 };
657
658 #if IS_ENABLED(CONFIG_PATA_MARVELL)
659 static int marvell_enable;
660 #else
661 static int marvell_enable = 1;
662 #endif
663 module_param(marvell_enable, int, 0644);
664 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
665
666 static int mobile_lpm_policy = -1;
667 module_param(mobile_lpm_policy, int, 0644);
668 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
669
670 static char *ahci_mask_port_map;
671 module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
672 MODULE_PARM_DESC(mask_port_map,
673 "32-bits port map masks to ignore controllers ports. "
674 "Valid values are: "
675 "\"<mask>\" to apply the same mask to all AHCI controller "
676 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
677 "specify different masks for the controllers specified, "
678 "where <pci_dev> is the PCI ID of an AHCI controller in the "
679 "form \"domain:bus:dev.func\"");
680
ahci_apply_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv,char * mask_s)681 static void ahci_apply_port_map_mask(struct device *dev,
682 struct ahci_host_priv *hpriv, char *mask_s)
683 {
684 unsigned int mask;
685
686 if (kstrtouint(mask_s, 0, &mask)) {
687 dev_err(dev, "Invalid port map mask\n");
688 return;
689 }
690
691 hpriv->mask_port_map = mask;
692 }
693
ahci_get_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv)694 static void ahci_get_port_map_mask(struct device *dev,
695 struct ahci_host_priv *hpriv)
696 {
697 char *param, *end, *str, *mask_s;
698 char *name;
699
700 if (!strlen(ahci_mask_port_map))
701 return;
702
703 str = kstrdup(ahci_mask_port_map, GFP_KERNEL);
704 if (!str)
705 return;
706
707 /* Handle single mask case */
708 if (!strchr(str, '=')) {
709 ahci_apply_port_map_mask(dev, hpriv, str);
710 goto free;
711 }
712
713 /*
714 * Mask list case: parse the parameter to apply the mask only if
715 * the device name matches.
716 */
717 param = str;
718 end = param + strlen(param);
719 while (param && param < end && *param) {
720 name = param;
721 param = strchr(name, '=');
722 if (!param)
723 break;
724
725 *param = '\0';
726 param++;
727 if (param >= end)
728 break;
729
730 if (strcmp(dev_name(dev), name) != 0) {
731 param = strchr(param, ',');
732 if (param)
733 param++;
734 continue;
735 }
736
737 mask_s = param;
738 param = strchr(mask_s, ',');
739 if (param) {
740 *param = '\0';
741 param++;
742 }
743
744 ahci_apply_port_map_mask(dev, hpriv, mask_s);
745 }
746
747 free:
748 kfree(str);
749 }
750
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)751 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
752 struct ahci_host_priv *hpriv)
753 {
754 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
755 dev_info(&pdev->dev, "JMB361 has only one port\n");
756 hpriv->saved_port_map = 1;
757 }
758
759 /*
760 * Temporary Marvell 6145 hack: PATA port presence
761 * is asserted through the standard AHCI port
762 * presence register, as bit 4 (counting from 0)
763 */
764 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
765 if (pdev->device == 0x6121)
766 hpriv->mask_port_map = 0x3;
767 else
768 hpriv->mask_port_map = 0xf;
769 dev_info(&pdev->dev,
770 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
771 }
772
773 /* Handle port map masks passed as module parameter. */
774 if (ahci_mask_port_map)
775 ahci_get_port_map_mask(&pdev->dev, hpriv);
776
777 ahci_save_initial_config(&pdev->dev, hpriv);
778 }
779
ahci_pci_reset_controller(struct ata_host * host)780 static int ahci_pci_reset_controller(struct ata_host *host)
781 {
782 struct pci_dev *pdev = to_pci_dev(host->dev);
783 struct ahci_host_priv *hpriv = host->private_data;
784 int rc;
785
786 rc = ahci_reset_controller(host);
787 if (rc)
788 return rc;
789
790 /*
791 * If platform firmware failed to enable ports, try to enable
792 * them here.
793 */
794 ahci_intel_pcs_quirk(pdev, hpriv);
795
796 return 0;
797 }
798
ahci_pci_init_controller(struct ata_host * host)799 static void ahci_pci_init_controller(struct ata_host *host)
800 {
801 struct ahci_host_priv *hpriv = host->private_data;
802 struct pci_dev *pdev = to_pci_dev(host->dev);
803 void __iomem *port_mmio;
804 u32 tmp;
805 int mv;
806
807 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
808 if (pdev->device == 0x6121)
809 mv = 2;
810 else
811 mv = 4;
812 port_mmio = __ahci_port_base(hpriv, mv);
813
814 writel(0, port_mmio + PORT_IRQ_MASK);
815
816 /* clear port IRQ */
817 tmp = readl(port_mmio + PORT_IRQ_STAT);
818 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
819 if (tmp)
820 writel(tmp, port_mmio + PORT_IRQ_STAT);
821 }
822
823 ahci_init_controller(host);
824 }
825
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)826 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
827 unsigned long deadline)
828 {
829 struct ata_port *ap = link->ap;
830 struct ahci_host_priv *hpriv = ap->host->private_data;
831 bool online;
832 int rc;
833
834 hpriv->stop_engine(ap);
835
836 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
837 deadline, &online, NULL);
838
839 hpriv->start_engine(ap);
840
841 /* vt8251 doesn't clear BSY on signature FIS reception,
842 * request follow-up softreset.
843 */
844 return online ? -EAGAIN : rc;
845 }
846
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)847 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
848 unsigned long deadline)
849 {
850 struct ata_port *ap = link->ap;
851 struct ahci_port_priv *pp = ap->private_data;
852 struct ahci_host_priv *hpriv = ap->host->private_data;
853 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
854 struct ata_taskfile tf;
855 bool online;
856 int rc;
857
858 hpriv->stop_engine(ap);
859
860 /* clear D2H reception area to properly wait for D2H FIS */
861 ata_tf_init(link->device, &tf);
862 tf.status = ATA_BUSY;
863 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
864
865 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
866 deadline, &online, NULL);
867
868 hpriv->start_engine(ap);
869
870 /* The pseudo configuration device on SIMG4726 attached to
871 * ASUS P5W-DH Deluxe doesn't send signature FIS after
872 * hardreset if no device is attached to the first downstream
873 * port && the pseudo device locks up on SRST w/ PMP==0. To
874 * work around this, wait for !BSY only briefly. If BSY isn't
875 * cleared, perform CLO and proceed to IDENTIFY (achieved by
876 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
877 *
878 * Wait for two seconds. Devices attached to downstream port
879 * which can't process the following IDENTIFY after this will
880 * have to be reset again. For most cases, this should
881 * suffice while making probing snappish enough.
882 */
883 if (online) {
884 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
885 ahci_check_ready);
886 if (rc)
887 ahci_kick_engine(ap);
888 }
889 return rc;
890 }
891
892 /*
893 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
894 *
895 * It has been observed with some SSDs that the timing of events in the
896 * link synchronization phase can leave the port in a state that can not
897 * be recovered by a SATA-hard-reset alone. The failing signature is
898 * SStatus.DET stuck at 1 ("Device presence detected but Phy
899 * communication not established"). It was found that unloading and
900 * reloading the driver when this problem occurs allows the drive
901 * connection to be recovered (DET advanced to 0x3). The critical
902 * component of reloading the driver is that the port state machines are
903 * reset by bouncing "port enable" in the AHCI PCS configuration
904 * register. So, reproduce that effect by bouncing a port whenever we
905 * see DET==1 after a reset.
906 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)907 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
908 unsigned long deadline)
909 {
910 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
911 struct ata_port *ap = link->ap;
912 struct ahci_port_priv *pp = ap->private_data;
913 struct ahci_host_priv *hpriv = ap->host->private_data;
914 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
915 unsigned long tmo = deadline - jiffies;
916 struct ata_taskfile tf;
917 bool online;
918 int rc, i;
919
920 hpriv->stop_engine(ap);
921
922 for (i = 0; i < 2; i++) {
923 u16 val;
924 u32 sstatus;
925 int port = ap->port_no;
926 struct ata_host *host = ap->host;
927 struct pci_dev *pdev = to_pci_dev(host->dev);
928
929 /* clear D2H reception area to properly wait for D2H FIS */
930 ata_tf_init(link->device, &tf);
931 tf.status = ATA_BUSY;
932 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
933
934 rc = sata_link_hardreset(link, timing, deadline, &online,
935 ahci_check_ready);
936
937 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
938 (sstatus & 0xf) != 1)
939 break;
940
941 ata_link_info(link, "avn bounce port%d\n", port);
942
943 pci_read_config_word(pdev, 0x92, &val);
944 val &= ~(1 << port);
945 pci_write_config_word(pdev, 0x92, val);
946 ata_msleep(ap, 1000);
947 val |= 1 << port;
948 pci_write_config_word(pdev, 0x92, val);
949 deadline += tmo;
950 }
951
952 hpriv->start_engine(ap);
953
954 if (online)
955 *class = ahci_dev_classify(ap);
956
957 return rc;
958 }
959
960
961 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)962 static void ahci_pci_disable_interrupts(struct ata_host *host)
963 {
964 struct ahci_host_priv *hpriv = host->private_data;
965 void __iomem *mmio = hpriv->mmio;
966 u32 ctl;
967
968 /* AHCI spec rev1.1 section 8.3.3:
969 * Software must disable interrupts prior to requesting a
970 * transition of the HBA to D3 state.
971 */
972 ctl = readl(mmio + HOST_CTL);
973 ctl &= ~HOST_IRQ_EN;
974 writel(ctl, mmio + HOST_CTL);
975 readl(mmio + HOST_CTL); /* flush */
976 }
977
ahci_pci_device_runtime_suspend(struct device * dev)978 static int ahci_pci_device_runtime_suspend(struct device *dev)
979 {
980 struct pci_dev *pdev = to_pci_dev(dev);
981 struct ata_host *host = pci_get_drvdata(pdev);
982
983 ahci_pci_disable_interrupts(host);
984 return 0;
985 }
986
ahci_pci_device_runtime_resume(struct device * dev)987 static int ahci_pci_device_runtime_resume(struct device *dev)
988 {
989 struct pci_dev *pdev = to_pci_dev(dev);
990 struct ata_host *host = pci_get_drvdata(pdev);
991 int rc;
992
993 rc = ahci_pci_reset_controller(host);
994 if (rc)
995 return rc;
996 ahci_pci_init_controller(host);
997 return 0;
998 }
999
1000 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)1001 static int ahci_pci_device_suspend(struct device *dev)
1002 {
1003 struct pci_dev *pdev = to_pci_dev(dev);
1004 struct ata_host *host = pci_get_drvdata(pdev);
1005 struct ahci_host_priv *hpriv = host->private_data;
1006
1007 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1008 dev_err(&pdev->dev,
1009 "BIOS update required for suspend/resume\n");
1010 return -EIO;
1011 }
1012
1013 ahci_pci_disable_interrupts(host);
1014 ata_host_suspend(host, PMSG_SUSPEND);
1015 return 0;
1016 }
1017
ahci_pci_device_resume(struct device * dev)1018 static int ahci_pci_device_resume(struct device *dev)
1019 {
1020 struct pci_dev *pdev = to_pci_dev(dev);
1021 struct ata_host *host = pci_get_drvdata(pdev);
1022 int rc;
1023
1024 /* Apple BIOS helpfully mangles the registers on resume */
1025 if (is_mcp89_apple(pdev))
1026 ahci_mcp89_apple_enable(pdev);
1027
1028 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1029 rc = ahci_pci_reset_controller(host);
1030 if (rc)
1031 return rc;
1032
1033 ahci_pci_init_controller(host);
1034 }
1035
1036 ata_host_resume(host);
1037
1038 return 0;
1039 }
1040 #endif
1041
1042 #endif /* CONFIG_PM */
1043
ahci_configure_dma_masks(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1044 static int ahci_configure_dma_masks(struct pci_dev *pdev,
1045 struct ahci_host_priv *hpriv)
1046 {
1047 int dma_bits;
1048 int rc;
1049
1050 if (hpriv->cap & HOST_CAP_64) {
1051 dma_bits = 64;
1052 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1053 dma_bits = 43;
1054 } else {
1055 dma_bits = 32;
1056 }
1057
1058 /*
1059 * If the device fixup already set the dma_mask to some non-standard
1060 * value, don't extend it here. This happens on STA2X11, for example.
1061 *
1062 * XXX: manipulating the DMA mask from platform code is completely
1063 * bogus, platform code should use dev->bus_dma_limit instead..
1064 */
1065 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1066 return 0;
1067
1068 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
1069 if (rc)
1070 dev_err(&pdev->dev, "DMA enable failed\n");
1071 return rc;
1072 }
1073
ahci_pci_print_info(struct ata_host * host)1074 static void ahci_pci_print_info(struct ata_host *host)
1075 {
1076 struct pci_dev *pdev = to_pci_dev(host->dev);
1077 u16 cc;
1078 const char *scc_s;
1079
1080 pci_read_config_word(pdev, 0x0a, &cc);
1081 if (cc == PCI_CLASS_STORAGE_IDE)
1082 scc_s = "IDE";
1083 else if (cc == PCI_CLASS_STORAGE_SATA)
1084 scc_s = "SATA";
1085 else if (cc == PCI_CLASS_STORAGE_RAID)
1086 scc_s = "RAID";
1087 else
1088 scc_s = "unknown";
1089
1090 ahci_print_info(host, scc_s);
1091 }
1092
1093 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1094 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1095 * support PMP and the 4726 either directly exports the device
1096 * attached to the first downstream port or acts as a hardware storage
1097 * controller and emulate a single ATA device (can be RAID 0/1 or some
1098 * other configuration).
1099 *
1100 * When there's no device attached to the first downstream port of the
1101 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1102 * configure the 4726. However, ATA emulation of the device is very
1103 * lame. It doesn't send signature D2H Reg FIS after the initial
1104 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1105 *
1106 * The following function works around the problem by always using
1107 * hardreset on the port and not depending on receiving signature FIS
1108 * afterward. If signature FIS isn't received soon, ATA class is
1109 * assumed without follow-up softreset.
1110 */
ahci_p5wdh_workaround(struct ata_host * host)1111 static void ahci_p5wdh_workaround(struct ata_host *host)
1112 {
1113 static const struct dmi_system_id sysids[] = {
1114 {
1115 .ident = "P5W DH Deluxe",
1116 .matches = {
1117 DMI_MATCH(DMI_SYS_VENDOR,
1118 "ASUSTEK COMPUTER INC"),
1119 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1120 },
1121 },
1122 { }
1123 };
1124 struct pci_dev *pdev = to_pci_dev(host->dev);
1125
1126 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1127 dmi_check_system(sysids)) {
1128 struct ata_port *ap = host->ports[1];
1129
1130 dev_info(&pdev->dev,
1131 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1132
1133 ap->ops = &ahci_p5wdh_ops;
1134 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1135 }
1136 }
1137
1138 /*
1139 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1140 * booting in BIOS compatibility mode. We restore the registers but not ID.
1141 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1142 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1143 {
1144 u32 val;
1145
1146 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1147
1148 pci_read_config_dword(pdev, 0xf8, &val);
1149 val |= 1 << 0x1b;
1150 /* the following changes the device ID, but appears not to affect function */
1151 /* val = (val & ~0xf0000000) | 0x80000000; */
1152 pci_write_config_dword(pdev, 0xf8, val);
1153
1154 pci_read_config_dword(pdev, 0x54c, &val);
1155 val |= 1 << 0xc;
1156 pci_write_config_dword(pdev, 0x54c, val);
1157
1158 pci_read_config_dword(pdev, 0x4a4, &val);
1159 val &= 0xff;
1160 val |= 0x01060100;
1161 pci_write_config_dword(pdev, 0x4a4, val);
1162
1163 pci_read_config_dword(pdev, 0x54c, &val);
1164 val &= ~(1 << 0xc);
1165 pci_write_config_dword(pdev, 0x54c, val);
1166
1167 pci_read_config_dword(pdev, 0xf8, &val);
1168 val &= ~(1 << 0x1b);
1169 pci_write_config_dword(pdev, 0xf8, val);
1170 }
1171
is_mcp89_apple(struct pci_dev * pdev)1172 static bool is_mcp89_apple(struct pci_dev *pdev)
1173 {
1174 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1175 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1176 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1177 pdev->subsystem_device == 0xcb89;
1178 }
1179
1180 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1181 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1182 {
1183 static const struct dmi_system_id sysids[] = {
1184 /*
1185 * The oldest version known to be broken is 0901 and
1186 * working is 1501 which was released on 2007-10-26.
1187 * Enable 64bit DMA on 1501 and anything newer.
1188 *
1189 * Please read bko#9412 for more info.
1190 */
1191 {
1192 .ident = "ASUS M2A-VM",
1193 .matches = {
1194 DMI_MATCH(DMI_BOARD_VENDOR,
1195 "ASUSTeK Computer INC."),
1196 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1197 },
1198 .driver_data = "20071026", /* yyyymmdd */
1199 },
1200 /*
1201 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1202 * support 64bit DMA.
1203 *
1204 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1205 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1206 * This spelling mistake was fixed in BIOS version 1.5, so
1207 * 1.5 and later have the Manufacturer as
1208 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1209 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1210 *
1211 * BIOS versions earlier than 1.9 had a Board Product Name
1212 * DMI field of "MS-7376". This was changed to be
1213 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1214 * match on DMI_BOARD_NAME of "MS-7376".
1215 */
1216 {
1217 .ident = "MSI K9A2 Platinum",
1218 .matches = {
1219 DMI_MATCH(DMI_BOARD_VENDOR,
1220 "MICRO-STAR INTER"),
1221 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1222 },
1223 },
1224 /*
1225 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1226 * 64bit DMA.
1227 *
1228 * This board also had the typo mentioned above in the
1229 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1230 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1231 */
1232 {
1233 .ident = "MSI K9AGM2",
1234 .matches = {
1235 DMI_MATCH(DMI_BOARD_VENDOR,
1236 "MICRO-STAR INTER"),
1237 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1238 },
1239 },
1240 /*
1241 * All BIOS versions for the Asus M3A support 64bit DMA.
1242 * (all release versions from 0301 to 1206 were tested)
1243 */
1244 {
1245 .ident = "ASUS M3A",
1246 .matches = {
1247 DMI_MATCH(DMI_BOARD_VENDOR,
1248 "ASUSTeK Computer INC."),
1249 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1250 },
1251 },
1252 { }
1253 };
1254 const struct dmi_system_id *match;
1255 int year, month, date;
1256 char buf[9];
1257
1258 match = dmi_first_match(sysids);
1259 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1260 !match)
1261 return false;
1262
1263 if (!match->driver_data)
1264 goto enable_64bit;
1265
1266 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1267 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1268
1269 if (strcmp(buf, match->driver_data) >= 0)
1270 goto enable_64bit;
1271 else {
1272 dev_warn(&pdev->dev,
1273 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1274 match->ident);
1275 return false;
1276 }
1277
1278 enable_64bit:
1279 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1280 return true;
1281 }
1282
ahci_broken_system_poweroff(struct pci_dev * pdev)1283 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1284 {
1285 static const struct dmi_system_id broken_systems[] = {
1286 {
1287 .ident = "HP Compaq nx6310",
1288 .matches = {
1289 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1290 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1291 },
1292 /* PCI slot number of the controller */
1293 .driver_data = (void *)0x1FUL,
1294 },
1295 {
1296 .ident = "HP Compaq 6720s",
1297 .matches = {
1298 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1299 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1300 },
1301 /* PCI slot number of the controller */
1302 .driver_data = (void *)0x1FUL,
1303 },
1304
1305 { } /* terminate list */
1306 };
1307 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1308
1309 if (dmi) {
1310 unsigned long slot = (unsigned long)dmi->driver_data;
1311 /* apply the quirk only to on-board controllers */
1312 return slot == PCI_SLOT(pdev->devfn);
1313 }
1314
1315 return false;
1316 }
1317
ahci_broken_suspend(struct pci_dev * pdev)1318 static bool ahci_broken_suspend(struct pci_dev *pdev)
1319 {
1320 static const struct dmi_system_id sysids[] = {
1321 /*
1322 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1323 * to the harddisk doesn't become online after
1324 * resuming from STR. Warn and fail suspend.
1325 *
1326 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1327 *
1328 * Use dates instead of versions to match as HP is
1329 * apparently recycling both product and version
1330 * strings.
1331 *
1332 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1333 */
1334 {
1335 .ident = "dv4",
1336 .matches = {
1337 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1338 DMI_MATCH(DMI_PRODUCT_NAME,
1339 "HP Pavilion dv4 Notebook PC"),
1340 },
1341 .driver_data = "20090105", /* F.30 */
1342 },
1343 {
1344 .ident = "dv5",
1345 .matches = {
1346 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1347 DMI_MATCH(DMI_PRODUCT_NAME,
1348 "HP Pavilion dv5 Notebook PC"),
1349 },
1350 .driver_data = "20090506", /* F.16 */
1351 },
1352 {
1353 .ident = "dv6",
1354 .matches = {
1355 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1356 DMI_MATCH(DMI_PRODUCT_NAME,
1357 "HP Pavilion dv6 Notebook PC"),
1358 },
1359 .driver_data = "20090423", /* F.21 */
1360 },
1361 {
1362 .ident = "HDX18",
1363 .matches = {
1364 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1365 DMI_MATCH(DMI_PRODUCT_NAME,
1366 "HP HDX18 Notebook PC"),
1367 },
1368 .driver_data = "20090430", /* F.23 */
1369 },
1370 /*
1371 * Acer eMachines G725 has the same problem. BIOS
1372 * V1.03 is known to be broken. V3.04 is known to
1373 * work. Between, there are V1.06, V2.06 and V3.03
1374 * that we don't have much idea about. For now,
1375 * blacklist anything older than V3.04.
1376 *
1377 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1378 */
1379 {
1380 .ident = "G725",
1381 .matches = {
1382 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1383 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1384 },
1385 .driver_data = "20091216", /* V3.04 */
1386 },
1387 { } /* terminate list */
1388 };
1389 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1390 int year, month, date;
1391 char buf[9];
1392
1393 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1394 return false;
1395
1396 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1397 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1398
1399 return strcmp(buf, dmi->driver_data) < 0;
1400 }
1401
ahci_broken_lpm(struct pci_dev * pdev)1402 static bool ahci_broken_lpm(struct pci_dev *pdev)
1403 {
1404 static const struct dmi_system_id sysids[] = {
1405 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1406 {
1407 .matches = {
1408 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1409 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1410 },
1411 .driver_data = "20180406", /* 1.31 */
1412 },
1413 {
1414 .matches = {
1415 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1416 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1417 },
1418 .driver_data = "20180420", /* 1.28 */
1419 },
1420 {
1421 .matches = {
1422 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1423 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1424 },
1425 .driver_data = "20180315", /* 1.33 */
1426 },
1427 {
1428 .matches = {
1429 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1430 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1431 },
1432 /*
1433 * Note date based on release notes, 2.35 has been
1434 * reported to be good, but I've been unable to get
1435 * a hold of the reporter to get the DMI BIOS date.
1436 * TODO: fix this.
1437 */
1438 .driver_data = "20180310", /* 2.35 */
1439 },
1440 { } /* terminate list */
1441 };
1442 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1443 int year, month, date;
1444 char buf[9];
1445
1446 if (!dmi)
1447 return false;
1448
1449 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1450 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1451
1452 return strcmp(buf, dmi->driver_data) < 0;
1453 }
1454
ahci_broken_online(struct pci_dev * pdev)1455 static bool ahci_broken_online(struct pci_dev *pdev)
1456 {
1457 #define ENCODE_BUSDEVFN(bus, slot, func) \
1458 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1459 static const struct dmi_system_id sysids[] = {
1460 /*
1461 * There are several gigabyte boards which use
1462 * SIMG5723s configured as hardware RAID. Certain
1463 * 5723 firmware revisions shipped there keep the link
1464 * online but fail to answer properly to SRST or
1465 * IDENTIFY when no device is attached downstream
1466 * causing libata to retry quite a few times leading
1467 * to excessive detection delay.
1468 *
1469 * As these firmwares respond to the second reset try
1470 * with invalid device signature, considering unknown
1471 * sig as offline works around the problem acceptably.
1472 */
1473 {
1474 .ident = "EP45-DQ6",
1475 .matches = {
1476 DMI_MATCH(DMI_BOARD_VENDOR,
1477 "Gigabyte Technology Co., Ltd."),
1478 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1479 },
1480 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1481 },
1482 {
1483 .ident = "EP45-DS5",
1484 .matches = {
1485 DMI_MATCH(DMI_BOARD_VENDOR,
1486 "Gigabyte Technology Co., Ltd."),
1487 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1488 },
1489 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1490 },
1491 { } /* terminate list */
1492 };
1493 #undef ENCODE_BUSDEVFN
1494 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1495 unsigned int val;
1496
1497 if (!dmi)
1498 return false;
1499
1500 val = (unsigned long)dmi->driver_data;
1501
1502 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1503 }
1504
ahci_broken_devslp(struct pci_dev * pdev)1505 static bool ahci_broken_devslp(struct pci_dev *pdev)
1506 {
1507 /* device with broken DEVSLP but still showing SDS capability */
1508 static const struct pci_device_id ids[] = {
1509 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1510 {}
1511 };
1512
1513 return pci_match_id(ids, pdev);
1514 }
1515
1516 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1517 static void ahci_gtf_filter_workaround(struct ata_host *host)
1518 {
1519 static const struct dmi_system_id sysids[] = {
1520 /*
1521 * Aspire 3810T issues a bunch of SATA enable commands
1522 * via _GTF including an invalid one and one which is
1523 * rejected by the device. Among the successful ones
1524 * is FPDMA non-zero offset enable which when enabled
1525 * only on the drive side leads to NCQ command
1526 * failures. Filter it out.
1527 */
1528 {
1529 .ident = "Aspire 3810T",
1530 .matches = {
1531 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1532 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1533 },
1534 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1535 },
1536 { }
1537 };
1538 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1539 unsigned int filter;
1540 int i;
1541
1542 if (!dmi)
1543 return;
1544
1545 filter = (unsigned long)dmi->driver_data;
1546 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1547 filter, dmi->ident);
1548
1549 for (i = 0; i < host->n_ports; i++) {
1550 struct ata_port *ap = host->ports[i];
1551 struct ata_link *link;
1552 struct ata_device *dev;
1553
1554 ata_for_each_link(link, ap, EDGE)
1555 ata_for_each_dev(dev, link, ALL)
1556 dev->gtf_filter |= filter;
1557 }
1558 }
1559 #else
ahci_gtf_filter_workaround(struct ata_host * host)1560 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1561 {}
1562 #endif
1563
1564 /*
1565 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1566 * as DUMMY, or detected but eventually get a "link down" and never get up
1567 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1568 * port_map may hold a value of 0x00.
1569 *
1570 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1571 * and can significantly reduce the occurrence of the problem.
1572 *
1573 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1574 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1575 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1576 struct pci_dev *pdev)
1577 {
1578 static const struct dmi_system_id sysids[] = {
1579 {
1580 .ident = "Acer Switch Alpha 12",
1581 .matches = {
1582 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1583 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1584 },
1585 },
1586 { }
1587 };
1588
1589 if (dmi_check_system(sysids)) {
1590 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1591 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1592 hpriv->port_map = 0x7;
1593 hpriv->cap = 0xC734FF02;
1594 }
1595 }
1596 }
1597
1598 #ifdef CONFIG_ARM64
1599 /*
1600 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1601 * Workaround is to make sure all pending IRQs are served before leaving
1602 * handler.
1603 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1604 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1605 {
1606 struct ata_host *host = dev_instance;
1607 struct ahci_host_priv *hpriv;
1608 unsigned int rc = 0;
1609 void __iomem *mmio;
1610 u32 irq_stat, irq_masked;
1611 unsigned int handled = 1;
1612
1613 hpriv = host->private_data;
1614 mmio = hpriv->mmio;
1615 irq_stat = readl(mmio + HOST_IRQ_STAT);
1616 if (!irq_stat)
1617 return IRQ_NONE;
1618
1619 do {
1620 irq_masked = irq_stat & hpriv->port_map;
1621 spin_lock(&host->lock);
1622 rc = ahci_handle_port_intr(host, irq_masked);
1623 if (!rc)
1624 handled = 0;
1625 writel(irq_stat, mmio + HOST_IRQ_STAT);
1626 irq_stat = readl(mmio + HOST_IRQ_STAT);
1627 spin_unlock(&host->lock);
1628 } while (irq_stat);
1629
1630 return IRQ_RETVAL(handled);
1631 }
1632 #endif
1633
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1634 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1635 struct ahci_host_priv *hpriv)
1636 {
1637 int i;
1638 u32 cap;
1639
1640 /*
1641 * Check if this device might have remapped nvme devices.
1642 */
1643 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1644 pci_resource_len(pdev, bar) < SZ_512K ||
1645 bar != AHCI_PCI_BAR_STANDARD ||
1646 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1647 return;
1648
1649 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1650 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1651 if ((cap & (1 << i)) == 0)
1652 continue;
1653 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1654 != PCI_CLASS_STORAGE_EXPRESS)
1655 continue;
1656
1657 /* We've found a remapped device */
1658 hpriv->remapped_nvme++;
1659 }
1660
1661 if (!hpriv->remapped_nvme)
1662 return;
1663
1664 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1665 hpriv->remapped_nvme);
1666 dev_warn(&pdev->dev,
1667 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1668
1669 /*
1670 * Don't rely on the msi-x capability in the remap case,
1671 * share the legacy interrupt across ahci and remapped devices.
1672 */
1673 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1674 }
1675
ahci_get_irq_vector(struct ata_host * host,int port)1676 static int ahci_get_irq_vector(struct ata_host *host, int port)
1677 {
1678 return pci_irq_vector(to_pci_dev(host->dev), port);
1679 }
1680
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1681 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1682 struct ahci_host_priv *hpriv)
1683 {
1684 int nvec;
1685
1686 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1687 return -ENODEV;
1688
1689 /*
1690 * If number of MSIs is less than number of ports then Sharing Last
1691 * Message mode could be enforced. In this case assume that advantage
1692 * of multipe MSIs is negated and use single MSI mode instead.
1693 */
1694 if (n_ports > 1) {
1695 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1696 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1697 if (nvec > 0) {
1698 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1699 hpriv->get_irq_vector = ahci_get_irq_vector;
1700 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1701 return nvec;
1702 }
1703
1704 /*
1705 * Fallback to single MSI mode if the controller
1706 * enforced MRSM mode.
1707 */
1708 printk(KERN_INFO
1709 "ahci: MRSM is on, fallback to single MSI\n");
1710 pci_free_irq_vectors(pdev);
1711 }
1712 }
1713
1714 /*
1715 * If the host is not capable of supporting per-port vectors, fall
1716 * back to single MSI before finally attempting single MSI-X.
1717 */
1718 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1719 if (nvec == 1)
1720 return nvec;
1721 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1722 }
1723
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1724 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1725 struct ahci_host_priv *hpriv)
1726 {
1727 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1728
1729
1730 /* Ignore processing for chipsets that don't use policy */
1731 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1732 return;
1733
1734 /* user modified policy via module param */
1735 if (mobile_lpm_policy != -1) {
1736 policy = mobile_lpm_policy;
1737 goto update_policy;
1738 }
1739
1740 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1741 if (hpriv->cap & HOST_CAP_PART)
1742 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1743 else if (hpriv->cap & HOST_CAP_SSC)
1744 policy = ATA_LPM_MIN_POWER;
1745 }
1746
1747 update_policy:
1748 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1749 ap->target_lpm_policy = policy;
1750 }
1751
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1752 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1753 {
1754 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1755 u16 tmp16;
1756
1757 /*
1758 * Only apply the 6-port PCS quirk for known legacy platforms.
1759 */
1760 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1761 return;
1762
1763 /* Skip applying the quirk on Denverton and beyond */
1764 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1765 return;
1766
1767 /*
1768 * port_map is determined from PORTS_IMPL PCI register which is
1769 * implemented as write or write-once register. If the register
1770 * isn't programmed, ahci automatically generates it from number
1771 * of ports, which is good enough for PCS programming. It is
1772 * otherwise expected that platform firmware enables the ports
1773 * before the OS boots.
1774 */
1775 pci_read_config_word(pdev, PCS_6, &tmp16);
1776 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1777 tmp16 |= hpriv->port_map;
1778 pci_write_config_word(pdev, PCS_6, tmp16);
1779 }
1780 }
1781
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1782 static ssize_t remapped_nvme_show(struct device *dev,
1783 struct device_attribute *attr,
1784 char *buf)
1785 {
1786 struct ata_host *host = dev_get_drvdata(dev);
1787 struct ahci_host_priv *hpriv = host->private_data;
1788
1789 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1790 }
1791
1792 static DEVICE_ATTR_RO(remapped_nvme);
1793
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1794 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1795 {
1796 unsigned int board_id = ent->driver_data;
1797 struct ata_port_info pi = ahci_port_info[board_id];
1798 const struct ata_port_info *ppi[] = { &pi, NULL };
1799 struct device *dev = &pdev->dev;
1800 struct ahci_host_priv *hpriv;
1801 struct ata_host *host;
1802 int n_ports, i, rc;
1803 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1804
1805 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1806
1807 ata_print_version_once(&pdev->dev, DRV_VERSION);
1808
1809 /* The AHCI driver can only drive the SATA ports, the PATA driver
1810 can drive them all so if both drivers are selected make sure
1811 AHCI stays out of the way */
1812 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1813 return -ENODEV;
1814
1815 /* Apple BIOS on MCP89 prevents us using AHCI */
1816 if (is_mcp89_apple(pdev))
1817 ahci_mcp89_apple_enable(pdev);
1818
1819 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1820 * At the moment, we can only use the AHCI mode. Let the users know
1821 * that for SAS drives they're out of luck.
1822 */
1823 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1824 dev_info(&pdev->dev,
1825 "PDC42819 can only drive SATA devices with this driver\n");
1826
1827 /* Some devices use non-standard BARs */
1828 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1829 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1830 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1831 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1832 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1833 if (pdev->device == 0xa01c)
1834 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1835 if (pdev->device == 0xa084)
1836 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1837 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1838 if (pdev->device == 0x7a08)
1839 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1840 }
1841
1842 /* acquire resources */
1843 rc = pcim_enable_device(pdev);
1844 if (rc)
1845 return rc;
1846
1847 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1848 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1849 u8 map;
1850
1851 /* ICH6s share the same PCI ID for both piix and ahci
1852 * modes. Enabling ahci mode while MAP indicates
1853 * combined mode is a bad idea. Yield to ata_piix.
1854 */
1855 pci_read_config_byte(pdev, ICH_MAP, &map);
1856 if (map & 0x3) {
1857 dev_info(&pdev->dev,
1858 "controller is in combined mode, can't enable AHCI mode\n");
1859 return -ENODEV;
1860 }
1861 }
1862
1863 /* AHCI controllers often implement SFF compatible interface.
1864 * Grab all PCI BARs just in case.
1865 */
1866 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1867 if (rc == -EBUSY)
1868 pcim_pin_device(pdev);
1869 if (rc)
1870 return rc;
1871
1872 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1873 if (!hpriv)
1874 return -ENOMEM;
1875 hpriv->flags |= (unsigned long)pi.private_data;
1876
1877 /* MCP65 revision A1 and A2 can't do MSI */
1878 if (board_id == board_ahci_mcp65 &&
1879 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1880 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1881
1882 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1883 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1884 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1885
1886 /* only some SB600s can do 64bit DMA */
1887 if (ahci_sb600_enable_64bit(pdev))
1888 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1889
1890 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1891
1892 /* detect remapped nvme devices */
1893 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1894
1895 sysfs_add_file_to_group(&pdev->dev.kobj,
1896 &dev_attr_remapped_nvme.attr,
1897 NULL);
1898
1899 /* must set flag prior to save config in order to take effect */
1900 if (ahci_broken_devslp(pdev))
1901 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1902
1903 #ifdef CONFIG_ARM64
1904 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1905 pdev->device == 0xa235 &&
1906 pdev->revision < 0x30)
1907 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1908
1909 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1910 hpriv->irq_handler = ahci_thunderx_irq_handler;
1911 #endif
1912
1913 /* save initial config */
1914 ahci_pci_save_initial_config(pdev, hpriv);
1915
1916 /* prepare host */
1917 if (hpriv->cap & HOST_CAP_NCQ) {
1918 pi.flags |= ATA_FLAG_NCQ;
1919 /*
1920 * Auto-activate optimization is supposed to be
1921 * supported on all AHCI controllers indicating NCQ
1922 * capability, but it seems to be broken on some
1923 * chipsets including NVIDIAs.
1924 */
1925 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1926 pi.flags |= ATA_FLAG_FPDMA_AA;
1927
1928 /*
1929 * All AHCI controllers should be forward-compatible
1930 * with the new auxiliary field. This code should be
1931 * conditionalized if any buggy AHCI controllers are
1932 * encountered.
1933 */
1934 pi.flags |= ATA_FLAG_FPDMA_AUX;
1935 }
1936
1937 if (hpriv->cap & HOST_CAP_PMP)
1938 pi.flags |= ATA_FLAG_PMP;
1939
1940 ahci_set_em_messages(hpriv, &pi);
1941
1942 if (ahci_broken_system_poweroff(pdev)) {
1943 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1944 dev_info(&pdev->dev,
1945 "quirky BIOS, skipping spindown on poweroff\n");
1946 }
1947
1948 if (ahci_broken_lpm(pdev)) {
1949 pi.flags |= ATA_FLAG_NO_LPM;
1950 dev_warn(&pdev->dev,
1951 "BIOS update required for Link Power Management support\n");
1952 }
1953
1954 if (ahci_broken_suspend(pdev)) {
1955 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1956 dev_warn(&pdev->dev,
1957 "BIOS update required for suspend/resume\n");
1958 }
1959
1960 if (ahci_broken_online(pdev)) {
1961 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1962 dev_info(&pdev->dev,
1963 "online status unreliable, applying workaround\n");
1964 }
1965
1966
1967 /* Acer SA5-271 workaround modifies private_data */
1968 acer_sa5_271_workaround(hpriv, pdev);
1969
1970 /* CAP.NP sometimes indicate the index of the last enabled
1971 * port, at other times, that of the last possible port, so
1972 * determining the maximum port number requires looking at
1973 * both CAP.NP and port_map.
1974 */
1975 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1976
1977 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1978 if (!host) {
1979 rc = -ENOMEM;
1980 goto err_rm_sysfs_file;
1981 }
1982 host->private_data = hpriv;
1983
1984 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1985 /* legacy intx interrupts */
1986 pci_intx(pdev, 1);
1987 }
1988 hpriv->irq = pci_irq_vector(pdev, 0);
1989
1990 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1991 host->flags |= ATA_HOST_PARALLEL_SCAN;
1992 else
1993 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1994
1995 if (!(hpriv->cap & HOST_CAP_PART))
1996 host->flags |= ATA_HOST_NO_PART;
1997
1998 if (!(hpriv->cap & HOST_CAP_SSC))
1999 host->flags |= ATA_HOST_NO_SSC;
2000
2001 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2002 host->flags |= ATA_HOST_NO_DEVSLP;
2003
2004 if (pi.flags & ATA_FLAG_EM)
2005 ahci_reset_em(host);
2006
2007 for (i = 0; i < host->n_ports; i++) {
2008 struct ata_port *ap = host->ports[i];
2009
2010 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
2011 ata_port_pbar_desc(ap, ahci_pci_bar,
2012 0x100 + ap->port_no * 0x80, "port");
2013
2014 /* set enclosure management message type */
2015 if (ap->flags & ATA_FLAG_EM)
2016 ap->em_message_type = hpriv->em_msg_type;
2017
2018 ahci_update_initial_lpm_policy(ap, hpriv);
2019
2020 /* disabled/not-implemented port */
2021 if (!(hpriv->port_map & (1 << i)))
2022 ap->ops = &ata_dummy_port_ops;
2023 }
2024
2025 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2026 ahci_p5wdh_workaround(host);
2027
2028 /* apply gtf filter quirk */
2029 ahci_gtf_filter_workaround(host);
2030
2031 /* initialize adapter */
2032 rc = ahci_configure_dma_masks(pdev, hpriv);
2033 if (rc)
2034 goto err_rm_sysfs_file;
2035
2036 rc = ahci_pci_reset_controller(host);
2037 if (rc)
2038 goto err_rm_sysfs_file;
2039
2040 ahci_pci_init_controller(host);
2041 ahci_pci_print_info(host);
2042
2043 pci_set_master(pdev);
2044
2045 rc = ahci_host_activate(host, &ahci_sht);
2046 if (rc)
2047 goto err_rm_sysfs_file;
2048
2049 pm_runtime_put_noidle(&pdev->dev);
2050 return 0;
2051
2052 err_rm_sysfs_file:
2053 sysfs_remove_file_from_group(&pdev->dev.kobj,
2054 &dev_attr_remapped_nvme.attr, NULL);
2055 return rc;
2056 }
2057
ahci_shutdown_one(struct pci_dev * pdev)2058 static void ahci_shutdown_one(struct pci_dev *pdev)
2059 {
2060 ata_pci_shutdown_one(pdev);
2061 }
2062
ahci_remove_one(struct pci_dev * pdev)2063 static void ahci_remove_one(struct pci_dev *pdev)
2064 {
2065 sysfs_remove_file_from_group(&pdev->dev.kobj,
2066 &dev_attr_remapped_nvme.attr,
2067 NULL);
2068 pm_runtime_get_noresume(&pdev->dev);
2069 ata_pci_remove_one(pdev);
2070 }
2071
2072 module_pci_driver(ahci_pci_driver);
2073
2074 MODULE_AUTHOR("Jeff Garzik");
2075 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2076 MODULE_LICENSE("GPL");
2077 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2078 MODULE_VERSION(DRV_VERSION);
2079