1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57
58 #include "bnxt_ulp.h"
59 #include "roce_hsi.h"
60 #include "qplib_res.h"
61 #include "qplib_sp.h"
62 #include "qplib_fp.h"
63 #include "qplib_rcfw.h"
64 #include "bnxt_re.h"
65 #include "ib_verbs.h"
66 #include <rdma/bnxt_re-abi.h>
67 #include "bnxt.h"
68 #include "hw_counters.h"
69
70 static char version[] =
71 BNXT_RE_DESC "\n";
72
73 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
74 MODULE_DESCRIPTION(BNXT_RE_DESC);
75 MODULE_LICENSE("Dual BSD/GPL");
76
77 /* globals */
78 static DEFINE_MUTEX(bnxt_re_mutex);
79
80 static void bnxt_re_stop_irq(void *handle);
81 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
82 static int bnxt_re_netdev_event(struct notifier_block *notifier,
83 unsigned long event, void *ptr);
84 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
85 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev);
86 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
87
88 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
89 u32 *offset);
bnxt_re_set_db_offset(struct bnxt_re_dev * rdev)90 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
91 {
92 struct bnxt_qplib_chip_ctx *cctx;
93 struct bnxt_en_dev *en_dev;
94 struct bnxt_qplib_res *res;
95 u32 l2db_len = 0;
96 u32 offset = 0;
97 u32 barlen;
98 int rc;
99
100 res = &rdev->qplib_res;
101 en_dev = rdev->en_dev;
102 cctx = rdev->chip_ctx;
103
104 /* Issue qcfg */
105 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
106 if (rc)
107 dev_info(rdev_to_dev(rdev),
108 "Couldn't get DB bar size, Low latency framework is disabled\n");
109 /* set register offsets for both UC and WC */
110 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
111 res->dpi_tbl.ucreg.offset = offset;
112 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
113 } else {
114 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
115 BNXT_QPLIB_DBR_PF_DB_OFFSET;
116 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
117 }
118
119 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
120 * is equal to the DB-Bar actual size. This indicates that L2
121 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
122 * in such cases and DB-push will be disabled.
123 */
124 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
125 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
126 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
127 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
128 }
129 }
130
bnxt_re_set_drv_mode(struct bnxt_re_dev * rdev,u8 mode)131 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode)
132 {
133 struct bnxt_qplib_chip_ctx *cctx;
134
135 cctx = rdev->chip_ctx;
136 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
137 mode : BNXT_QPLIB_WQE_MODE_STATIC;
138 if (bnxt_re_hwrm_qcaps(rdev))
139 dev_err(rdev_to_dev(rdev),
140 "Failed to query hwrm qcaps\n");
141 }
142
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)143 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
144 {
145 struct bnxt_qplib_chip_ctx *chip_ctx;
146
147 if (!rdev->chip_ctx)
148 return;
149 chip_ctx = rdev->chip_ctx;
150 rdev->chip_ctx = NULL;
151 rdev->rcfw.res = NULL;
152 rdev->qplib_res.cctx = NULL;
153 rdev->qplib_res.pdev = NULL;
154 rdev->qplib_res.netdev = NULL;
155 kfree(chip_ctx);
156 }
157
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev,u8 wqe_mode)158 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode)
159 {
160 struct bnxt_qplib_chip_ctx *chip_ctx;
161 struct bnxt_en_dev *en_dev;
162 int rc;
163
164 en_dev = rdev->en_dev;
165
166 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
167 if (!chip_ctx)
168 return -ENOMEM;
169 chip_ctx->chip_num = en_dev->chip_num;
170 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
171
172 rdev->chip_ctx = chip_ctx;
173 /* rest members to follow eventually */
174
175 rdev->qplib_res.cctx = rdev->chip_ctx;
176 rdev->rcfw.res = &rdev->qplib_res;
177 rdev->qplib_res.dattr = &rdev->dev_attr;
178 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
179
180 bnxt_re_set_drv_mode(rdev, wqe_mode);
181
182 bnxt_re_set_db_offset(rdev);
183 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
184 if (rc) {
185 kfree(rdev->chip_ctx);
186 rdev->chip_ctx = NULL;
187 return rc;
188 }
189
190 if (bnxt_qplib_determine_atomics(en_dev->pdev))
191 ibdev_info(&rdev->ibdev,
192 "platform doesn't support global atomics.");
193 return 0;
194 }
195
196 /* SR-IOV helper functions */
197
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)198 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
199 {
200 if (BNXT_EN_VF(rdev->en_dev))
201 rdev->is_virtfn = 1;
202 }
203
204 /* Set the maximum number of each resource that the driver actually wants
205 * to allocate. This may be up to the maximum number the firmware has
206 * reserved for the function. The driver may choose to allocate fewer
207 * resources than the firmware maximum.
208 */
bnxt_re_limit_pf_res(struct bnxt_re_dev * rdev)209 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
210 {
211 struct bnxt_qplib_dev_attr *attr;
212 struct bnxt_qplib_ctx *ctx;
213 int i;
214
215 attr = &rdev->dev_attr;
216 ctx = &rdev->qplib_ctx;
217
218 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
219 attr->max_qp);
220 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
221 /* Use max_mr from fw since max_mrw does not get set */
222 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
223 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
224 attr->max_srq);
225 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
226 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
227 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
228 rdev->qplib_ctx.tqm_ctx.qcount[i] =
229 rdev->dev_attr.tqm_alloc_reqs[i];
230 }
231
bnxt_re_limit_vf_res(struct bnxt_qplib_ctx * qplib_ctx,u32 num_vf)232 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
233 {
234 struct bnxt_qplib_vf_res *vf_res;
235 u32 mrws = 0;
236 u32 vf_pct;
237 u32 nvfs;
238
239 vf_res = &qplib_ctx->vf_res;
240 /*
241 * Reserve a set of resources for the PF. Divide the remaining
242 * resources among the VFs
243 */
244 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
245 nvfs = num_vf;
246 num_vf = 100 * num_vf;
247 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
248 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
249 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
250 /*
251 * The driver allows many more MRs than other resources. If the
252 * firmware does also, then reserve a fixed amount for the PF and
253 * divide the rest among VFs. VFs may use many MRs for NFS
254 * mounts, ISER, NVME applications, etc. If the firmware severely
255 * restricts the number of MRs, then let PF have half and divide
256 * the rest among VFs, as for the other resource types.
257 */
258 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
259 mrws = qplib_ctx->mrw_count * vf_pct;
260 nvfs = num_vf;
261 } else {
262 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
263 }
264 vf_res->max_mrw_per_vf = (mrws / nvfs);
265 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
266 }
267
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)268 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
269 {
270 u32 num_vfs;
271
272 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
273 bnxt_re_limit_pf_res(rdev);
274
275 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
276 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
277 if (num_vfs)
278 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
279 }
280
bnxt_re_vf_res_config(struct bnxt_re_dev * rdev)281 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
282 {
283
284 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
285 return;
286 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
287 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
288 bnxt_re_set_resource_limits(rdev);
289 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
290 &rdev->qplib_ctx);
291 }
292 }
293
bnxt_re_shutdown(struct auxiliary_device * adev)294 static void bnxt_re_shutdown(struct auxiliary_device *adev)
295 {
296 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
297
298 if (!rdev)
299 return;
300 ib_unregister_device(&rdev->ibdev);
301 bnxt_re_dev_uninit(rdev);
302 }
303
bnxt_re_stop_irq(void * handle)304 static void bnxt_re_stop_irq(void *handle)
305 {
306 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
307 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
308 struct bnxt_qplib_nq *nq;
309 int indx;
310
311 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) {
312 nq = &rdev->nq[indx - 1];
313 bnxt_qplib_nq_stop_irq(nq, false);
314 }
315
316 bnxt_qplib_rcfw_stop_irq(rcfw, false);
317 }
318
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)319 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
320 {
321 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
322 struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries;
323 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
324 struct bnxt_qplib_nq *nq;
325 int indx, rc;
326
327 if (!ent) {
328 /* Not setting the f/w timeout bit in rcfw.
329 * During the driver unload the first command
330 * to f/w will timeout and that will set the
331 * timeout bit.
332 */
333 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
334 return;
335 }
336
337 /* Vectors may change after restart, so update with new vectors
338 * in device sctructure.
339 */
340 for (indx = 0; indx < rdev->num_msix; indx++)
341 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector;
342
343 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
344 false);
345 if (rc) {
346 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
347 return;
348 }
349 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) {
350 nq = &rdev->nq[indx - 1];
351 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
352 msix_ent[indx].vector, false);
353 if (rc) {
354 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
355 indx - 1);
356 return;
357 }
358 }
359 }
360
361 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
362 .ulp_irq_stop = bnxt_re_stop_irq,
363 .ulp_irq_restart = bnxt_re_start_irq
364 };
365
366 /* RoCE -> Net driver */
367
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)368 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
369 {
370 struct bnxt_en_dev *en_dev;
371 int rc;
372
373 en_dev = rdev->en_dev;
374
375 rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev);
376 if (!rc)
377 rdev->qplib_res.pdev = rdev->en_dev->pdev;
378 return rc;
379 }
380
bnxt_re_init_hwrm_hdr(struct input * hdr,u16 opcd)381 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
382 {
383 hdr->req_type = cpu_to_le16(opcd);
384 hdr->cmpl_ring = cpu_to_le16(-1);
385 hdr->target_id = cpu_to_le16(-1);
386 }
387
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)388 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
389 int msg_len, void *resp, int resp_max_len,
390 int timeout)
391 {
392 fw_msg->msg = msg;
393 fw_msg->msg_len = msg_len;
394 fw_msg->resp = resp;
395 fw_msg->resp_max_len = resp_max_len;
396 fw_msg->timeout = timeout;
397 }
398
399 /* Query device config using common hwrm */
bnxt_re_hwrm_qcfg(struct bnxt_re_dev * rdev,u32 * db_len,u32 * offset)400 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
401 u32 *offset)
402 {
403 struct bnxt_en_dev *en_dev = rdev->en_dev;
404 struct hwrm_func_qcfg_output resp = {0};
405 struct hwrm_func_qcfg_input req = {0};
406 struct bnxt_fw_msg fw_msg = {};
407 int rc;
408
409 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
410 req.fid = cpu_to_le16(0xffff);
411 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
412 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
413 rc = bnxt_send_msg(en_dev, &fw_msg);
414 if (!rc) {
415 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
416 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
417 }
418 return rc;
419 }
420
421 /* Query function capabilities using common hwrm */
bnxt_re_hwrm_qcaps(struct bnxt_re_dev * rdev)422 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
423 {
424 struct bnxt_en_dev *en_dev = rdev->en_dev;
425 struct hwrm_func_qcaps_output resp = {};
426 struct hwrm_func_qcaps_input req = {};
427 struct bnxt_qplib_chip_ctx *cctx;
428 struct bnxt_fw_msg fw_msg = {};
429 int rc;
430
431 cctx = rdev->chip_ctx;
432 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
433 req.fid = cpu_to_le16(0xffff);
434 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
435 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
436
437 rc = bnxt_send_msg(en_dev, &fw_msg);
438 if (rc)
439 return rc;
440 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
441
442 cctx->modes.dbr_pacing =
443 le32_to_cpu(resp.flags_ext2) &
444 FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED;
445 return 0;
446 }
447
bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev * rdev)448 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
449 {
450 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
451 struct hwrm_func_dbr_pacing_qcfg_input req = {};
452 struct bnxt_en_dev *en_dev = rdev->en_dev;
453 struct bnxt_qplib_chip_ctx *cctx;
454 struct bnxt_fw_msg fw_msg = {};
455 int rc;
456
457 cctx = rdev->chip_ctx;
458 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
459 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
460 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
461 rc = bnxt_send_msg(en_dev, &fw_msg);
462 if (rc)
463 return rc;
464
465 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
466 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
467 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
468 cctx->dbr_stat_db_fifo =
469 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
470 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
471 return 0;
472 }
473
474 /* Update the pacing tunable parameters to the default values */
bnxt_re_set_default_pacing_data(struct bnxt_re_dev * rdev)475 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
476 {
477 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
478
479 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
480 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
481 pacing_data->alarm_th =
482 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
483 }
484
__wait_for_fifo_occupancy_below_th(struct bnxt_re_dev * rdev)485 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
486 {
487 u32 read_val, fifo_occup;
488
489 /* loop shouldn't run infintely as the occupancy usually goes
490 * below pacing algo threshold as soon as pacing kicks in.
491 */
492 while (1) {
493 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
494 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
495 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
496 BNXT_RE_DB_FIFO_ROOM_SHIFT);
497 /* Fifo occupancy cannot be greater the MAX FIFO depth */
498 if (fifo_occup > BNXT_RE_MAX_FIFO_DEPTH)
499 break;
500
501 if (fifo_occup < rdev->qplib_res.pacing_data->pacing_th)
502 break;
503 }
504 }
505
bnxt_re_db_fifo_check(struct work_struct * work)506 static void bnxt_re_db_fifo_check(struct work_struct *work)
507 {
508 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
509 dbq_fifo_check_work);
510 struct bnxt_qplib_db_pacing_data *pacing_data;
511 u32 pacing_save;
512
513 if (!mutex_trylock(&rdev->pacing.dbq_lock))
514 return;
515 pacing_data = rdev->qplib_res.pacing_data;
516 pacing_save = rdev->pacing.do_pacing_save;
517 __wait_for_fifo_occupancy_below_th(rdev);
518 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
519 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
520 /* Double the do_pacing value during the congestion */
521 pacing_save = pacing_save << 1;
522 } else {
523 /*
524 * when a new congestion is detected increase the do_pacing
525 * by 8 times. And also increase the pacing_th by 4 times. The
526 * reason to increase pacing_th is to give more space for the
527 * queue to oscillate down without getting empty, but also more
528 * room for the queue to increase without causing another alarm.
529 */
530 pacing_save = pacing_save << 3;
531 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
532 }
533
534 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
535 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
536
537 pacing_data->do_pacing = pacing_save;
538 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
539 pacing_data->alarm_th =
540 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
541 schedule_delayed_work(&rdev->dbq_pacing_work,
542 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
543 rdev->stats.pacing.alerts++;
544 mutex_unlock(&rdev->pacing.dbq_lock);
545 }
546
bnxt_re_pacing_timer_exp(struct work_struct * work)547 static void bnxt_re_pacing_timer_exp(struct work_struct *work)
548 {
549 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
550 dbq_pacing_work.work);
551 struct bnxt_qplib_db_pacing_data *pacing_data;
552 u32 read_val, fifo_occup;
553
554 if (!mutex_trylock(&rdev->pacing.dbq_lock))
555 return;
556
557 pacing_data = rdev->qplib_res.pacing_data;
558 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
559 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
560 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
561 BNXT_RE_DB_FIFO_ROOM_SHIFT);
562
563 if (fifo_occup > pacing_data->pacing_th)
564 goto restart_timer;
565
566 /*
567 * Instead of immediately going back to the default do_pacing
568 * reduce it by 1/8 times and restart the timer.
569 */
570 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
571 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
572 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
573 bnxt_re_set_default_pacing_data(rdev);
574 rdev->stats.pacing.complete++;
575 goto dbq_unlock;
576 }
577
578 restart_timer:
579 schedule_delayed_work(&rdev->dbq_pacing_work,
580 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
581 rdev->stats.pacing.resched++;
582 dbq_unlock:
583 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
584 mutex_unlock(&rdev->pacing.dbq_lock);
585 }
586
bnxt_re_pacing_alert(struct bnxt_re_dev * rdev)587 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
588 {
589 struct bnxt_qplib_db_pacing_data *pacing_data;
590
591 if (!rdev->pacing.dbr_pacing)
592 return;
593 mutex_lock(&rdev->pacing.dbq_lock);
594 pacing_data = rdev->qplib_res.pacing_data;
595
596 /*
597 * Increase the alarm_th to max so that other user lib instances do not
598 * keep alerting the driver.
599 */
600 pacing_data->alarm_th = BNXT_RE_MAX_FIFO_DEPTH;
601 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
602 cancel_work_sync(&rdev->dbq_fifo_check_work);
603 schedule_work(&rdev->dbq_fifo_check_work);
604 mutex_unlock(&rdev->pacing.dbq_lock);
605 }
606
bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev * rdev)607 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
608 {
609 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev))
610 return -EIO;
611
612 /* Allocate a page for app use */
613 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
614 if (!rdev->pacing.dbr_page)
615 return -ENOMEM;
616
617 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
618 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
619
620 /* MAP HW window 2 for reading db fifo depth */
621 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
622 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
623 rdev->pacing.dbr_db_fifo_reg_off =
624 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
625 BNXT_RE_GRC_FIFO_REG_BASE;
626 rdev->pacing.dbr_bar_addr =
627 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
628
629 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
630 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
631 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
632 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
633 rdev->qplib_res.pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH;
634 rdev->qplib_res.pacing_data->fifo_room_mask = BNXT_RE_DB_FIFO_ROOM_MASK;
635 rdev->qplib_res.pacing_data->fifo_room_shift = BNXT_RE_DB_FIFO_ROOM_SHIFT;
636 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
637 bnxt_re_set_default_pacing_data(rdev);
638 /* Initialize worker for DBR Pacing */
639 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
640 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
641 return 0;
642 }
643
bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev * rdev)644 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
645 {
646 cancel_work_sync(&rdev->dbq_fifo_check_work);
647 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
648 if (rdev->pacing.dbr_page)
649 free_page((u64)rdev->pacing.dbr_page);
650
651 rdev->pacing.dbr_page = NULL;
652 rdev->pacing.dbr_pacing = false;
653 }
654
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)655 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
656 u16 fw_ring_id, int type)
657 {
658 struct bnxt_en_dev *en_dev;
659 struct hwrm_ring_free_input req = {};
660 struct hwrm_ring_free_output resp;
661 struct bnxt_fw_msg fw_msg = {};
662 int rc = -EINVAL;
663
664 if (!rdev)
665 return rc;
666
667 en_dev = rdev->en_dev;
668
669 if (!en_dev)
670 return rc;
671
672 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
673 return 0;
674
675 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
676 req.ring_type = type;
677 req.ring_id = cpu_to_le16(fw_ring_id);
678 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
679 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
680 rc = bnxt_send_msg(en_dev, &fw_msg);
681 if (rc)
682 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
683 req.ring_id, rc);
684 return rc;
685 }
686
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,struct bnxt_re_ring_attr * ring_attr,u16 * fw_ring_id)687 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
688 struct bnxt_re_ring_attr *ring_attr,
689 u16 *fw_ring_id)
690 {
691 struct bnxt_en_dev *en_dev = rdev->en_dev;
692 struct hwrm_ring_alloc_input req = {};
693 struct hwrm_ring_alloc_output resp;
694 struct bnxt_fw_msg fw_msg = {};
695 int rc = -EINVAL;
696
697 if (!en_dev)
698 return rc;
699
700 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
701 req.enables = 0;
702 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
703 if (ring_attr->pages > 1) {
704 /* Page size is in log2 units */
705 req.page_size = BNXT_PAGE_SHIFT;
706 req.page_tbl_depth = 1;
707 }
708 req.fbo = 0;
709 /* Association of ring index with doorbell index and MSIX number */
710 req.logical_id = cpu_to_le16(ring_attr->lrid);
711 req.length = cpu_to_le32(ring_attr->depth + 1);
712 req.ring_type = ring_attr->type;
713 req.int_mode = ring_attr->mode;
714 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
715 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
716 rc = bnxt_send_msg(en_dev, &fw_msg);
717 if (!rc)
718 *fw_ring_id = le16_to_cpu(resp.ring_id);
719
720 return rc;
721 }
722
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)723 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
724 u32 fw_stats_ctx_id)
725 {
726 struct bnxt_en_dev *en_dev = rdev->en_dev;
727 struct hwrm_stat_ctx_free_input req = {};
728 struct hwrm_stat_ctx_free_output resp = {};
729 struct bnxt_fw_msg fw_msg = {};
730 int rc = -EINVAL;
731
732 if (!en_dev)
733 return rc;
734
735 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
736 return 0;
737
738 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
739 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
740 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
741 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
742 rc = bnxt_send_msg(en_dev, &fw_msg);
743 if (rc)
744 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
745 rc);
746
747 return rc;
748 }
749
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,dma_addr_t dma_map,u32 * fw_stats_ctx_id)750 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
751 dma_addr_t dma_map,
752 u32 *fw_stats_ctx_id)
753 {
754 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
755 struct hwrm_stat_ctx_alloc_output resp = {};
756 struct hwrm_stat_ctx_alloc_input req = {};
757 struct bnxt_en_dev *en_dev = rdev->en_dev;
758 struct bnxt_fw_msg fw_msg = {};
759 int rc = -EINVAL;
760
761 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
762
763 if (!en_dev)
764 return rc;
765
766 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
767 req.update_period_ms = cpu_to_le32(1000);
768 req.stats_dma_addr = cpu_to_le64(dma_map);
769 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
770 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
771 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
772 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
773 rc = bnxt_send_msg(en_dev, &fw_msg);
774 if (!rc)
775 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
776
777 return rc;
778 }
779
bnxt_re_disassociate_ucontext(struct ib_ucontext * ibcontext)780 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
781 {
782 }
783
784 /* Device */
785
bnxt_re_from_netdev(struct net_device * netdev)786 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
787 {
788 struct ib_device *ibdev =
789 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
790 if (!ibdev)
791 return NULL;
792
793 return container_of(ibdev, struct bnxt_re_dev, ibdev);
794 }
795
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)796 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
797 char *buf)
798 {
799 struct bnxt_re_dev *rdev =
800 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
801
802 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
803 }
804 static DEVICE_ATTR_RO(hw_rev);
805
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)806 static ssize_t hca_type_show(struct device *device,
807 struct device_attribute *attr, char *buf)
808 {
809 struct bnxt_re_dev *rdev =
810 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
811
812 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
813 }
814 static DEVICE_ATTR_RO(hca_type);
815
816 static struct attribute *bnxt_re_attributes[] = {
817 &dev_attr_hw_rev.attr,
818 &dev_attr_hca_type.attr,
819 NULL
820 };
821
822 static const struct attribute_group bnxt_re_dev_attr_group = {
823 .attrs = bnxt_re_attributes,
824 };
825
826 static const struct ib_device_ops bnxt_re_dev_ops = {
827 .owner = THIS_MODULE,
828 .driver_id = RDMA_DRIVER_BNXT_RE,
829 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
830
831 .add_gid = bnxt_re_add_gid,
832 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
833 .alloc_mr = bnxt_re_alloc_mr,
834 .alloc_pd = bnxt_re_alloc_pd,
835 .alloc_ucontext = bnxt_re_alloc_ucontext,
836 .create_ah = bnxt_re_create_ah,
837 .create_cq = bnxt_re_create_cq,
838 .create_qp = bnxt_re_create_qp,
839 .create_srq = bnxt_re_create_srq,
840 .create_user_ah = bnxt_re_create_ah,
841 .dealloc_pd = bnxt_re_dealloc_pd,
842 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
843 .del_gid = bnxt_re_del_gid,
844 .dereg_mr = bnxt_re_dereg_mr,
845 .destroy_ah = bnxt_re_destroy_ah,
846 .destroy_cq = bnxt_re_destroy_cq,
847 .destroy_qp = bnxt_re_destroy_qp,
848 .destroy_srq = bnxt_re_destroy_srq,
849 .device_group = &bnxt_re_dev_attr_group,
850 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
851 .get_dev_fw_str = bnxt_re_query_fw_str,
852 .get_dma_mr = bnxt_re_get_dma_mr,
853 .get_hw_stats = bnxt_re_ib_get_hw_stats,
854 .get_link_layer = bnxt_re_get_link_layer,
855 .get_port_immutable = bnxt_re_get_port_immutable,
856 .map_mr_sg = bnxt_re_map_mr_sg,
857 .mmap = bnxt_re_mmap,
858 .mmap_free = bnxt_re_mmap_free,
859 .modify_qp = bnxt_re_modify_qp,
860 .modify_srq = bnxt_re_modify_srq,
861 .poll_cq = bnxt_re_poll_cq,
862 .post_recv = bnxt_re_post_recv,
863 .post_send = bnxt_re_post_send,
864 .post_srq_recv = bnxt_re_post_srq_recv,
865 .query_ah = bnxt_re_query_ah,
866 .query_device = bnxt_re_query_device,
867 .query_pkey = bnxt_re_query_pkey,
868 .query_port = bnxt_re_query_port,
869 .query_qp = bnxt_re_query_qp,
870 .query_srq = bnxt_re_query_srq,
871 .reg_user_mr = bnxt_re_reg_user_mr,
872 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
873 .req_notify_cq = bnxt_re_req_notify_cq,
874 .resize_cq = bnxt_re_resize_cq,
875 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
876 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
877 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
878 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
879 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
880 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
881 };
882
bnxt_re_register_ib(struct bnxt_re_dev * rdev)883 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
884 {
885 struct ib_device *ibdev = &rdev->ibdev;
886 int ret;
887
888 /* ib device init */
889 ibdev->node_type = RDMA_NODE_IB_CA;
890 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
891 strlen(BNXT_RE_DESC) + 5);
892 ibdev->phys_port_cnt = 1;
893
894 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
895
896 ibdev->num_comp_vectors = rdev->num_msix - 1;
897 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
898 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
899
900 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
901 ibdev->driver_def = bnxt_re_uapi_defs;
902
903 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
904 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
905 if (ret)
906 return ret;
907
908 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
909 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
910 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
911 }
912
bnxt_re_dev_add(struct bnxt_aux_priv * aux_priv,struct bnxt_en_dev * en_dev)913 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv,
914 struct bnxt_en_dev *en_dev)
915 {
916 struct bnxt_re_dev *rdev;
917
918 /* Allocate bnxt_re_dev instance here */
919 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
920 if (!rdev) {
921 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
922 ROCE_DRV_MODULE_NAME);
923 return NULL;
924 }
925 /* Default values */
926 rdev->nb.notifier_call = NULL;
927 rdev->netdev = en_dev->net;
928 rdev->en_dev = en_dev;
929 rdev->id = rdev->en_dev->pdev->devfn;
930 INIT_LIST_HEAD(&rdev->qp_list);
931 mutex_init(&rdev->qp_lock);
932 mutex_init(&rdev->pacing.dbq_lock);
933 atomic_set(&rdev->stats.res.qp_count, 0);
934 atomic_set(&rdev->stats.res.cq_count, 0);
935 atomic_set(&rdev->stats.res.srq_count, 0);
936 atomic_set(&rdev->stats.res.mr_count, 0);
937 atomic_set(&rdev->stats.res.mw_count, 0);
938 atomic_set(&rdev->stats.res.ah_count, 0);
939 atomic_set(&rdev->stats.res.pd_count, 0);
940 rdev->cosq[0] = 0xFFFF;
941 rdev->cosq[1] = 0xFFFF;
942
943 return rdev;
944 }
945
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)946 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
947 *unaffi_async)
948 {
949 switch (unaffi_async->event) {
950 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
951 break;
952 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
953 break;
954 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
955 break;
956 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
957 break;
958 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
959 break;
960 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
961 break;
962 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
963 break;
964 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
965 break;
966 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
967 break;
968 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
969 break;
970 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
971 break;
972 default:
973 return -EINVAL;
974 }
975 return 0;
976 }
977
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)978 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
979 struct bnxt_re_qp *qp)
980 {
981 struct ib_event event = {};
982 unsigned int flags;
983
984 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
985 rdma_is_kernel_res(&qp->ib_qp.res)) {
986 flags = bnxt_re_lock_cqs(qp);
987 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
988 bnxt_re_unlock_cqs(qp, flags);
989 }
990
991 if (qp->qplib_qp.srq) {
992 event.device = &qp->rdev->ibdev;
993 event.element.qp = &qp->ib_qp;
994 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
995 }
996
997 if (event.device && qp->ib_qp.event_handler)
998 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
999
1000 return 0;
1001 }
1002
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)1003 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1004 void *obj)
1005 {
1006 int rc = 0;
1007 u8 event;
1008
1009 if (!obj)
1010 return rc; /* QP was already dead, still return success */
1011
1012 event = affi_async->event;
1013 if (event == CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION) {
1014 struct bnxt_qplib_qp *lib_qp = obj;
1015 struct bnxt_re_qp *qp = container_of(lib_qp, struct bnxt_re_qp,
1016 qplib_qp);
1017 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1018 }
1019 return rc;
1020 }
1021
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)1022 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1023 void *aeqe, void *obj)
1024 {
1025 struct creq_qp_event *affi_async;
1026 struct creq_func_event *unaffi_async;
1027 u8 type;
1028 int rc;
1029
1030 type = ((struct creq_base *)aeqe)->type;
1031 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1032 unaffi_async = aeqe;
1033 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1034 } else {
1035 affi_async = aeqe;
1036 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1037 }
1038
1039 return rc;
1040 }
1041
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)1042 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1043 struct bnxt_qplib_srq *handle, u8 event)
1044 {
1045 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1046 qplib_srq);
1047 struct ib_event ib_event;
1048
1049 ib_event.device = &srq->rdev->ibdev;
1050 ib_event.element.srq = &srq->ib_srq;
1051 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1052 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1053 else
1054 ib_event.event = IB_EVENT_SRQ_ERR;
1055
1056 if (srq->ib_srq.event_handler) {
1057 /* Lock event_handler? */
1058 (*srq->ib_srq.event_handler)(&ib_event,
1059 srq->ib_srq.srq_context);
1060 }
1061 return 0;
1062 }
1063
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)1064 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1065 struct bnxt_qplib_cq *handle)
1066 {
1067 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1068 qplib_cq);
1069
1070 if (cq->ib_cq.comp_handler) {
1071 /* Lock comp_handler? */
1072 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1073 }
1074
1075 return 0;
1076 }
1077
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)1078 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1079 {
1080 int i;
1081
1082 for (i = 1; i < rdev->num_msix; i++)
1083 bnxt_qplib_disable_nq(&rdev->nq[i - 1]);
1084
1085 if (rdev->qplib_res.rcfw)
1086 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1087 }
1088
bnxt_re_init_res(struct bnxt_re_dev * rdev)1089 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1090 {
1091 int num_vec_enabled = 0;
1092 int rc = 0, i;
1093 u32 db_offt;
1094
1095 bnxt_qplib_init_res(&rdev->qplib_res);
1096
1097 for (i = 1; i < rdev->num_msix ; i++) {
1098 db_offt = rdev->en_dev->msix_entries[i].db_offset;
1099 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
1100 i - 1, rdev->en_dev->msix_entries[i].vector,
1101 db_offt, &bnxt_re_cqn_handler,
1102 &bnxt_re_srqn_handler);
1103 if (rc) {
1104 ibdev_err(&rdev->ibdev,
1105 "Failed to enable NQ with rc = 0x%x", rc);
1106 goto fail;
1107 }
1108 num_vec_enabled++;
1109 }
1110 return 0;
1111 fail:
1112 for (i = num_vec_enabled; i >= 0; i--)
1113 bnxt_qplib_disable_nq(&rdev->nq[i]);
1114 return rc;
1115 }
1116
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)1117 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1118 {
1119 u8 type;
1120 int i;
1121
1122 for (i = 0; i < rdev->num_msix - 1; i++) {
1123 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1124 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1125 bnxt_qplib_free_nq(&rdev->nq[i]);
1126 rdev->nq[i].res = NULL;
1127 }
1128 }
1129
bnxt_re_free_res(struct bnxt_re_dev * rdev)1130 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1131 {
1132 bnxt_re_free_nq_res(rdev);
1133
1134 if (rdev->qplib_res.dpi_tbl.max) {
1135 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1136 &rdev->dpi_privileged);
1137 }
1138 if (rdev->qplib_res.rcfw) {
1139 bnxt_qplib_free_res(&rdev->qplib_res);
1140 rdev->qplib_res.rcfw = NULL;
1141 }
1142 }
1143
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)1144 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1145 {
1146 struct bnxt_re_ring_attr rattr = {};
1147 int num_vec_created = 0;
1148 int rc, i;
1149 u8 type;
1150
1151 /* Configure and allocate resources for qplib */
1152 rdev->qplib_res.rcfw = &rdev->rcfw;
1153 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1154 if (rc)
1155 goto fail;
1156
1157 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev,
1158 rdev->netdev, &rdev->dev_attr);
1159 if (rc)
1160 goto fail;
1161
1162 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1163 &rdev->dpi_privileged,
1164 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1165 if (rc)
1166 goto dealloc_res;
1167
1168 for (i = 0; i < rdev->num_msix - 1; i++) {
1169 struct bnxt_qplib_nq *nq;
1170
1171 nq = &rdev->nq[i];
1172 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1173 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]);
1174 if (rc) {
1175 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1176 i, rc);
1177 goto free_nq;
1178 }
1179 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1180 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1181 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count;
1182 rattr.type = type;
1183 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1184 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1185 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx;
1186 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1187 if (rc) {
1188 ibdev_err(&rdev->ibdev,
1189 "Failed to allocate NQ fw id with rc = 0x%x",
1190 rc);
1191 bnxt_qplib_free_nq(&rdev->nq[i]);
1192 goto free_nq;
1193 }
1194 num_vec_created++;
1195 }
1196 return 0;
1197 free_nq:
1198 for (i = num_vec_created - 1; i >= 0; i--) {
1199 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1200 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1201 bnxt_qplib_free_nq(&rdev->nq[i]);
1202 }
1203 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1204 &rdev->dpi_privileged);
1205 dealloc_res:
1206 bnxt_qplib_free_res(&rdev->qplib_res);
1207
1208 fail:
1209 rdev->qplib_res.rcfw = NULL;
1210 return rc;
1211 }
1212
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1213 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1214 u8 port_num, enum ib_event_type event)
1215 {
1216 struct ib_event ib_event;
1217
1218 ib_event.device = ibdev;
1219 if (qp) {
1220 ib_event.element.qp = qp;
1221 ib_event.event = event;
1222 if (qp->event_handler)
1223 qp->event_handler(&ib_event, qp->qp_context);
1224
1225 } else {
1226 ib_event.element.port_num = port_num;
1227 ib_event.event = event;
1228 ib_dispatch_event(&ib_event);
1229 }
1230 }
1231
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1232 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1233 struct bnxt_re_qp *qp)
1234 {
1235 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1236 (qp == rdev->gsi_ctx.gsi_sqp);
1237 }
1238
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1239 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1240 {
1241 int mask = IB_QP_STATE;
1242 struct ib_qp_attr qp_attr;
1243 struct bnxt_re_qp *qp;
1244
1245 qp_attr.qp_state = IB_QPS_ERR;
1246 mutex_lock(&rdev->qp_lock);
1247 list_for_each_entry(qp, &rdev->qp_list, list) {
1248 /* Modify the state of all QPs except QP1/Shadow QP */
1249 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1250 if (qp->qplib_qp.state !=
1251 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1252 qp->qplib_qp.state !=
1253 CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1254 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1255 1, IB_EVENT_QP_FATAL);
1256 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask,
1257 NULL);
1258 }
1259 }
1260 }
1261 mutex_unlock(&rdev->qp_lock);
1262 }
1263
bnxt_re_update_gid(struct bnxt_re_dev * rdev)1264 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1265 {
1266 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1267 struct bnxt_qplib_gid gid;
1268 u16 gid_idx, index;
1269 int rc = 0;
1270
1271 if (!ib_device_try_get(&rdev->ibdev))
1272 return 0;
1273
1274 for (index = 0; index < sgid_tbl->active; index++) {
1275 gid_idx = sgid_tbl->hw_id[index];
1276
1277 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1278 sizeof(bnxt_qplib_gid_zero)))
1279 continue;
1280 /* need to modify the VLAN enable setting of non VLAN GID only
1281 * as setting is done for VLAN GID while adding GID
1282 */
1283 if (sgid_tbl->vlan[index])
1284 continue;
1285
1286 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1287
1288 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1289 rdev->qplib_res.netdev->dev_addr);
1290 }
1291
1292 ib_device_put(&rdev->ibdev);
1293 return rc;
1294 }
1295
bnxt_re_get_priority_mask(struct bnxt_re_dev * rdev)1296 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1297 {
1298 u32 prio_map = 0, tmp_map = 0;
1299 struct net_device *netdev;
1300 struct dcb_app app = {};
1301
1302 netdev = rdev->netdev;
1303
1304 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1305 app.protocol = ETH_P_IBOE;
1306 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1307 prio_map = tmp_map;
1308
1309 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1310 app.protocol = ROCE_V2_UDP_DPORT;
1311 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1312 prio_map |= tmp_map;
1313
1314 return prio_map;
1315 }
1316
bnxt_re_setup_qos(struct bnxt_re_dev * rdev)1317 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1318 {
1319 u8 prio_map = 0;
1320
1321 /* Get priority for roce */
1322 prio_map = bnxt_re_get_priority_mask(rdev);
1323
1324 if (prio_map == rdev->cur_prio_map)
1325 return 0;
1326 rdev->cur_prio_map = prio_map;
1327 /* Actual priorities are not programmed as they are already
1328 * done by L2 driver; just enable or disable priority vlan tagging
1329 */
1330 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1331 (prio_map != 0 && !rdev->qplib_res.prio)) {
1332 rdev->qplib_res.prio = prio_map;
1333 bnxt_re_update_gid(rdev);
1334 }
1335
1336 return 0;
1337 }
1338
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1339 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1340 {
1341 struct bnxt_en_dev *en_dev = rdev->en_dev;
1342 struct hwrm_ver_get_output resp = {};
1343 struct hwrm_ver_get_input req = {};
1344 struct bnxt_qplib_chip_ctx *cctx;
1345 struct bnxt_fw_msg fw_msg = {};
1346 int rc;
1347
1348 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1349 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1350 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1351 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1352 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1353 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1354 rc = bnxt_send_msg(en_dev, &fw_msg);
1355 if (rc) {
1356 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1357 rc);
1358 return;
1359 }
1360
1361 cctx = rdev->chip_ctx;
1362 cctx->hwrm_intf_ver =
1363 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1364 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1365 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1366 le16_to_cpu(resp.hwrm_intf_patch);
1367
1368 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1369
1370 if (!cctx->hwrm_cmd_max_timeout)
1371 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1372 }
1373
bnxt_re_ib_init(struct bnxt_re_dev * rdev)1374 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1375 {
1376 int rc;
1377 u32 event;
1378
1379 /* Register ib dev */
1380 rc = bnxt_re_register_ib(rdev);
1381 if (rc) {
1382 pr_err("Failed to register with IB: %#x\n", rc);
1383 return rc;
1384 }
1385 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1386 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1387
1388 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1389 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1390
1391 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1392
1393 return rc;
1394 }
1395
bnxt_re_dev_uninit(struct bnxt_re_dev * rdev)1396 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev)
1397 {
1398 u8 type;
1399 int rc;
1400
1401 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1402 cancel_delayed_work_sync(&rdev->worker);
1403
1404 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1405 &rdev->flags))
1406 bnxt_re_cleanup_res(rdev);
1407 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1408 bnxt_re_free_res(rdev);
1409
1410 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1411 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1412 if (rc)
1413 ibdev_warn(&rdev->ibdev,
1414 "Failed to deinitialize RCFW: %#x", rc);
1415 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1416 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1417 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1418 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1419 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1420 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1421 }
1422
1423 rdev->num_msix = 0;
1424
1425 if (rdev->pacing.dbr_pacing)
1426 bnxt_re_deinitialize_dbr_pacing(rdev);
1427
1428 bnxt_re_destroy_chip_ctx(rdev);
1429 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1430 bnxt_unregister_dev(rdev->en_dev);
1431 }
1432
1433 /* worker thread for polling periodic events. Now used for QoS programming*/
bnxt_re_worker(struct work_struct * work)1434 static void bnxt_re_worker(struct work_struct *work)
1435 {
1436 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1437 worker.work);
1438
1439 bnxt_re_setup_qos(rdev);
1440 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1441 }
1442
bnxt_re_dev_init(struct bnxt_re_dev * rdev,u8 wqe_mode)1443 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)
1444 {
1445 struct bnxt_re_ring_attr rattr = {};
1446 struct bnxt_qplib_creq_ctx *creq;
1447 u32 db_offt;
1448 int vid;
1449 u8 type;
1450 int rc;
1451
1452 /* Registered a new RoCE device instance to netdev */
1453 rc = bnxt_re_register_netdev(rdev);
1454 if (rc) {
1455 ibdev_err(&rdev->ibdev,
1456 "Failed to register with netedev: %#x\n", rc);
1457 return -EINVAL;
1458 }
1459 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1460
1461 rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode);
1462 if (rc) {
1463 bnxt_unregister_dev(rdev->en_dev);
1464 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1465 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1466 return -EINVAL;
1467 }
1468
1469 /* Check whether VF or PF */
1470 bnxt_re_get_sriov_func_type(rdev);
1471
1472 if (!rdev->en_dev->ulp_tbl->msix_requested) {
1473 ibdev_err(&rdev->ibdev,
1474 "Failed to get MSI-X vectors: %#x\n", rc);
1475 rc = -EINVAL;
1476 goto fail;
1477 }
1478 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1479 rdev->en_dev->ulp_tbl->msix_requested);
1480 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1481
1482 bnxt_re_query_hwrm_intf_version(rdev);
1483
1484 /* Establish RCFW Communication Channel to initialize the context
1485 * memory for the function and all child VFs
1486 */
1487 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
1488 &rdev->qplib_ctx,
1489 BNXT_RE_MAX_QPC_COUNT);
1490 if (rc) {
1491 ibdev_err(&rdev->ibdev,
1492 "Failed to allocate RCFW Channel: %#x\n", rc);
1493 goto fail;
1494 }
1495
1496 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1497 creq = &rdev->rcfw.creq;
1498 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1499 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
1500 rattr.type = type;
1501 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1502 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
1503 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1504 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
1505 if (rc) {
1506 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
1507 goto free_rcfw;
1508 }
1509 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
1510 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
1511 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
1512 vid, db_offt,
1513 &bnxt_re_aeq_handler);
1514 if (rc) {
1515 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
1516 rc);
1517 goto free_ring;
1518 }
1519
1520 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
1521 rc = bnxt_re_initialize_dbr_pacing(rdev);
1522 if (!rc) {
1523 rdev->pacing.dbr_pacing = true;
1524 } else {
1525 ibdev_err(&rdev->ibdev,
1526 "DBR pacing disabled with error : %d\n", rc);
1527 rdev->pacing.dbr_pacing = false;
1528 }
1529 }
1530 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1531 if (rc)
1532 goto disable_rcfw;
1533
1534 bnxt_re_set_resource_limits(rdev);
1535
1536 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
1537 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
1538 if (rc) {
1539 ibdev_err(&rdev->ibdev,
1540 "Failed to allocate QPLIB context: %#x\n", rc);
1541 goto disable_rcfw;
1542 }
1543 rc = bnxt_re_net_stats_ctx_alloc(rdev,
1544 rdev->qplib_ctx.stats.dma_map,
1545 &rdev->qplib_ctx.stats.fw_id);
1546 if (rc) {
1547 ibdev_err(&rdev->ibdev,
1548 "Failed to allocate stats context: %#x\n", rc);
1549 goto free_ctx;
1550 }
1551
1552 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1553 rdev->is_virtfn);
1554 if (rc) {
1555 ibdev_err(&rdev->ibdev,
1556 "Failed to initialize RCFW: %#x\n", rc);
1557 goto free_sctx;
1558 }
1559 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1560
1561 /* Resources based on the 'new' device caps */
1562 rc = bnxt_re_alloc_res(rdev);
1563 if (rc) {
1564 ibdev_err(&rdev->ibdev,
1565 "Failed to allocate resources: %#x\n", rc);
1566 goto fail;
1567 }
1568 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1569 rc = bnxt_re_init_res(rdev);
1570 if (rc) {
1571 ibdev_err(&rdev->ibdev,
1572 "Failed to initialize resources: %#x\n", rc);
1573 goto fail;
1574 }
1575
1576 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1577
1578 if (!rdev->is_virtfn) {
1579 rc = bnxt_re_setup_qos(rdev);
1580 if (rc)
1581 ibdev_info(&rdev->ibdev,
1582 "RoCE priority not yet configured\n");
1583
1584 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1585 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1586 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1587 /*
1588 * Use the total VF count since the actual VF count may not be
1589 * available at this point.
1590 */
1591 bnxt_re_vf_res_config(rdev);
1592 }
1593
1594 return 0;
1595 free_sctx:
1596 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1597 free_ctx:
1598 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1599 disable_rcfw:
1600 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1601 free_ring:
1602 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1603 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1604 free_rcfw:
1605 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1606 fail:
1607 bnxt_re_dev_uninit(rdev);
1608
1609 return rc;
1610 }
1611
bnxt_re_add_device(struct auxiliary_device * adev,u8 wqe_mode)1612 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode)
1613 {
1614 struct bnxt_aux_priv *aux_priv =
1615 container_of(adev, struct bnxt_aux_priv, aux_dev);
1616 struct bnxt_en_dev *en_dev;
1617 struct bnxt_re_dev *rdev;
1618 int rc;
1619
1620 /* en_dev should never be NULL as long as adev and aux_dev are valid. */
1621 en_dev = aux_priv->edev;
1622
1623 rdev = bnxt_re_dev_add(aux_priv, en_dev);
1624 if (!rdev || !rdev_to_dev(rdev)) {
1625 rc = -ENOMEM;
1626 goto exit;
1627 }
1628
1629 rc = bnxt_re_dev_init(rdev, wqe_mode);
1630 if (rc)
1631 goto re_dev_dealloc;
1632
1633 rc = bnxt_re_ib_init(rdev);
1634 if (rc) {
1635 pr_err("Failed to register with IB: %s",
1636 aux_priv->aux_dev.name);
1637 goto re_dev_uninit;
1638 }
1639 auxiliary_set_drvdata(adev, rdev);
1640
1641 return 0;
1642
1643 re_dev_uninit:
1644 bnxt_re_dev_uninit(rdev);
1645 re_dev_dealloc:
1646 ib_dealloc_device(&rdev->ibdev);
1647 exit:
1648 return rc;
1649 }
1650
bnxt_re_setup_cc(struct bnxt_re_dev * rdev,bool enable)1651 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
1652 {
1653 struct bnxt_qplib_cc_param cc_param = {};
1654
1655 /* Do not enable congestion control on VFs */
1656 if (rdev->is_virtfn)
1657 return;
1658
1659 /* Currently enabling only for GenP5 adapters */
1660 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
1661 return;
1662
1663 if (enable) {
1664 cc_param.enable = 1;
1665 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE;
1666 }
1667
1668 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE |
1669 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
1670 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
1671
1672 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
1673 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
1674 }
1675
1676 /*
1677 * "Notifier chain callback can be invoked for the same chain from
1678 * different CPUs at the same time".
1679 *
1680 * For cases when the netdev is already present, our call to the
1681 * register_netdevice_notifier() will actually get the rtnl_lock()
1682 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1683 * events.
1684 *
1685 * But for cases when the netdev is not already present, the notifier
1686 * chain is subjected to be invoked from different CPUs simultaneously.
1687 *
1688 * This is protected by the netdev_mutex.
1689 */
bnxt_re_netdev_event(struct notifier_block * notifier,unsigned long event,void * ptr)1690 static int bnxt_re_netdev_event(struct notifier_block *notifier,
1691 unsigned long event, void *ptr)
1692 {
1693 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1694 struct bnxt_re_dev *rdev;
1695
1696 real_dev = rdma_vlan_dev_real_dev(netdev);
1697 if (!real_dev)
1698 real_dev = netdev;
1699
1700 if (real_dev != netdev)
1701 goto exit;
1702
1703 rdev = bnxt_re_from_netdev(real_dev);
1704 if (!rdev)
1705 return NOTIFY_DONE;
1706
1707
1708 switch (event) {
1709 case NETDEV_UP:
1710 case NETDEV_DOWN:
1711 case NETDEV_CHANGE:
1712 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1713 netif_carrier_ok(real_dev) ?
1714 IB_EVENT_PORT_ACTIVE :
1715 IB_EVENT_PORT_ERR);
1716 break;
1717 default:
1718 break;
1719 }
1720 ib_device_put(&rdev->ibdev);
1721 exit:
1722 return NOTIFY_DONE;
1723 }
1724
1725 #define BNXT_ADEV_NAME "bnxt_en"
1726
bnxt_re_remove(struct auxiliary_device * adev)1727 static void bnxt_re_remove(struct auxiliary_device *adev)
1728 {
1729 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1730
1731 if (!rdev)
1732 return;
1733
1734 mutex_lock(&bnxt_re_mutex);
1735 if (rdev->nb.notifier_call) {
1736 unregister_netdevice_notifier(&rdev->nb);
1737 rdev->nb.notifier_call = NULL;
1738 } else {
1739 /* If notifier is null, we should have already done a
1740 * clean up before coming here.
1741 */
1742 goto skip_remove;
1743 }
1744 bnxt_re_setup_cc(rdev, false);
1745 ib_unregister_device(&rdev->ibdev);
1746 bnxt_re_dev_uninit(rdev);
1747 ib_dealloc_device(&rdev->ibdev);
1748 skip_remove:
1749 mutex_unlock(&bnxt_re_mutex);
1750 }
1751
bnxt_re_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1752 static int bnxt_re_probe(struct auxiliary_device *adev,
1753 const struct auxiliary_device_id *id)
1754 {
1755 struct bnxt_re_dev *rdev;
1756 int rc;
1757
1758 mutex_lock(&bnxt_re_mutex);
1759 rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC);
1760 if (rc) {
1761 mutex_unlock(&bnxt_re_mutex);
1762 return rc;
1763 }
1764
1765 rdev = auxiliary_get_drvdata(adev);
1766
1767 rdev->nb.notifier_call = bnxt_re_netdev_event;
1768 rc = register_netdevice_notifier(&rdev->nb);
1769 if (rc) {
1770 rdev->nb.notifier_call = NULL;
1771 pr_err("%s: Cannot register to netdevice_notifier",
1772 ROCE_DRV_MODULE_NAME);
1773 goto err;
1774 }
1775
1776 bnxt_re_setup_cc(rdev, true);
1777 mutex_unlock(&bnxt_re_mutex);
1778 return 0;
1779
1780 err:
1781 mutex_unlock(&bnxt_re_mutex);
1782 bnxt_re_remove(adev);
1783
1784 return rc;
1785 }
1786
bnxt_re_suspend(struct auxiliary_device * adev,pm_message_t state)1787 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
1788 {
1789 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1790
1791 if (!rdev)
1792 return 0;
1793
1794 mutex_lock(&bnxt_re_mutex);
1795 /* L2 driver may invoke this callback during device error/crash or device
1796 * reset. Current RoCE driver doesn't recover the device in case of
1797 * error. Handle the error by dispatching fatal events to all qps
1798 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1799 * L2 driver want to modify the MSIx table.
1800 */
1801
1802 ibdev_info(&rdev->ibdev, "Handle device suspend call");
1803 /* Check the current device state from bnxt_en_dev and move the
1804 * device to detached state if FW_FATAL_COND is set.
1805 * This prevents more commands to HW during clean-up,
1806 * in case the device is already in error.
1807 */
1808 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state))
1809 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1810
1811 bnxt_re_dev_stop(rdev);
1812 bnxt_re_stop_irq(rdev);
1813 /* Move the device states to detached and avoid sending any more
1814 * commands to HW
1815 */
1816 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
1817 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1818 wake_up_all(&rdev->rcfw.cmdq.waitq);
1819 mutex_unlock(&bnxt_re_mutex);
1820
1821 return 0;
1822 }
1823
bnxt_re_resume(struct auxiliary_device * adev)1824 static int bnxt_re_resume(struct auxiliary_device *adev)
1825 {
1826 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1827
1828 if (!rdev)
1829 return 0;
1830
1831 mutex_lock(&bnxt_re_mutex);
1832 /* L2 driver may invoke this callback during device recovery, resume.
1833 * reset. Current RoCE driver doesn't recover the device in case of
1834 * error. Handle the error by dispatching fatal events to all qps
1835 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1836 * L2 driver want to modify the MSIx table.
1837 */
1838
1839 ibdev_info(&rdev->ibdev, "Handle device resume call");
1840 mutex_unlock(&bnxt_re_mutex);
1841
1842 return 0;
1843 }
1844
1845 static const struct auxiliary_device_id bnxt_re_id_table[] = {
1846 { .name = BNXT_ADEV_NAME ".rdma", },
1847 {},
1848 };
1849
1850 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
1851
1852 static struct auxiliary_driver bnxt_re_driver = {
1853 .name = "rdma",
1854 .probe = bnxt_re_probe,
1855 .remove = bnxt_re_remove,
1856 .shutdown = bnxt_re_shutdown,
1857 .suspend = bnxt_re_suspend,
1858 .resume = bnxt_re_resume,
1859 .id_table = bnxt_re_id_table,
1860 };
1861
bnxt_re_mod_init(void)1862 static int __init bnxt_re_mod_init(void)
1863 {
1864 int rc;
1865
1866 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
1867 rc = auxiliary_driver_register(&bnxt_re_driver);
1868 if (rc) {
1869 pr_err("%s: Failed to register auxiliary driver\n",
1870 ROCE_DRV_MODULE_NAME);
1871 return rc;
1872 }
1873 return 0;
1874 }
1875
bnxt_re_mod_exit(void)1876 static void __exit bnxt_re_mod_exit(void)
1877 {
1878 auxiliary_driver_unregister(&bnxt_re_driver);
1879 }
1880
1881 module_init(bnxt_re_mod_init);
1882 module_exit(bnxt_re_mod_exit);
1883