1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Slow Path Operators
37 */
38
39 #define dev_fmt(fmt) "QPLIB: " fmt
40
41 #include <linux/interrupt.h>
42 #include <linux/spinlock.h>
43 #include <linux/sched.h>
44 #include <linux/pci.h>
45
46 #include "roce_hsi.h"
47
48 #include "qplib_res.h"
49 #include "qplib_rcfw.h"
50 #include "qplib_sp.h"
51 #include "qplib_tlv.h"
52
53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0,
54 0, 0, 0, 0, 0, 0, 0, 0 } };
55
56 /* Device */
57
bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw * rcfw)58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)
59 {
60 u16 pcie_ctl2 = 0;
61
62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx))
63 return false;
64
65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2);
66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);
67 }
68
bnxt_qplib_query_version(struct bnxt_qplib_rcfw * rcfw,char * fw_ver)69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw,
70 char *fw_ver)
71 {
72 struct creq_query_version_resp resp = {};
73 struct bnxt_qplib_cmdqmsg msg = {};
74 struct cmdq_query_version req = {};
75 int rc;
76
77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
78 CMDQ_BASE_OPCODE_QUERY_VERSION,
79 sizeof(req));
80
81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
83 if (rc)
84 return;
85 fw_ver[0] = resp.fw_maj;
86 fw_ver[1] = resp.fw_minor;
87 fw_ver[2] = resp.fw_bld;
88 fw_ver[3] = resp.fw_rsvd;
89 }
90
bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_dev_attr * attr)91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
92 struct bnxt_qplib_dev_attr *attr)
93 {
94 struct creq_query_func_resp resp = {};
95 struct bnxt_qplib_cmdqmsg msg = {};
96 struct creq_query_func_resp_sb *sb;
97 struct bnxt_qplib_rcfw_sbuf sbuf;
98 struct cmdq_query_func req = {};
99 u8 *tqm_alloc;
100 int i, rc;
101 u32 temp;
102
103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
104 CMDQ_BASE_OPCODE_QUERY_FUNC,
105 sizeof(req));
106
107 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
108 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
109 &sbuf.dma_addr, GFP_KERNEL);
110 if (!sbuf.sb)
111 return -ENOMEM;
112 sb = sbuf.sb;
113 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
114 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
115 sizeof(resp), 0);
116 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
117 if (rc)
118 goto bail;
119
120 /* Extract the context from the side buffer */
121 attr->max_qp = le32_to_cpu(sb->max_qp);
122 /* max_qp value reported by FW doesn't include the QP1 */
123 attr->max_qp += 1;
124 attr->max_qp_rd_atom =
125 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
126 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom;
127 attr->max_qp_init_rd_atom =
128 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom;
130 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr);
131 /*
132 * 128 WQEs needs to be reserved for the HW (8916). Prevent
133 * reporting the max number
134 */
135 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1;
136 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx) ?
137 6 : sb->max_sge;
138 attr->max_cq = le32_to_cpu(sb->max_cq);
139 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);
140 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
141 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes);
142 attr->max_cq_sges = attr->max_qp_sges;
143 attr->max_mr = le32_to_cpu(sb->max_mr);
144 attr->max_mw = le32_to_cpu(sb->max_mw);
145
146 attr->max_mr_size = le64_to_cpu(sb->max_mr_size);
147 attr->max_pd = 64 * 1024;
148 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp);
149 attr->max_ah = le32_to_cpu(sb->max_ah);
150
151 attr->max_srq = le16_to_cpu(sb->max_srq);
152 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1;
153 attr->max_srq_sges = sb->max_srq_sge;
154 attr->max_pkey = 1;
155 attr->max_inline_data = le32_to_cpu(sb->max_inline_data);
156 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
157 attr->l2_db_size = (sb->l2_db_space_size + 1) *
158 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
159 /*
160 * Read the max gid supported by HW.
161 * For each entry in HW GID in HW table, we consume 2
162 * GID entries in the kernel GID table. So max_gid reported
163 * to stack can be up to twice the value reported by the HW, up to 256 gids.
164 */
165 attr->max_sgid = le32_to_cpu(sb->max_gid);
166 attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid);
167 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
168
169 bnxt_qplib_query_version(rcfw, attr->fw_ver);
170
171 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) {
172 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]);
173 tqm_alloc = (u8 *)&temp;
174 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc;
175 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc);
176 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc);
177 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
178 }
179
180 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI)
181 attr->max_dpi = le32_to_cpu(sb->max_dpi);
182
183 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
184 bail:
185 dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
186 sbuf.sb, sbuf.dma_addr);
187 return rc;
188 }
189
bnxt_qplib_set_func_resources(struct bnxt_qplib_res * res,struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_ctx * ctx)190 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res,
191 struct bnxt_qplib_rcfw *rcfw,
192 struct bnxt_qplib_ctx *ctx)
193 {
194 struct creq_set_func_resources_resp resp = {};
195 struct cmdq_set_func_resources req = {};
196 struct bnxt_qplib_cmdqmsg msg = {};
197 int rc;
198
199 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
200 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES,
201 sizeof(req));
202
203 req.number_of_qp = cpu_to_le32(ctx->qpc_count);
204 req.number_of_mrw = cpu_to_le32(ctx->mrw_count);
205 req.number_of_srq = cpu_to_le32(ctx->srqc_count);
206 req.number_of_cq = cpu_to_le32(ctx->cq_count);
207
208 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
209 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
210 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
211 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
212 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
213
214 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
215 sizeof(resp), 0);
216 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
217 if (rc) {
218 dev_err(&res->pdev->dev, "Failed to set function resources\n");
219 }
220 return rc;
221 }
222
223 /* SGID */
bnxt_qplib_get_sgid(struct bnxt_qplib_res * res,struct bnxt_qplib_sgid_tbl * sgid_tbl,int index,struct bnxt_qplib_gid * gid)224 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
225 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index,
226 struct bnxt_qplib_gid *gid)
227 {
228 if (index >= sgid_tbl->max) {
229 dev_err(&res->pdev->dev,
230 "Index %d exceeded SGID table max (%d)\n",
231 index, sgid_tbl->max);
232 return -EINVAL;
233 }
234 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid));
235 return 0;
236 }
237
bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl * sgid_tbl,struct bnxt_qplib_gid * gid,u16 vlan_id,bool update)238 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
239 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update)
240 {
241 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
242 struct bnxt_qplib_res,
243 sgid_tbl);
244 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
245 int index;
246
247 /* Do we need a sgid_lock here? */
248 if (!sgid_tbl->active) {
249 dev_err(&res->pdev->dev, "SGID table has no active entries\n");
250 return -ENOMEM;
251 }
252 for (index = 0; index < sgid_tbl->max; index++) {
253 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) &&
254 vlan_id == sgid_tbl->tbl[index].vlan_id)
255 break;
256 }
257 if (index == sgid_tbl->max) {
258 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n");
259 return 0;
260 }
261 /* Remove GID from the SGID table */
262 if (update) {
263 struct creq_delete_gid_resp resp = {};
264 struct bnxt_qplib_cmdqmsg msg = {};
265 struct cmdq_delete_gid req = {};
266 int rc;
267
268 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
269 CMDQ_BASE_OPCODE_DELETE_GID,
270 sizeof(req));
271 if (sgid_tbl->hw_id[index] == 0xFFFF) {
272 dev_err(&res->pdev->dev,
273 "GID entry contains an invalid HW id\n");
274 return -EINVAL;
275 }
276 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]);
277 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
278 sizeof(resp), 0);
279 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
280 if (rc)
281 return rc;
282 }
283 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero,
284 sizeof(bnxt_qplib_gid_zero));
285 sgid_tbl->tbl[index].vlan_id = 0xFFFF;
286 sgid_tbl->vlan[index] = 0;
287 sgid_tbl->active--;
288 dev_dbg(&res->pdev->dev,
289 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n",
290 index, sgid_tbl->hw_id[index], sgid_tbl->active);
291 sgid_tbl->hw_id[index] = (u16)-1;
292
293 /* unlock */
294 return 0;
295 }
296
bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl * sgid_tbl,struct bnxt_qplib_gid * gid,const u8 * smac,u16 vlan_id,bool update,u32 * index)297 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
298 struct bnxt_qplib_gid *gid, const u8 *smac,
299 u16 vlan_id, bool update, u32 *index)
300 {
301 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
302 struct bnxt_qplib_res,
303 sgid_tbl);
304 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
305 int i, free_idx;
306
307 /* Do we need a sgid_lock here? */
308 if (sgid_tbl->active == sgid_tbl->max) {
309 dev_err(&res->pdev->dev, "SGID table is full\n");
310 return -ENOMEM;
311 }
312 free_idx = sgid_tbl->max;
313 for (i = 0; i < sgid_tbl->max; i++) {
314 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) &&
315 sgid_tbl->tbl[i].vlan_id == vlan_id) {
316 dev_dbg(&res->pdev->dev,
317 "SGID entry already exist in entry %d!\n", i);
318 *index = i;
319 return -EALREADY;
320 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero,
321 sizeof(bnxt_qplib_gid_zero)) &&
322 free_idx == sgid_tbl->max) {
323 free_idx = i;
324 }
325 }
326 if (free_idx == sgid_tbl->max) {
327 dev_err(&res->pdev->dev,
328 "SGID table is FULL but count is not MAX??\n");
329 return -ENOMEM;
330 }
331 if (update) {
332 struct creq_add_gid_resp resp = {};
333 struct bnxt_qplib_cmdqmsg msg = {};
334 struct cmdq_add_gid req = {};
335 int rc;
336
337 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
338 CMDQ_BASE_OPCODE_ADD_GID,
339 sizeof(req));
340
341 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
342 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
343 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
344 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
345 /*
346 * driver should ensure that all RoCE traffic is always VLAN
347 * tagged if RoCE traffic is running on non-zero VLAN ID or
348 * RoCE traffic is running on non-zero Priority.
349 */
350 if ((vlan_id != 0xFFFF) || res->prio) {
351 if (vlan_id != 0xFFFF)
352 req.vlan = cpu_to_le16
353 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK);
354 req.vlan |= cpu_to_le16
355 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
356 CMDQ_ADD_GID_VLAN_VLAN_EN);
357 }
358
359 /* MAC in network format */
360 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
361 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
362 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
363
364 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
365 sizeof(resp), 0);
366 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
367 if (rc)
368 return rc;
369 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid);
370 }
371 /* Add GID to the sgid_tbl */
372 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid));
373 sgid_tbl->tbl[free_idx].vlan_id = vlan_id;
374 sgid_tbl->active++;
375 if (vlan_id != 0xFFFF)
376 sgid_tbl->vlan[free_idx] = 1;
377
378 dev_dbg(&res->pdev->dev,
379 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n",
380 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active);
381
382 *index = free_idx;
383 /* unlock */
384 return 0;
385 }
386
bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl * sgid_tbl,struct bnxt_qplib_gid * gid,u16 gid_idx,const u8 * smac)387 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
388 struct bnxt_qplib_gid *gid, u16 gid_idx,
389 const u8 *smac)
390 {
391 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
392 struct bnxt_qplib_res,
393 sgid_tbl);
394 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
395 struct creq_modify_gid_resp resp = {};
396 struct bnxt_qplib_cmdqmsg msg = {};
397 struct cmdq_modify_gid req = {};
398 int rc;
399
400 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
401 CMDQ_BASE_OPCODE_MODIFY_GID,
402 sizeof(req));
403
404 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
405 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
406 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
407 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
408 if (res->prio) {
409 req.vlan |= cpu_to_le16
410 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
411 CMDQ_ADD_GID_VLAN_VLAN_EN);
412 }
413
414 /* MAC in network format */
415 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
416 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
417 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
418
419 req.gid_index = cpu_to_le16(gid_idx);
420
421 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
422 sizeof(resp), 0);
423 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
424 return rc;
425 }
426
427 /* AH */
bnxt_qplib_create_ah(struct bnxt_qplib_res * res,struct bnxt_qplib_ah * ah,bool block)428 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
429 bool block)
430 {
431 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
432 struct creq_create_ah_resp resp = {};
433 struct bnxt_qplib_cmdqmsg msg = {};
434 struct cmdq_create_ah req = {};
435 u32 temp32[4];
436 u16 temp16[3];
437 int rc;
438
439 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
440 CMDQ_BASE_OPCODE_CREATE_AH,
441 sizeof(req));
442
443 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid));
444 req.dgid[0] = cpu_to_le32(temp32[0]);
445 req.dgid[1] = cpu_to_le32(temp32[1]);
446 req.dgid[2] = cpu_to_le32(temp32[2]);
447 req.dgid[3] = cpu_to_le32(temp32[3]);
448
449 req.type = ah->nw_type;
450 req.hop_limit = ah->hop_limit;
451 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]);
452 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label &
453 CMDQ_CREATE_AH_FLOW_LABEL_MASK) |
454 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK);
455 req.pd_id = cpu_to_le32(ah->pd->id);
456 req.traffic_class = ah->traffic_class;
457
458 /* MAC in network format */
459 memcpy(temp16, ah->dmac, 6);
460 req.dest_mac[0] = cpu_to_le16(temp16[0]);
461 req.dest_mac[1] = cpu_to_le16(temp16[1]);
462 req.dest_mac[2] = cpu_to_le16(temp16[2]);
463
464 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
465 sizeof(resp), block);
466 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
467 if (rc)
468 return rc;
469
470 ah->id = le32_to_cpu(resp.xid);
471 return 0;
472 }
473
bnxt_qplib_destroy_ah(struct bnxt_qplib_res * res,struct bnxt_qplib_ah * ah,bool block)474 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
475 bool block)
476 {
477 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
478 struct creq_destroy_ah_resp resp = {};
479 struct bnxt_qplib_cmdqmsg msg = {};
480 struct cmdq_destroy_ah req = {};
481 int rc;
482
483 /* Clean up the AH table in the device */
484 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
485 CMDQ_BASE_OPCODE_DESTROY_AH,
486 sizeof(req));
487
488 req.ah_cid = cpu_to_le32(ah->id);
489
490 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
491 sizeof(resp), block);
492 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
493 return rc;
494 }
495
496 /* MRW */
bnxt_qplib_free_mrw(struct bnxt_qplib_res * res,struct bnxt_qplib_mrw * mrw)497 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
498 {
499 struct creq_deallocate_key_resp resp = {};
500 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
501 struct cmdq_deallocate_key req = {};
502 struct bnxt_qplib_cmdqmsg msg = {};
503 int rc;
504
505 if (mrw->lkey == 0xFFFFFFFF) {
506 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n");
507 return 0;
508 }
509
510 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
511 CMDQ_BASE_OPCODE_DEALLOCATE_KEY,
512 sizeof(req));
513
514 req.mrw_flags = mrw->type;
515
516 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) ||
517 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
518 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
519 req.key = cpu_to_le32(mrw->rkey);
520 else
521 req.key = cpu_to_le32(mrw->lkey);
522
523 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
524 sizeof(resp), 0);
525 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
526 if (rc)
527 return rc;
528
529 /* Free the qplib's MRW memory */
530 if (mrw->hwq.max_elements)
531 bnxt_qplib_free_hwq(res, &mrw->hwq);
532
533 return 0;
534 }
535
bnxt_qplib_alloc_mrw(struct bnxt_qplib_res * res,struct bnxt_qplib_mrw * mrw)536 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
537 {
538 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
539 struct creq_allocate_mrw_resp resp = {};
540 struct bnxt_qplib_cmdqmsg msg = {};
541 struct cmdq_allocate_mrw req = {};
542 unsigned long tmp;
543 int rc;
544
545 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
546 CMDQ_BASE_OPCODE_ALLOCATE_MRW,
547 sizeof(req));
548
549 req.pd_id = cpu_to_le32(mrw->pd->id);
550 req.mrw_flags = mrw->type;
551 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR &&
552 mrw->flags & BNXT_QPLIB_FR_PMR) ||
553 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A ||
554 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)
555 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY;
556 tmp = (unsigned long)mrw;
557 req.mrw_handle = cpu_to_le64(tmp);
558
559 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
560 sizeof(resp), 0);
561 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
562 if (rc)
563 return rc;
564
565 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) ||
566 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
567 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
568 mrw->rkey = le32_to_cpu(resp.xid);
569 else
570 mrw->lkey = le32_to_cpu(resp.xid);
571 return 0;
572 }
573
bnxt_qplib_dereg_mrw(struct bnxt_qplib_res * res,struct bnxt_qplib_mrw * mrw,bool block)574 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw,
575 bool block)
576 {
577 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
578 struct creq_deregister_mr_resp resp = {};
579 struct bnxt_qplib_cmdqmsg msg = {};
580 struct cmdq_deregister_mr req = {};
581 int rc;
582
583 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
584 CMDQ_BASE_OPCODE_DEREGISTER_MR,
585 sizeof(req));
586
587 req.lkey = cpu_to_le32(mrw->lkey);
588 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
589 sizeof(resp), block);
590 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
591 if (rc)
592 return rc;
593
594 /* Free the qplib's MR memory */
595 if (mrw->hwq.max_elements) {
596 mrw->va = 0;
597 mrw->total_size = 0;
598 bnxt_qplib_free_hwq(res, &mrw->hwq);
599 }
600
601 return 0;
602 }
603
bnxt_qplib_reg_mr(struct bnxt_qplib_res * res,struct bnxt_qplib_mrw * mr,struct ib_umem * umem,int num_pbls,u32 buf_pg_size)604 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr,
605 struct ib_umem *umem, int num_pbls, u32 buf_pg_size)
606 {
607 struct bnxt_qplib_rcfw *rcfw = res->rcfw;
608 struct bnxt_qplib_hwq_attr hwq_attr = {};
609 struct bnxt_qplib_sg_info sginfo = {};
610 struct creq_register_mr_resp resp = {};
611 struct bnxt_qplib_cmdqmsg msg = {};
612 struct cmdq_register_mr req = {};
613 int pages, rc;
614 u32 pg_size;
615 u16 level;
616
617 if (num_pbls) {
618 pages = roundup_pow_of_two(num_pbls);
619 /* Allocate memory for the non-leaf pages to store buf ptrs.
620 * Non-leaf pages always uses system PAGE_SIZE
621 */
622 /* Free the hwq if it already exist, must be a rereg */
623 if (mr->hwq.max_elements)
624 bnxt_qplib_free_hwq(res, &mr->hwq);
625 hwq_attr.res = res;
626 hwq_attr.depth = pages;
627 hwq_attr.stride = sizeof(dma_addr_t);
628 hwq_attr.type = HWQ_TYPE_MR;
629 hwq_attr.sginfo = &sginfo;
630 hwq_attr.sginfo->umem = umem;
631 hwq_attr.sginfo->npages = pages;
632 hwq_attr.sginfo->pgsize = buf_pg_size;
633 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size);
634 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr);
635 if (rc) {
636 dev_err(&res->pdev->dev,
637 "SP: Reg MR memory allocation failed\n");
638 return -ENOMEM;
639 }
640 }
641
642 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
643 CMDQ_BASE_OPCODE_REGISTER_MR,
644 sizeof(req));
645
646 /* Configure the request */
647 if (mr->hwq.level == PBL_LVL_MAX) {
648 /* No PBL provided, just use system PAGE_SIZE */
649 level = 0;
650 req.pbl = 0;
651 pg_size = PAGE_SIZE;
652 } else {
653 level = mr->hwq.level;
654 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
655 }
656 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE;
657 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) |
658 ((ilog2(pg_size) <<
659 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) &
660 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK);
661 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) <<
662 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) &
663 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK));
664 req.access = (mr->flags & 0xFFFF);
665 req.va = cpu_to_le64(mr->va);
666 req.key = cpu_to_le32(mr->lkey);
667 req.mr_size = cpu_to_le64(mr->total_size);
668
669 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
670 sizeof(resp), 0);
671 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
672 if (rc)
673 goto fail;
674
675 return 0;
676
677 fail:
678 if (mr->hwq.max_elements)
679 bnxt_qplib_free_hwq(res, &mr->hwq);
680 return rc;
681 }
682
bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res * res,struct bnxt_qplib_frpl * frpl,int max_pg_ptrs)683 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res,
684 struct bnxt_qplib_frpl *frpl,
685 int max_pg_ptrs)
686 {
687 struct bnxt_qplib_hwq_attr hwq_attr = {};
688 struct bnxt_qplib_sg_info sginfo = {};
689 int pg_ptrs, pages, rc;
690
691 /* Re-calculate the max to fit the HWQ allocation model */
692 pg_ptrs = roundup_pow_of_two(max_pg_ptrs);
693 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT;
694 if (!pages)
695 pages++;
696
697 if (pages > MAX_PBL_LVL_1_PGS)
698 return -ENOMEM;
699
700 sginfo.pgsize = PAGE_SIZE;
701 sginfo.nopte = true;
702
703 hwq_attr.res = res;
704 hwq_attr.depth = pg_ptrs;
705 hwq_attr.stride = PAGE_SIZE;
706 hwq_attr.sginfo = &sginfo;
707 hwq_attr.type = HWQ_TYPE_CTX;
708 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr);
709 if (!rc)
710 frpl->max_pg_ptrs = pg_ptrs;
711
712 return rc;
713 }
714
bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res * res,struct bnxt_qplib_frpl * frpl)715 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res,
716 struct bnxt_qplib_frpl *frpl)
717 {
718 bnxt_qplib_free_hwq(res, &frpl->hwq);
719 return 0;
720 }
721
bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_roce_stats * stats)722 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw,
723 struct bnxt_qplib_roce_stats *stats)
724 {
725 struct creq_query_roce_stats_resp resp = {};
726 struct creq_query_roce_stats_resp_sb *sb;
727 struct cmdq_query_roce_stats req = {};
728 struct bnxt_qplib_cmdqmsg msg = {};
729 struct bnxt_qplib_rcfw_sbuf sbuf;
730 int rc;
731
732 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
733 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS,
734 sizeof(req));
735
736 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
737 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
738 &sbuf.dma_addr, GFP_KERNEL);
739 if (!sbuf.sb)
740 return -ENOMEM;
741 sb = sbuf.sb;
742
743 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
744 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
745 sizeof(resp), 0);
746 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
747 if (rc)
748 goto bail;
749 /* Extract the context from the side buffer */
750 stats->to_retransmits = le64_to_cpu(sb->to_retransmits);
751 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd);
752 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded);
753 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd);
754 stats->missing_resp = le64_to_cpu(sb->missing_resp);
755 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err);
756 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err);
757 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err);
758 stats->local_protection_err = le64_to_cpu(sb->local_protection_err);
759 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err);
760 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err);
761 stats->remote_access_err = le64_to_cpu(sb->remote_access_err);
762 stats->remote_op_err = le64_to_cpu(sb->remote_op_err);
763 stats->dup_req = le64_to_cpu(sb->dup_req);
764 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max);
765 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch);
766 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe);
767 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err);
768 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey);
769 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err);
770 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm);
771 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err);
772 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey);
773 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err);
774 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm);
775 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err);
776 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow);
777 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode);
778 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic);
779 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err);
780 stats->res_mem_error = le64_to_cpu(sb->res_mem_error);
781 stats->res_srq_err = le64_to_cpu(sb->res_srq_err);
782 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err);
783 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey);
784 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err);
785 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err);
786 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err);
787 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err);
788 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err);
789 if (!rcfw->init_oos_stats) {
790 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
791 rcfw->init_oos_stats = 1;
792 } else {
793 stats->res_oos_drop_count +=
794 (le64_to_cpu(sb->res_oos_drop_count) -
795 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK;
796 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
797 }
798
799 bail:
800 dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
801 sbuf.sb, sbuf.dma_addr);
802 return rc;
803 }
804
bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw * rcfw,u32 fid,struct bnxt_qplib_ext_stat * estat)805 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid,
806 struct bnxt_qplib_ext_stat *estat)
807 {
808 struct creq_query_roce_stats_ext_resp resp = {};
809 struct creq_query_roce_stats_ext_resp_sb *sb;
810 struct cmdq_query_roce_stats_ext req = {};
811 struct bnxt_qplib_cmdqmsg msg = {};
812 struct bnxt_qplib_rcfw_sbuf sbuf;
813 int rc;
814
815 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
816 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
817 &sbuf.dma_addr, GFP_KERNEL);
818 if (!sbuf.sb)
819 return -ENOMEM;
820
821 sb = sbuf.sb;
822 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
823 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS,
824 sizeof(req));
825
826 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
827 req.resp_addr = cpu_to_le64(sbuf.dma_addr);
828 req.function_id = cpu_to_le32(fid);
829 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID);
830
831 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
832 sizeof(resp), 0);
833 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
834 if (rc)
835 goto bail;
836
837 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts);
838 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts);
839 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts);
840 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts);
841 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts);
842 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts);
843 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes);
844 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts);
845 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts);
846 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts);
847 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts);
848 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts);
849 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts);
850 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes);
851 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts);
852 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes);
853 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts);
854 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts);
855 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts);
856 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts);
857 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts);
858
859 bail:
860 dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
861 sbuf.sb, sbuf.dma_addr);
862 return rc;
863 }
864
bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv * ext_req,struct bnxt_qplib_cc_param_ext * cc_ext)865 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req,
866 struct bnxt_qplib_cc_param_ext *cc_ext)
867 {
868 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask);
869 cc_ext->ext_mask = 0;
870 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi);
871 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp);
872 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp);
873 ext_req->tr_update_mode = cc_ext->tr_update_mode;
874 ext_req->tr_update_cycles = cc_ext->tr_update_cyls;
875 ext_req->fr_num_rtts = cc_ext->fr_rtt;
876 ext_req->ai_rate_increase = cc_ext->ai_rate_incr;
877 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th);
878 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th);
879 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th);
880 ext_req->bw_avg_weight = cc_ext->bw_avg_weight;
881 ext_req->actual_cr_factor = cc_ext->cr_factor;
882 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp);
883 ext_req->cp_bias_en = cc_ext->cp_bias_en;
884 ext_req->cp_bias = cc_ext->cp_bias;
885 ext_req->cnp_ecn = cc_ext->cnp_ecn;
886 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en;
887 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec);
888 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th);
889 ext_req->cr_width = cc_ext->cr_width;
890 ext_req->quota_period_min = cc_ext->min_quota;
891 ext_req->quota_period_max = cc_ext->max_quota;
892 ext_req->quota_period_abs_max = cc_ext->abs_max_quota;
893 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb);
894 ext_req->cr_prob_factor = cc_ext->cr_prob_fac;
895 ext_req->tr_prob_factor = cc_ext->tr_prob_fac;
896 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th);
897 ext_req->red_div = cc_ext->red_div;
898 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th;
899 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt);
900 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio;
901 ext_req->use_rate_table = cc_ext->low_rate_en;
902 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th);
903 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1);
904 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2);
905 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th);
906 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1);
907 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2);
908 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt);
909 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes;
910 }
911
bnxt_qplib_modify_cc(struct bnxt_qplib_res * res,struct bnxt_qplib_cc_param * cc_param)912 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res,
913 struct bnxt_qplib_cc_param *cc_param)
914 {
915 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {};
916 struct creq_modify_roce_cc_resp resp = {};
917 struct bnxt_qplib_cmdqmsg msg = {};
918 struct cmdq_modify_roce_cc *req;
919 int req_size;
920 void *cmd;
921 int rc;
922
923 /* Prepare the older base command */
924 req = &tlv_req.base_req;
925 cmd = req;
926 req_size = sizeof(*req);
927 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC,
928 sizeof(*req));
929 req->modify_mask = cpu_to_le32(cc_param->mask);
930 req->enable_cc = cc_param->enable;
931 req->g = cc_param->g;
932 req->num_phases_per_state = cc_param->nph_per_state;
933 req->time_per_phase = cc_param->time_pph;
934 req->pkts_per_phase = cc_param->pkts_pph;
935 req->init_cr = cpu_to_le16(cc_param->init_cr);
936 req->init_tr = cpu_to_le16(cc_param->init_tr);
937 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) |
938 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK);
939 req->alt_vlan_pcp = cc_param->alt_vlan_pcp;
940 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp);
941 req->rtt = cpu_to_le16(cc_param->rtt);
942 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp);
943 req->cc_mode = cc_param->cc_mode;
944 req->inactivity_th = cpu_to_le16(cc_param->inact_th);
945
946 /* For chip gen P5 onwards fill extended cmd and header */
947 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) {
948 struct roce_tlv *hdr;
949 u32 payload;
950 u32 chunks;
951
952 cmd = &tlv_req;
953 req_size = sizeof(tlv_req);
954 /* Prepare primary tlv header */
955 hdr = &tlv_req.tlv_hdr;
956 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req));
957 payload = sizeof(struct cmdq_modify_roce_cc);
958 __roce_1st_tlv_prep(hdr, chunks, payload, true);
959 /* Prepare secondary tlv header */
960 hdr = (struct roce_tlv *)&tlv_req.ext_req;
961 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) -
962 sizeof(struct roce_tlv);
963 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true);
964 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext);
965 }
966
967 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size,
968 sizeof(resp), 0);
969 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg);
970 return rc;
971 }
972