1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/arch/mips/bcm63xx/cpu.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <ram.h>
14 #include <asm/io.h>
15
16 #define SDRAM_CFG_REG 0x0
17 #define SDRAM_CFG_COL_SHIFT 4
18 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
19 #define SDRAM_CFG_ROW_SHIFT 6
20 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
21 #define SDRAM_CFG_32B_SHIFT 10
22 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
23 #define SDRAM_CFG_BANK_SHIFT 13
24 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
25 #define SDRAM_6318_SPACE_SHIFT 4
26 #define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
27
28 #define MEMC_CFG_REG 0x4
29 #define MEMC_CFG_32B_SHIFT 1
30 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
31 #define MEMC_CFG_COL_SHIFT 3
32 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
33 #define MEMC_CFG_ROW_SHIFT 6
34 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
35
36 #define DDR_CSEND_REG 0x8
37
38 struct bmips_ram_priv;
39
40 struct bmips_ram_hw {
41 ulong (*get_ram_size)(struct bmips_ram_priv *);
42 };
43
44 struct bmips_ram_priv {
45 void __iomem *regs;
46 u32 force_size;
47 const struct bmips_ram_hw *hw;
48 };
49
bcm6318_get_ram_size(struct bmips_ram_priv * priv)50 static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
51 {
52 u32 val;
53
54 val = readl_be(priv->regs + SDRAM_CFG_REG);
55 val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
56
57 return (1 << (val + 20));
58 }
59
bcm6328_get_ram_size(struct bmips_ram_priv * priv)60 static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
61 {
62 return readl_be(priv->regs + DDR_CSEND_REG) << 24;
63 }
64
bmips_dram_size(unsigned int cols,unsigned int rows,unsigned int is_32b,unsigned int banks)65 static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
66 unsigned int is_32b, unsigned int banks)
67 {
68 rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
69 cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
70 is_32b += 1;
71
72 return 1 << (cols + rows + is_32b + banks);
73 }
74
bcm6338_get_ram_size(struct bmips_ram_priv * priv)75 static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
76 {
77 unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
78 u32 val;
79
80 val = readl_be(priv->regs + SDRAM_CFG_REG);
81 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
82 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
83 is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
84 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
85
86 return bmips_dram_size(cols, rows, is_32b, banks);
87 }
88
bcm6358_get_ram_size(struct bmips_ram_priv * priv)89 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
90 {
91 unsigned int cols = 0, rows = 0, is_32b = 0;
92 u32 val;
93
94 val = readl_be(priv->regs + MEMC_CFG_REG);
95 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
96 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
97 is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
98
99 return bmips_dram_size(cols, rows, is_32b, 2);
100 }
101
bmips_ram_get_info(struct udevice * dev,struct ram_info * info)102 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
103 {
104 struct bmips_ram_priv *priv = dev_get_priv(dev);
105 const struct bmips_ram_hw *hw = priv->hw;
106
107 info->base = 0x80000000;
108 if (priv->force_size)
109 info->size = priv->force_size;
110 else
111 info->size = hw->get_ram_size(priv);
112
113 return 0;
114 }
115
116 static const struct ram_ops bmips_ram_ops = {
117 .get_info = bmips_ram_get_info,
118 };
119
120 static const struct bmips_ram_hw bmips_ram_bcm6318 = {
121 .get_ram_size = bcm6318_get_ram_size,
122 };
123
124 static const struct bmips_ram_hw bmips_ram_bcm6328 = {
125 .get_ram_size = bcm6328_get_ram_size,
126 };
127
128 static const struct bmips_ram_hw bmips_ram_bcm6338 = {
129 .get_ram_size = bcm6338_get_ram_size,
130 };
131
132 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
133 .get_ram_size = bcm6358_get_ram_size,
134 };
135
136 static const struct udevice_id bmips_ram_ids[] = {
137 {
138 .compatible = "brcm,bcm6318-mc",
139 .data = (ulong)&bmips_ram_bcm6318,
140 }, {
141 .compatible = "brcm,bcm6328-mc",
142 .data = (ulong)&bmips_ram_bcm6328,
143 }, {
144 .compatible = "brcm,bcm6338-mc",
145 .data = (ulong)&bmips_ram_bcm6338,
146 }, {
147 .compatible = "brcm,bcm6358-mc",
148 .data = (ulong)&bmips_ram_bcm6358,
149 }, { /* sentinel */ }
150 };
151
bmips_ram_probe(struct udevice * dev)152 static int bmips_ram_probe(struct udevice *dev)
153 {
154 struct bmips_ram_priv *priv = dev_get_priv(dev);
155 const struct bmips_ram_hw *hw =
156 (const struct bmips_ram_hw *)dev_get_driver_data(dev);
157
158 priv->regs = dev_remap_addr(dev);
159 if (!priv->regs)
160 return -EINVAL;
161
162 dev_read_u32(dev, "force-size", &priv->force_size);
163
164 priv->hw = hw;
165
166 return 0;
167 }
168
169 U_BOOT_DRIVER(bmips_ram) = {
170 .name = "bmips-mc",
171 .id = UCLASS_RAM,
172 .of_match = bmips_ram_ids,
173 .probe = bmips_ram_probe,
174 .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
175 .ops = &bmips_ram_ops,
176 };
177