xref: /openbmc/linux/drivers/pwm/pwm-stm32.c (revision 060f35a317ef09101b128f399dce7ed13d019461)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * Copyright (C) STMicroelectronics 2016
4   *
5   * Author: Gerald Baeza <gerald.baeza@st.com>
6   *
7   * Inspired by timer-stm32.c from Maxime Coquelin
8   *             pwm-atmel.c from Bo Shen
9   */
10  
11  #include <linux/bitfield.h>
12  #include <linux/mfd/stm32-timers.h>
13  #include <linux/module.h>
14  #include <linux/of.h>
15  #include <linux/pinctrl/consumer.h>
16  #include <linux/platform_device.h>
17  #include <linux/pwm.h>
18  
19  #define CCMR_CHANNEL_SHIFT 8
20  #define CCMR_CHANNEL_MASK  0xFF
21  #define MAX_BREAKINPUT 2
22  
23  struct stm32_breakinput {
24  	u32 index;
25  	u32 level;
26  	u32 filter;
27  };
28  
29  struct stm32_pwm {
30  	struct pwm_chip chip;
31  	struct mutex lock; /* protect pwm config/enable */
32  	struct clk *clk;
33  	struct regmap *regmap;
34  	u32 max_arr;
35  	bool have_complementary_output;
36  	struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37  	unsigned int num_breakinputs;
38  	u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
39  };
40  
to_stm32_pwm_dev(struct pwm_chip * chip)41  static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42  {
43  	return container_of(chip, struct stm32_pwm, chip);
44  }
45  
active_channels(struct stm32_pwm * dev)46  static u32 active_channels(struct stm32_pwm *dev)
47  {
48  	u32 ccer;
49  
50  	regmap_read(dev->regmap, TIM_CCER, &ccer);
51  
52  	return ccer & TIM_CCER_CCXE;
53  }
54  
write_ccrx(struct stm32_pwm * dev,int ch,u32 value)55  static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
56  {
57  	switch (ch) {
58  	case 0:
59  		return regmap_write(dev->regmap, TIM_CCR1, value);
60  	case 1:
61  		return regmap_write(dev->regmap, TIM_CCR2, value);
62  	case 2:
63  		return regmap_write(dev->regmap, TIM_CCR3, value);
64  	case 3:
65  		return regmap_write(dev->regmap, TIM_CCR4, value);
66  	}
67  	return -EINVAL;
68  }
69  
70  #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
71  #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
72  #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
73  #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
74  
75  /*
76   * Capture using PWM input mode:
77   *                              ___          ___
78   * TI[1, 2, 3 or 4]: ........._|   |________|
79   *                             ^0  ^1       ^2
80   *                              .   .        .
81   *                              .   .        XXXXX
82   *                              .   .   XXXXX     |
83   *                              .  XXXXX     .    |
84   *                            XXXXX .        .    |
85   * COUNTER:        ______XXXXX  .   .        .    |_XXX
86   *                 start^       .   .        .        ^stop
87   *                      .       .   .        .
88   *                      v       v   .        v
89   *                                  v
90   * CCR1/CCR3:       tx..........t0...........t2
91   * CCR2/CCR4:       tx..............t1.........
92   *
93   * DMA burst transfer:          |            |
94   *                              v            v
95   * DMA buffer:                  { t0, tx }   { t2, t1 }
96   * DMA done:                                 ^
97   *
98   * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
99   *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
100   * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
101   * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
102   *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
103   *
104   * DMA done, compute:
105   * - Period     = t2 - t0
106   * - Duty cycle = t1 - t0
107   */
stm32_pwm_raw_capture(struct stm32_pwm * priv,struct pwm_device * pwm,unsigned long tmo_ms,u32 * raw_prd,u32 * raw_dty)108  static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
109  				 unsigned long tmo_ms, u32 *raw_prd,
110  				 u32 *raw_dty)
111  {
112  	struct device *parent = priv->chip.dev->parent;
113  	enum stm32_timers_dmas dma_id;
114  	u32 ccen, ccr;
115  	int ret;
116  
117  	/* Ensure registers have been updated, enable counter and capture */
118  	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
119  	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
120  
121  	/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
122  	dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
123  	ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
124  	ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
125  	regmap_set_bits(priv->regmap, TIM_CCER, ccen);
126  
127  	/*
128  	 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
129  	 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
130  	 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
131  	 * or { CCR3, CCR4 }, { CCR3, CCR4 }
132  	 */
133  	ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
134  					  2, tmo_ms);
135  	if (ret)
136  		goto stop;
137  
138  	/* Period: t2 - t0 (take care of counter overflow) */
139  	if (priv->capture[0] <= priv->capture[2])
140  		*raw_prd = priv->capture[2] - priv->capture[0];
141  	else
142  		*raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
143  
144  	/* Duty cycle capture requires at least two capture units */
145  	if (pwm->chip->npwm < 2)
146  		*raw_dty = 0;
147  	else if (priv->capture[0] <= priv->capture[3])
148  		*raw_dty = priv->capture[3] - priv->capture[0];
149  	else
150  		*raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
151  
152  	if (*raw_dty > *raw_prd) {
153  		/*
154  		 * Race beetween PWM input and DMA: it may happen
155  		 * falling edge triggers new capture on TI2/4 before DMA
156  		 * had a chance to read CCR2/4. It means capture[1]
157  		 * contains period + duty_cycle. So, subtract period.
158  		 */
159  		*raw_dty -= *raw_prd;
160  	}
161  
162  stop:
163  	regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
164  	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
165  
166  	return ret;
167  }
168  
stm32_pwm_capture(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_capture * result,unsigned long tmo_ms)169  static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
170  			     struct pwm_capture *result, unsigned long tmo_ms)
171  {
172  	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
173  	unsigned long long prd, div, dty;
174  	unsigned long rate;
175  	unsigned int psc = 0, icpsc, scale;
176  	u32 raw_prd = 0, raw_dty = 0;
177  	int ret = 0;
178  
179  	mutex_lock(&priv->lock);
180  
181  	if (active_channels(priv)) {
182  		ret = -EBUSY;
183  		goto unlock;
184  	}
185  
186  	ret = clk_enable(priv->clk);
187  	if (ret) {
188  		dev_err(priv->chip.dev, "failed to enable counter clock\n");
189  		goto unlock;
190  	}
191  
192  	rate = clk_get_rate(priv->clk);
193  	if (!rate) {
194  		ret = -EINVAL;
195  		goto clk_dis;
196  	}
197  
198  	/* prescaler: fit timeout window provided by upper layer */
199  	div = (unsigned long long)rate * (unsigned long long)tmo_ms;
200  	do_div(div, MSEC_PER_SEC);
201  	prd = div;
202  	while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
203  		psc++;
204  		div = prd;
205  		do_div(div, psc + 1);
206  	}
207  	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
208  	regmap_write(priv->regmap, TIM_PSC, psc);
209  
210  	/* Reset input selector to its default input and disable slave mode */
211  	regmap_write(priv->regmap, TIM_TISEL, 0x0);
212  	regmap_write(priv->regmap, TIM_SMCR, 0x0);
213  
214  	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
215  	regmap_update_bits(priv->regmap,
216  			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
217  			   TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
218  			   TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
219  			   TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
220  
221  	/* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
222  	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
223  			   TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
224  			   TIM_CCER_CC2P : TIM_CCER_CC4P);
225  
226  	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
227  	if (ret)
228  		goto stop;
229  
230  	/*
231  	 * Got a capture. Try to improve accuracy at high rates:
232  	 * - decrease counter clock prescaler, scale up to max rate.
233  	 * - use input prescaler, capture once every /2 /4 or /8 edges.
234  	 */
235  	if (raw_prd) {
236  		u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
237  
238  		scale = max_arr / min(max_arr, raw_prd);
239  	} else {
240  		scale = priv->max_arr; /* bellow resolution, use max scale */
241  	}
242  
243  	if (psc && scale > 1) {
244  		/* 2nd measure with new scale */
245  		psc /= scale;
246  		regmap_write(priv->regmap, TIM_PSC, psc);
247  		ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
248  					    &raw_dty);
249  		if (ret)
250  			goto stop;
251  	}
252  
253  	/* Compute intermediate period not to exceed timeout at low rates */
254  	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
255  	do_div(prd, rate);
256  
257  	for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
258  		/* input prescaler: also keep arbitrary margin */
259  		if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
260  			break;
261  		if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
262  			break;
263  	}
264  
265  	if (!icpsc)
266  		goto done;
267  
268  	/* Last chance to improve period accuracy, using input prescaler */
269  	regmap_update_bits(priv->regmap,
270  			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
271  			   TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
272  			   FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
273  			   FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
274  
275  	ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
276  	if (ret)
277  		goto stop;
278  
279  	if (raw_dty >= (raw_prd >> icpsc)) {
280  		/*
281  		 * We may fall here using input prescaler, when input
282  		 * capture starts on high side (before falling edge).
283  		 * Example with icpsc to capture on each 4 events:
284  		 *
285  		 *       start   1st capture                     2nd capture
286  		 *         v     v                               v
287  		 *         ___   _____   _____   _____   _____   ____
288  		 * TI1..4     |__|    |__|    |__|    |__|    |__|
289  		 *            v  v    .  .    .  .    .       v  v
290  		 * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
291  		 * icpsc2/4:  0       1       2       3       0
292  		 *            v  v                            v  v
293  		 * CCR1/3  ......t0..............................t2
294  		 * CCR2/4  ..t1..............................t1'...
295  		 *               .                            .  .
296  		 * Capture0:     .<----------------------------->.
297  		 * Capture1:     .<-------------------------->.  .
298  		 *               .                            .  .
299  		 * Period:       .<------>                    .  .
300  		 * Low side:                                  .<>.
301  		 *
302  		 * Result:
303  		 * - Period = Capture0 / icpsc
304  		 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
305  		 */
306  		raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
307  	}
308  
309  done:
310  	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
311  	result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
312  	dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
313  	result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
314  stop:
315  	regmap_write(priv->regmap, TIM_CCER, 0);
316  	regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
317  	regmap_write(priv->regmap, TIM_PSC, 0);
318  clk_dis:
319  	clk_disable(priv->clk);
320  unlock:
321  	mutex_unlock(&priv->lock);
322  
323  	return ret;
324  }
325  
stm32_pwm_config(struct stm32_pwm * priv,int ch,int duty_ns,int period_ns)326  static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
327  			    int duty_ns, int period_ns)
328  {
329  	unsigned long long prd, div, dty;
330  	unsigned int prescaler = 0;
331  	u32 ccmr, mask, shift;
332  
333  	/* Period and prescaler values depends on clock rate */
334  	div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
335  
336  	do_div(div, NSEC_PER_SEC);
337  	prd = div;
338  
339  	while (div > priv->max_arr) {
340  		prescaler++;
341  		div = prd;
342  		do_div(div, prescaler + 1);
343  	}
344  
345  	prd = div;
346  
347  	if (!prd)
348  		return -EINVAL;
349  
350  	if (prescaler > MAX_TIM_PSC)
351  		return -EINVAL;
352  
353  	/*
354  	 * All channels share the same prescaler and counter so when two
355  	 * channels are active at the same time we can't change them
356  	 */
357  	if (active_channels(priv) & ~(1 << ch * 4)) {
358  		u32 psc, arr;
359  
360  		regmap_read(priv->regmap, TIM_PSC, &psc);
361  		regmap_read(priv->regmap, TIM_ARR, &arr);
362  
363  		if ((psc != prescaler) || (arr != prd - 1))
364  			return -EBUSY;
365  	}
366  
367  	regmap_write(priv->regmap, TIM_PSC, prescaler);
368  	regmap_write(priv->regmap, TIM_ARR, prd - 1);
369  	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
370  
371  	/* Calculate the duty cycles */
372  	dty = prd * duty_ns;
373  	do_div(dty, period_ns);
374  
375  	write_ccrx(priv, ch, dty);
376  
377  	/* Configure output mode */
378  	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
379  	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
380  	mask = CCMR_CHANNEL_MASK << shift;
381  
382  	if (ch < 2)
383  		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
384  	else
385  		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
386  
387  	regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
388  
389  	return 0;
390  }
391  
stm32_pwm_set_polarity(struct stm32_pwm * priv,int ch,enum pwm_polarity polarity)392  static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
393  				  enum pwm_polarity polarity)
394  {
395  	u32 mask;
396  
397  	mask = TIM_CCER_CC1P << (ch * 4);
398  	if (priv->have_complementary_output)
399  		mask |= TIM_CCER_CC1NP << (ch * 4);
400  
401  	regmap_update_bits(priv->regmap, TIM_CCER, mask,
402  			   polarity == PWM_POLARITY_NORMAL ? 0 : mask);
403  
404  	return 0;
405  }
406  
stm32_pwm_enable(struct stm32_pwm * priv,int ch)407  static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
408  {
409  	u32 mask;
410  	int ret;
411  
412  	ret = clk_enable(priv->clk);
413  	if (ret)
414  		return ret;
415  
416  	/* Enable channel */
417  	mask = TIM_CCER_CC1E << (ch * 4);
418  	if (priv->have_complementary_output)
419  		mask |= TIM_CCER_CC1NE << (ch * 4);
420  
421  	regmap_set_bits(priv->regmap, TIM_CCER, mask);
422  
423  	/* Make sure that registers are updated */
424  	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
425  
426  	/* Enable controller */
427  	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
428  
429  	return 0;
430  }
431  
stm32_pwm_disable(struct stm32_pwm * priv,int ch)432  static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
433  {
434  	u32 mask;
435  
436  	/* Disable channel */
437  	mask = TIM_CCER_CC1E << (ch * 4);
438  	if (priv->have_complementary_output)
439  		mask |= TIM_CCER_CC1NE << (ch * 4);
440  
441  	regmap_clear_bits(priv->regmap, TIM_CCER, mask);
442  
443  	/* When all channels are disabled, we can disable the controller */
444  	if (!active_channels(priv))
445  		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
446  
447  	clk_disable(priv->clk);
448  }
449  
stm32_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)450  static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
451  			   const struct pwm_state *state)
452  {
453  	bool enabled;
454  	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
455  	int ret;
456  
457  	enabled = pwm->state.enabled;
458  
459  	if (!state->enabled) {
460  		if (enabled)
461  			stm32_pwm_disable(priv, pwm->hwpwm);
462  		return 0;
463  	}
464  
465  	if (state->polarity != pwm->state.polarity)
466  		stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
467  
468  	ret = stm32_pwm_config(priv, pwm->hwpwm,
469  			       state->duty_cycle, state->period);
470  	if (ret)
471  		return ret;
472  
473  	if (!enabled && state->enabled)
474  		ret = stm32_pwm_enable(priv, pwm->hwpwm);
475  
476  	return ret;
477  }
478  
stm32_pwm_apply_locked(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)479  static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
480  				  const struct pwm_state *state)
481  {
482  	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
483  	int ret;
484  
485  	/* protect common prescaler for all active channels */
486  	mutex_lock(&priv->lock);
487  	ret = stm32_pwm_apply(chip, pwm, state);
488  	mutex_unlock(&priv->lock);
489  
490  	return ret;
491  }
492  
493  static const struct pwm_ops stm32pwm_ops = {
494  	.owner = THIS_MODULE,
495  	.apply = stm32_pwm_apply_locked,
496  	.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
497  };
498  
stm32_pwm_set_breakinput(struct stm32_pwm * priv,const struct stm32_breakinput * bi)499  static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
500  				    const struct stm32_breakinput *bi)
501  {
502  	u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
503  	u32 bke = TIM_BDTR_BKE(bi->index);
504  	u32 bkp = TIM_BDTR_BKP(bi->index);
505  	u32 bkf = TIM_BDTR_BKF(bi->index);
506  	u32 mask = bkf | bkp | bke;
507  	u32 bdtr;
508  
509  	bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
510  
511  	if (bi->level)
512  		bdtr |= bkp;
513  
514  	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
515  
516  	regmap_read(priv->regmap, TIM_BDTR, &bdtr);
517  
518  	return (bdtr & bke) ? 0 : -EINVAL;
519  }
520  
stm32_pwm_apply_breakinputs(struct stm32_pwm * priv)521  static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
522  {
523  	unsigned int i;
524  	int ret;
525  
526  	for (i = 0; i < priv->num_breakinputs; i++) {
527  		ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
528  		if (ret < 0)
529  			return ret;
530  	}
531  
532  	return 0;
533  }
534  
stm32_pwm_probe_breakinputs(struct stm32_pwm * priv,struct device_node * np)535  static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
536  				       struct device_node *np)
537  {
538  	int nb, ret, array_size;
539  	unsigned int i;
540  
541  	nb = of_property_count_elems_of_size(np, "st,breakinput",
542  					     sizeof(struct stm32_breakinput));
543  
544  	/*
545  	 * Because "st,breakinput" parameter is optional do not make probe
546  	 * failed if it doesn't exist.
547  	 */
548  	if (nb <= 0)
549  		return 0;
550  
551  	if (nb > MAX_BREAKINPUT)
552  		return -EINVAL;
553  
554  	priv->num_breakinputs = nb;
555  	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
556  	ret = of_property_read_u32_array(np, "st,breakinput",
557  					 (u32 *)priv->breakinputs, array_size);
558  	if (ret)
559  		return ret;
560  
561  	for (i = 0; i < priv->num_breakinputs; i++) {
562  		if (priv->breakinputs[i].index > 1 ||
563  		    priv->breakinputs[i].level > 1 ||
564  		    priv->breakinputs[i].filter > 15)
565  			return -EINVAL;
566  	}
567  
568  	return stm32_pwm_apply_breakinputs(priv);
569  }
570  
stm32_pwm_detect_complementary(struct stm32_pwm * priv)571  static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
572  {
573  	u32 ccer;
574  
575  	/*
576  	 * If complementary bit doesn't exist writing 1 will have no
577  	 * effect so we can detect it.
578  	 */
579  	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
580  	regmap_read(priv->regmap, TIM_CCER, &ccer);
581  	regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
582  
583  	priv->have_complementary_output = (ccer != 0);
584  }
585  
stm32_pwm_detect_channels(struct stm32_pwm * priv,unsigned int * num_enabled)586  static unsigned int stm32_pwm_detect_channels(struct stm32_pwm *priv,
587  					      unsigned int *num_enabled)
588  {
589  	u32 ccer, ccer_backup;
590  
591  	/*
592  	 * If channels enable bits don't exist writing 1 will have no
593  	 * effect so we can detect and count them.
594  	 */
595  	regmap_read(priv->regmap, TIM_CCER, &ccer_backup);
596  	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
597  	regmap_read(priv->regmap, TIM_CCER, &ccer);
598  	regmap_write(priv->regmap, TIM_CCER, ccer_backup);
599  
600  	*num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
601  
602  	return hweight32(ccer & TIM_CCER_CCXE);
603  }
604  
stm32_pwm_probe(struct platform_device * pdev)605  static int stm32_pwm_probe(struct platform_device *pdev)
606  {
607  	struct device *dev = &pdev->dev;
608  	struct device_node *np = dev->of_node;
609  	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
610  	struct stm32_pwm *priv;
611  	unsigned int num_enabled;
612  	unsigned int i;
613  	int ret;
614  
615  	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
616  	if (!priv)
617  		return -ENOMEM;
618  
619  	mutex_init(&priv->lock);
620  	priv->regmap = ddata->regmap;
621  	priv->clk = ddata->clk;
622  	priv->max_arr = ddata->max_arr;
623  
624  	if (!priv->regmap || !priv->clk)
625  		return -EINVAL;
626  
627  	ret = stm32_pwm_probe_breakinputs(priv, np);
628  	if (ret)
629  		return ret;
630  
631  	stm32_pwm_detect_complementary(priv);
632  
633  	priv->chip.dev = dev;
634  	priv->chip.ops = &stm32pwm_ops;
635  	priv->chip.npwm = stm32_pwm_detect_channels(priv, &num_enabled);
636  
637  	/* Initialize clock refcount to number of enabled PWM channels. */
638  	for (i = 0; i < num_enabled; i++) {
639  		ret = clk_enable(priv->clk);
640  		if (ret)
641  			return ret;
642  	}
643  
644  	ret = devm_pwmchip_add(dev, &priv->chip);
645  	if (ret < 0)
646  		return ret;
647  
648  	platform_set_drvdata(pdev, priv);
649  
650  	return 0;
651  }
652  
stm32_pwm_suspend(struct device * dev)653  static int __maybe_unused stm32_pwm_suspend(struct device *dev)
654  {
655  	struct stm32_pwm *priv = dev_get_drvdata(dev);
656  	unsigned int i;
657  	u32 ccer, mask;
658  
659  	/* Look for active channels */
660  	ccer = active_channels(priv);
661  
662  	for (i = 0; i < priv->chip.npwm; i++) {
663  		mask = TIM_CCER_CC1E << (i * 4);
664  		if (ccer & mask) {
665  			dev_err(dev, "PWM %u still in use by consumer %s\n",
666  				i, priv->chip.pwms[i].label);
667  			return -EBUSY;
668  		}
669  	}
670  
671  	return pinctrl_pm_select_sleep_state(dev);
672  }
673  
stm32_pwm_resume(struct device * dev)674  static int __maybe_unused stm32_pwm_resume(struct device *dev)
675  {
676  	struct stm32_pwm *priv = dev_get_drvdata(dev);
677  	int ret;
678  
679  	ret = pinctrl_pm_select_default_state(dev);
680  	if (ret)
681  		return ret;
682  
683  	/* restore breakinput registers that may have been lost in low power */
684  	return stm32_pwm_apply_breakinputs(priv);
685  }
686  
687  static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
688  
689  static const struct of_device_id stm32_pwm_of_match[] = {
690  	{ .compatible = "st,stm32-pwm",	},
691  	{ /* end node */ },
692  };
693  MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
694  
695  static struct platform_driver stm32_pwm_driver = {
696  	.probe	= stm32_pwm_probe,
697  	.driver	= {
698  		.name = "stm32-pwm",
699  		.of_match_table = stm32_pwm_of_match,
700  		.pm = &stm32_pwm_pm_ops,
701  	},
702  };
703  module_platform_driver(stm32_pwm_driver);
704  
705  MODULE_ALIAS("platform:stm32-pwm");
706  MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
707  MODULE_LICENSE("GPL v2");
708