xref: /openbmc/linux/drivers/clk/actions/owl-s900.c (revision 1fdfd517)
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // OWL S900 SoC clock driver
4 //
5 // Copyright (c) 2014 Actions Semi Inc.
6 // Author: David Liu <liuwei@actions-semi.com>
7 //
8 // Copyright (c) 2018 Linaro Ltd.
9 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 
11 #include <linux/clk-provider.h>
12 #include <linux/platform_device.h>
13 
14 #include "owl-common.h"
15 #include "owl-composite.h"
16 #include "owl-divider.h"
17 #include "owl-factor.h"
18 #include "owl-fixed-factor.h"
19 #include "owl-gate.h"
20 #include "owl-mux.h"
21 #include "owl-pll.h"
22 #include "owl-reset.h"
23 
24 #include <dt-bindings/clock/actions,s900-cmu.h>
25 #include <dt-bindings/reset/actions,s900-reset.h>
26 
27 #define CMU_COREPLL		(0x0000)
28 #define CMU_DEVPLL		(0x0004)
29 #define CMU_DDRPLL		(0x0008)
30 #define CMU_NANDPLL		(0x000C)
31 #define CMU_DISPLAYPLL		(0x0010)
32 #define CMU_AUDIOPLL		(0x0014)
33 #define CMU_TVOUTPLL		(0x0018)
34 #define CMU_BUSCLK		(0x001C)
35 #define CMU_SENSORCLK		(0x0020)
36 #define CMU_LCDCLK		(0x0024)
37 #define CMU_DSICLK		(0x0028)
38 #define CMU_CSICLK		(0x002C)
39 #define CMU_DECLK		(0x0030)
40 #define CMU_BISPCLK		(0x0034)
41 #define CMU_IMXCLK		(0x0038)
42 #define CMU_HDECLK		(0x003C)
43 #define CMU_VDECLK		(0x0040)
44 #define CMU_VCECLK		(0x0044)
45 #define CMU_NANDCCLK		(0x004C)
46 #define CMU_SD0CLK		(0x0050)
47 #define CMU_SD1CLK		(0x0054)
48 #define CMU_SD2CLK		(0x0058)
49 #define CMU_UART0CLK		(0x005C)
50 #define CMU_UART1CLK		(0x0060)
51 #define CMU_UART2CLK		(0x0064)
52 #define CMU_PWM0CLK		(0x0070)
53 #define CMU_PWM1CLK		(0x0074)
54 #define CMU_PWM2CLK		(0x0078)
55 #define CMU_PWM3CLK		(0x007C)
56 #define CMU_USBPLL		(0x0080)
57 #define CMU_ASSISTPLL		(0x0084)
58 #define CMU_EDPCLK		(0x0088)
59 #define CMU_GPU3DCLK		(0x0090)
60 #define CMU_CORECTL		(0x009C)
61 #define CMU_DEVCLKEN0		(0x00A0)
62 #define CMU_DEVCLKEN1		(0x00A4)
63 #define CMU_DEVRST0		(0x00A8)
64 #define CMU_DEVRST1		(0x00AC)
65 #define CMU_UART3CLK		(0x00B0)
66 #define CMU_UART4CLK		(0x00B4)
67 #define CMU_UART5CLK		(0x00B8)
68 #define CMU_UART6CLK		(0x00BC)
69 #define CMU_TLSCLK		(0x00C0)
70 #define CMU_SD3CLK		(0x00C4)
71 #define CMU_PWM4CLK		(0x00C8)
72 #define CMU_PWM5CLK		(0x00CC)
73 
74 static struct clk_pll_table clk_audio_pll_table[] = {
75 	{ 0, 45158400 }, { 1, 49152000 },
76 	{ /* sentinel */ }
77 };
78 
79 static struct clk_pll_table clk_edp_pll_table[] = {
80 	{ 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
81 	{ /* sentinel */ }
82 };
83 
84 /* pll clocks */
85 static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
86 static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
87 static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
88 static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
89 static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
90 static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
91 static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
92 static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
93 
94 static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
95 static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
96 static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
97 static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
98 static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
99 static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
100 static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
101 static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
102 static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
103 static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
104 static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
105 static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
106 static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
107 static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
108 static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
109 static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
110 static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
111 static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
112 
113 /* mux clocks */
114 static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
115 static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
116 static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
117 
118 static struct clk_div_table nand_div_table[] = {
119 	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
120 	{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
121 	{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
122 	{ 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
123 	{ /* sentinel */ }
124 };
125 
126 static struct clk_div_table apb_div_table[] = {
127 	{ 1, 2 }, { 2, 3 }, { 3, 4 },
128 	{ /* sentinel */ }
129 };
130 
131 static struct clk_div_table eth_mac_div_table[] = {
132 	{ 0, 2 }, { 1, 4 },
133 	{ /* sentinel */ }
134 };
135 
136 static struct clk_div_table rmii_ref_div_table[] = {
137 	{ 0, 4 },	  { 1, 10 },
138 	{ /* sentinel */ }
139 };
140 
141 static struct clk_div_table usb3_mac_div_table[] = {
142 	{ 1, 2 }, { 2, 3 }, { 3, 4 },
143 	{ /* sentinel */ }
144 };
145 
146 static struct clk_div_table i2s_div_table[] = {
147 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
148 	{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
149 	{ 8, 24 },
150 	{ /* sentinel */ }
151 };
152 
153 static struct clk_div_table hdmia_div_table[] = {
154 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
155 	{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
156 	{ 8, 24 },
157 	{ /* sentinel */ }
158 };
159 
160 /* divider clocks */
161 static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
162 static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
163 static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
164 static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
165 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
166 
167 static struct clk_factor_table sd_factor_table[] = {
168 	/* bit0 ~ 4 */
169 	{ 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
170 	{ 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
171 	{ 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
172 	{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
173 	{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
174 	{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
175 	{ 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
176 	{ 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
177 
178 	/* bit8: /128 */
179 	{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
180 	{ 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
181 	{ 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
182 	{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
183 	{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
184 	{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
185 	{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
186 	{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
187 
188 	{ /* sentinel */ }
189 };
190 
191 static struct clk_factor_table dmm_factor_table[] = {
192 	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
193 	{ 4, 1, 4 },
194 	{ /* sentinel */ }
195 };
196 
197 static struct clk_factor_table noc_factor_table[] = {
198 	{ 0, 1, 1 },   { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
199 	{ /* sentinel */ }
200 };
201 
202 static struct clk_factor_table bisp_factor_table[] = {
203 	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
204 	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
205 	{ /* sentinel */ }
206 };
207 
208 /* factor clocks */
209 static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
210 static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
211 static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
212 static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
213 
214 /* gate clocks */
215 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
216 static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
217 static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
218 static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
219 static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
220 static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
221 static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
222 static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
223 static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
224 static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
225 static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
226 static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
227 static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
228 static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
229 static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
230 static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
231 static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
232 static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
233 static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
234 static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
235 static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
236 static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
237 static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
238 
239 /* composite clocks */
240 static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
241 			OWL_MUX_HW(CMU_BISPCLK, 4, 1),
242 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
243 			OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
244 			0);
245 
246 static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
247 			OWL_MUX_HW(CMU_CSICLK, 4, 1),
248 			OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
249 			OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
250 			0);
251 
252 static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
253 			OWL_MUX_HW(CMU_CSICLK, 20, 1),
254 			OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
255 			OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
256 			0);
257 
258 static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
259 			OWL_MUX_HW(CMU_DECLK, 12, 1),
260 			OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
261 			0);
262 
263 static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
264 			OWL_MUX_HW(CMU_BUSCLK, 10, 2),
265 			OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
266 			OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
267 			CLK_IGNORE_UNUSED);
268 
269 static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
270 			OWL_MUX_HW(CMU_EDPCLK, 19, 1),
271 			OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
272 			OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
273 			0);
274 
275 static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
276 			OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
277 			OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
278 			0);
279 
280 static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
281 			OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
282 			OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
283 			OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
284 			0);
285 
286 static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
287 			OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
288 			OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
289 			OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
290 			0);
291 
292 static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
293 			OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
294 			OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
295 			OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
296 			0);
297 
298 static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
299 			OWL_MUX_HW(CMU_HDECLK, 4, 2),
300 			OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
301 			OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
302 			0);
303 
304 static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
305 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
306 			OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
307 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
308 			0);
309 
310 static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
311 			OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
312 			1, 5, 0);
313 
314 static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
315 			OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
316 			1, 5, 0);
317 
318 static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
319 			OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
320 			1, 5, 0);
321 
322 static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
323 			OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
324 			1, 5, 0);
325 
326 static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
327 			OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
328 			1, 5, 0);
329 
330 static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
331 			OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
332 			1, 5, 0);
333 
334 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
335 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
336 			OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
337 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
338 			0);
339 
340 static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
341 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
342 			OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
343 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
344 			0);
345 
346 static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
347 			OWL_MUX_HW(CMU_IMXCLK, 4, 1),
348 			OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
349 			OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
350 			0);
351 
352 static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
353 			OWL_MUX_HW(CMU_LCDCLK, 12, 2),
354 			OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
355 			OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
356 			0);
357 
358 static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
359 			OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
360 			OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
361 			OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
362 			CLK_SET_RATE_PARENT);
363 
364 static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
365 			OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
366 			OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
367 			OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
368 			CLK_SET_RATE_PARENT);
369 
370 static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
371 			OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
372 			OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
373 			0);
374 
375 static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
376 			OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
377 			OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
378 			0);
379 /*
380  * pwm2 may be for backlight, do not gate it
381  * even it is "unused", because it may be
382  * enabled at boot stage, and in kernel, driver
383  * has no effective method to know the real status,
384  * so, the best way is keeping it as what it was.
385  */
386 static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
387 			OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
388 			OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
389 			CLK_IGNORE_UNUSED);
390 
391 static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
392 			OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
393 			OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
394 			0);
395 
396 static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
397 			OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
398 			OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
399 			0);
400 
401 static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
402 			OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
403 			OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
404 			0);
405 
406 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
407 			OWL_MUX_HW(CMU_SD0CLK, 9, 1),
408 			OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
409 			OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
410 			0);
411 
412 static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
413 			OWL_MUX_HW(CMU_SD1CLK, 9, 1),
414 			OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
415 			OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
416 			0);
417 
418 static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
419 			OWL_MUX_HW(CMU_SD2CLK, 9, 1),
420 			OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
421 			OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
422 			0);
423 
424 static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
425 			OWL_MUX_HW(CMU_SD3CLK, 9, 1),
426 			OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
427 			OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
428 			0);
429 
430 static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
431 			OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
432 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
433 			OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
434 			0);
435 
436 static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
437 			"hosc",
438 			OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
439 			OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
440 			0);
441 
442 static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
443 			"hosc",
444 			OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
445 			OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
446 			0);
447 
448 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
449 			OWL_MUX_HW(CMU_UART0CLK, 16, 1),
450 			OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
451 			OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
452 			CLK_IGNORE_UNUSED);
453 
454 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
455 			OWL_MUX_HW(CMU_UART1CLK, 16, 1),
456 			OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
457 			OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
458 			CLK_IGNORE_UNUSED);
459 
460 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
461 			OWL_MUX_HW(CMU_UART2CLK, 16, 1),
462 			OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
463 			OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
464 			CLK_IGNORE_UNUSED);
465 
466 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
467 			OWL_MUX_HW(CMU_UART3CLK, 16, 1),
468 			OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
469 			OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
470 			CLK_IGNORE_UNUSED);
471 
472 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
473 			OWL_MUX_HW(CMU_UART4CLK, 16, 1),
474 			OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
475 			OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
476 			CLK_IGNORE_UNUSED);
477 
478 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
479 			OWL_MUX_HW(CMU_UART5CLK, 16, 1),
480 			OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
481 			OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
482 			CLK_IGNORE_UNUSED);
483 
484 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
485 			OWL_MUX_HW(CMU_UART6CLK, 16, 1),
486 			OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
487 			OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
488 			CLK_IGNORE_UNUSED);
489 
490 static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
491 			OWL_MUX_HW(CMU_VCECLK, 4, 2),
492 			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
493 			OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
494 			0);
495 
496 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
497 			OWL_MUX_HW(CMU_VDECLK, 4, 2),
498 			OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
499 			OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
500 			0);
501 
502 static struct owl_clk_common *s900_clks[] = {
503 	&core_pll_clk.common,
504 	&dev_pll_clk.common,
505 	&ddr_pll_clk.common,
506 	&nand_pll_clk.common,
507 	&display_pll_clk.common,
508 	&assist_pll_clk.common,
509 	&audio_pll_clk.common,
510 	&edp_pll_clk.common,
511 	&cpu_clk.common,
512 	&dev_clk.common,
513 	&noc_clk_mux.common,
514 	&noc_clk_div.common,
515 	&ahb_clk.common,
516 	&apb_clk.common,
517 	&usb3_mac_clk.common,
518 	&rmii_ref_clk.common,
519 	&noc_clk.common,
520 	&de_clk1.common,
521 	&de_clk2.common,
522 	&de_clk3.common,
523 	&gpio_clk.common,
524 	&gpu_clk.common,
525 	&dmac_clk.common,
526 	&timer_clk.common,
527 	&dsi_clk.common,
528 	&ddr0_clk.common,
529 	&ddr1_clk.common,
530 	&usb3_480mpll0_clk.common,
531 	&usb3_480mphy0_clk.common,
532 	&usb3_5gphy_clk.common,
533 	&usb3_cce_clk.common,
534 	&edp24M_clk.common,
535 	&edp_link_clk.common,
536 	&usbh0_pllen_clk.common,
537 	&usbh0_phy_clk.common,
538 	&usbh0_cce_clk.common,
539 	&usbh1_pllen_clk.common,
540 	&usbh1_phy_clk.common,
541 	&usbh1_cce_clk.common,
542 	&i2c0_clk.common,
543 	&i2c1_clk.common,
544 	&i2c2_clk.common,
545 	&i2c3_clk.common,
546 	&i2c4_clk.common,
547 	&i2c5_clk.common,
548 	&spi0_clk.common,
549 	&spi1_clk.common,
550 	&spi2_clk.common,
551 	&spi3_clk.common,
552 	&bisp_clk.common,
553 	&csi0_clk.common,
554 	&csi1_clk.common,
555 	&de_clk.common,
556 	&dmm_clk.common,
557 	&edp_clk.common,
558 	&eth_mac_clk.common,
559 	&gpu_core_clk.common,
560 	&gpu_mem_clk.common,
561 	&gpu_sys_clk.common,
562 	&hde_clk.common,
563 	&hdmia_clk.common,
564 	&i2srx_clk.common,
565 	&i2stx_clk.common,
566 	&imx_clk.common,
567 	&lcd_clk.common,
568 	&nand0_clk.common,
569 	&nand1_clk.common,
570 	&pwm0_clk.common,
571 	&pwm1_clk.common,
572 	&pwm2_clk.common,
573 	&pwm3_clk.common,
574 	&pwm4_clk.common,
575 	&pwm5_clk.common,
576 	&sd0_clk.common,
577 	&sd1_clk.common,
578 	&sd2_clk.common,
579 	&sd3_clk.common,
580 	&sensor_clk.common,
581 	&speed_sensor_clk.common,
582 	&thermal_sensor_clk.common,
583 	&uart0_clk.common,
584 	&uart1_clk.common,
585 	&uart2_clk.common,
586 	&uart3_clk.common,
587 	&uart4_clk.common,
588 	&uart5_clk.common,
589 	&uart6_clk.common,
590 	&vce_clk.common,
591 	&vde_clk.common,
592 };
593 
594 static struct clk_hw_onecell_data s900_hw_clks = {
595 	.hws	= {
596 		[CLK_CORE_PLL]		= &core_pll_clk.common.hw,
597 		[CLK_DEV_PLL]		= &dev_pll_clk.common.hw,
598 		[CLK_DDR_PLL]		= &ddr_pll_clk.common.hw,
599 		[CLK_NAND_PLL]		= &nand_pll_clk.common.hw,
600 		[CLK_DISPLAY_PLL]	= &display_pll_clk.common.hw,
601 		[CLK_ASSIST_PLL]	= &assist_pll_clk.common.hw,
602 		[CLK_AUDIO_PLL]		= &audio_pll_clk.common.hw,
603 		[CLK_EDP_PLL]		= &edp_pll_clk.common.hw,
604 		[CLK_CPU]		= &cpu_clk.common.hw,
605 		[CLK_DEV]		= &dev_clk.common.hw,
606 		[CLK_NOC_MUX]		= &noc_clk_mux.common.hw,
607 		[CLK_NOC_DIV]		= &noc_clk_div.common.hw,
608 		[CLK_AHB]		= &ahb_clk.common.hw,
609 		[CLK_APB]		= &apb_clk.common.hw,
610 		[CLK_USB3_MAC]		= &usb3_mac_clk.common.hw,
611 		[CLK_RMII_REF]		= &rmii_ref_clk.common.hw,
612 		[CLK_NOC]		= &noc_clk.common.hw,
613 		[CLK_DE1]		= &de_clk1.common.hw,
614 		[CLK_DE2]		= &de_clk2.common.hw,
615 		[CLK_DE3]		= &de_clk3.common.hw,
616 		[CLK_GPIO]		= &gpio_clk.common.hw,
617 		[CLK_GPU]		= &gpu_clk.common.hw,
618 		[CLK_DMAC]		= &dmac_clk.common.hw,
619 		[CLK_TIMER]		= &timer_clk.common.hw,
620 		[CLK_DSI]		= &dsi_clk.common.hw,
621 		[CLK_DDR0]		= &ddr0_clk.common.hw,
622 		[CLK_DDR1]		= &ddr1_clk.common.hw,
623 		[CLK_USB3_480MPLL0]	= &usb3_480mpll0_clk.common.hw,
624 		[CLK_USB3_480MPHY0]	= &usb3_480mphy0_clk.common.hw,
625 		[CLK_USB3_5GPHY]	= &usb3_5gphy_clk.common.hw,
626 		[CLK_USB3_CCE]		= &usb3_cce_clk.common.hw,
627 		[CLK_24M_EDP]		= &edp24M_clk.common.hw,
628 		[CLK_EDP_LINK]		= &edp_link_clk.common.hw,
629 		[CLK_USB2H0_PLLEN]	= &usbh0_pllen_clk.common.hw,
630 		[CLK_USB2H0_PHY]	= &usbh0_phy_clk.common.hw,
631 		[CLK_USB2H0_CCE]	= &usbh0_cce_clk.common.hw,
632 		[CLK_USB2H1_PLLEN]	= &usbh1_pllen_clk.common.hw,
633 		[CLK_USB2H1_PHY]	= &usbh1_phy_clk.common.hw,
634 		[CLK_USB2H1_CCE]	= &usbh1_cce_clk.common.hw,
635 		[CLK_I2C0]		= &i2c0_clk.common.hw,
636 		[CLK_I2C1]		= &i2c1_clk.common.hw,
637 		[CLK_I2C2]		= &i2c2_clk.common.hw,
638 		[CLK_I2C3]		= &i2c3_clk.common.hw,
639 		[CLK_I2C4]		= &i2c4_clk.common.hw,
640 		[CLK_I2C5]		= &i2c5_clk.common.hw,
641 		[CLK_SPI0]		= &spi0_clk.common.hw,
642 		[CLK_SPI1]		= &spi1_clk.common.hw,
643 		[CLK_SPI2]		= &spi2_clk.common.hw,
644 		[CLK_SPI3]		= &spi3_clk.common.hw,
645 		[CLK_BISP]		= &bisp_clk.common.hw,
646 		[CLK_CSI0]		= &csi0_clk.common.hw,
647 		[CLK_CSI1]		= &csi1_clk.common.hw,
648 		[CLK_DE0]		= &de_clk.common.hw,
649 		[CLK_DMM]		= &dmm_clk.common.hw,
650 		[CLK_EDP]		= &edp_clk.common.hw,
651 		[CLK_ETH_MAC]		= &eth_mac_clk.common.hw,
652 		[CLK_GPU_CORE]		= &gpu_core_clk.common.hw,
653 		[CLK_GPU_MEM]		= &gpu_mem_clk.common.hw,
654 		[CLK_GPU_SYS]		= &gpu_sys_clk.common.hw,
655 		[CLK_HDE]		= &hde_clk.common.hw,
656 		[CLK_HDMI_AUDIO]	= &hdmia_clk.common.hw,
657 		[CLK_I2SRX]		= &i2srx_clk.common.hw,
658 		[CLK_I2STX]		= &i2stx_clk.common.hw,
659 		[CLK_IMX]		= &imx_clk.common.hw,
660 		[CLK_LCD]		= &lcd_clk.common.hw,
661 		[CLK_NAND0]		= &nand0_clk.common.hw,
662 		[CLK_NAND1]		= &nand1_clk.common.hw,
663 		[CLK_PWM0]		= &pwm0_clk.common.hw,
664 		[CLK_PWM1]		= &pwm1_clk.common.hw,
665 		[CLK_PWM2]		= &pwm2_clk.common.hw,
666 		[CLK_PWM3]		= &pwm3_clk.common.hw,
667 		[CLK_PWM4]		= &pwm4_clk.common.hw,
668 		[CLK_PWM5]		= &pwm5_clk.common.hw,
669 		[CLK_SD0]		= &sd0_clk.common.hw,
670 		[CLK_SD1]		= &sd1_clk.common.hw,
671 		[CLK_SD2]		= &sd2_clk.common.hw,
672 		[CLK_SD3]		= &sd3_clk.common.hw,
673 		[CLK_SENSOR]		= &sensor_clk.common.hw,
674 		[CLK_SPEED_SENSOR]	= &speed_sensor_clk.common.hw,
675 		[CLK_THERMAL_SENSOR]	= &thermal_sensor_clk.common.hw,
676 		[CLK_UART0]		= &uart0_clk.common.hw,
677 		[CLK_UART1]		= &uart1_clk.common.hw,
678 		[CLK_UART2]		= &uart2_clk.common.hw,
679 		[CLK_UART3]		= &uart3_clk.common.hw,
680 		[CLK_UART4]		= &uart4_clk.common.hw,
681 		[CLK_UART5]		= &uart5_clk.common.hw,
682 		[CLK_UART6]		= &uart6_clk.common.hw,
683 		[CLK_VCE]		= &vce_clk.common.hw,
684 		[CLK_VDE]		= &vde_clk.common.hw,
685 	},
686 	.num	= CLK_NR_CLKS,
687 };
688 
689 static const struct owl_reset_map s900_resets[] = {
690 	[RESET_DMAC]		= { CMU_DEVRST0, BIT(0) },
691 	[RESET_SRAMI]		= { CMU_DEVRST0, BIT(1) },
692 	[RESET_DDR_CTL_PHY]	= { CMU_DEVRST0, BIT(2) },
693 	[RESET_NANDC0]		= { CMU_DEVRST0, BIT(3) },
694 	[RESET_SD0]		= { CMU_DEVRST0, BIT(4) },
695 	[RESET_SD1]		= { CMU_DEVRST0, BIT(5) },
696 	[RESET_PCM1]		= { CMU_DEVRST0, BIT(6) },
697 	[RESET_DE]		= { CMU_DEVRST0, BIT(7) },
698 	[RESET_LVDS]		= { CMU_DEVRST0, BIT(8) },
699 	[RESET_SD2]		= { CMU_DEVRST0, BIT(9) },
700 	[RESET_DSI]		= { CMU_DEVRST0, BIT(10) },
701 	[RESET_CSI0]		= { CMU_DEVRST0, BIT(11) },
702 	[RESET_BISP_AXI]	= { CMU_DEVRST0, BIT(12) },
703 	[RESET_CSI1]		= { CMU_DEVRST0, BIT(13) },
704 	[RESET_GPIO]		= { CMU_DEVRST0, BIT(15) },
705 	[RESET_EDP]		= { CMU_DEVRST0, BIT(16) },
706 	[RESET_AUDIO]		= { CMU_DEVRST0, BIT(17) },
707 	[RESET_PCM0]		= { CMU_DEVRST0, BIT(18) },
708 	[RESET_HDE]		= { CMU_DEVRST0, BIT(21) },
709 	[RESET_GPU3D_PA]	= { CMU_DEVRST0, BIT(22) },
710 	[RESET_IMX]		= { CMU_DEVRST0, BIT(23) },
711 	[RESET_SE]		= { CMU_DEVRST0, BIT(24) },
712 	[RESET_NANDC1]		= { CMU_DEVRST0, BIT(25) },
713 	[RESET_SD3]		= { CMU_DEVRST0, BIT(26) },
714 	[RESET_GIC]		= { CMU_DEVRST0, BIT(27) },
715 	[RESET_GPU3D_PB]	= { CMU_DEVRST0, BIT(28) },
716 	[RESET_DDR_CTL_PHY_AXI]	= { CMU_DEVRST0, BIT(29) },
717 	[RESET_CMU_DDR]		= { CMU_DEVRST0, BIT(30) },
718 	[RESET_DMM]		= { CMU_DEVRST0, BIT(31) },
719 	[RESET_USB2HUB]		= { CMU_DEVRST1, BIT(0) },
720 	[RESET_USB2HSIC]	= { CMU_DEVRST1, BIT(1) },
721 	[RESET_HDMI]		= { CMU_DEVRST1, BIT(2) },
722 	[RESET_HDCP2TX]		= { CMU_DEVRST1, BIT(3) },
723 	[RESET_UART6]		= { CMU_DEVRST1, BIT(4) },
724 	[RESET_UART0]		= { CMU_DEVRST1, BIT(5) },
725 	[RESET_UART1]		= { CMU_DEVRST1, BIT(6) },
726 	[RESET_UART2]		= { CMU_DEVRST1, BIT(7) },
727 	[RESET_SPI0]		= { CMU_DEVRST1, BIT(8) },
728 	[RESET_SPI1]		= { CMU_DEVRST1, BIT(9) },
729 	[RESET_SPI2]		= { CMU_DEVRST1, BIT(10) },
730 	[RESET_SPI3]		= { CMU_DEVRST1, BIT(11) },
731 	[RESET_I2C0]		= { CMU_DEVRST1, BIT(12) },
732 	[RESET_I2C1]		= { CMU_DEVRST1, BIT(13) },
733 	[RESET_USB3]		= { CMU_DEVRST1, BIT(14) },
734 	[RESET_UART3]		= { CMU_DEVRST1, BIT(15) },
735 	[RESET_UART4]		= { CMU_DEVRST1, BIT(16) },
736 	[RESET_UART5]		= { CMU_DEVRST1, BIT(17) },
737 	[RESET_I2C2]		= { CMU_DEVRST1, BIT(18) },
738 	[RESET_I2C3]		= { CMU_DEVRST1, BIT(19) },
739 	[RESET_ETHERNET]	= { CMU_DEVRST1, BIT(20) },
740 	[RESET_CHIPID]		= { CMU_DEVRST1, BIT(21) },
741 	[RESET_I2C4]		= { CMU_DEVRST1, BIT(22) },
742 	[RESET_I2C5]		= { CMU_DEVRST1, BIT(23) },
743 	[RESET_CPU_SCNT]	= { CMU_DEVRST1, BIT(30) }
744 };
745 
746 static struct owl_clk_desc s900_clk_desc = {
747 	.clks	    = s900_clks,
748 	.num_clks   = ARRAY_SIZE(s900_clks),
749 
750 	.hw_clks    = &s900_hw_clks,
751 
752 	.resets     = s900_resets,
753 	.num_resets = ARRAY_SIZE(s900_resets),
754 };
755 
s900_clk_probe(struct platform_device * pdev)756 static int s900_clk_probe(struct platform_device *pdev)
757 {
758 	struct owl_clk_desc *desc;
759 	struct owl_reset *reset;
760 	int ret;
761 
762 	desc = &s900_clk_desc;
763 	owl_clk_regmap_init(pdev, desc);
764 
765 	/*
766 	 * FIXME: Reset controller registration should be moved to
767 	 * common code, once all SoCs of Owl family supports it.
768 	 */
769 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
770 	if (!reset)
771 		return -ENOMEM;
772 
773 	reset->rcdev.of_node = pdev->dev.of_node;
774 	reset->rcdev.ops = &owl_reset_ops;
775 	reset->rcdev.nr_resets = desc->num_resets;
776 	reset->reset_map = desc->resets;
777 	reset->regmap = desc->regmap;
778 
779 	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
780 	if (ret)
781 		dev_err(&pdev->dev, "Failed to register reset controller\n");
782 
783 	return owl_clk_probe(&pdev->dev, desc->hw_clks);
784 }
785 
786 static const struct of_device_id s900_clk_of_match[] = {
787 	{ .compatible = "actions,s900-cmu", },
788 	{ /* sentinel */ }
789 };
790 
791 static struct platform_driver s900_clk_driver = {
792 	.probe = s900_clk_probe,
793 	.driver = {
794 		.name = "s900-cmu",
795 		.of_match_table = s900_clk_of_match,
796 	},
797 };
798 
s900_clk_init(void)799 static int __init s900_clk_init(void)
800 {
801 	return platform_driver_register(&s900_clk_driver);
802 }
803 core_initcall(s900_clk_init);
804