1 #ifndef TARGET_ARM_TRANSLATE_H 2 #define TARGET_ARM_TRANSLATE_H 3 4 #include "cpu.h" 5 #include "tcg/tcg-op.h" 6 #include "tcg/tcg-op-gvec.h" 7 #include "exec/translator.h" 8 #include "exec/translation-block.h" 9 #include "exec/helper-gen.h" 10 #include "internals.h" 11 #include "cpu-features.h" 12 13 /* internal defines */ 14 15 /* 16 * Save pc_save across a branch, so that we may restore the value from 17 * before the branch at the point the label is emitted. 18 */ 19 typedef struct DisasLabel { 20 TCGLabel *label; 21 target_ulong pc_save; 22 } DisasLabel; 23 24 /* 25 * Emit an exception call out of line. 26 */ 27 typedef struct DisasDelayException { 28 struct DisasDelayException *next; 29 TCGLabel *lab; 30 target_long pc_curr; 31 target_long pc_save; 32 int condexec_mask; 33 int condexec_cond; 34 uint32_t excp; 35 uint32_t syn; 36 uint32_t target_el; 37 } DisasDelayException; 38 39 typedef struct DisasContext { 40 DisasContextBase base; 41 const ARMISARegisters *isar; 42 DisasDelayException *delay_excp_list; 43 44 /* The address of the current instruction being translated. */ 45 target_ulong pc_curr; 46 /* 47 * For CF_PCREL, the full value of cpu_pc is not known 48 * (although the page offset is known). For convenience, the 49 * translation loop uses the full virtual address that triggered 50 * the translation, from base.pc_start through pc_curr. 51 * For efficiency, we do not update cpu_pc for every instruction. 52 * Instead, pc_save has the value of pc_curr at the time of the 53 * last update to cpu_pc, which allows us to compute the addend 54 * needed to bring cpu_pc current: pc_curr - pc_save. 55 * If cpu_pc now contains the destination of an indirect branch, 56 * pc_save contains -1 to indicate that relative updates are no 57 * longer possible. 58 */ 59 target_ulong pc_save; 60 target_ulong page_start; 61 uint32_t insn; 62 /* Nonzero if this instruction has been conditionally skipped. */ 63 int condjmp; 64 /* The label that will be jumped to when the instruction is skipped. */ 65 DisasLabel condlabel; 66 /* Thumb-2 conditional execution bits. */ 67 int condexec_mask; 68 int condexec_cond; 69 /* M-profile ECI/ICI exception-continuable instruction state */ 70 int eci; 71 /* 72 * trans_ functions for insns which are continuable should set this true 73 * after decode (ie after any UNDEF checks) 74 */ 75 bool eci_handled; 76 int sctlr_b; 77 MemOp be_data; 78 #if !defined(CONFIG_USER_ONLY) 79 int user; 80 #endif 81 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ 82 uint8_t tbii; /* TBI1|TBI0 for insns */ 83 uint8_t tbid; /* TBI1|TBI0 for data */ 84 uint8_t tcma; /* TCMA1|TCMA0 for MTE */ 85 bool ns; /* Use non-secure CPREG bank on access */ 86 int fp_excp_el; /* FP exception EL or 0 if enabled */ 87 int sve_excp_el; /* SVE exception EL or 0 if enabled */ 88 int sme_excp_el; /* SME exception EL or 0 if enabled */ 89 int zt0_excp_el; /* ZT0 exception EL or 0 if enabled */ 90 int vl; /* current vector length in bytes */ 91 int svl; /* current streaming vector length in bytes */ 92 int max_svl; /* maximum implemented streaming vector length */ 93 bool vfp_enabled; /* FP enabled via FPSCR.EN */ 94 int vec_len; 95 int vec_stride; 96 bool v7m_handler_mode; 97 bool v8m_secure; /* true if v8M and we're in Secure mode */ 98 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ 99 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ 100 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ 101 bool v7m_lspact; /* FPCCR.LSPACT set */ 102 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI 103 * so that top level loop can generate correct syndrome information. 104 */ 105 uint32_t svc_imm; 106 int current_el; 107 GHashTable *cp_regs; 108 uint64_t features; /* CPU features bits */ 109 bool aarch64; 110 bool thumb; 111 bool lse2; 112 /* 113 * Because unallocated encodings generate different exception syndrome 114 * information from traps due to FP being disabled, we can't do a single 115 * "is fp access disabled" check at a high level in the decode tree. 116 * To help in catching bugs where the access check was forgotten in some 117 * code path, we set this flag when the access check is done, and assert 118 * that it is set at the point where we actually touch the FP regs. 119 * 0: not checked, 120 * 1: checked, access ok 121 * -1: checked, access denied 122 */ 123 int8_t fp_access_checked; 124 int8_t sve_access_checked; 125 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub 126 * single-step support). 127 */ 128 bool ss_active; 129 bool pstate_ss; 130 /* True if the insn just emitted was a load-exclusive instruction 131 * (necessary for syndrome information for single step exceptions), 132 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. 133 */ 134 bool is_ldex; 135 /* True if AccType_UNPRIV should be used for LDTR et al */ 136 bool unpriv; 137 /* True if v8.3-PAuth is active. */ 138 bool pauth_active; 139 /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */ 140 bool ata[2]; 141 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ 142 bool mte_active[2]; 143 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ 144 bool bt; 145 /* True if any CP15 access is trapped by HSTR_EL2 */ 146 bool hstr_active; 147 /* True if memory operations require alignment */ 148 bool align_mem; 149 /* True if PSTATE.IL is set */ 150 bool pstate_il; 151 /* True if PSTATE.SM is set. */ 152 bool pstate_sm; 153 /* True if PSTATE.ZA is set. */ 154 bool pstate_za; 155 /* True if non-streaming insns should raise an SME Streaming exception. */ 156 bool sme_trap_nonstreaming; 157 /* True if the current instruction is non-streaming. */ 158 bool is_nonstreaming; 159 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ 160 bool mve_no_pred; 161 /* True if fine-grained traps are active */ 162 bool fgt_active; 163 /* True if fine-grained trap on SVC is enabled */ 164 bool fgt_svc; 165 /* True if a trap on ERET is enabled (FGT or NV) */ 166 bool trap_eret; 167 /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ 168 bool naa; 169 /* True if HCR_EL2.E2H is set */ 170 bool e2h; 171 /* True if FEAT_NV HCR_EL2.NV is enabled */ 172 bool nv; 173 /* True if NV enabled and HCR_EL2.NV1 is set */ 174 bool nv1; 175 /* True if NV enabled and HCR_EL2.NV2 is set */ 176 bool nv2; 177 /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */ 178 bool nv2_mem_e20; 179 /* True if NV2 enabled and NV2 RAM accesses are big-endian */ 180 bool nv2_mem_be; 181 /* True if FPCR.AH is 1 (alternate floating point handling) */ 182 bool fpcr_ah; 183 /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */ 184 bool fpcr_nep; 185 /* True if GCSEnabled. */ 186 bool gcs_en; 187 /* True if GCSReturnValueCheckEnabled. */ 188 bool gcs_rvcen; 189 /* GCSSTR exception EL or 0 if enabled */ 190 uint8_t gcsstr_el; 191 /* 192 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. 193 * < 0, set by the current instruction. 194 */ 195 int8_t btype; 196 /* A copy of cpu->dcz_blocksize. */ 197 uint8_t dcz_blocksize; 198 /* A copy of cpu->gm_blocksize. */ 199 uint8_t gm_blocksize; 200 /* True if the current insn_start has been updated. */ 201 bool insn_start_updated; 202 /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ 203 uint32_t nv2_redirect_offset; 204 } DisasContext; 205 206 typedef struct DisasCompare { 207 TCGCond cond; 208 TCGv_i32 value; 209 } DisasCompare; 210 211 /* Share the TCG temporaries common between 32 and 64 bit modes. */ 212 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; 213 extern TCGv_i64 cpu_exclusive_addr; 214 extern TCGv_i64 cpu_exclusive_val; 215 216 /* 217 * Constant expanders for the decoders. 218 */ 219 220 static inline int negate(DisasContext *s, int x) 221 { 222 return -x; 223 } 224 225 static inline int plus_1(DisasContext *s, int x) 226 { 227 return x + 1; 228 } 229 230 static inline int plus_2(DisasContext *s, int x) 231 { 232 return x + 2; 233 } 234 235 static inline int plus_8(DisasContext *s, int x) 236 { 237 return x + 8; 238 } 239 240 static inline int plus_12(DisasContext *s, int x) 241 { 242 return x + 12; 243 } 244 245 static inline int times_2(DisasContext *s, int x) 246 { 247 return x * 2; 248 } 249 250 static inline int times_4(DisasContext *s, int x) 251 { 252 return x * 4; 253 } 254 255 static inline int times_8(DisasContext *s, int x) 256 { 257 return x * 8; 258 } 259 260 static inline int times_2_plus_1(DisasContext *s, int x) 261 { 262 return x * 2 + 1; 263 } 264 265 static inline int rsub_64(DisasContext *s, int x) 266 { 267 return 64 - x; 268 } 269 270 static inline int rsub_32(DisasContext *s, int x) 271 { 272 return 32 - x; 273 } 274 275 static inline int rsub_16(DisasContext *s, int x) 276 { 277 return 16 - x; 278 } 279 280 static inline int rsub_8(DisasContext *s, int x) 281 { 282 return 8 - x; 283 } 284 285 static inline int shl_12(DisasContext *s, int x) 286 { 287 return x << 12; 288 } 289 290 static inline int xor_2(DisasContext *s, int x) 291 { 292 return x ^ 2; 293 } 294 295 static inline int neon_3same_fp_size(DisasContext *s, int x) 296 { 297 /* Convert 0==fp32, 1==fp16 into a MO_* value */ 298 return MO_32 - x; 299 } 300 301 static inline int arm_dc_feature(DisasContext *dc, int feature) 302 { 303 return (dc->features & (1ULL << feature)) != 0; 304 } 305 306 static inline int get_mem_index(DisasContext *s) 307 { 308 return arm_to_core_mmu_idx(s->mmu_idx); 309 } 310 311 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) 312 { 313 /* We don't need to save all of the syndrome so we mask and shift 314 * out unneeded bits to help the sleb128 encoder do a better job. 315 */ 316 syn &= ARM_INSN_START_WORD2_MASK; 317 syn >>= ARM_INSN_START_WORD2_SHIFT; 318 319 /* Check for multiple updates. */ 320 assert(!s->insn_start_updated); 321 s->insn_start_updated = true; 322 tcg_set_insn_start_param(s->base.insn_start, 2, syn); 323 } 324 325 static inline int curr_insn_len(DisasContext *s) 326 { 327 return s->base.pc_next - s->pc_curr; 328 } 329 330 /* is_jmp field values */ 331 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 332 /* CPU state was modified dynamically; exit to main loop for interrupts. */ 333 #define DISAS_UPDATE_EXIT DISAS_TARGET_1 334 /* These instructions trap after executing, so the A32/T32 decoder must 335 * defer them until after the conditional execution state has been updated. 336 * WFI also needs special handling when single-stepping. 337 */ 338 #define DISAS_WFI DISAS_TARGET_2 339 #define DISAS_SWI DISAS_TARGET_3 340 /* WFE */ 341 #define DISAS_WFE DISAS_TARGET_4 342 #define DISAS_HVC DISAS_TARGET_5 343 #define DISAS_SMC DISAS_TARGET_6 344 #define DISAS_YIELD DISAS_TARGET_7 345 /* M profile branch which might be an exception return (and so needs 346 * custom end-of-TB code) 347 */ 348 #define DISAS_BX_EXCRET DISAS_TARGET_8 349 /* 350 * For instructions which want an immediate exit to the main loop, as opposed 351 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this 352 * doesn't write the PC on exiting the translation loop so you need to ensure 353 * something (gen_a64_update_pc or runtime helper) has done so before we reach 354 * return from cpu_tb_exec. 355 */ 356 #define DISAS_EXIT DISAS_TARGET_9 357 /* CPU state was modified dynamically; no need to exit, but do not chain. */ 358 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 359 360 #ifdef TARGET_AARCH64 361 void a64_translate_init(void); 362 void gen_a64_update_pc(DisasContext *s, target_long diff); 363 extern const TranslatorOps aarch64_translator_ops; 364 #else 365 static inline void a64_translate_init(void) 366 { 367 } 368 369 static inline void gen_a64_update_pc(DisasContext *s, target_long diff) 370 { 371 } 372 #endif 373 374 void arm_test_cc(DisasCompare *cmp, int cc); 375 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); 376 void arm_gen_test_cc(int cc, TCGLabel *label); 377 MemOp pow2_align(unsigned i); 378 void unallocated_encoding(DisasContext *s); 379 void gen_exception_internal(int excp); 380 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, 381 uint32_t syn, uint32_t target_el); 382 void gen_exception_insn(DisasContext *s, target_long pc_diff, 383 int excp, uint32_t syn); 384 TCGLabel *delay_exception_el(DisasContext *s, int excp, 385 uint32_t syn, uint32_t target_el); 386 TCGLabel *delay_exception(DisasContext *s, int excp, uint32_t syn); 387 void emit_delayed_exceptions(DisasContext *s); 388 389 /* Return state of Alternate Half-precision flag, caller frees result */ 390 static inline TCGv_i32 get_ahp_flag(void) 391 { 392 TCGv_i32 ret = tcg_temp_new_i32(); 393 394 tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr)); 395 tcg_gen_extract_i32(ret, ret, 26, 1); 396 397 return ret; 398 } 399 400 /* Set bits within PSTATE. */ 401 static inline void set_pstate_bits(uint64_t bits) 402 { 403 TCGv_i64 p = tcg_temp_new_i64(); 404 405 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 406 407 tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); 408 tcg_gen_ori_i64(p, p, bits); 409 tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); 410 } 411 412 /* Clear bits within PSTATE. */ 413 static inline void clear_pstate_bits(uint64_t bits) 414 { 415 TCGv_i64 p = tcg_temp_new_i64(); 416 417 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 418 419 tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); 420 tcg_gen_andi_i64(p, p, ~bits); 421 tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); 422 } 423 424 /* If the singlestep state is Active-not-pending, advance to Active-pending. */ 425 static inline void gen_ss_advance(DisasContext *s) 426 { 427 if (s->ss_active) { 428 s->pstate_ss = 0; 429 clear_pstate_bits(PSTATE_SS); 430 } 431 } 432 433 /* Generate an architectural singlestep exception */ 434 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) 435 { 436 /* Fill in the same_el field of the syndrome in the helper. */ 437 uint32_t syn = syn_swstep(false, isv, ex); 438 gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn)); 439 } 440 441 /* 442 * Given a VFP floating point constant encoded into an 8 bit immediate in an 443 * instruction, expand it to the actual constant value of the specified 444 * size, as per the VFPExpandImm() pseudocode in the Arm ARM. 445 */ 446 uint64_t vfp_expand_imm(int size, uint8_t imm8); 447 448 static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s) 449 { 450 tcg_gen_andi_i32(d, s, INT16_MAX); 451 } 452 453 static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s) 454 { 455 tcg_gen_andi_i32(d, s, INT32_MAX); 456 } 457 458 static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s) 459 { 460 tcg_gen_andi_i64(d, s, INT64_MAX); 461 } 462 463 static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s) 464 { 465 tcg_gen_xori_i32(d, s, 1u << 15); 466 } 467 468 static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s) 469 { 470 tcg_gen_xori_i32(d, s, 1u << 31); 471 } 472 473 static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s) 474 { 475 tcg_gen_xori_i64(d, s, 1ull << 63); 476 } 477 478 /* Vector operations shared between ARM and AArch64. */ 479 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 480 uint32_t opr_sz, uint32_t max_sz); 481 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 482 uint32_t opr_sz, uint32_t max_sz); 483 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 484 uint32_t opr_sz, uint32_t max_sz); 485 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 486 uint32_t opr_sz, uint32_t max_sz); 487 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 488 uint32_t opr_sz, uint32_t max_sz); 489 490 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 491 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 492 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 493 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 494 495 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 496 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 497 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 498 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 499 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 500 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 501 void gen_gvec_srshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 502 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 503 void gen_gvec_urshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 504 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 505 void gen_neon_sqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 506 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 507 void gen_neon_uqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 508 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 509 void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 510 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 511 void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 512 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 513 514 void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 515 int64_t c, uint32_t opr_sz, uint32_t max_sz); 516 void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 517 int64_t c, uint32_t opr_sz, uint32_t max_sz); 518 void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 519 int64_t c, uint32_t opr_sz, uint32_t max_sz); 520 521 void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 522 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 523 void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 524 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 525 void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 526 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 527 void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 528 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 529 void gen_gvec_srhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 530 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 531 void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 532 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 533 534 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 535 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 536 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 537 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 538 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 539 540 void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 541 TCGv_i64 a, TCGv_i64 b, MemOp esz); 542 void gen_uqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 543 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 544 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 545 546 void gen_sqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 547 TCGv_i64 a, TCGv_i64 b, MemOp esz); 548 void gen_sqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 549 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 550 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 551 552 void gen_uqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 553 TCGv_i64 a, TCGv_i64 b, MemOp esz); 554 void gen_uqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 555 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 556 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 557 558 void gen_sqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 559 TCGv_i64 a, TCGv_i64 b, MemOp esz); 560 void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 561 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 562 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 563 564 void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 565 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 566 void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 567 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 568 569 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 570 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 571 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 572 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 573 574 void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 575 void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 576 void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 577 void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 578 579 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 580 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 581 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 582 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 583 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 584 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 585 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 586 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 587 588 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 589 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 590 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 591 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 592 593 void gen_gvec_sqdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 594 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 595 void gen_gvec_sqrdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 596 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 597 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 598 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 599 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 600 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 601 602 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 603 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 604 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 605 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 606 607 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 608 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 609 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 610 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 611 612 void gen_gvec_addp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 613 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 614 void gen_gvec_smaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 615 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 616 void gen_gvec_sminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 617 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 618 void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 619 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 620 void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 621 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 622 623 void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 624 uint32_t opr_sz, uint32_t max_sz); 625 void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 626 uint32_t opr_sz, uint32_t max_sz); 627 void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 628 uint32_t opr_sz, uint32_t max_sz); 629 void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 630 uint32_t opr_sz, uint32_t max_sz); 631 void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 632 uint32_t opr_sz, uint32_t max_sz); 633 void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 634 uint32_t opr_sz, uint32_t max_sz); 635 void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 636 uint32_t opr_sz, uint32_t max_sz); 637 638 void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 639 uint32_t opr_sz, uint32_t max_sz); 640 void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 641 uint32_t opr_sz, uint32_t max_sz); 642 void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 643 uint32_t opr_sz, uint32_t max_sz); 644 void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 645 uint32_t opr_sz, uint32_t max_sz); 646 647 /* These exclusively manipulate the sign bit. */ 648 void gen_gvec_fabs(unsigned vece, uint32_t dofs, uint32_t aofs, 649 uint32_t oprsz, uint32_t maxsz); 650 void gen_gvec_fneg(unsigned vece, uint32_t dofs, uint32_t aofs, 651 uint32_t oprsz, uint32_t maxsz); 652 653 void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 654 uint32_t opr_sz, uint32_t max_sz); 655 void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 656 uint32_t opr_sz, uint32_t max_sz); 657 658 /* 659 * Forward to the isar_feature_* tests given a DisasContext pointer. 660 */ 661 #define dc_isar_feature(name, ctx) \ 662 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) 663 664 /* Note that the gvec expanders operate on offsets + sizes. */ 665 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); 666 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, 667 uint32_t, uint32_t); 668 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, 669 uint32_t, uint32_t, uint32_t); 670 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, 671 uint32_t, uint32_t, uint32_t); 672 typedef void GVecGen3FnVar(unsigned, TCGv_ptr, uint32_t, TCGv_ptr, uint32_t, 673 TCGv_ptr, uint32_t, uint32_t, uint32_t); 674 675 /* Function prototype for gen_ functions for calling Neon helpers */ 676 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); 677 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); 678 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); 679 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 680 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, 681 TCGv_i32, TCGv_i32); 682 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); 683 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); 684 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); 685 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); 686 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); 687 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); 688 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); 689 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); 690 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); 691 typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64); 692 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); 693 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 694 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 695 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); 696 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); 697 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); 698 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); 699 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 700 701 /** 702 * arm_tbflags_from_tb: 703 * @tb: the TranslationBlock 704 * 705 * Extract the flag values from @tb. 706 */ 707 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) 708 { 709 return (CPUARMTBFlags){ tb->flags, tb->cs_base }; 710 } 711 712 /** 713 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field 714 * 715 * We have multiple softfloat float_status fields in the Arm CPU state struct 716 * (see the comment in cpu.h for details). Return a TCGv_ptr which has 717 * been set up to point to the requested field in the CPU state struct. 718 */ 719 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) 720 { 721 TCGv_ptr statusptr = tcg_temp_new_ptr(); 722 int offset = offsetof(CPUARMState, vfp.fp_status[flavour]); 723 724 tcg_gen_addi_ptr(statusptr, tcg_env, offset); 725 return statusptr; 726 } 727 728 /** 729 * finalize_memop_atom: 730 * @s: DisasContext 731 * @opc: size+sign+align of the memory operation 732 * @atom: atomicity of the memory operation 733 * 734 * Build the complete MemOp for a memory operation, including alignment, 735 * endianness, and atomicity. 736 * 737 * If (op & MO_AMASK) then the operation already contains the required 738 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally 739 * unaligned operation, e.g. for AccType_NORMAL. 740 * 741 * In the latter case, there are configuration bits that require alignment, 742 * and this is applied here. Note that there is no way to indicate that 743 * no alignment should ever be enforced; this must be handled manually. 744 */ 745 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom) 746 { 747 if (!(opc & MO_AMASK)) { 748 opc |= MO_ALIGN | (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); 749 } 750 return opc | atom | s->be_data; 751 } 752 753 /** 754 * finalize_memop: 755 * @s: DisasContext 756 * @opc: size+sign+align of the memory operation 757 * 758 * Like finalize_memop_atom, but with default atomicity. 759 */ 760 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) 761 { 762 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; 763 return finalize_memop_atom(s, opc, atom); 764 } 765 766 /** 767 * finalize_memop_pair: 768 * @s: DisasContext 769 * @opc: size+sign+align of the memory operation 770 * 771 * Like finalize_memop_atom, but with atomicity for a pair. 772 * C.f. Pseudocode for Mem[], operand ispair. 773 */ 774 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) 775 { 776 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; 777 return finalize_memop_atom(s, opc, atom); 778 } 779 780 /** 781 * finalize_memop_asimd: 782 * @s: DisasContext 783 * @opc: size+sign+align of the memory operation 784 * 785 * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. 786 */ 787 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) 788 { 789 /* 790 * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16, 791 * if IsAligned(8), the first case provides separate atomicity for 792 * the pair of 64-bit accesses. If !IsAligned(8), the middle cases 793 * do not apply, and we're left with the final case of no atomicity. 794 * Thus MO_ATOM_IFALIGN_PAIR. 795 * 796 * For other sizes, normal LSE2 rules apply. 797 */ 798 if ((opc & MO_SIZE) == MO_128) { 799 return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); 800 } 801 return finalize_memop(s, opc); 802 } 803 804 /** 805 * asimd_imm_const: Expand an encoded SIMD constant value 806 * 807 * Expand a SIMD constant value. This is essentially the pseudocode 808 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for 809 * VMVN and VBIC (when cmode < 14 && op == 1). 810 * 811 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; 812 * callers must catch this; we return the 64-bit constant value defined 813 * for AArch64. 814 * 815 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but 816 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; 817 * we produce an immediate constant value of 0 in these cases. 818 */ 819 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); 820 821 /* 822 * gen_disas_label: 823 * Create a label and cache a copy of pc_save. 824 */ 825 static inline DisasLabel gen_disas_label(DisasContext *s) 826 { 827 return (DisasLabel){ 828 .label = gen_new_label(), 829 .pc_save = s->pc_save, 830 }; 831 } 832 833 /* 834 * set_disas_label: 835 * Emit a label and restore the cached copy of pc_save. 836 */ 837 static inline void set_disas_label(DisasContext *s, DisasLabel l) 838 { 839 gen_set_label(l.label); 840 s->pc_save = l.pc_save; 841 } 842 843 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) 844 { 845 TCGv_ptr ret = tcg_temp_new_ptr(); 846 gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key)); 847 return ret; 848 } 849 850 /* 851 * Set and reset rounding mode around another operation. 852 */ 853 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) 854 { 855 TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); 856 TCGv_i32 old = tcg_temp_new_i32(); 857 858 gen_helper_set_rmode(old, new, fpst); 859 return old; 860 } 861 862 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) 863 { 864 gen_helper_set_rmode(old, old, fpst); 865 } 866 867 /* 868 * Helpers for implementing sets of trans_* functions. 869 * Defer the implementation of NAME to FUNC, with optional extra arguments. 870 */ 871 #define TRANS(NAME, FUNC, ...) \ 872 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 873 { return FUNC(s, __VA_ARGS__); } 874 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ 875 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 876 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 877 878 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ 879 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 880 { \ 881 s->is_nonstreaming = true; \ 882 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ 883 } 884 885 #endif /* TARGET_ARM_TRANSLATE_H */ 886