xref: /openbmc/linux/drivers/gpu/drm/i915/i915_pci.c (revision 2c27770a)
1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <drm/drm_color_mgmt.h>
26 #include <drm/drm_drv.h>
27 #include <drm/i915_pciids.h>
28 
29 #include "display/intel_display.h"
30 #include "display/intel_display_driver.h"
31 #include "gt/intel_gt_regs.h"
32 #include "gt/intel_sa_media.h"
33 #include "gem/i915_gem_object_types.h"
34 
35 #include "i915_driver.h"
36 #include "i915_drv.h"
37 #include "i915_pci.h"
38 #include "i915_reg.h"
39 #include "intel_pci_config.h"
40 
41 #define PLATFORM(x) .platform = (x)
42 #define GEN(x) \
43 	.__runtime.graphics.ip.ver = (x), \
44 	.__runtime.media.ip.ver = (x)
45 
46 #define LEGACY_CACHELEVEL \
47 	.cachelevel_to_pat = { \
48 		[I915_CACHE_NONE]   = 0, \
49 		[I915_CACHE_LLC]    = 1, \
50 		[I915_CACHE_L3_LLC] = 2, \
51 		[I915_CACHE_WT]     = 3, \
52 	}
53 
54 #define TGL_CACHELEVEL \
55 	.cachelevel_to_pat = { \
56 		[I915_CACHE_NONE]   = 3, \
57 		[I915_CACHE_LLC]    = 0, \
58 		[I915_CACHE_L3_LLC] = 0, \
59 		[I915_CACHE_WT]     = 2, \
60 	}
61 
62 #define PVC_CACHELEVEL \
63 	.cachelevel_to_pat = { \
64 		[I915_CACHE_NONE]   = 0, \
65 		[I915_CACHE_LLC]    = 3, \
66 		[I915_CACHE_L3_LLC] = 3, \
67 		[I915_CACHE_WT]     = 2, \
68 	}
69 
70 #define MTL_CACHELEVEL \
71 	.cachelevel_to_pat = { \
72 		[I915_CACHE_NONE]   = 2, \
73 		[I915_CACHE_LLC]    = 3, \
74 		[I915_CACHE_L3_LLC] = 3, \
75 		[I915_CACHE_WT]     = 1, \
76 	}
77 
78 /* Keep in gen based order, and chronological order within a gen */
79 
80 #define GEN_DEFAULT_PAGE_SIZES \
81 	.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
82 
83 #define GEN_DEFAULT_REGIONS \
84 	.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
85 
86 #define I830_FEATURES \
87 	GEN(2), \
88 	.is_mobile = 1, \
89 	.gpu_reset_clobbers_display = true, \
90 	.has_3d_pipeline = 1, \
91 	.hws_needs_physical = 1, \
92 	.unfenced_needs_alignment = 1, \
93 	.platform_engine_mask = BIT(RCS0), \
94 	.has_snoop = true, \
95 	.has_coherent_ggtt = false, \
96 	.dma_mask_size = 32, \
97 	.max_pat_index = 3, \
98 	GEN_DEFAULT_PAGE_SIZES, \
99 	GEN_DEFAULT_REGIONS, \
100 	LEGACY_CACHELEVEL
101 
102 #define I845_FEATURES \
103 	GEN(2), \
104 	.has_3d_pipeline = 1, \
105 	.gpu_reset_clobbers_display = true, \
106 	.hws_needs_physical = 1, \
107 	.unfenced_needs_alignment = 1, \
108 	.platform_engine_mask = BIT(RCS0), \
109 	.has_snoop = true, \
110 	.has_coherent_ggtt = false, \
111 	.dma_mask_size = 32, \
112 	.max_pat_index = 3, \
113 	GEN_DEFAULT_PAGE_SIZES, \
114 	GEN_DEFAULT_REGIONS, \
115 	LEGACY_CACHELEVEL
116 
117 static const struct intel_device_info i830_info = {
118 	I830_FEATURES,
119 	PLATFORM(INTEL_I830),
120 };
121 
122 static const struct intel_device_info i845g_info = {
123 	I845_FEATURES,
124 	PLATFORM(INTEL_I845G),
125 };
126 
127 static const struct intel_device_info i85x_info = {
128 	I830_FEATURES,
129 	PLATFORM(INTEL_I85X),
130 };
131 
132 static const struct intel_device_info i865g_info = {
133 	I845_FEATURES,
134 	PLATFORM(INTEL_I865G),
135 };
136 
137 #define GEN3_FEATURES \
138 	GEN(3), \
139 	.gpu_reset_clobbers_display = true, \
140 	.platform_engine_mask = BIT(RCS0), \
141 	.has_3d_pipeline = 1, \
142 	.has_snoop = true, \
143 	.has_coherent_ggtt = true, \
144 	.dma_mask_size = 32, \
145 	.max_pat_index = 3, \
146 	GEN_DEFAULT_PAGE_SIZES, \
147 	GEN_DEFAULT_REGIONS, \
148 	LEGACY_CACHELEVEL
149 
150 static const struct intel_device_info i915g_info = {
151 	GEN3_FEATURES,
152 	PLATFORM(INTEL_I915G),
153 	.has_coherent_ggtt = false,
154 	.hws_needs_physical = 1,
155 	.unfenced_needs_alignment = 1,
156 };
157 
158 static const struct intel_device_info i915gm_info = {
159 	GEN3_FEATURES,
160 	PLATFORM(INTEL_I915GM),
161 	.is_mobile = 1,
162 	.hws_needs_physical = 1,
163 	.unfenced_needs_alignment = 1,
164 };
165 
166 static const struct intel_device_info i945g_info = {
167 	GEN3_FEATURES,
168 	PLATFORM(INTEL_I945G),
169 	.hws_needs_physical = 1,
170 	.unfenced_needs_alignment = 1,
171 };
172 
173 static const struct intel_device_info i945gm_info = {
174 	GEN3_FEATURES,
175 	PLATFORM(INTEL_I945GM),
176 	.is_mobile = 1,
177 	.hws_needs_physical = 1,
178 	.unfenced_needs_alignment = 1,
179 };
180 
181 static const struct intel_device_info g33_info = {
182 	GEN3_FEATURES,
183 	PLATFORM(INTEL_G33),
184 	.dma_mask_size = 36,
185 };
186 
187 static const struct intel_device_info pnv_g_info = {
188 	GEN3_FEATURES,
189 	PLATFORM(INTEL_PINEVIEW),
190 	.dma_mask_size = 36,
191 };
192 
193 static const struct intel_device_info pnv_m_info = {
194 	GEN3_FEATURES,
195 	PLATFORM(INTEL_PINEVIEW),
196 	.is_mobile = 1,
197 	.dma_mask_size = 36,
198 };
199 
200 #define GEN4_FEATURES \
201 	GEN(4), \
202 	.gpu_reset_clobbers_display = true, \
203 	.platform_engine_mask = BIT(RCS0), \
204 	.has_3d_pipeline = 1, \
205 	.has_snoop = true, \
206 	.has_coherent_ggtt = true, \
207 	.dma_mask_size = 36, \
208 	.max_pat_index = 3, \
209 	GEN_DEFAULT_PAGE_SIZES, \
210 	GEN_DEFAULT_REGIONS, \
211 	LEGACY_CACHELEVEL
212 
213 static const struct intel_device_info i965g_info = {
214 	GEN4_FEATURES,
215 	PLATFORM(INTEL_I965G),
216 	.hws_needs_physical = 1,
217 	.has_snoop = false,
218 };
219 
220 static const struct intel_device_info i965gm_info = {
221 	GEN4_FEATURES,
222 	PLATFORM(INTEL_I965GM),
223 	.is_mobile = 1,
224 	.hws_needs_physical = 1,
225 	.has_snoop = false,
226 };
227 
228 static const struct intel_device_info g45_info = {
229 	GEN4_FEATURES,
230 	PLATFORM(INTEL_G45),
231 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
232 	.gpu_reset_clobbers_display = false,
233 };
234 
235 static const struct intel_device_info gm45_info = {
236 	GEN4_FEATURES,
237 	PLATFORM(INTEL_GM45),
238 	.is_mobile = 1,
239 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
240 	.gpu_reset_clobbers_display = false,
241 };
242 
243 #define GEN5_FEATURES \
244 	GEN(5), \
245 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
246 	.has_3d_pipeline = 1, \
247 	.has_snoop = true, \
248 	.has_coherent_ggtt = true, \
249 	/* ilk does support rc6, but we do not implement [power] contexts */ \
250 	.has_rc6 = 0, \
251 	.dma_mask_size = 36, \
252 	.max_pat_index = 3, \
253 	GEN_DEFAULT_PAGE_SIZES, \
254 	GEN_DEFAULT_REGIONS, \
255 	LEGACY_CACHELEVEL
256 
257 static const struct intel_device_info ilk_d_info = {
258 	GEN5_FEATURES,
259 	PLATFORM(INTEL_IRONLAKE),
260 };
261 
262 static const struct intel_device_info ilk_m_info = {
263 	GEN5_FEATURES,
264 	PLATFORM(INTEL_IRONLAKE),
265 	.is_mobile = 1,
266 	.has_rps = true,
267 };
268 
269 #define GEN6_FEATURES \
270 	GEN(6), \
271 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
272 	.has_3d_pipeline = 1, \
273 	.has_coherent_ggtt = true, \
274 	.has_llc = 1, \
275 	.has_rc6 = 1, \
276 	/* snb does support rc6p, but enabling it causes various issues */ \
277 	.has_rc6p = 0, \
278 	.has_rps = true, \
279 	.dma_mask_size = 40, \
280 	.max_pat_index = 3, \
281 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
282 	.__runtime.ppgtt_size = 31, \
283 	GEN_DEFAULT_PAGE_SIZES, \
284 	GEN_DEFAULT_REGIONS, \
285 	LEGACY_CACHELEVEL
286 
287 #define SNB_D_PLATFORM \
288 	GEN6_FEATURES, \
289 	PLATFORM(INTEL_SANDYBRIDGE)
290 
291 static const struct intel_device_info snb_d_gt1_info = {
292 	SNB_D_PLATFORM,
293 	.gt = 1,
294 };
295 
296 static const struct intel_device_info snb_d_gt2_info = {
297 	SNB_D_PLATFORM,
298 	.gt = 2,
299 };
300 
301 #define SNB_M_PLATFORM \
302 	GEN6_FEATURES, \
303 	PLATFORM(INTEL_SANDYBRIDGE), \
304 	.is_mobile = 1
305 
306 
307 static const struct intel_device_info snb_m_gt1_info = {
308 	SNB_M_PLATFORM,
309 	.gt = 1,
310 };
311 
312 static const struct intel_device_info snb_m_gt2_info = {
313 	SNB_M_PLATFORM,
314 	.gt = 2,
315 };
316 
317 #define GEN7_FEATURES  \
318 	GEN(7), \
319 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
320 	.has_3d_pipeline = 1, \
321 	.has_coherent_ggtt = true, \
322 	.has_llc = 1, \
323 	.has_rc6 = 1, \
324 	.has_rc6p = 1, \
325 	.has_reset_engine = true, \
326 	.has_rps = true, \
327 	.dma_mask_size = 40, \
328 	.max_pat_index = 3, \
329 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
330 	.__runtime.ppgtt_size = 31, \
331 	GEN_DEFAULT_PAGE_SIZES, \
332 	GEN_DEFAULT_REGIONS, \
333 	LEGACY_CACHELEVEL
334 
335 #define IVB_D_PLATFORM \
336 	GEN7_FEATURES, \
337 	PLATFORM(INTEL_IVYBRIDGE), \
338 	.has_l3_dpf = 1
339 
340 static const struct intel_device_info ivb_d_gt1_info = {
341 	IVB_D_PLATFORM,
342 	.gt = 1,
343 };
344 
345 static const struct intel_device_info ivb_d_gt2_info = {
346 	IVB_D_PLATFORM,
347 	.gt = 2,
348 };
349 
350 #define IVB_M_PLATFORM \
351 	GEN7_FEATURES, \
352 	PLATFORM(INTEL_IVYBRIDGE), \
353 	.is_mobile = 1, \
354 	.has_l3_dpf = 1
355 
356 static const struct intel_device_info ivb_m_gt1_info = {
357 	IVB_M_PLATFORM,
358 	.gt = 1,
359 };
360 
361 static const struct intel_device_info ivb_m_gt2_info = {
362 	IVB_M_PLATFORM,
363 	.gt = 2,
364 };
365 
366 static const struct intel_device_info ivb_q_info = {
367 	GEN7_FEATURES,
368 	PLATFORM(INTEL_IVYBRIDGE),
369 	.gt = 2,
370 	.has_l3_dpf = 1,
371 };
372 
373 static const struct intel_device_info vlv_info = {
374 	PLATFORM(INTEL_VALLEYVIEW),
375 	GEN(7),
376 	.is_lp = 1,
377 	.has_runtime_pm = 1,
378 	.has_rc6 = 1,
379 	.has_reset_engine = true,
380 	.has_rps = true,
381 	.dma_mask_size = 40,
382 	.max_pat_index = 3,
383 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
384 	.__runtime.ppgtt_size = 31,
385 	.has_snoop = true,
386 	.has_coherent_ggtt = false,
387 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
388 	GEN_DEFAULT_PAGE_SIZES,
389 	GEN_DEFAULT_REGIONS,
390 	LEGACY_CACHELEVEL,
391 };
392 
393 #define G75_FEATURES  \
394 	GEN7_FEATURES, \
395 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
396 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
397 	.has_runtime_pm = 1
398 
399 #define HSW_PLATFORM \
400 	G75_FEATURES, \
401 	PLATFORM(INTEL_HASWELL), \
402 	.has_l3_dpf = 1
403 
404 static const struct intel_device_info hsw_gt1_info = {
405 	HSW_PLATFORM,
406 	.gt = 1,
407 };
408 
409 static const struct intel_device_info hsw_gt2_info = {
410 	HSW_PLATFORM,
411 	.gt = 2,
412 };
413 
414 static const struct intel_device_info hsw_gt3_info = {
415 	HSW_PLATFORM,
416 	.gt = 3,
417 };
418 
419 #define GEN8_FEATURES \
420 	G75_FEATURES, \
421 	GEN(8), \
422 	.has_logical_ring_contexts = 1, \
423 	.dma_mask_size = 39, \
424 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
425 	.__runtime.ppgtt_size = 48, \
426 	.has_64bit_reloc = 1
427 
428 #define BDW_PLATFORM \
429 	GEN8_FEATURES, \
430 	PLATFORM(INTEL_BROADWELL)
431 
432 static const struct intel_device_info bdw_gt1_info = {
433 	BDW_PLATFORM,
434 	.gt = 1,
435 };
436 
437 static const struct intel_device_info bdw_gt2_info = {
438 	BDW_PLATFORM,
439 	.gt = 2,
440 };
441 
442 static const struct intel_device_info bdw_rsvd_info = {
443 	BDW_PLATFORM,
444 	.gt = 3,
445 	/* According to the device ID those devices are GT3, they were
446 	 * previously treated as not GT3, keep it like that.
447 	 */
448 };
449 
450 static const struct intel_device_info bdw_gt3_info = {
451 	BDW_PLATFORM,
452 	.gt = 3,
453 	.platform_engine_mask =
454 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
455 };
456 
457 static const struct intel_device_info chv_info = {
458 	PLATFORM(INTEL_CHERRYVIEW),
459 	GEN(8),
460 	.is_lp = 1,
461 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
462 	.has_64bit_reloc = 1,
463 	.has_runtime_pm = 1,
464 	.has_rc6 = 1,
465 	.has_rps = true,
466 	.has_logical_ring_contexts = 1,
467 	.dma_mask_size = 39,
468 	.max_pat_index = 3,
469 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
470 	.__runtime.ppgtt_size = 32,
471 	.has_reset_engine = 1,
472 	.has_snoop = true,
473 	.has_coherent_ggtt = false,
474 	GEN_DEFAULT_PAGE_SIZES,
475 	GEN_DEFAULT_REGIONS,
476 	LEGACY_CACHELEVEL,
477 };
478 
479 #define GEN9_DEFAULT_PAGE_SIZES \
480 	.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
481 		I915_GTT_PAGE_SIZE_64K
482 
483 #define GEN9_FEATURES \
484 	GEN8_FEATURES, \
485 	GEN(9), \
486 	GEN9_DEFAULT_PAGE_SIZES, \
487 	.has_gt_uc = 1
488 
489 #define SKL_PLATFORM \
490 	GEN9_FEATURES, \
491 	PLATFORM(INTEL_SKYLAKE)
492 
493 static const struct intel_device_info skl_gt1_info = {
494 	SKL_PLATFORM,
495 	.gt = 1,
496 };
497 
498 static const struct intel_device_info skl_gt2_info = {
499 	SKL_PLATFORM,
500 	.gt = 2,
501 };
502 
503 #define SKL_GT3_PLUS_PLATFORM \
504 	SKL_PLATFORM, \
505 	.platform_engine_mask = \
506 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
507 
508 
509 static const struct intel_device_info skl_gt3_info = {
510 	SKL_GT3_PLUS_PLATFORM,
511 	.gt = 3,
512 };
513 
514 static const struct intel_device_info skl_gt4_info = {
515 	SKL_GT3_PLUS_PLATFORM,
516 	.gt = 4,
517 };
518 
519 #define GEN9_LP_FEATURES \
520 	GEN(9), \
521 	.is_lp = 1, \
522 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
523 	.has_3d_pipeline = 1, \
524 	.has_64bit_reloc = 1, \
525 	.has_runtime_pm = 1, \
526 	.has_rc6 = 1, \
527 	.has_rps = true, \
528 	.has_logical_ring_contexts = 1, \
529 	.has_gt_uc = 1, \
530 	.dma_mask_size = 39, \
531 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
532 	.__runtime.ppgtt_size = 48, \
533 	.has_reset_engine = 1, \
534 	.has_snoop = true, \
535 	.has_coherent_ggtt = false, \
536 	.max_pat_index = 3, \
537 	GEN9_DEFAULT_PAGE_SIZES, \
538 	GEN_DEFAULT_REGIONS, \
539 	LEGACY_CACHELEVEL
540 
541 static const struct intel_device_info bxt_info = {
542 	GEN9_LP_FEATURES,
543 	PLATFORM(INTEL_BROXTON),
544 };
545 
546 static const struct intel_device_info glk_info = {
547 	GEN9_LP_FEATURES,
548 	PLATFORM(INTEL_GEMINILAKE),
549 };
550 
551 #define KBL_PLATFORM \
552 	GEN9_FEATURES, \
553 	PLATFORM(INTEL_KABYLAKE)
554 
555 static const struct intel_device_info kbl_gt1_info = {
556 	KBL_PLATFORM,
557 	.gt = 1,
558 };
559 
560 static const struct intel_device_info kbl_gt2_info = {
561 	KBL_PLATFORM,
562 	.gt = 2,
563 };
564 
565 static const struct intel_device_info kbl_gt3_info = {
566 	KBL_PLATFORM,
567 	.gt = 3,
568 	.platform_engine_mask =
569 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
570 };
571 
572 #define CFL_PLATFORM \
573 	GEN9_FEATURES, \
574 	PLATFORM(INTEL_COFFEELAKE)
575 
576 static const struct intel_device_info cfl_gt1_info = {
577 	CFL_PLATFORM,
578 	.gt = 1,
579 };
580 
581 static const struct intel_device_info cfl_gt2_info = {
582 	CFL_PLATFORM,
583 	.gt = 2,
584 };
585 
586 static const struct intel_device_info cfl_gt3_info = {
587 	CFL_PLATFORM,
588 	.gt = 3,
589 	.platform_engine_mask =
590 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
591 };
592 
593 #define CML_PLATFORM \
594 	GEN9_FEATURES, \
595 	PLATFORM(INTEL_COMETLAKE)
596 
597 static const struct intel_device_info cml_gt1_info = {
598 	CML_PLATFORM,
599 	.gt = 1,
600 };
601 
602 static const struct intel_device_info cml_gt2_info = {
603 	CML_PLATFORM,
604 	.gt = 2,
605 };
606 
607 #define GEN11_DEFAULT_PAGE_SIZES \
608 	.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
609 		I915_GTT_PAGE_SIZE_64K |		\
610 		I915_GTT_PAGE_SIZE_2M
611 
612 #define GEN11_FEATURES \
613 	GEN9_FEATURES, \
614 	GEN11_DEFAULT_PAGE_SIZES, \
615 	GEN(11), \
616 	.has_coherent_ggtt = false, \
617 	.has_logical_ring_elsq = 1
618 
619 static const struct intel_device_info icl_info = {
620 	GEN11_FEATURES,
621 	PLATFORM(INTEL_ICELAKE),
622 	.platform_engine_mask =
623 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
624 };
625 
626 static const struct intel_device_info ehl_info = {
627 	GEN11_FEATURES,
628 	PLATFORM(INTEL_ELKHARTLAKE),
629 	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
630 	.__runtime.ppgtt_size = 36,
631 };
632 
633 static const struct intel_device_info jsl_info = {
634 	GEN11_FEATURES,
635 	PLATFORM(INTEL_JASPERLAKE),
636 	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
637 	.__runtime.ppgtt_size = 36,
638 };
639 
640 #define GEN12_FEATURES \
641 	GEN11_FEATURES, \
642 	GEN(12), \
643 	TGL_CACHELEVEL, \
644 	.has_global_mocs = 1, \
645 	.has_pxp = 1, \
646 	.max_pat_index = 3
647 
648 static const struct intel_device_info tgl_info = {
649 	GEN12_FEATURES,
650 	PLATFORM(INTEL_TIGERLAKE),
651 	.platform_engine_mask =
652 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
653 };
654 
655 static const struct intel_device_info rkl_info = {
656 	GEN12_FEATURES,
657 	PLATFORM(INTEL_ROCKETLAKE),
658 	.platform_engine_mask =
659 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
660 };
661 
662 #define DGFX_FEATURES \
663 	.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
664 	.has_llc = 0, \
665 	.has_pxp = 0, \
666 	.has_snoop = 1, \
667 	.is_dgfx = 1, \
668 	.has_heci_gscfi = 1
669 
670 static const struct intel_device_info dg1_info = {
671 	GEN12_FEATURES,
672 	DGFX_FEATURES,
673 	.__runtime.graphics.ip.rel = 10,
674 	PLATFORM(INTEL_DG1),
675 	.require_force_probe = 1,
676 	.platform_engine_mask =
677 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
678 		BIT(VCS0) | BIT(VCS2),
679 	/* Wa_16011227922 */
680 	.__runtime.ppgtt_size = 47,
681 };
682 
683 static const struct intel_device_info adl_s_info = {
684 	GEN12_FEATURES,
685 	PLATFORM(INTEL_ALDERLAKE_S),
686 	.platform_engine_mask =
687 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
688 	.dma_mask_size = 39,
689 };
690 
691 static const struct intel_device_info adl_p_info = {
692 	GEN12_FEATURES,
693 	PLATFORM(INTEL_ALDERLAKE_P),
694 	.platform_engine_mask =
695 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
696 	.__runtime.ppgtt_size = 48,
697 	.dma_mask_size = 39,
698 };
699 
700 #undef GEN
701 
702 #define XE_HP_PAGE_SIZES \
703 	.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
704 		I915_GTT_PAGE_SIZE_64K |		\
705 		I915_GTT_PAGE_SIZE_2M
706 
707 #define XE_HP_FEATURES \
708 	.__runtime.graphics.ip.ver = 12, \
709 	.__runtime.graphics.ip.rel = 50, \
710 	XE_HP_PAGE_SIZES, \
711 	TGL_CACHELEVEL, \
712 	.dma_mask_size = 46, \
713 	.has_3d_pipeline = 1, \
714 	.has_64bit_reloc = 1, \
715 	.has_flat_ccs = 1, \
716 	.has_4tile = 1, \
717 	.has_global_mocs = 1, \
718 	.has_gt_uc = 1, \
719 	.has_llc = 1, \
720 	.has_logical_ring_contexts = 1, \
721 	.has_logical_ring_elsq = 1, \
722 	.has_mslice_steering = 1, \
723 	.has_oa_bpc_reporting = 1, \
724 	.has_oa_slice_contrib_limits = 1, \
725 	.has_oam = 1, \
726 	.has_rc6 = 1, \
727 	.has_reset_engine = 1, \
728 	.has_rps = 1, \
729 	.has_runtime_pm = 1, \
730 	.max_pat_index = 3, \
731 	.__runtime.ppgtt_size = 48, \
732 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL
733 
734 #define XE_HPM_FEATURES \
735 	.__runtime.media.ip.ver = 12, \
736 	.__runtime.media.ip.rel = 50
737 
738 __maybe_unused
739 static const struct intel_device_info xehpsdv_info = {
740 	XE_HP_FEATURES,
741 	XE_HPM_FEATURES,
742 	DGFX_FEATURES,
743 	PLATFORM(INTEL_XEHPSDV),
744 	.has_64k_pages = 1,
745 	.has_media_ratio_mode = 1,
746 	.platform_engine_mask =
747 		BIT(RCS0) | BIT(BCS0) |
748 		BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
749 		BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
750 		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
751 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
752 	.require_force_probe = 1,
753 };
754 
755 #define DG2_FEATURES \
756 	XE_HP_FEATURES, \
757 	XE_HPM_FEATURES, \
758 	DGFX_FEATURES, \
759 	.__runtime.graphics.ip.rel = 55, \
760 	.__runtime.media.ip.rel = 55, \
761 	PLATFORM(INTEL_DG2), \
762 	.has_64k_pages = 1, \
763 	.has_guc_deprivilege = 1, \
764 	.has_heci_pxp = 1, \
765 	.has_media_ratio_mode = 1, \
766 	.platform_engine_mask = \
767 		BIT(RCS0) | BIT(BCS0) | \
768 		BIT(VECS0) | BIT(VECS1) | \
769 		BIT(VCS0) | BIT(VCS2) | \
770 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
771 
772 static const struct intel_device_info dg2_info = {
773 	DG2_FEATURES,
774 };
775 
776 static const struct intel_device_info ats_m_info = {
777 	DG2_FEATURES,
778 	.require_force_probe = 1,
779 	.tuning_thread_rr_after_dep = 1,
780 };
781 
782 #define XE_HPC_FEATURES \
783 	XE_HP_FEATURES, \
784 	.dma_mask_size = 52, \
785 	.has_3d_pipeline = 0, \
786 	.has_guc_deprivilege = 1, \
787 	.has_l3_ccs_read = 1, \
788 	.has_mslice_steering = 0, \
789 	.has_one_eu_per_fuse_bit = 1
790 
791 __maybe_unused
792 static const struct intel_device_info pvc_info = {
793 	XE_HPC_FEATURES,
794 	XE_HPM_FEATURES,
795 	DGFX_FEATURES,
796 	.__runtime.graphics.ip.rel = 60,
797 	.__runtime.media.ip.rel = 60,
798 	PLATFORM(INTEL_PONTEVECCHIO),
799 	.has_flat_ccs = 0,
800 	.max_pat_index = 7,
801 	.platform_engine_mask =
802 		BIT(BCS0) |
803 		BIT(VCS0) |
804 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
805 	.require_force_probe = 1,
806 	PVC_CACHELEVEL,
807 };
808 
809 static const struct intel_gt_definition xelpmp_extra_gt[] = {
810 	{
811 		.type = GT_MEDIA,
812 		.name = "Standalone Media GT",
813 		.gsi_offset = MTL_MEDIA_GSI_BASE,
814 		.engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),
815 	},
816 	{}
817 };
818 
819 static const struct intel_device_info mtl_info = {
820 	XE_HP_FEATURES,
821 	/*
822 	 * Real graphics IP version will be obtained from hardware GMD_ID
823 	 * register.  Value provided here is just for sanity checking.
824 	 */
825 	.__runtime.graphics.ip.ver = 12,
826 	.__runtime.graphics.ip.rel = 70,
827 	.__runtime.media.ip.ver = 13,
828 	PLATFORM(INTEL_METEORLAKE),
829 	.extra_gt_list = xelpmp_extra_gt,
830 	.has_flat_ccs = 0,
831 	.has_gmd_id = 1,
832 	.has_guc_deprivilege = 1,
833 	.has_llc = 0,
834 	.has_mslice_steering = 0,
835 	.has_snoop = 1,
836 	.max_pat_index = 4,
837 	.has_pxp = 1,
838 	.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
839 	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
840 	.require_force_probe = 1,
841 	MTL_CACHELEVEL,
842 };
843 
844 #undef PLATFORM
845 
846 /*
847  * Make sure any device matches here are from most specific to most
848  * general.  For example, since the Quanta match is based on the subsystem
849  * and subvendor IDs, we need it to come before the more general IVB
850  * PCI ID matches, otherwise we'll use the wrong info struct above.
851  */
852 static const struct pci_device_id pciidlist[] = {
853 	INTEL_I830_IDS(&i830_info),
854 	INTEL_I845G_IDS(&i845g_info),
855 	INTEL_I85X_IDS(&i85x_info),
856 	INTEL_I865G_IDS(&i865g_info),
857 	INTEL_I915G_IDS(&i915g_info),
858 	INTEL_I915GM_IDS(&i915gm_info),
859 	INTEL_I945G_IDS(&i945g_info),
860 	INTEL_I945GM_IDS(&i945gm_info),
861 	INTEL_I965G_IDS(&i965g_info),
862 	INTEL_G33_IDS(&g33_info),
863 	INTEL_I965GM_IDS(&i965gm_info),
864 	INTEL_GM45_IDS(&gm45_info),
865 	INTEL_G45_IDS(&g45_info),
866 	INTEL_PINEVIEW_G_IDS(&pnv_g_info),
867 	INTEL_PINEVIEW_M_IDS(&pnv_m_info),
868 	INTEL_IRONLAKE_D_IDS(&ilk_d_info),
869 	INTEL_IRONLAKE_M_IDS(&ilk_m_info),
870 	INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
871 	INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
872 	INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
873 	INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
874 	INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
875 	INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
876 	INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
877 	INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
878 	INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
879 	INTEL_HSW_GT1_IDS(&hsw_gt1_info),
880 	INTEL_HSW_GT2_IDS(&hsw_gt2_info),
881 	INTEL_HSW_GT3_IDS(&hsw_gt3_info),
882 	INTEL_VLV_IDS(&vlv_info),
883 	INTEL_BDW_GT1_IDS(&bdw_gt1_info),
884 	INTEL_BDW_GT2_IDS(&bdw_gt2_info),
885 	INTEL_BDW_GT3_IDS(&bdw_gt3_info),
886 	INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
887 	INTEL_CHV_IDS(&chv_info),
888 	INTEL_SKL_GT1_IDS(&skl_gt1_info),
889 	INTEL_SKL_GT2_IDS(&skl_gt2_info),
890 	INTEL_SKL_GT3_IDS(&skl_gt3_info),
891 	INTEL_SKL_GT4_IDS(&skl_gt4_info),
892 	INTEL_BXT_IDS(&bxt_info),
893 	INTEL_GLK_IDS(&glk_info),
894 	INTEL_KBL_GT1_IDS(&kbl_gt1_info),
895 	INTEL_KBL_GT2_IDS(&kbl_gt2_info),
896 	INTEL_KBL_GT3_IDS(&kbl_gt3_info),
897 	INTEL_KBL_GT4_IDS(&kbl_gt3_info),
898 	INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
899 	INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
900 	INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
901 	INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
902 	INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
903 	INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
904 	INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
905 	INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
906 	INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
907 	INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
908 	INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
909 	INTEL_CML_GT1_IDS(&cml_gt1_info),
910 	INTEL_CML_GT2_IDS(&cml_gt2_info),
911 	INTEL_CML_U_GT1_IDS(&cml_gt1_info),
912 	INTEL_CML_U_GT2_IDS(&cml_gt2_info),
913 	INTEL_ICL_11_IDS(&icl_info),
914 	INTEL_EHL_IDS(&ehl_info),
915 	INTEL_JSL_IDS(&jsl_info),
916 	INTEL_TGL_12_IDS(&tgl_info),
917 	INTEL_RKL_IDS(&rkl_info),
918 	INTEL_ADLS_IDS(&adl_s_info),
919 	INTEL_ADLP_IDS(&adl_p_info),
920 	INTEL_ADLN_IDS(&adl_p_info),
921 	INTEL_DG1_IDS(&dg1_info),
922 	INTEL_RPLS_IDS(&adl_s_info),
923 	INTEL_RPLP_IDS(&adl_p_info),
924 	INTEL_DG2_IDS(&dg2_info),
925 	INTEL_ATS_M_IDS(&ats_m_info),
926 	INTEL_MTL_IDS(&mtl_info),
927 	{0, 0, 0}
928 };
929 MODULE_DEVICE_TABLE(pci, pciidlist);
930 
i915_pci_remove(struct pci_dev * pdev)931 static void i915_pci_remove(struct pci_dev *pdev)
932 {
933 	struct drm_i915_private *i915;
934 
935 	i915 = pci_get_drvdata(pdev);
936 	if (!i915) /* driver load aborted, nothing to cleanup */
937 		return;
938 
939 	i915_driver_remove(i915);
940 	pci_set_drvdata(pdev, NULL);
941 }
942 
943 /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)944 static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
945 {
946 	char *s, *p, *tok;
947 	bool ret;
948 
949 	if (!devices || !*devices)
950 		return false;
951 
952 	/* match everything */
953 	if (negative && strcmp(devices, "!*") == 0)
954 		return true;
955 	if (!negative && strcmp(devices, "*") == 0)
956 		return true;
957 
958 	s = kstrdup(devices, GFP_KERNEL);
959 	if (!s)
960 		return false;
961 
962 	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
963 		u16 val;
964 
965 		if (negative && tok[0] == '!')
966 			tok++;
967 		else if ((negative && tok[0] != '!') ||
968 			 (!negative && tok[0] == '!'))
969 			continue;
970 
971 		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
972 			ret = true;
973 			break;
974 		}
975 	}
976 
977 	kfree(s);
978 
979 	return ret;
980 }
981 
id_forced(u16 device_id)982 static bool id_forced(u16 device_id)
983 {
984 	return device_id_in_list(device_id, i915_modparams.force_probe, false);
985 }
986 
id_blocked(u16 device_id)987 static bool id_blocked(u16 device_id)
988 {
989 	return device_id_in_list(device_id, i915_modparams.force_probe, true);
990 }
991 
i915_pci_resource_valid(struct pci_dev * pdev,int bar)992 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
993 {
994 	if (!pci_resource_flags(pdev, bar))
995 		return false;
996 
997 	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
998 		return false;
999 
1000 	if (!pci_resource_len(pdev, bar))
1001 		return false;
1002 
1003 	return true;
1004 }
1005 
intel_mmio_bar_valid(struct pci_dev * pdev,struct intel_device_info * intel_info)1006 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
1007 {
1008 	return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver));
1009 }
1010 
i915_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1011 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1012 {
1013 	struct intel_device_info *intel_info =
1014 		(struct intel_device_info *) ent->driver_data;
1015 	int err;
1016 
1017 	if (intel_info->require_force_probe && !id_forced(pdev->device)) {
1018 		dev_info(&pdev->dev,
1019 			 "Your graphics device %04x is not properly supported by i915 in this\n"
1020 			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1021 			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1022 			 "or (recommended) check for kernel updates.\n",
1023 			 pdev->device, pdev->device, pdev->device);
1024 		return -ENODEV;
1025 	}
1026 
1027 	if (id_blocked(pdev->device)) {
1028 		dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n",
1029 			 pdev->device);
1030 		return -ENODEV;
1031 	}
1032 
1033 	if (intel_info->require_force_probe) {
1034 		dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n",
1035 			 pdev->device);
1036 		add_taint(TAINT_USER, LOCKDEP_STILL_OK);
1037 	}
1038 
1039 	/* Only bind to function 0 of the device. Early generations
1040 	 * used function 1 as a placeholder for multi-head. This causes
1041 	 * us confusion instead, especially on the systems where both
1042 	 * functions have the same PCI-ID!
1043 	 */
1044 	if (PCI_FUNC(pdev->devfn))
1045 		return -ENODEV;
1046 
1047 	if (!intel_mmio_bar_valid(pdev, intel_info))
1048 		return -ENXIO;
1049 
1050 	/* Detect if we need to wait for other drivers early on */
1051 	if (intel_display_driver_probe_defer(pdev))
1052 		return -EPROBE_DEFER;
1053 
1054 	err = i915_driver_probe(pdev, ent);
1055 	if (err)
1056 		return err;
1057 
1058 	if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1059 		i915_pci_remove(pdev);
1060 		return -ENODEV;
1061 	}
1062 
1063 	err = i915_live_selftests(pdev);
1064 	if (err) {
1065 		i915_pci_remove(pdev);
1066 		return err > 0 ? -ENOTTY : err;
1067 	}
1068 
1069 	err = i915_perf_selftests(pdev);
1070 	if (err) {
1071 		i915_pci_remove(pdev);
1072 		return err > 0 ? -ENOTTY : err;
1073 	}
1074 
1075 	return 0;
1076 }
1077 
i915_pci_shutdown(struct pci_dev * pdev)1078 static void i915_pci_shutdown(struct pci_dev *pdev)
1079 {
1080 	struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1081 
1082 	i915_driver_shutdown(i915);
1083 }
1084 
1085 static struct pci_driver i915_pci_driver = {
1086 	.name = DRIVER_NAME,
1087 	.id_table = pciidlist,
1088 	.probe = i915_pci_probe,
1089 	.remove = i915_pci_remove,
1090 	.shutdown = i915_pci_shutdown,
1091 	.driver.pm = &i915_pm_ops,
1092 };
1093 
i915_pci_register_driver(void)1094 int i915_pci_register_driver(void)
1095 {
1096 	return pci_register_driver(&i915_pci_driver);
1097 }
1098 
i915_pci_unregister_driver(void)1099 void i915_pci_unregister_driver(void)
1100 {
1101 	pci_unregister_driver(&i915_pci_driver);
1102 }
1103