1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET MDIO routines
4 *
5 * Copyright (c) 2014-2024 Broadcom
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
25
26 #include "bcmgenet.h"
27
bcmgenet_mac_config(struct net_device * dev)28 static void bcmgenet_mac_config(struct net_device *dev)
29 {
30 struct bcmgenet_priv *priv = netdev_priv(dev);
31 struct phy_device *phydev = dev->phydev;
32 u32 reg, cmd_bits = 0;
33
34 /* speed */
35 if (phydev->speed == SPEED_1000)
36 cmd_bits = CMD_SPEED_1000;
37 else if (phydev->speed == SPEED_100)
38 cmd_bits = CMD_SPEED_100;
39 else
40 cmd_bits = CMD_SPEED_10;
41 cmd_bits <<= CMD_SPEED_SHIFT;
42
43 /* duplex */
44 if (phydev->duplex != DUPLEX_FULL) {
45 cmd_bits |= CMD_HD_EN |
46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
47 } else {
48 /* pause capability defaults to Symmetric */
49 if (priv->autoneg_pause) {
50 bool tx_pause = 0, rx_pause = 0;
51
52 if (phydev->autoneg)
53 phy_get_pause(phydev, &tx_pause, &rx_pause);
54
55 if (!tx_pause)
56 cmd_bits |= CMD_TX_PAUSE_IGNORE;
57 if (!rx_pause)
58 cmd_bits |= CMD_RX_PAUSE_IGNORE;
59 }
60
61 /* Manual override */
62 if (!priv->rx_pause)
63 cmd_bits |= CMD_RX_PAUSE_IGNORE;
64 if (!priv->tx_pause)
65 cmd_bits |= CMD_TX_PAUSE_IGNORE;
66 }
67
68 /* Program UMAC and RGMII block based on established
69 * link speed, duplex, and pause. The speed set in
70 * umac->cmd tell RGMII block which clock to use for
71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
72 * Receive clock is provided by the PHY.
73 */
74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
75 reg |= RGMII_LINK;
76 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
77
78 spin_lock_bh(&priv->reg_lock);
79 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
80 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
81 CMD_HD_EN |
82 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
83 reg |= cmd_bits;
84 if (reg & CMD_SW_RESET) {
85 reg &= ~CMD_SW_RESET;
86 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
87 udelay(2);
88 reg |= CMD_TX_EN | CMD_RX_EN;
89 }
90 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
91 spin_unlock_bh(&priv->reg_lock);
92
93 priv->eee.eee_active = phy_init_eee(phydev, 0) >= 0;
94 bcmgenet_eee_enable_set(dev,
95 priv->eee.eee_enabled && priv->eee.eee_active,
96 priv->eee.tx_lpi_enabled);
97 }
98
99 /* setup netdev link state when PHY link status change and
100 * update UMAC and RGMII block when link up
101 */
bcmgenet_mii_setup(struct net_device * dev)102 void bcmgenet_mii_setup(struct net_device *dev)
103 {
104 struct bcmgenet_priv *priv = netdev_priv(dev);
105 struct phy_device *phydev = dev->phydev;
106 u32 reg;
107
108 if (phydev->link) {
109 bcmgenet_mac_config(dev);
110 } else {
111 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
112 reg &= ~RGMII_LINK;
113 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
114 }
115
116 phy_print_status(phydev);
117 }
118
119
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)120 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
121 struct fixed_phy_status *status)
122 {
123 struct bcmgenet_priv *priv;
124 u32 reg;
125
126 if (dev && dev->phydev && status) {
127 priv = netdev_priv(dev);
128 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
129 status->link = !!(reg & MODE_LINK_STATUS);
130 }
131
132 return 0;
133 }
134
bcmgenet_phy_pause_set(struct net_device * dev,bool rx,bool tx)135 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx)
136 {
137 struct phy_device *phydev = dev->phydev;
138
139 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx);
140 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising,
141 rx | tx);
142 phy_start_aneg(phydev);
143
144 mutex_lock(&phydev->lock);
145 if (phydev->link)
146 bcmgenet_mac_config(dev);
147 mutex_unlock(&phydev->lock);
148 }
149
bcmgenet_phy_power_set(struct net_device * dev,bool enable)150 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
151 {
152 struct bcmgenet_priv *priv = netdev_priv(dev);
153 u32 reg = 0;
154
155 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
156 if (GENET_IS_V4(priv) || priv->ephy_16nm) {
157 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
158 if (enable) {
159 reg &= ~EXT_CK25_DIS;
160 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
161 mdelay(1);
162
163 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
164 EXT_CFG_IDDQ_GLOBAL_PWR);
165 reg |= EXT_GPHY_RESET;
166 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
167 mdelay(1);
168
169 reg &= ~EXT_GPHY_RESET;
170 } else {
171 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
172 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR;
173 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
174 mdelay(1);
175 reg |= EXT_CK25_DIS;
176 }
177 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
178 udelay(60);
179 } else {
180 mdelay(1);
181 }
182 }
183
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)184 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
185 {
186 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
187 fixed_phy_set_link_update(priv->dev->phydev,
188 bcmgenet_fixed_phy_link_update);
189 }
190
bcmgenet_mii_config(struct net_device * dev,bool init)191 int bcmgenet_mii_config(struct net_device *dev, bool init)
192 {
193 struct bcmgenet_priv *priv = netdev_priv(dev);
194 struct phy_device *phydev = dev->phydev;
195 struct device *kdev = &priv->pdev->dev;
196 const char *phy_name = NULL;
197 u32 id_mode_dis = 0;
198 u32 port_ctrl;
199 u32 reg;
200
201 switch (priv->phy_interface) {
202 case PHY_INTERFACE_MODE_INTERNAL:
203 phy_name = "internal PHY";
204 fallthrough;
205 case PHY_INTERFACE_MODE_MOCA:
206 /* Irrespective of the actually configured PHY speed (100 or
207 * 1000) GENETv4 only has an internal GPHY so we will just end
208 * up masking the Gigabit features from what we support, not
209 * switching to the EPHY
210 */
211 if (GENET_IS_V4(priv))
212 port_ctrl = PORT_MODE_INT_GPHY;
213 else
214 port_ctrl = PORT_MODE_INT_EPHY;
215
216 if (!phy_name) {
217 phy_name = "MoCA";
218 if (!GENET_IS_V5(priv))
219 port_ctrl |= LED_ACT_SOURCE_MAC;
220 bcmgenet_moca_phy_setup(priv);
221 }
222 break;
223
224 case PHY_INTERFACE_MODE_MII:
225 phy_name = "external MII";
226 phy_set_max_speed(phydev, SPEED_100);
227 port_ctrl = PORT_MODE_EXT_EPHY;
228 break;
229
230 case PHY_INTERFACE_MODE_REVMII:
231 phy_name = "external RvMII";
232 /* of_mdiobus_register took care of reading the 'max-speed'
233 * PHY property for us, effectively limiting the PHY supported
234 * capabilities, use that knowledge to also configure the
235 * Reverse MII interface correctly.
236 */
237 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
238 dev->phydev->supported))
239 port_ctrl = PORT_MODE_EXT_RVMII_50;
240 else
241 port_ctrl = PORT_MODE_EXT_RVMII_25;
242 break;
243
244 case PHY_INTERFACE_MODE_RGMII:
245 /* RGMII_NO_ID: TXC transitions at the same time as TXD
246 * (requires PCB or receiver-side delay)
247 *
248 * ID is implicitly disabled for 100Mbps (RG)MII operation.
249 */
250 phy_name = "external RGMII (no delay)";
251 id_mode_dis = BIT(16);
252 port_ctrl = PORT_MODE_EXT_GPHY;
253 break;
254
255 case PHY_INTERFACE_MODE_RGMII_TXID:
256 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
257 phy_name = "external RGMII (TX delay)";
258 port_ctrl = PORT_MODE_EXT_GPHY;
259 break;
260
261 case PHY_INTERFACE_MODE_RGMII_RXID:
262 phy_name = "external RGMII (RX delay)";
263 port_ctrl = PORT_MODE_EXT_GPHY;
264 break;
265 default:
266 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
267 return -EINVAL;
268 }
269
270 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
271
272 priv->ext_phy = !priv->internal_phy &&
273 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
274
275 /* This is an external PHY (xMII), so we need to enable the RGMII
276 * block for the interface to work, unconditionally clear the
277 * Out-of-band disable since we do not need it.
278 */
279 mutex_lock(&phydev->lock);
280 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
281 reg &= ~OOB_DISABLE;
282 if (priv->ext_phy) {
283 reg &= ~ID_MODE_DIS;
284 reg |= id_mode_dis;
285 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
286 reg |= RGMII_MODE_EN_V123;
287 else
288 reg |= RGMII_MODE_EN;
289 }
290 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
291 mutex_unlock(&phydev->lock);
292
293 if (init)
294 dev_info(kdev, "configuring instance for %s\n", phy_name);
295
296 return 0;
297 }
298
bcmgenet_mii_probe(struct net_device * dev)299 int bcmgenet_mii_probe(struct net_device *dev)
300 {
301 struct bcmgenet_priv *priv = netdev_priv(dev);
302 struct device *kdev = &priv->pdev->dev;
303 struct device_node *dn = kdev->of_node;
304 phy_interface_t phy_iface = priv->phy_interface;
305 struct phy_device *phydev;
306 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE |
307 PHY_BRCM_DIS_TXCRXC_NOENRGY |
308 PHY_BRCM_IDDQ_SUSPEND;
309 int ret;
310
311 /* Communicate the integrated PHY revision */
312 if (priv->internal_phy)
313 phy_flags = priv->gphy_rev;
314
315 /* This is an ugly quirk but we have not been correctly interpreting
316 * the phy_interface values and we have done that across different
317 * drivers, so at least we are consistent in our mistakes.
318 *
319 * When the Generic PHY driver is in use either the PHY has been
320 * strapped or programmed correctly by the boot loader so we should
321 * stick to our incorrect interpretation since we have validated it.
322 *
323 * Now when a dedicated PHY driver is in use, we need to reverse the
324 * meaning of the phy_interface_mode values to something that the PHY
325 * driver will interpret and act on such that we have two mistakes
326 * canceling themselves so to speak. We only do this for the two
327 * modes that GENET driver officially supports on Broadcom STB chips:
328 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other
329 * modes are not *officially* supported with the boot loader and the
330 * scripted environment generating Device Tree blobs for those
331 * platforms.
332 *
333 * Note that internal PHY, MoCA and fixed-link configurations are not
334 * affected because they use different phy_interface_t values or the
335 * Generic PHY driver.
336 */
337 switch (priv->phy_interface) {
338 case PHY_INTERFACE_MODE_RGMII:
339 phy_iface = PHY_INTERFACE_MODE_RGMII_ID;
340 break;
341 case PHY_INTERFACE_MODE_RGMII_TXID:
342 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID;
343 break;
344 default:
345 break;
346 }
347
348 if (dn) {
349 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
350 phy_flags, phy_iface);
351 if (!phydev) {
352 pr_err("could not attach to PHY\n");
353 return -ENODEV;
354 }
355 } else {
356 if (has_acpi_companion(kdev)) {
357 char mdio_bus_id[MII_BUS_ID_SIZE];
358 struct mii_bus *unimacbus;
359
360 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
361 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
362
363 unimacbus = mdio_find_bus(mdio_bus_id);
364 if (!unimacbus) {
365 pr_err("Unable to find mii\n");
366 return -ENODEV;
367 }
368 phydev = phy_find_first(unimacbus);
369 put_device(&unimacbus->dev);
370 if (!phydev) {
371 pr_err("Unable to find PHY\n");
372 return -ENODEV;
373 }
374 } else {
375 phydev = dev->phydev;
376 }
377 phydev->dev_flags = phy_flags;
378
379 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
380 phy_iface);
381 if (ret) {
382 pr_err("could not attach to PHY\n");
383 return -ENODEV;
384 }
385 }
386
387 /* Configure port multiplexer based on what the probed PHY device since
388 * reading the 'max-speed' property determines the maximum supported
389 * PHY speed which is needed for bcmgenet_mii_config() to configure
390 * things appropriately.
391 */
392 ret = bcmgenet_mii_config(dev, true);
393 if (ret) {
394 phy_disconnect(dev->phydev);
395 return ret;
396 }
397
398 /* The internal PHY has its link interrupts routed to the
399 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
400 * that prevents the signaling of link UP interrupts when
401 * the link operates at 10Mbps, so fallback to polling for
402 * those versions of GENET.
403 */
404 if (priv->internal_phy && !GENET_IS_V5(priv))
405 dev->phydev->irq = PHY_MAC_INTERRUPT;
406
407 /* Indicate that the MAC is responsible for PHY PM */
408 dev->phydev->mac_managed_pm = true;
409
410 return 0;
411 }
412
bcmgenet_mii_of_find_mdio(struct bcmgenet_priv * priv)413 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
414 {
415 struct device_node *dn = priv->pdev->dev.of_node;
416 struct device *kdev = &priv->pdev->dev;
417 char *compat;
418
419 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
420 if (!compat)
421 return NULL;
422
423 priv->mdio_dn = of_get_compatible_child(dn, compat);
424 kfree(compat);
425 if (!priv->mdio_dn) {
426 dev_err(kdev, "unable to find MDIO bus node\n");
427 return NULL;
428 }
429
430 return priv->mdio_dn;
431 }
432
bcmgenet_mii_pdata_init(struct bcmgenet_priv * priv,struct unimac_mdio_pdata * ppd)433 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
434 struct unimac_mdio_pdata *ppd)
435 {
436 struct device *kdev = &priv->pdev->dev;
437 struct bcmgenet_platform_data *pd = kdev->platform_data;
438
439 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
440 /*
441 * Internal or external PHY with MDIO access
442 */
443 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
444 ppd->phy_mask = 1 << pd->phy_address;
445 else
446 ppd->phy_mask = 0;
447 }
448 }
449
bcmgenet_mii_wait(void * wait_func_data)450 static int bcmgenet_mii_wait(void *wait_func_data)
451 {
452 struct bcmgenet_priv *priv = wait_func_data;
453
454 wait_event_timeout(priv->wq,
455 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
456 & MDIO_START_BUSY),
457 HZ / 100);
458 return 0;
459 }
460
bcmgenet_mii_register(struct bcmgenet_priv * priv)461 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
462 {
463 struct platform_device *pdev = priv->pdev;
464 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
465 struct device_node *dn = pdev->dev.of_node;
466 struct unimac_mdio_pdata ppd;
467 struct platform_device *ppdev;
468 struct resource *pres, res;
469 int id, ret;
470
471 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
472 if (!pres) {
473 dev_err(&pdev->dev, "Invalid resource\n");
474 return -EINVAL;
475 }
476 memset(&res, 0, sizeof(res));
477 memset(&ppd, 0, sizeof(ppd));
478
479 ppd.wait_func = bcmgenet_mii_wait;
480 ppd.wait_func_data = priv;
481 ppd.bus_name = "bcmgenet MII bus";
482
483 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
484 * and is 2 * 32-bits word long, 8 bytes total.
485 */
486 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
487 res.end = res.start + 8;
488 res.flags = IORESOURCE_MEM;
489
490 if (dn)
491 id = of_alias_get_id(dn, "eth");
492 else
493 id = pdev->id;
494
495 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
496 if (!ppdev)
497 return -ENOMEM;
498
499 /* Retain this platform_device pointer for later cleanup */
500 priv->mii_pdev = ppdev;
501 ppdev->dev.parent = &pdev->dev;
502 if (dn)
503 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
504 else if (pdata)
505 bcmgenet_mii_pdata_init(priv, &ppd);
506 else
507 ppd.phy_mask = ~0;
508
509 ret = platform_device_add_resources(ppdev, &res, 1);
510 if (ret)
511 goto out;
512
513 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
514 if (ret)
515 goto out;
516
517 ret = platform_device_add(ppdev);
518 if (ret)
519 goto out;
520
521 return 0;
522 out:
523 platform_device_put(ppdev);
524 return ret;
525 }
526
bcmgenet_phy_interface_init(struct bcmgenet_priv * priv)527 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
528 {
529 struct device *kdev = &priv->pdev->dev;
530 int phy_mode = device_get_phy_mode(kdev);
531
532 if (phy_mode < 0) {
533 dev_err(kdev, "invalid PHY mode property\n");
534 return phy_mode;
535 }
536
537 priv->phy_interface = phy_mode;
538
539 /* We need to specifically look up whether this PHY interface is
540 * internal or not *before* we even try to probe the PHY driver
541 * over MDIO as we may have shut down the internal PHY for power
542 * saving purposes.
543 */
544 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
545 priv->internal_phy = true;
546
547 return 0;
548 }
549
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)550 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
551 {
552 struct device_node *dn = priv->pdev->dev.of_node;
553 struct phy_device *phydev;
554 int ret;
555
556 /* Fetch the PHY phandle */
557 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
558
559 /* In the case of a fixed PHY, the DT node associated
560 * to the PHY is the Ethernet MAC DT node.
561 */
562 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
563 ret = of_phy_register_fixed_link(dn);
564 if (ret)
565 return ret;
566
567 priv->phy_dn = of_node_get(dn);
568 }
569
570 /* Get the link mode */
571 ret = bcmgenet_phy_interface_init(priv);
572 if (ret)
573 return ret;
574
575 /* Make sure we initialize MoCA PHYs with a link down */
576 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
577 phydev = of_phy_find_device(dn);
578 if (phydev) {
579 phydev->link = 0;
580 put_device(&phydev->mdio.dev);
581 }
582 }
583
584 return 0;
585 }
586
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)587 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
588 {
589 struct device *kdev = &priv->pdev->dev;
590 struct bcmgenet_platform_data *pd = kdev->platform_data;
591 char phy_name[MII_BUS_ID_SIZE + 3];
592 char mdio_bus_id[MII_BUS_ID_SIZE];
593 struct phy_device *phydev;
594
595 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
596 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
597
598 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
599 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
600 mdio_bus_id, pd->phy_address);
601
602 /*
603 * Internal or external PHY with MDIO access
604 */
605 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
606 if (IS_ERR(phydev)) {
607 dev_err(kdev, "failed to register PHY device\n");
608 return PTR_ERR(phydev);
609 }
610 } else {
611 /*
612 * MoCA port or no MDIO access.
613 * Use fixed PHY to represent the link layer.
614 */
615 struct fixed_phy_status fphy_status = {
616 .link = 1,
617 .speed = pd->phy_speed,
618 .duplex = pd->phy_duplex,
619 .pause = 0,
620 .asym_pause = 0,
621 };
622
623 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
624 if (IS_ERR(phydev)) {
625 dev_err(kdev, "failed to register fixed PHY device\n");
626 return PTR_ERR(phydev);
627 }
628
629 /* Make sure we initialize MoCA PHYs with a link down */
630 phydev->link = 0;
631
632 }
633
634 priv->phy_interface = pd->phy_interface;
635
636 return 0;
637 }
638
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)639 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
640 {
641 struct device *kdev = &priv->pdev->dev;
642 struct device_node *dn = kdev->of_node;
643
644 if (dn)
645 return bcmgenet_mii_of_init(priv);
646 else if (has_acpi_companion(kdev))
647 return bcmgenet_phy_interface_init(priv);
648 else
649 return bcmgenet_mii_pd_init(priv);
650 }
651
bcmgenet_mii_init(struct net_device * dev)652 int bcmgenet_mii_init(struct net_device *dev)
653 {
654 struct bcmgenet_priv *priv = netdev_priv(dev);
655 int ret;
656
657 ret = bcmgenet_mii_register(priv);
658 if (ret)
659 return ret;
660
661 ret = bcmgenet_mii_bus_init(priv);
662 if (ret)
663 goto out;
664
665 return 0;
666
667 out:
668 bcmgenet_mii_exit(dev);
669 return ret;
670 }
671
bcmgenet_mii_exit(struct net_device * dev)672 void bcmgenet_mii_exit(struct net_device *dev)
673 {
674 struct bcmgenet_priv *priv = netdev_priv(dev);
675 struct device_node *dn = priv->pdev->dev.of_node;
676
677 if (of_phy_is_fixed_link(dn))
678 of_phy_deregister_fixed_link(dn);
679 of_node_put(priv->phy_dn);
680 clk_prepare_enable(priv->clk);
681 platform_device_unregister(priv->mii_pdev);
682 clk_disable_unprepare(priv->clk);
683 }
684