xref: /openbmc/linux/drivers/net/dsa/bcm_sf2.c (revision a7d2808d)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Broadcom Starfighter 2 DSA switch driver
4  *
5  * Copyright (C) 2014, Broadcom Corporation
6  */
7 
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/clk.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <net/dsa.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_bridge.h>
26 #include <linux/brcmphy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/platform_data/b53.h>
29 
30 #include "bcm_sf2.h"
31 #include "bcm_sf2_regs.h"
32 #include "b53/b53_priv.h"
33 #include "b53/b53_regs.h"
34 
bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv * priv,int port)35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36 {
37 	switch (priv->type) {
38 	case BCM4908_DEVICE_ID:
39 		switch (port) {
40 		case 7:
41 			return REG_RGMII_11_CNTRL;
42 		default:
43 			break;
44 		}
45 		break;
46 	default:
47 		switch (port) {
48 		case 0:
49 			return REG_RGMII_0_CNTRL;
50 		case 1:
51 			return REG_RGMII_1_CNTRL;
52 		case 2:
53 			return REG_RGMII_2_CNTRL;
54 		default:
55 			break;
56 		}
57 	}
58 
59 	WARN_ONCE(1, "Unsupported port %d\n", port);
60 
61 	/* RO fallback reg */
62 	return REG_SWITCH_STATUS;
63 }
64 
bcm_sf2_reg_led_base(struct bcm_sf2_priv * priv,int port)65 static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
66 {
67 	switch (port) {
68 	case 0:
69 		return REG_LED_0_CNTRL;
70 	case 1:
71 		return REG_LED_1_CNTRL;
72 	case 2:
73 		return REG_LED_2_CNTRL;
74 	}
75 
76 	switch (priv->type) {
77 	case BCM4908_DEVICE_ID:
78 		switch (port) {
79 		case 3:
80 			return REG_LED_3_CNTRL;
81 		case 7:
82 			return REG_LED_4_CNTRL;
83 		default:
84 			break;
85 		}
86 		break;
87 	default:
88 		break;
89 	}
90 
91 	WARN_ONCE(1, "Unsupported port %d\n", port);
92 
93 	/* RO fallback reg */
94 	return REG_SWITCH_STATUS;
95 }
96 
bcm_sf2_port_override_offset(struct bcm_sf2_priv * priv,int port)97 static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port)
98 {
99 	switch (priv->type) {
100 	case BCM4908_DEVICE_ID:
101 	case BCM7445_DEVICE_ID:
102 		return port == 8 ? CORE_STS_OVERRIDE_IMP :
103 				   CORE_STS_OVERRIDE_GMIIP_PORT(port);
104 	case BCM7278_DEVICE_ID:
105 		return port == 8 ? CORE_STS_OVERRIDE_IMP2 :
106 				   CORE_STS_OVERRIDE_GMIIP2_PORT(port);
107 	default:
108 		WARN_ONCE(1, "Unsupported device: %d\n", priv->type);
109 	}
110 
111 	/* RO fallback register */
112 	return REG_SWITCH_STATUS;
113 }
114 
115 /* Return the number of active ports, not counting the IMP (CPU) port */
bcm_sf2_num_active_ports(struct dsa_switch * ds)116 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
117 {
118 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
119 	unsigned int port, count = 0;
120 
121 	for (port = 0; port < ds->num_ports; port++) {
122 		if (dsa_is_cpu_port(ds, port))
123 			continue;
124 		if (priv->port_sts[port].enabled)
125 			count++;
126 	}
127 
128 	return count;
129 }
130 
bcm_sf2_recalc_clock(struct dsa_switch * ds)131 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
132 {
133 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
134 	unsigned long new_rate;
135 	unsigned int ports_active;
136 	/* Frequenty in Mhz */
137 	static const unsigned long rate_table[] = {
138 		59220000,
139 		60820000,
140 		62500000,
141 		62500000,
142 	};
143 
144 	ports_active = bcm_sf2_num_active_ports(ds);
145 	if (ports_active == 0 || !priv->clk_mdiv)
146 		return;
147 
148 	/* If we overflow our table, just use the recommended operational
149 	 * frequency
150 	 */
151 	if (ports_active > ARRAY_SIZE(rate_table))
152 		new_rate = 90000000;
153 	else
154 		new_rate = rate_table[ports_active - 1];
155 	clk_set_rate(priv->clk_mdiv, new_rate);
156 }
157 
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)158 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
159 {
160 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 	unsigned int i;
162 	u32 reg;
163 
164 	/* Enable the port memories */
165 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 	reg &= ~P_TXQ_PSM_VDD(port);
167 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
168 
169 	/* Enable forwarding */
170 	core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
171 
172 	/* Enable IMP port in dumb mode */
173 	reg = core_readl(priv, CORE_SWITCH_CTRL);
174 	reg |= MII_DUMB_FWDG_EN;
175 	core_writel(priv, reg, CORE_SWITCH_CTRL);
176 
177 	/* Configure Traffic Class to QoS mapping, allow each priority to map
178 	 * to a different queue number
179 	 */
180 	reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
181 	for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
182 		reg |= i << (PRT_TO_QID_SHIFT * i);
183 	core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
184 
185 	b53_brcm_hdr_setup(ds, port);
186 
187 	if (port == 8) {
188 		/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
189 		reg = core_readl(priv, CORE_IMP_CTL);
190 		reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
191 		reg &= ~(RX_DIS | TX_DIS);
192 		core_writel(priv, reg, CORE_IMP_CTL);
193 	} else {
194 		reg = core_readl(priv, CORE_G_PCTL_PORT(port));
195 		reg &= ~(RX_DIS | TX_DIS);
196 		core_writel(priv, reg, CORE_G_PCTL_PORT(port));
197 	}
198 
199 	priv->port_sts[port].enabled = true;
200 }
201 
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)202 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
203 {
204 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
205 	u32 reg;
206 
207 	reg = reg_readl(priv, REG_SPHY_CNTRL);
208 	if (enable) {
209 		reg |= PHY_RESET;
210 		reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
211 		reg_writel(priv, reg, REG_SPHY_CNTRL);
212 		udelay(21);
213 		reg = reg_readl(priv, REG_SPHY_CNTRL);
214 		reg &= ~PHY_RESET;
215 	} else {
216 		reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
217 		reg_writel(priv, reg, REG_SPHY_CNTRL);
218 		mdelay(1);
219 		reg |= CK25_DIS;
220 	}
221 	reg_writel(priv, reg, REG_SPHY_CNTRL);
222 
223 	/* Use PHY-driven LED signaling */
224 	if (!enable) {
225 		u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
226 
227 		if (priv->type == BCM7278_DEVICE_ID ||
228 		    priv->type == BCM7445_DEVICE_ID) {
229 			reg = reg_led_readl(priv, led_ctrl, 0);
230 			reg |= LED_CNTRL_SPDLNK_SRC_SEL;
231 			reg_led_writel(priv, reg, led_ctrl, 0);
232 		}
233 	}
234 }
235 
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)236 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
237 					    int port)
238 {
239 	unsigned int off;
240 
241 	switch (port) {
242 	case 7:
243 		off = P7_IRQ_OFF;
244 		break;
245 	case 0:
246 		/* Port 0 interrupts are located on the first bank */
247 		intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
248 		return;
249 	default:
250 		off = P_IRQ_OFF(port);
251 		break;
252 	}
253 
254 	intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
255 }
256 
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)257 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
258 					     int port)
259 {
260 	unsigned int off;
261 
262 	switch (port) {
263 	case 7:
264 		off = P7_IRQ_OFF;
265 		break;
266 	case 0:
267 		/* Port 0 interrupts are located on the first bank */
268 		intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
269 		intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
270 		return;
271 	default:
272 		off = P_IRQ_OFF(port);
273 		break;
274 	}
275 
276 	intrl2_1_mask_set(priv, P_IRQ_MASK(off));
277 	intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
278 }
279 
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)280 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
281 			      struct phy_device *phy)
282 {
283 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
284 	unsigned int i;
285 	u32 reg;
286 
287 	if (!dsa_is_user_port(ds, port))
288 		return 0;
289 
290 	priv->port_sts[port].enabled = true;
291 
292 	bcm_sf2_recalc_clock(ds);
293 
294 	/* Clear the memory power down */
295 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
296 	reg &= ~P_TXQ_PSM_VDD(port);
297 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
298 
299 	/* Enable Broadcom tags for that port if requested */
300 	if (priv->brcm_tag_mask & BIT(port))
301 		b53_brcm_hdr_setup(ds, port);
302 
303 	/* Configure Traffic Class to QoS mapping, allow each priority to map
304 	 * to a different queue number
305 	 */
306 	reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
307 	for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
308 		reg |= i << (PRT_TO_QID_SHIFT * i);
309 	core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
310 
311 	/* Re-enable the GPHY and re-apply workarounds */
312 	if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
313 		bcm_sf2_gphy_enable_set(ds, true);
314 		if (phy) {
315 			/* if phy_stop() has been called before, phy
316 			 * will be in halted state, and phy_start()
317 			 * will call resume.
318 			 *
319 			 * the resume path does not configure back
320 			 * autoneg settings, and since we hard reset
321 			 * the phy manually here, we need to reset the
322 			 * state machine also.
323 			 */
324 			phy->state = PHY_READY;
325 			phy_init_hw(phy);
326 		}
327 	}
328 
329 	/* Enable MoCA port interrupts to get notified */
330 	if (port == priv->moca_port)
331 		bcm_sf2_port_intr_enable(priv, port);
332 
333 	/* Set per-queue pause threshold to 32 */
334 	core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
335 
336 	/* Set ACB threshold to 24 */
337 	for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
338 		reg = acb_readl(priv, ACB_QUEUE_CFG(port *
339 						    SF2_NUM_EGRESS_QUEUES + i));
340 		reg &= ~XOFF_THRESHOLD_MASK;
341 		reg |= 24;
342 		acb_writel(priv, reg, ACB_QUEUE_CFG(port *
343 						    SF2_NUM_EGRESS_QUEUES + i));
344 	}
345 
346 	return b53_enable_port(ds, port, phy);
347 }
348 
bcm_sf2_port_disable(struct dsa_switch * ds,int port)349 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
350 {
351 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
352 	u32 reg;
353 
354 	/* Disable learning while in WoL mode */
355 	if (priv->wol_ports_mask & (1 << port)) {
356 		reg = core_readl(priv, CORE_DIS_LEARN);
357 		reg |= BIT(port);
358 		core_writel(priv, reg, CORE_DIS_LEARN);
359 		return;
360 	}
361 
362 	if (port == priv->moca_port)
363 		bcm_sf2_port_intr_disable(priv, port);
364 
365 	if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
366 		bcm_sf2_gphy_enable_set(ds, false);
367 
368 	b53_disable_port(ds, port);
369 
370 	/* Power down the port memory */
371 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
372 	reg |= P_TXQ_PSM_VDD(port);
373 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
374 
375 	priv->port_sts[port].enabled = false;
376 
377 	bcm_sf2_recalc_clock(ds);
378 }
379 
380 
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)381 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
382 			       int regnum, u16 val)
383 {
384 	int ret = 0;
385 	u32 reg;
386 
387 	reg = reg_readl(priv, REG_SWITCH_CNTRL);
388 	reg |= MDIO_MASTER_SEL;
389 	reg_writel(priv, reg, REG_SWITCH_CNTRL);
390 
391 	/* Page << 8 | offset */
392 	reg = 0x70;
393 	reg <<= 2;
394 	core_writel(priv, addr, reg);
395 
396 	/* Page << 8 | offset */
397 	reg = 0x80 << 8 | regnum << 1;
398 	reg <<= 2;
399 
400 	if (op)
401 		ret = core_readl(priv, reg);
402 	else
403 		core_writel(priv, val, reg);
404 
405 	reg = reg_readl(priv, REG_SWITCH_CNTRL);
406 	reg &= ~MDIO_MASTER_SEL;
407 	reg_writel(priv, reg, REG_SWITCH_CNTRL);
408 
409 	return ret & 0xffff;
410 }
411 
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)412 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
413 {
414 	struct bcm_sf2_priv *priv = bus->priv;
415 
416 	/* Intercept reads from Broadcom pseudo-PHY address, else, send
417 	 * them to our master MDIO bus controller
418 	 */
419 	if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
420 		return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
421 	else
422 		return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
423 }
424 
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)425 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
426 				 u16 val)
427 {
428 	struct bcm_sf2_priv *priv = bus->priv;
429 
430 	/* Intercept writes to the Broadcom pseudo-PHY address, else,
431 	 * send them to our master MDIO bus controller
432 	 */
433 	if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
434 		return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
435 	else
436 		return mdiobus_write_nested(priv->master_mii_bus, addr,
437 				regnum, val);
438 }
439 
bcm_sf2_switch_0_isr(int irq,void * dev_id)440 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
441 {
442 	struct dsa_switch *ds = dev_id;
443 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
444 
445 	priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
446 				~priv->irq0_mask;
447 	intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
448 
449 	return IRQ_HANDLED;
450 }
451 
bcm_sf2_switch_1_isr(int irq,void * dev_id)452 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
453 {
454 	struct dsa_switch *ds = dev_id;
455 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
456 
457 	priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
458 				~priv->irq1_mask;
459 	intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
460 
461 	if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
462 		priv->port_sts[7].link = true;
463 		dsa_port_phylink_mac_change(ds, 7, true);
464 	}
465 	if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
466 		priv->port_sts[7].link = false;
467 		dsa_port_phylink_mac_change(ds, 7, false);
468 	}
469 
470 	return IRQ_HANDLED;
471 }
472 
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)473 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
474 {
475 	unsigned int timeout = 1000;
476 	u32 reg;
477 	int ret;
478 
479 	/* The watchdog reset does not work on 7278, we need to hit the
480 	 * "external" reset line through the reset controller.
481 	 */
482 	if (priv->type == BCM7278_DEVICE_ID) {
483 		ret = reset_control_assert(priv->rcdev);
484 		if (ret)
485 			return ret;
486 
487 		return reset_control_deassert(priv->rcdev);
488 	}
489 
490 	reg = core_readl(priv, CORE_WATCHDOG_CTRL);
491 	reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
492 	core_writel(priv, reg, CORE_WATCHDOG_CTRL);
493 
494 	do {
495 		reg = core_readl(priv, CORE_WATCHDOG_CTRL);
496 		if (!(reg & SOFTWARE_RESET))
497 			break;
498 
499 		usleep_range(1000, 2000);
500 	} while (timeout-- > 0);
501 
502 	if (timeout == 0)
503 		return -ETIMEDOUT;
504 
505 	return 0;
506 }
507 
bcm_sf2_crossbar_setup(struct bcm_sf2_priv * priv)508 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
509 {
510 	struct device *dev = priv->dev->ds->dev;
511 	int shift;
512 	u32 mask;
513 	u32 reg;
514 	int i;
515 
516 	mask = BIT(priv->num_crossbar_int_ports) - 1;
517 
518 	reg = reg_readl(priv, REG_CROSSBAR);
519 	switch (priv->type) {
520 	case BCM4908_DEVICE_ID:
521 		shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
522 		reg &= ~(mask << shift);
523 		if (0) /* FIXME */
524 			reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
525 		else if (priv->int_phy_mask & BIT(7))
526 			reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
527 		else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
528 			reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
529 		else if (WARN(1, "Invalid port mode\n"))
530 			return;
531 		break;
532 	default:
533 		return;
534 	}
535 	reg_writel(priv, reg, REG_CROSSBAR);
536 
537 	reg = reg_readl(priv, REG_CROSSBAR);
538 	for (i = 0; i < priv->num_crossbar_int_ports; i++) {
539 		shift = i * priv->num_crossbar_int_ports;
540 
541 		dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
542 			(reg >> shift) & mask);
543 	}
544 }
545 
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)546 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
547 {
548 	intrl2_0_mask_set(priv, 0xffffffff);
549 	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
550 	intrl2_1_mask_set(priv, 0xffffffff);
551 	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
552 }
553 
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)554 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
555 				   struct device_node *dn)
556 {
557 	struct device *dev = priv->dev->ds->dev;
558 	struct bcm_sf2_port_status *port_st;
559 	struct device_node *port;
560 	unsigned int port_num;
561 	struct property *prop;
562 	int err;
563 
564 	priv->moca_port = -1;
565 
566 	for_each_available_child_of_node(dn, port) {
567 		if (of_property_read_u32(port, "reg", &port_num))
568 			continue;
569 
570 		if (port_num >= DSA_MAX_PORTS) {
571 			dev_err(dev, "Invalid port number %d\n", port_num);
572 			continue;
573 		}
574 
575 		port_st = &priv->port_sts[port_num];
576 
577 		/* Internal PHYs get assigned a specific 'phy-mode' property
578 		 * value: "internal" to help flag them before MDIO probing
579 		 * has completed, since they might be turned off at that
580 		 * time
581 		 */
582 		err = of_get_phy_mode(port, &port_st->mode);
583 		if (err)
584 			continue;
585 
586 		if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
587 			priv->int_phy_mask |= 1 << port_num;
588 
589 		if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
590 			priv->moca_port = port_num;
591 
592 		if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
593 			priv->brcm_tag_mask |= 1 << port_num;
594 
595 		/* Ensure that port 5 is not picked up as a DSA CPU port
596 		 * flavour but a regular port instead. We should be using
597 		 * devlink to be able to set the port flavour.
598 		 */
599 		if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
600 			prop = of_find_property(port, "ethernet", NULL);
601 			if (prop)
602 				of_remove_property(port, prop);
603 		}
604 	}
605 }
606 
bcm_sf2_mdio_register(struct dsa_switch * ds)607 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
608 {
609 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
610 	struct device_node *dn, *child;
611 	struct phy_device *phydev;
612 	struct property *prop;
613 	static int index;
614 	int err, reg;
615 
616 	/* Find our integrated MDIO bus node */
617 	dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
618 	priv->master_mii_bus = of_mdio_find_bus(dn);
619 	if (!priv->master_mii_bus) {
620 		err = -EPROBE_DEFER;
621 		goto err_of_node_put;
622 	}
623 
624 	priv->master_mii_dn = dn;
625 
626 	priv->slave_mii_bus = mdiobus_alloc();
627 	if (!priv->slave_mii_bus) {
628 		err = -ENOMEM;
629 		goto err_put_master_mii_bus_dev;
630 	}
631 
632 	priv->slave_mii_bus->priv = priv;
633 	priv->slave_mii_bus->name = "sf2 slave mii";
634 	priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
635 	priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
636 	snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
637 		 index++);
638 	priv->slave_mii_bus->dev.of_node = dn;
639 
640 	/* Include the pseudo-PHY address to divert reads towards our
641 	 * workaround. This is only required for 7445D0, since 7445E0
642 	 * disconnects the internal switch pseudo-PHY such that we can use the
643 	 * regular SWITCH_MDIO master controller instead.
644 	 *
645 	 * Here we flag the pseudo PHY as needing special treatment and would
646 	 * otherwise make all other PHY read/writes go to the master MDIO bus
647 	 * controller that comes with this switch backed by the "mdio-unimac"
648 	 * driver.
649 	 */
650 	if (of_machine_is_compatible("brcm,bcm7445d0"))
651 		priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
652 	else
653 		priv->indir_phy_mask = 0;
654 
655 	ds->phys_mii_mask = priv->indir_phy_mask;
656 	ds->slave_mii_bus = priv->slave_mii_bus;
657 	priv->slave_mii_bus->parent = ds->dev->parent;
658 	priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
659 
660 	/* We need to make sure that of_phy_connect() will not work by
661 	 * removing the 'phandle' and 'linux,phandle' properties and
662 	 * unregister the existing PHY device that was already registered.
663 	 */
664 	for_each_available_child_of_node(dn, child) {
665 		if (of_property_read_u32(child, "reg", &reg) ||
666 		    reg >= PHY_MAX_ADDR)
667 			continue;
668 
669 		if (!(priv->indir_phy_mask & BIT(reg)))
670 			continue;
671 
672 		prop = of_find_property(child, "phandle", NULL);
673 		if (prop)
674 			of_remove_property(child, prop);
675 
676 		prop = of_find_property(child, "linux,phandle", NULL);
677 		if (prop)
678 			of_remove_property(child, prop);
679 
680 		phydev = of_phy_find_device(child);
681 		if (phydev) {
682 			phy_device_remove(phydev);
683 			phy_device_free(phydev);
684 		}
685 	}
686 
687 	err = mdiobus_register(priv->slave_mii_bus);
688 	if (err && dn)
689 		goto err_free_slave_mii_bus;
690 
691 	return 0;
692 
693 err_free_slave_mii_bus:
694 	mdiobus_free(priv->slave_mii_bus);
695 err_put_master_mii_bus_dev:
696 	put_device(&priv->master_mii_bus->dev);
697 err_of_node_put:
698 	of_node_put(dn);
699 	return err;
700 }
701 
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)702 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
703 {
704 	mdiobus_unregister(priv->slave_mii_bus);
705 	mdiobus_free(priv->slave_mii_bus);
706 	put_device(&priv->master_mii_bus->dev);
707 	of_node_put(priv->master_mii_dn);
708 }
709 
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)710 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
711 {
712 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
713 
714 	/* The BCM7xxx PHY driver expects to find the integrated PHY revision
715 	 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
716 	 * the REG_PHY_REVISION register layout is.
717 	 */
718 	if (priv->int_phy_mask & BIT(port))
719 		return priv->hw_params.gphy_rev;
720 	else
721 		return PHY_BRCM_AUTO_PWRDWN_ENABLE |
722 		       PHY_BRCM_DIS_TXCRXC_NOENRGY |
723 		       PHY_BRCM_IDDQ_SUSPEND;
724 }
725 
bcm_sf2_sw_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)726 static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
727 				struct phylink_config *config)
728 {
729 	unsigned long *interfaces = config->supported_interfaces;
730 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
731 
732 	if (priv->int_phy_mask & BIT(port)) {
733 		__set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
734 	} else if (priv->moca_port == port) {
735 		__set_bit(PHY_INTERFACE_MODE_MOCA, interfaces);
736 	} else {
737 		__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
738 		__set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
739 		__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
740 		phy_interface_set_rgmii(interfaces);
741 	}
742 
743 	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
744 		MAC_10 | MAC_100 | MAC_1000;
745 }
746 
bcm_sf2_sw_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)747 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
748 				  unsigned int mode,
749 				  const struct phylink_link_state *state)
750 {
751 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
752 	u32 id_mode_dis = 0, port_mode;
753 	u32 reg_rgmii_ctrl;
754 	u32 reg;
755 
756 	if (port == core_readl(priv, CORE_IMP0_PRT_ID))
757 		return;
758 
759 	switch (state->interface) {
760 	case PHY_INTERFACE_MODE_RGMII:
761 		id_mode_dis = 1;
762 		fallthrough;
763 	case PHY_INTERFACE_MODE_RGMII_TXID:
764 		port_mode = EXT_GPHY;
765 		break;
766 	case PHY_INTERFACE_MODE_MII:
767 		port_mode = EXT_EPHY;
768 		break;
769 	case PHY_INTERFACE_MODE_REVMII:
770 		port_mode = EXT_REVMII;
771 		break;
772 	default:
773 		/* Nothing required for all other PHYs: internal and MoCA */
774 		return;
775 	}
776 
777 	reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
778 
779 	/* Clear id_mode_dis bit, and the existing port mode, let
780 	 * RGMII_MODE_EN bet set by mac_link_{up,down}
781 	 */
782 	reg = reg_readl(priv, reg_rgmii_ctrl);
783 	reg &= ~ID_MODE_DIS;
784 	reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
785 
786 	reg |= port_mode;
787 	if (id_mode_dis)
788 		reg |= ID_MODE_DIS;
789 
790 	reg_writel(priv, reg, reg_rgmii_ctrl);
791 }
792 
bcm_sf2_sw_mac_link_set(struct dsa_switch * ds,int port,phy_interface_t interface,bool link)793 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
794 				    phy_interface_t interface, bool link)
795 {
796 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
797 	u32 reg_rgmii_ctrl;
798 	u32 reg;
799 
800 	if (!phy_interface_mode_is_rgmii(interface) &&
801 	    interface != PHY_INTERFACE_MODE_MII &&
802 	    interface != PHY_INTERFACE_MODE_REVMII)
803 		return;
804 
805 	reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
806 
807 	/* If the link is down, just disable the interface to conserve power */
808 	reg = reg_readl(priv, reg_rgmii_ctrl);
809 	if (link)
810 		reg |= RGMII_MODE_EN;
811 	else
812 		reg &= ~RGMII_MODE_EN;
813 	reg_writel(priv, reg, reg_rgmii_ctrl);
814 }
815 
bcm_sf2_sw_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)816 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
817 				     unsigned int mode,
818 				     phy_interface_t interface)
819 {
820 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
821 	u32 reg, offset;
822 
823 	if (priv->wol_ports_mask & BIT(port))
824 		return;
825 
826 	offset = bcm_sf2_port_override_offset(priv, port);
827 	reg = core_readl(priv, offset);
828 	reg &= ~LINK_STS;
829 	core_writel(priv, reg, offset);
830 
831 	bcm_sf2_sw_mac_link_set(ds, port, interface, false);
832 }
833 
bcm_sf2_sw_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)834 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
835 				   unsigned int mode,
836 				   phy_interface_t interface,
837 				   struct phy_device *phydev,
838 				   int speed, int duplex,
839 				   bool tx_pause, bool rx_pause)
840 {
841 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
842 	struct ethtool_eee *p = &priv->dev->ports[port].eee;
843 	u32 reg_rgmii_ctrl = 0;
844 	u32 reg, offset;
845 
846 	bcm_sf2_sw_mac_link_set(ds, port, interface, true);
847 
848 	offset = bcm_sf2_port_override_offset(priv, port);
849 
850 	if (phy_interface_mode_is_rgmii(interface) ||
851 	    interface == PHY_INTERFACE_MODE_MII ||
852 	    interface == PHY_INTERFACE_MODE_REVMII) {
853 		reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
854 		reg = reg_readl(priv, reg_rgmii_ctrl);
855 		reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
856 
857 		if (tx_pause)
858 			reg |= TX_PAUSE_EN;
859 		if (rx_pause)
860 			reg |= RX_PAUSE_EN;
861 
862 		reg_writel(priv, reg, reg_rgmii_ctrl);
863 	}
864 
865 	reg = LINK_STS;
866 	if (port == 8) {
867 		if (priv->type == BCM4908_DEVICE_ID)
868 			reg |= GMII_SPEED_UP_2G;
869 		reg |= MII_SW_OR;
870 	} else {
871 		reg |= SW_OVERRIDE;
872 	}
873 
874 	switch (speed) {
875 	case SPEED_1000:
876 		reg |= SPDSTS_1000 << SPEED_SHIFT;
877 		break;
878 	case SPEED_100:
879 		reg |= SPDSTS_100 << SPEED_SHIFT;
880 		break;
881 	}
882 
883 	if (duplex == DUPLEX_FULL)
884 		reg |= DUPLX_MODE;
885 
886 	if (tx_pause)
887 		reg |= TXFLOW_CNTL;
888 	if (rx_pause)
889 		reg |= RXFLOW_CNTL;
890 
891 	core_writel(priv, reg, offset);
892 
893 	if (mode == MLO_AN_PHY && phydev)
894 		p->eee_enabled = b53_eee_init(ds, port, phydev);
895 }
896 
bcm_sf2_sw_fixed_state(struct dsa_switch * ds,int port,struct phylink_link_state * status)897 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
898 				   struct phylink_link_state *status)
899 {
900 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
901 
902 	status->link = false;
903 
904 	/* MoCA port is special as we do not get link status from CORE_LNKSTS,
905 	 * which means that we need to force the link at the port override
906 	 * level to get the data to flow. We do use what the interrupt handler
907 	 * did determine before.
908 	 *
909 	 * For the other ports, we just force the link status, since this is
910 	 * a fixed PHY device.
911 	 */
912 	if (port == priv->moca_port) {
913 		status->link = priv->port_sts[port].link;
914 		/* For MoCA interfaces, also force a link down notification
915 		 * since some version of the user-space daemon (mocad) use
916 		 * cmd->autoneg to force the link, which messes up the PHY
917 		 * state machine and make it go in PHY_FORCING state instead.
918 		 */
919 		if (!status->link)
920 			netif_carrier_off(dsa_to_port(ds, port)->slave);
921 		status->duplex = DUPLEX_FULL;
922 	} else {
923 		status->link = true;
924 	}
925 }
926 
bcm_sf2_enable_acb(struct dsa_switch * ds)927 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
928 {
929 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
930 	u32 reg;
931 
932 	/* Enable ACB globally */
933 	reg = acb_readl(priv, ACB_CONTROL);
934 	reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
935 	acb_writel(priv, reg, ACB_CONTROL);
936 	reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
937 	reg |= ACB_EN | ACB_ALGORITHM;
938 	acb_writel(priv, reg, ACB_CONTROL);
939 }
940 
bcm_sf2_sw_suspend(struct dsa_switch * ds)941 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
942 {
943 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
944 	unsigned int port;
945 
946 	bcm_sf2_intr_disable(priv);
947 
948 	/* Disable all ports physically present including the IMP
949 	 * port, the other ones have already been disabled during
950 	 * bcm_sf2_sw_setup
951 	 */
952 	for (port = 0; port < ds->num_ports; port++) {
953 		if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
954 			bcm_sf2_port_disable(ds, port);
955 	}
956 
957 	if (!priv->wol_ports_mask)
958 		clk_disable_unprepare(priv->clk);
959 
960 	return 0;
961 }
962 
bcm_sf2_sw_resume(struct dsa_switch * ds)963 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
964 {
965 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
966 	int ret;
967 
968 	if (!priv->wol_ports_mask)
969 		clk_prepare_enable(priv->clk);
970 
971 	ret = bcm_sf2_sw_rst(priv);
972 	if (ret) {
973 		pr_err("%s: failed to software reset switch\n", __func__);
974 		return ret;
975 	}
976 
977 	bcm_sf2_crossbar_setup(priv);
978 
979 	ret = bcm_sf2_cfp_resume(ds);
980 	if (ret)
981 		return ret;
982 
983 	if (priv->hw_params.num_gphy == 1)
984 		bcm_sf2_gphy_enable_set(ds, true);
985 
986 	ds->ops->setup(ds);
987 
988 	return 0;
989 }
990 
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)991 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
992 			       struct ethtool_wolinfo *wol)
993 {
994 	struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
995 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
996 	struct ethtool_wolinfo pwol = { };
997 
998 	/* Get the parent device WoL settings */
999 	if (p->ethtool_ops->get_wol)
1000 		p->ethtool_ops->get_wol(p, &pwol);
1001 
1002 	/* Advertise the parent device supported settings */
1003 	wol->supported = pwol.supported;
1004 	memset(&wol->sopass, 0, sizeof(wol->sopass));
1005 
1006 	if (pwol.wolopts & WAKE_MAGICSECURE)
1007 		memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1008 
1009 	if (priv->wol_ports_mask & (1 << port))
1010 		wol->wolopts = pwol.wolopts;
1011 	else
1012 		wol->wolopts = 0;
1013 }
1014 
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)1015 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1016 			      struct ethtool_wolinfo *wol)
1017 {
1018 	struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
1019 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1020 	s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1021 	struct ethtool_wolinfo pwol =  { };
1022 
1023 	if (p->ethtool_ops->get_wol)
1024 		p->ethtool_ops->get_wol(p, &pwol);
1025 	if (wol->wolopts & ~pwol.supported)
1026 		return -EINVAL;
1027 
1028 	if (wol->wolopts)
1029 		priv->wol_ports_mask |= (1 << port);
1030 	else
1031 		priv->wol_ports_mask &= ~(1 << port);
1032 
1033 	/* If we have at least one port enabled, make sure the CPU port
1034 	 * is also enabled. If the CPU port is the last one enabled, we disable
1035 	 * it since this configuration does not make sense.
1036 	 */
1037 	if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1038 		priv->wol_ports_mask |= (1 << cpu_port);
1039 	else
1040 		priv->wol_ports_mask &= ~(1 << cpu_port);
1041 
1042 	return p->ethtool_ops->set_wol(p, wol);
1043 }
1044 
bcm_sf2_sw_setup(struct dsa_switch * ds)1045 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1046 {
1047 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1048 	unsigned int port;
1049 
1050 	/* Enable all valid ports and disable those unused */
1051 	for (port = 0; port < priv->hw_params.num_ports; port++) {
1052 		/* IMP port receives special treatment */
1053 		if (dsa_is_user_port(ds, port))
1054 			bcm_sf2_port_setup(ds, port, NULL);
1055 		else if (dsa_is_cpu_port(ds, port))
1056 			bcm_sf2_imp_setup(ds, port);
1057 		else
1058 			bcm_sf2_port_disable(ds, port);
1059 	}
1060 
1061 	b53_configure_vlan(ds);
1062 	bcm_sf2_enable_acb(ds);
1063 
1064 	return b53_setup_devlink_resources(ds);
1065 }
1066 
bcm_sf2_sw_teardown(struct dsa_switch * ds)1067 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1068 {
1069 	dsa_devlink_resources_unregister(ds);
1070 }
1071 
1072 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
1073  * register basis so we need to translate that into an address that the
1074  * bus-glue understands.
1075  */
1076 #define SF2_PAGE_REG_MKADDR(page, reg)	((page) << 10 | (reg) << 2)
1077 
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)1078 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1079 			      u8 *val)
1080 {
1081 	struct bcm_sf2_priv *priv = dev->priv;
1082 
1083 	*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1084 
1085 	return 0;
1086 }
1087 
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)1088 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1089 			       u16 *val)
1090 {
1091 	struct bcm_sf2_priv *priv = dev->priv;
1092 
1093 	*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1094 
1095 	return 0;
1096 }
1097 
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)1098 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1099 			       u32 *val)
1100 {
1101 	struct bcm_sf2_priv *priv = dev->priv;
1102 
1103 	*val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1104 
1105 	return 0;
1106 }
1107 
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)1108 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1109 			       u64 *val)
1110 {
1111 	struct bcm_sf2_priv *priv = dev->priv;
1112 
1113 	*val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1114 
1115 	return 0;
1116 }
1117 
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)1118 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1119 			       u8 value)
1120 {
1121 	struct bcm_sf2_priv *priv = dev->priv;
1122 
1123 	core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1124 
1125 	return 0;
1126 }
1127 
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)1128 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1129 				u16 value)
1130 {
1131 	struct bcm_sf2_priv *priv = dev->priv;
1132 
1133 	core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1134 
1135 	return 0;
1136 }
1137 
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)1138 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1139 				u32 value)
1140 {
1141 	struct bcm_sf2_priv *priv = dev->priv;
1142 
1143 	core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1144 
1145 	return 0;
1146 }
1147 
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)1148 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1149 				u64 value)
1150 {
1151 	struct bcm_sf2_priv *priv = dev->priv;
1152 
1153 	core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1154 
1155 	return 0;
1156 }
1157 
1158 static const struct b53_io_ops bcm_sf2_io_ops = {
1159 	.read8	= bcm_sf2_core_read8,
1160 	.read16	= bcm_sf2_core_read16,
1161 	.read32	= bcm_sf2_core_read32,
1162 	.read48	= bcm_sf2_core_read64,
1163 	.read64	= bcm_sf2_core_read64,
1164 	.write8	= bcm_sf2_core_write8,
1165 	.write16 = bcm_sf2_core_write16,
1166 	.write32 = bcm_sf2_core_write32,
1167 	.write48 = bcm_sf2_core_write64,
1168 	.write64 = bcm_sf2_core_write64,
1169 };
1170 
bcm_sf2_sw_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1171 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1172 				   u32 stringset, uint8_t *data)
1173 {
1174 	int cnt = b53_get_sset_count(ds, port, stringset);
1175 
1176 	b53_get_strings(ds, port, stringset, data);
1177 	bcm_sf2_cfp_get_strings(ds, port, stringset,
1178 				data + cnt * ETH_GSTRING_LEN);
1179 }
1180 
bcm_sf2_sw_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1181 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1182 					 uint64_t *data)
1183 {
1184 	int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1185 
1186 	b53_get_ethtool_stats(ds, port, data);
1187 	bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1188 }
1189 
bcm_sf2_sw_get_sset_count(struct dsa_switch * ds,int port,int sset)1190 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1191 				     int sset)
1192 {
1193 	int cnt = b53_get_sset_count(ds, port, sset);
1194 
1195 	if (cnt < 0)
1196 		return cnt;
1197 
1198 	cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1199 
1200 	return cnt;
1201 }
1202 
1203 static const struct dsa_switch_ops bcm_sf2_ops = {
1204 	.get_tag_protocol	= b53_get_tag_protocol,
1205 	.setup			= bcm_sf2_sw_setup,
1206 	.teardown		= bcm_sf2_sw_teardown,
1207 	.get_strings		= bcm_sf2_sw_get_strings,
1208 	.get_ethtool_stats	= bcm_sf2_sw_get_ethtool_stats,
1209 	.get_sset_count		= bcm_sf2_sw_get_sset_count,
1210 	.get_ethtool_phy_stats	= b53_get_ethtool_phy_stats,
1211 	.get_phy_flags		= bcm_sf2_sw_get_phy_flags,
1212 	.phylink_get_caps	= bcm_sf2_sw_get_caps,
1213 	.phylink_mac_config	= bcm_sf2_sw_mac_config,
1214 	.phylink_mac_link_down	= bcm_sf2_sw_mac_link_down,
1215 	.phylink_mac_link_up	= bcm_sf2_sw_mac_link_up,
1216 	.phylink_fixed_state	= bcm_sf2_sw_fixed_state,
1217 	.suspend		= bcm_sf2_sw_suspend,
1218 	.resume			= bcm_sf2_sw_resume,
1219 	.get_wol		= bcm_sf2_sw_get_wol,
1220 	.set_wol		= bcm_sf2_sw_set_wol,
1221 	.port_enable		= bcm_sf2_port_setup,
1222 	.port_disable		= bcm_sf2_port_disable,
1223 	.get_mac_eee		= b53_get_mac_eee,
1224 	.set_mac_eee		= b53_set_mac_eee,
1225 	.port_bridge_join	= b53_br_join,
1226 	.port_bridge_leave	= b53_br_leave,
1227 	.port_pre_bridge_flags	= b53_br_flags_pre,
1228 	.port_bridge_flags	= b53_br_flags,
1229 	.port_stp_state_set	= b53_br_set_stp_state,
1230 	.port_fast_age		= b53_br_fast_age,
1231 	.port_vlan_filtering	= b53_vlan_filtering,
1232 	.port_vlan_add		= b53_vlan_add,
1233 	.port_vlan_del		= b53_vlan_del,
1234 	.port_fdb_dump		= b53_fdb_dump,
1235 	.port_fdb_add		= b53_fdb_add,
1236 	.port_fdb_del		= b53_fdb_del,
1237 	.get_rxnfc		= bcm_sf2_get_rxnfc,
1238 	.set_rxnfc		= bcm_sf2_set_rxnfc,
1239 	.port_mirror_add	= b53_mirror_add,
1240 	.port_mirror_del	= b53_mirror_del,
1241 	.port_mdb_add		= b53_mdb_add,
1242 	.port_mdb_del		= b53_mdb_del,
1243 };
1244 
1245 struct bcm_sf2_of_data {
1246 	u32 type;
1247 	const u16 *reg_offsets;
1248 	unsigned int core_reg_align;
1249 	unsigned int num_cfp_rules;
1250 	unsigned int num_crossbar_int_ports;
1251 };
1252 
1253 static const u16 bcm_sf2_4908_reg_offsets[] = {
1254 	[REG_SWITCH_CNTRL]	= 0x00,
1255 	[REG_SWITCH_STATUS]	= 0x04,
1256 	[REG_DIR_DATA_WRITE]	= 0x08,
1257 	[REG_DIR_DATA_READ]	= 0x0c,
1258 	[REG_SWITCH_REVISION]	= 0x10,
1259 	[REG_PHY_REVISION]	= 0x14,
1260 	[REG_SPHY_CNTRL]	= 0x24,
1261 	[REG_CROSSBAR]		= 0xc8,
1262 	[REG_RGMII_11_CNTRL]	= 0x014c,
1263 	[REG_LED_0_CNTRL]		= 0x40,
1264 	[REG_LED_1_CNTRL]		= 0x4c,
1265 	[REG_LED_2_CNTRL]		= 0x58,
1266 	[REG_LED_3_CNTRL]		= 0x64,
1267 	[REG_LED_4_CNTRL]		= 0x88,
1268 	[REG_LED_5_CNTRL]		= 0xa0,
1269 	[REG_LED_AGGREGATE_CTRL]	= 0xb8,
1270 
1271 };
1272 
1273 static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1274 	.type		= BCM4908_DEVICE_ID,
1275 	.core_reg_align	= 0,
1276 	.reg_offsets	= bcm_sf2_4908_reg_offsets,
1277 	.num_cfp_rules	= 256,
1278 	.num_crossbar_int_ports = 2,
1279 };
1280 
1281 /* Register offsets for the SWITCH_REG_* block */
1282 static const u16 bcm_sf2_7445_reg_offsets[] = {
1283 	[REG_SWITCH_CNTRL]	= 0x00,
1284 	[REG_SWITCH_STATUS]	= 0x04,
1285 	[REG_DIR_DATA_WRITE]	= 0x08,
1286 	[REG_DIR_DATA_READ]	= 0x0C,
1287 	[REG_SWITCH_REVISION]	= 0x18,
1288 	[REG_PHY_REVISION]	= 0x1C,
1289 	[REG_SPHY_CNTRL]	= 0x2C,
1290 	[REG_RGMII_0_CNTRL]	= 0x34,
1291 	[REG_RGMII_1_CNTRL]	= 0x40,
1292 	[REG_RGMII_2_CNTRL]	= 0x4c,
1293 	[REG_LED_0_CNTRL]	= 0x90,
1294 	[REG_LED_1_CNTRL]	= 0x94,
1295 	[REG_LED_2_CNTRL]	= 0x98,
1296 };
1297 
1298 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1299 	.type		= BCM7445_DEVICE_ID,
1300 	.core_reg_align	= 0,
1301 	.reg_offsets	= bcm_sf2_7445_reg_offsets,
1302 	.num_cfp_rules	= 256,
1303 };
1304 
1305 static const u16 bcm_sf2_7278_reg_offsets[] = {
1306 	[REG_SWITCH_CNTRL]	= 0x00,
1307 	[REG_SWITCH_STATUS]	= 0x04,
1308 	[REG_DIR_DATA_WRITE]	= 0x08,
1309 	[REG_DIR_DATA_READ]	= 0x0c,
1310 	[REG_SWITCH_REVISION]	= 0x10,
1311 	[REG_PHY_REVISION]	= 0x14,
1312 	[REG_SPHY_CNTRL]	= 0x24,
1313 	[REG_RGMII_0_CNTRL]	= 0xe0,
1314 	[REG_RGMII_1_CNTRL]	= 0xec,
1315 	[REG_RGMII_2_CNTRL]	= 0xf8,
1316 	[REG_LED_0_CNTRL]	= 0x40,
1317 	[REG_LED_1_CNTRL]	= 0x4c,
1318 	[REG_LED_2_CNTRL]	= 0x58,
1319 };
1320 
1321 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1322 	.type		= BCM7278_DEVICE_ID,
1323 	.core_reg_align	= 1,
1324 	.reg_offsets	= bcm_sf2_7278_reg_offsets,
1325 	.num_cfp_rules	= 128,
1326 };
1327 
1328 static const struct of_device_id bcm_sf2_of_match[] = {
1329 	{ .compatible = "brcm,bcm4908-switch",
1330 	  .data = &bcm_sf2_4908_data
1331 	},
1332 	{ .compatible = "brcm,bcm7445-switch-v4.0",
1333 	  .data = &bcm_sf2_7445_data
1334 	},
1335 	{ .compatible = "brcm,bcm7278-switch-v4.0",
1336 	  .data = &bcm_sf2_7278_data
1337 	},
1338 	{ .compatible = "brcm,bcm7278-switch-v4.8",
1339 	  .data = &bcm_sf2_7278_data
1340 	},
1341 	{ /* sentinel */ },
1342 };
1343 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1344 
bcm_sf2_sw_probe(struct platform_device * pdev)1345 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1346 {
1347 	const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1348 	struct device_node *dn = pdev->dev.of_node;
1349 	const struct of_device_id *of_id = NULL;
1350 	const struct bcm_sf2_of_data *data;
1351 	struct b53_platform_data *pdata;
1352 	struct dsa_switch_ops *ops;
1353 	struct device_node *ports;
1354 	struct bcm_sf2_priv *priv;
1355 	struct b53_device *dev;
1356 	struct dsa_switch *ds;
1357 	void __iomem **base;
1358 	unsigned int i;
1359 	u32 reg, rev;
1360 	int ret;
1361 
1362 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1363 	if (!priv)
1364 		return -ENOMEM;
1365 
1366 	ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1367 	if (!ops)
1368 		return -ENOMEM;
1369 
1370 	dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1371 	if (!dev)
1372 		return -ENOMEM;
1373 
1374 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1375 	if (!pdata)
1376 		return -ENOMEM;
1377 
1378 	of_id = of_match_node(bcm_sf2_of_match, dn);
1379 	if (!of_id || !of_id->data)
1380 		return -EINVAL;
1381 
1382 	data = of_id->data;
1383 
1384 	/* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1385 	priv->type = data->type;
1386 	priv->reg_offsets = data->reg_offsets;
1387 	priv->core_reg_align = data->core_reg_align;
1388 	priv->num_cfp_rules = data->num_cfp_rules;
1389 	priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1390 
1391 	priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1392 								"switch");
1393 	if (IS_ERR(priv->rcdev))
1394 		return PTR_ERR(priv->rcdev);
1395 
1396 	/* Auto-detection using standard registers will not work, so
1397 	 * provide an indication of what kind of device we are for
1398 	 * b53_common to work with
1399 	 */
1400 	pdata->chip_id = priv->type;
1401 	dev->pdata = pdata;
1402 
1403 	priv->dev = dev;
1404 	ds = dev->ds;
1405 	ds->ops = &bcm_sf2_ops;
1406 
1407 	/* Advertise the 8 egress queues */
1408 	ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1409 
1410 	dev_set_drvdata(&pdev->dev, priv);
1411 
1412 	spin_lock_init(&priv->indir_lock);
1413 	mutex_init(&priv->cfp.lock);
1414 	INIT_LIST_HEAD(&priv->cfp.rules_list);
1415 
1416 	/* CFP rule #0 cannot be used for specific classifications, flag it as
1417 	 * permanently used
1418 	 */
1419 	set_bit(0, priv->cfp.used);
1420 	set_bit(0, priv->cfp.unique);
1421 
1422 	/* Balance of_node_put() done by of_find_node_by_name() */
1423 	of_node_get(dn);
1424 	ports = of_find_node_by_name(dn, "ports");
1425 	if (ports) {
1426 		bcm_sf2_identify_ports(priv, ports);
1427 		of_node_put(ports);
1428 	}
1429 
1430 	priv->irq0 = irq_of_parse_and_map(dn, 0);
1431 	priv->irq1 = irq_of_parse_and_map(dn, 1);
1432 
1433 	base = &priv->core;
1434 	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1435 		*base = devm_platform_ioremap_resource(pdev, i);
1436 		if (IS_ERR(*base)) {
1437 			pr_err("unable to find register: %s\n", reg_names[i]);
1438 			return PTR_ERR(*base);
1439 		}
1440 		base++;
1441 	}
1442 
1443 	priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1444 	if (IS_ERR(priv->clk))
1445 		return PTR_ERR(priv->clk);
1446 
1447 	ret = clk_prepare_enable(priv->clk);
1448 	if (ret)
1449 		return ret;
1450 
1451 	priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1452 	if (IS_ERR(priv->clk_mdiv)) {
1453 		ret = PTR_ERR(priv->clk_mdiv);
1454 		goto out_clk;
1455 	}
1456 
1457 	ret = clk_prepare_enable(priv->clk_mdiv);
1458 	if (ret)
1459 		goto out_clk;
1460 
1461 	ret = bcm_sf2_sw_rst(priv);
1462 	if (ret) {
1463 		pr_err("unable to software reset switch: %d\n", ret);
1464 		goto out_clk_mdiv;
1465 	}
1466 
1467 	bcm_sf2_crossbar_setup(priv);
1468 
1469 	bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1470 
1471 	ret = bcm_sf2_mdio_register(ds);
1472 	if (ret) {
1473 		pr_err("failed to register MDIO bus\n");
1474 		goto out_clk_mdiv;
1475 	}
1476 
1477 	bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1478 
1479 	ret = bcm_sf2_cfp_rst(priv);
1480 	if (ret) {
1481 		pr_err("failed to reset CFP\n");
1482 		goto out_mdio;
1483 	}
1484 
1485 	/* Disable all interrupts and request them */
1486 	bcm_sf2_intr_disable(priv);
1487 
1488 	ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1489 			       "switch_0", ds);
1490 	if (ret < 0) {
1491 		pr_err("failed to request switch_0 IRQ\n");
1492 		goto out_mdio;
1493 	}
1494 
1495 	ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1496 			       "switch_1", ds);
1497 	if (ret < 0) {
1498 		pr_err("failed to request switch_1 IRQ\n");
1499 		goto out_mdio;
1500 	}
1501 
1502 	/* Reset the MIB counters */
1503 	reg = core_readl(priv, CORE_GMNCFGCFG);
1504 	reg |= RST_MIB_CNT;
1505 	core_writel(priv, reg, CORE_GMNCFGCFG);
1506 	reg &= ~RST_MIB_CNT;
1507 	core_writel(priv, reg, CORE_GMNCFGCFG);
1508 
1509 	/* Get the maximum number of ports for this switch */
1510 	priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1511 	if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1512 		priv->hw_params.num_ports = DSA_MAX_PORTS;
1513 
1514 	/* Assume a single GPHY setup if we can't read that property */
1515 	if (of_property_read_u32(dn, "brcm,num-gphy",
1516 				 &priv->hw_params.num_gphy))
1517 		priv->hw_params.num_gphy = 1;
1518 
1519 	rev = reg_readl(priv, REG_SWITCH_REVISION);
1520 	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1521 					SWITCH_TOP_REV_MASK;
1522 	priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1523 
1524 	rev = reg_readl(priv, REG_PHY_REVISION);
1525 	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1526 
1527 	ret = b53_switch_register(dev);
1528 	if (ret)
1529 		goto out_mdio;
1530 
1531 	dev_info(&pdev->dev,
1532 		 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1533 		 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1534 		 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1535 		 priv->irq0, priv->irq1);
1536 
1537 	return 0;
1538 
1539 out_mdio:
1540 	bcm_sf2_mdio_unregister(priv);
1541 out_clk_mdiv:
1542 	clk_disable_unprepare(priv->clk_mdiv);
1543 out_clk:
1544 	clk_disable_unprepare(priv->clk);
1545 	return ret;
1546 }
1547 
bcm_sf2_sw_remove(struct platform_device * pdev)1548 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1549 {
1550 	struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1551 
1552 	if (!priv)
1553 		return 0;
1554 
1555 	priv->wol_ports_mask = 0;
1556 	/* Disable interrupts */
1557 	bcm_sf2_intr_disable(priv);
1558 	dsa_unregister_switch(priv->dev->ds);
1559 	bcm_sf2_cfp_exit(priv->dev->ds);
1560 	bcm_sf2_mdio_unregister(priv);
1561 	clk_disable_unprepare(priv->clk_mdiv);
1562 	clk_disable_unprepare(priv->clk);
1563 	if (priv->type == BCM7278_DEVICE_ID)
1564 		reset_control_assert(priv->rcdev);
1565 
1566 	return 0;
1567 }
1568 
bcm_sf2_sw_shutdown(struct platform_device * pdev)1569 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1570 {
1571 	struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1572 
1573 	if (!priv)
1574 		return;
1575 
1576 	/* For a kernel about to be kexec'd we want to keep the GPHY on for a
1577 	 * successful MDIO bus scan to occur. If we did turn off the GPHY
1578 	 * before (e.g: port_disable), this will also power it back on.
1579 	 *
1580 	 * Do not rely on kexec_in_progress, just power the PHY on.
1581 	 */
1582 	if (priv->hw_params.num_gphy == 1)
1583 		bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1584 
1585 	dsa_switch_shutdown(priv->dev->ds);
1586 
1587 	platform_set_drvdata(pdev, NULL);
1588 }
1589 
1590 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1591 static int bcm_sf2_suspend(struct device *dev)
1592 {
1593 	struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1594 
1595 	return dsa_switch_suspend(priv->dev->ds);
1596 }
1597 
bcm_sf2_resume(struct device * dev)1598 static int bcm_sf2_resume(struct device *dev)
1599 {
1600 	struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1601 
1602 	return dsa_switch_resume(priv->dev->ds);
1603 }
1604 #endif /* CONFIG_PM_SLEEP */
1605 
1606 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1607 			 bcm_sf2_suspend, bcm_sf2_resume);
1608 
1609 
1610 static struct platform_driver bcm_sf2_driver = {
1611 	.probe	= bcm_sf2_sw_probe,
1612 	.remove	= bcm_sf2_sw_remove,
1613 	.shutdown = bcm_sf2_sw_shutdown,
1614 	.driver = {
1615 		.name = "brcm-sf2",
1616 		.of_match_table = bcm_sf2_of_match,
1617 		.pm = &bcm_sf2_pm_ops,
1618 	},
1619 };
1620 module_platform_driver(bcm_sf2_driver);
1621 
1622 MODULE_AUTHOR("Broadcom Corporation");
1623 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1624 MODULE_LICENSE("GPL");
1625 MODULE_ALIAS("platform:brcm-sf2");
1626