xref: /openbmc/qemu/hw/arm/bcm2838_peripherals.c (revision d8a57715)
1 /*
2  * BCM2838 peripherals emulation
3  *
4  * Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "qemu/module.h"
12 #include "hw/arm/raspi_platform.h"
13 #include "hw/arm/bcm2838_peripherals.h"
14 
15 #define CLOCK_ISP_OFFSET        0xc11000
16 #define CLOCK_ISP_SIZE          0x100
17 
18 /* Lower peripheral base address on the VC (GPU) system bus */
19 #define BCM2838_VC_PERI_LOW_BASE 0x7c000000
20 
21 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
22 #define BCM2835_SDHC_CAPAREG 0x52134b4
23 
bcm2838_peripherals_init(Object * obj)24 static void bcm2838_peripherals_init(Object *obj)
25 {
26     BCM2838PeripheralState *s = BCM2838_PERIPHERALS(obj);
27     BCM2838PeripheralClass *bc = BCM2838_PERIPHERALS_GET_CLASS(obj);
28     BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(obj);
29 
30     /* Lower memory region for peripheral devices (exported to the Soc) */
31     memory_region_init(&s->peri_low_mr, obj, "bcm2838-peripherals",
32                        bc->peri_low_size);
33     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_low_mr);
34 
35     /* Extended Mass Media Controller 2 */
36     object_initialize_child(obj, "emmc2", &s->emmc2, TYPE_SYSBUS_SDHCI);
37 
38     /* GPIO */
39     object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2838_GPIO);
40 
41     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
42                                    OBJECT(&s_base->sdhci.sdbus));
43     object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
44                                    OBJECT(&s_base->sdhost.sdbus));
45 
46     object_initialize_child(obj, "mmc_irq_orgate", &s->mmc_irq_orgate,
47                             TYPE_OR_IRQ);
48     object_property_set_int(OBJECT(&s->mmc_irq_orgate), "num-lines", 2,
49                             &error_abort);
50 
51     object_initialize_child(obj, "dma_7_8_irq_orgate", &s->dma_7_8_irq_orgate,
52                             TYPE_OR_IRQ);
53     object_property_set_int(OBJECT(&s->dma_7_8_irq_orgate), "num-lines", 2,
54                             &error_abort);
55 
56     object_initialize_child(obj, "dma_9_10_irq_orgate", &s->dma_9_10_irq_orgate,
57                             TYPE_OR_IRQ);
58     object_property_set_int(OBJECT(&s->dma_9_10_irq_orgate), "num-lines", 2,
59                             &error_abort);
60 }
61 
bcm2838_peripherals_realize(DeviceState * dev,Error ** errp)62 static void bcm2838_peripherals_realize(DeviceState *dev, Error **errp)
63 {
64     DeviceState *mmc_irq_orgate;
65     DeviceState *dma_7_8_irq_orgate;
66     DeviceState *dma_9_10_irq_orgate;
67     MemoryRegion *mphi_mr;
68     BCM2838PeripheralState *s = BCM2838_PERIPHERALS(dev);
69     BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(dev);
70     int n;
71 
72     bcm_soc_peripherals_common_realize(dev, errp);
73 
74     /* Map lower peripherals into the GPU address space */
75     memory_region_init_alias(&s->peri_low_mr_alias, OBJECT(s),
76                              "bcm2838-peripherals", &s->peri_low_mr, 0,
77                              memory_region_size(&s->peri_low_mr));
78     memory_region_add_subregion_overlap(&s_base->gpu_bus_mr,
79                                         BCM2838_VC_PERI_LOW_BASE,
80                                         &s->peri_low_mr_alias, 1);
81 
82     /* Extended Mass Media Controller 2 */
83     object_property_set_uint(OBJECT(&s->emmc2), "sd-spec-version", 3,
84                              &error_abort);
85     object_property_set_uint(OBJECT(&s->emmc2), "capareg",
86                              BCM2835_SDHC_CAPAREG, &error_abort);
87     object_property_set_bool(OBJECT(&s->emmc2), "pending-insert-quirk", true,
88                              &error_abort);
89     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc2), errp)) {
90         return;
91     }
92 
93     memory_region_add_subregion(&s_base->peri_mr, EMMC2_OFFSET,
94                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->emmc2),
95                                 0));
96 
97     /* According to DTS, EMMC and EMMC2 share one irq */
98     if (!qdev_realize(DEVICE(&s->mmc_irq_orgate), NULL, errp)) {
99         return;
100     }
101 
102     mmc_irq_orgate = DEVICE(&s->mmc_irq_orgate);
103     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc2), 0,
104                        qdev_get_gpio_in(mmc_irq_orgate, 0));
105 
106     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0,
107                        qdev_get_gpio_in(mmc_irq_orgate, 1));
108 
109    /* Connect EMMC and EMMC2 to the interrupt controller */
110     qdev_connect_gpio_out(mmc_irq_orgate, 0,
111                           qdev_get_gpio_in_named(DEVICE(&s_base->ic),
112                                                  BCM2835_IC_GPU_IRQ,
113                                                  INTERRUPT_ARASANSDIO));
114 
115     /* Connect DMA 0-6 to the interrupt controller */
116     for (n = 0; n < 7; n++) {
117         sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n,
118                            qdev_get_gpio_in_named(DEVICE(&s_base->ic),
119                                                   BCM2835_IC_GPU_IRQ,
120                                                   GPU_INTERRUPT_DMA0 + n));
121     }
122 
123    /* According to DTS, DMA 7 and 8 share one irq */
124     if (!qdev_realize(DEVICE(&s->dma_7_8_irq_orgate), NULL, errp)) {
125         return;
126     }
127     dma_7_8_irq_orgate = DEVICE(&s->dma_7_8_irq_orgate);
128 
129     /* Connect DMA 7-8 to the interrupt controller */
130     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 7,
131                        qdev_get_gpio_in(dma_7_8_irq_orgate, 0));
132     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 8,
133                        qdev_get_gpio_in(dma_7_8_irq_orgate, 1));
134 
135     qdev_connect_gpio_out(dma_7_8_irq_orgate, 0,
136                           qdev_get_gpio_in_named(DEVICE(&s_base->ic),
137                                                  BCM2835_IC_GPU_IRQ,
138                                                  GPU_INTERRUPT_DMA7_8));
139 
140      /* According to DTS, DMA 9 and 10 share one irq */
141     if (!qdev_realize(DEVICE(&s->dma_9_10_irq_orgate), NULL, errp)) {
142         return;
143     }
144     dma_9_10_irq_orgate = DEVICE(&s->dma_9_10_irq_orgate);
145 
146    /* Connect DMA 9-10 to the interrupt controller */
147     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 9,
148                        qdev_get_gpio_in(dma_9_10_irq_orgate, 0));
149     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 10,
150                        qdev_get_gpio_in(dma_9_10_irq_orgate, 1));
151 
152     qdev_connect_gpio_out(dma_9_10_irq_orgate, 0,
153                           qdev_get_gpio_in_named(DEVICE(&s_base->ic),
154                                                  BCM2835_IC_GPU_IRQ,
155                                                  GPU_INTERRUPT_DMA9_10));
156 
157     /* Connect DMA 11-14 to the interrupt controller */
158     for (n = 11; n < 15; n++) {
159         sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n,
160                            qdev_get_gpio_in_named(DEVICE(&s_base->ic),
161                                                   BCM2835_IC_GPU_IRQ,
162                                                   GPU_INTERRUPT_DMA11 + n
163                                                   - 11));
164     }
165 
166     /*
167      * Connect DMA 15 to the interrupt controller, it is physically removed
168      * from other DMA channels and exclusively used by the GPU
169      */
170     sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 15,
171                         qdev_get_gpio_in_named(DEVICE(&s_base->ic),
172                                                BCM2835_IC_GPU_IRQ,
173                                                GPU_INTERRUPT_DMA15));
174 
175     /* Map MPHI to BCM2838 memory map */
176     mphi_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s_base->mphi), 0);
177     memory_region_init_alias(&s->mphi_mr_alias, OBJECT(s), "mphi", mphi_mr, 0,
178                              BCM2838_MPHI_SIZE);
179     memory_region_add_subregion(&s_base->peri_mr, BCM2838_MPHI_OFFSET,
180                                 &s->mphi_mr_alias);
181 
182     create_unimp(s_base, &s->clkisp, "bcm2835-clkisp", CLOCK_ISP_OFFSET,
183                  CLOCK_ISP_SIZE);
184 
185     /* GPIO */
186     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
187         return;
188     }
189     memory_region_add_subregion(
190         &s_base->peri_mr, GPIO_OFFSET,
191         sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
192 
193     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
194 
195     /* BCM2838 RPiVid ASB must be mapped to prevent kernel crash */
196     create_unimp(s_base, &s->asb, "bcm2838-asb", BRDG_OFFSET, 0x24);
197 }
198 
bcm2838_peripherals_class_init(ObjectClass * oc,void * data)199 static void bcm2838_peripherals_class_init(ObjectClass *oc, void *data)
200 {
201     DeviceClass *dc = DEVICE_CLASS(oc);
202     BCM2838PeripheralClass *bc = BCM2838_PERIPHERALS_CLASS(oc);
203     BCMSocPeripheralBaseClass *bc_base = BCM_SOC_PERIPHERALS_BASE_CLASS(oc);
204 
205     bc->peri_low_size = 0x2000000;
206     bc_base->peri_size = 0x1800000;
207     dc->realize = bcm2838_peripherals_realize;
208 }
209 
210 static const TypeInfo bcm2838_peripherals_type_info = {
211     .name = TYPE_BCM2838_PERIPHERALS,
212     .parent = TYPE_BCM_SOC_PERIPHERALS_BASE,
213     .instance_size = sizeof(BCM2838PeripheralState),
214     .instance_init = bcm2838_peripherals_init,
215     .class_size = sizeof(BCM2838PeripheralClass),
216     .class_init = bcm2838_peripherals_class_init,
217 };
218 
bcm2838_peripherals_register_types(void)219 static void bcm2838_peripherals_register_types(void)
220 {
221     type_register_static(&bcm2838_peripherals_type_info);
222 }
223 
224 type_init(bcm2838_peripherals_register_types)
225