1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr) {
679 dma_unmap_single(ab->dev, rx_tid->paddr,
680 rx_tid->size, DMA_BIDIRECTIONAL);
681 kfree(rx_tid->vaddr);
682 rx_tid->vaddr = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr) {
693 dma_unmap_single(ab->dev, rx_tid->paddr,
694 rx_tid->size, DMA_BIDIRECTIONAL);
695 kfree(rx_tid->vaddr);
696 rx_tid->vaddr = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr) {
712 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
713 DMA_BIDIRECTIONAL);
714 kfree(rx_tid->vaddr);
715 rx_tid->vaddr = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {0};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
753 DMA_BIDIRECTIONAL);
754 kfree(rx_tid->vaddr);
755 rx_tid->vaddr = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
806 DMA_BIDIRECTIONAL);
807 kfree(rx_tid->vaddr);
808 rx_tid->vaddr = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {0};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
835 DMA_BIDIRECTIONAL);
836 kfree(rx_tid->vaddr);
837 rx_tid->vaddr = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->size = 0;
842 }
843
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)844 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
845 u32 *link_desc,
846 enum hal_wbm_rel_bm_act action)
847 {
848 struct ath11k_dp *dp = &ab->dp;
849 struct hal_srng *srng;
850 u32 *desc;
851 int ret = 0;
852
853 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
854
855 spin_lock_bh(&srng->lock);
856
857 ath11k_hal_srng_access_begin(ab, srng);
858
859 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
860 if (!desc) {
861 ret = -ENOBUFS;
862 goto exit;
863 }
864
865 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
866 action);
867
868 exit:
869 ath11k_hal_srng_access_end(ab, srng);
870
871 spin_unlock_bh(&srng->lock);
872
873 return ret;
874 }
875
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)876 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
877 {
878 struct ath11k_base *ab = rx_tid->ab;
879
880 lockdep_assert_held(&ab->base_lock);
881
882 if (rx_tid->dst_ring_desc) {
883 if (rel_link_desc)
884 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
885 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
886 kfree(rx_tid->dst_ring_desc);
887 rx_tid->dst_ring_desc = NULL;
888 }
889
890 rx_tid->cur_sn = 0;
891 rx_tid->last_frag_no = 0;
892 rx_tid->rx_frag_bitmap = 0;
893 __skb_queue_purge(&rx_tid->rx_frags);
894 }
895
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)896 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
897 {
898 struct dp_rx_tid *rx_tid;
899 int i;
900
901 lockdep_assert_held(&ar->ab->base_lock);
902
903 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
904 rx_tid = &peer->rx_tid[i];
905
906 spin_unlock_bh(&ar->ab->base_lock);
907 del_timer_sync(&rx_tid->frag_timer);
908 spin_lock_bh(&ar->ab->base_lock);
909
910 ath11k_dp_rx_frags_cleanup(rx_tid, true);
911 }
912 }
913
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)914 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
915 {
916 struct dp_rx_tid *rx_tid;
917 int i;
918
919 lockdep_assert_held(&ar->ab->base_lock);
920
921 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
922 rx_tid = &peer->rx_tid[i];
923
924 ath11k_peer_rx_tid_delete(ar, peer, i);
925 ath11k_dp_rx_frags_cleanup(rx_tid, true);
926
927 spin_unlock_bh(&ar->ab->base_lock);
928 del_timer_sync(&rx_tid->frag_timer);
929 spin_lock_bh(&ar->ab->base_lock);
930 }
931 }
932
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)933 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
934 struct ath11k_peer *peer,
935 struct dp_rx_tid *rx_tid,
936 u32 ba_win_sz, u16 ssn,
937 bool update_ssn)
938 {
939 struct ath11k_hal_reo_cmd cmd = {0};
940 int ret;
941
942 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
943 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
944 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
945 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
946 cmd.ba_window_size = ba_win_sz;
947
948 if (update_ssn) {
949 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
950 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
951 }
952
953 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
954 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
955 NULL);
956 if (ret) {
957 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
958 rx_tid->tid, ret);
959 return ret;
960 }
961
962 rx_tid->ba_win_sz = ba_win_sz;
963
964 return 0;
965 }
966
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)967 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
968 const u8 *peer_mac, int vdev_id, u8 tid)
969 {
970 struct ath11k_peer *peer;
971 struct dp_rx_tid *rx_tid;
972
973 spin_lock_bh(&ab->base_lock);
974
975 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
976 if (!peer) {
977 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
978 goto unlock_exit;
979 }
980
981 rx_tid = &peer->rx_tid[tid];
982 if (!rx_tid->active)
983 goto unlock_exit;
984
985 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
986 DMA_BIDIRECTIONAL);
987 kfree(rx_tid->vaddr);
988 rx_tid->vaddr = NULL;
989
990 rx_tid->active = false;
991
992 unlock_exit:
993 spin_unlock_bh(&ab->base_lock);
994 }
995
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)996 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
997 u8 tid, u32 ba_win_sz, u16 ssn,
998 enum hal_pn_type pn_type)
999 {
1000 struct ath11k_base *ab = ar->ab;
1001 struct ath11k_peer *peer;
1002 struct dp_rx_tid *rx_tid;
1003 u32 hw_desc_sz;
1004 u32 *addr_aligned;
1005 void *vaddr;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1054 if (!vaddr) {
1055 spin_unlock_bh(&ab->base_lock);
1056 return -ENOMEM;
1057 }
1058
1059 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1060
1061 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1062 ssn, pn_type);
1063
1064 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1065 DMA_BIDIRECTIONAL);
1066
1067 ret = dma_mapping_error(ab->dev, paddr);
1068 if (ret) {
1069 spin_unlock_bh(&ab->base_lock);
1070 ath11k_warn(ab, "failed to setup dma map for peer %pM rx tid %d: %d\n",
1071 peer_mac, tid, ret);
1072 goto err_mem_free;
1073 }
1074
1075 rx_tid->vaddr = vaddr;
1076 rx_tid->paddr = paddr;
1077 rx_tid->size = hw_desc_sz;
1078 rx_tid->active = true;
1079
1080 spin_unlock_bh(&ab->base_lock);
1081
1082 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1083 paddr, tid, 1, ba_win_sz);
1084 if (ret) {
1085 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1086 peer_mac, tid, ret);
1087 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1088 }
1089
1090 return ret;
1091
1092 err_mem_free:
1093 kfree(rx_tid->vaddr);
1094 rx_tid->vaddr = NULL;
1095
1096 return ret;
1097 }
1098
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1099 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1100 struct ieee80211_ampdu_params *params)
1101 {
1102 struct ath11k_base *ab = ar->ab;
1103 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1104 int vdev_id = arsta->arvif->vdev_id;
1105 int ret;
1106
1107 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1108 params->tid, params->buf_size,
1109 params->ssn, arsta->pn_type);
1110 if (ret)
1111 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1112
1113 return ret;
1114 }
1115
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1116 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1117 struct ieee80211_ampdu_params *params)
1118 {
1119 struct ath11k_base *ab = ar->ab;
1120 struct ath11k_peer *peer;
1121 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1122 int vdev_id = arsta->arvif->vdev_id;
1123 dma_addr_t paddr;
1124 bool active;
1125 int ret;
1126
1127 spin_lock_bh(&ab->base_lock);
1128
1129 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1130 if (!peer) {
1131 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1132 spin_unlock_bh(&ab->base_lock);
1133 return -ENOENT;
1134 }
1135
1136 paddr = peer->rx_tid[params->tid].paddr;
1137 active = peer->rx_tid[params->tid].active;
1138
1139 if (!active) {
1140 spin_unlock_bh(&ab->base_lock);
1141 return 0;
1142 }
1143
1144 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1145 spin_unlock_bh(&ab->base_lock);
1146 if (ret) {
1147 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1148 params->tid, ret);
1149 return ret;
1150 }
1151
1152 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1153 params->sta->addr, paddr,
1154 params->tid, 1, 1);
1155 if (ret)
1156 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1157 ret);
1158
1159 return ret;
1160 }
1161
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1162 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1163 const u8 *peer_addr,
1164 enum set_key_cmd key_cmd,
1165 struct ieee80211_key_conf *key)
1166 {
1167 struct ath11k *ar = arvif->ar;
1168 struct ath11k_base *ab = ar->ab;
1169 struct ath11k_hal_reo_cmd cmd = {0};
1170 struct ath11k_peer *peer;
1171 struct dp_rx_tid *rx_tid;
1172 u8 tid;
1173 int ret = 0;
1174
1175 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1176 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1177 * for now.
1178 */
1179 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1180 return 0;
1181
1182 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1183 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1184 HAL_REO_CMD_UPD0_PN_SIZE |
1185 HAL_REO_CMD_UPD0_PN_VALID |
1186 HAL_REO_CMD_UPD0_PN_CHECK |
1187 HAL_REO_CMD_UPD0_SVLD;
1188
1189 switch (key->cipher) {
1190 case WLAN_CIPHER_SUITE_TKIP:
1191 case WLAN_CIPHER_SUITE_CCMP:
1192 case WLAN_CIPHER_SUITE_CCMP_256:
1193 case WLAN_CIPHER_SUITE_GCMP:
1194 case WLAN_CIPHER_SUITE_GCMP_256:
1195 if (key_cmd == SET_KEY) {
1196 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1197 cmd.pn_size = 48;
1198 }
1199 break;
1200 default:
1201 break;
1202 }
1203
1204 spin_lock_bh(&ab->base_lock);
1205
1206 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1207 if (!peer) {
1208 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1209 spin_unlock_bh(&ab->base_lock);
1210 return -ENOENT;
1211 }
1212
1213 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1214 rx_tid = &peer->rx_tid[tid];
1215 if (!rx_tid->active)
1216 continue;
1217 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1218 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1219 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1220 HAL_REO_CMD_UPDATE_RX_QUEUE,
1221 &cmd, NULL);
1222 if (ret) {
1223 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1224 tid, ret);
1225 break;
1226 }
1227 }
1228
1229 spin_unlock_bh(&ab->base_lock);
1230
1231 return ret;
1232 }
1233
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1234 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1235 u16 peer_id)
1236 {
1237 int i;
1238
1239 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1240 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1241 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1242 return i;
1243 } else {
1244 return i;
1245 }
1246 }
1247
1248 return -EINVAL;
1249 }
1250
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1251 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1252 u16 tag, u16 len, const void *ptr,
1253 void *data)
1254 {
1255 struct htt_ppdu_stats_info *ppdu_info;
1256 struct htt_ppdu_user_stats *user_stats;
1257 int cur_user;
1258 u16 peer_id;
1259
1260 ppdu_info = (struct htt_ppdu_stats_info *)data;
1261
1262 switch (tag) {
1263 case HTT_PPDU_STATS_TAG_COMMON:
1264 if (len < sizeof(struct htt_ppdu_stats_common)) {
1265 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 len, tag);
1267 return -EINVAL;
1268 }
1269 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1270 sizeof(struct htt_ppdu_stats_common));
1271 break;
1272 case HTT_PPDU_STATS_TAG_USR_RATE:
1273 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1274 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1275 len, tag);
1276 return -EINVAL;
1277 }
1278
1279 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1280 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1281 peer_id);
1282 if (cur_user < 0)
1283 return -EINVAL;
1284 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1285 user_stats->peer_id = peer_id;
1286 user_stats->is_valid_peer_id = true;
1287 memcpy((void *)&user_stats->rate, ptr,
1288 sizeof(struct htt_ppdu_stats_user_rate));
1289 user_stats->tlv_flags |= BIT(tag);
1290 break;
1291 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1292 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1293 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1294 len, tag);
1295 return -EINVAL;
1296 }
1297
1298 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1299 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1300 peer_id);
1301 if (cur_user < 0)
1302 return -EINVAL;
1303 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1304 user_stats->peer_id = peer_id;
1305 user_stats->is_valid_peer_id = true;
1306 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1307 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1308 user_stats->tlv_flags |= BIT(tag);
1309 break;
1310 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1311 if (len <
1312 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1313 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1314 len, tag);
1315 return -EINVAL;
1316 }
1317
1318 peer_id =
1319 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1320 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1321 peer_id);
1322 if (cur_user < 0)
1323 return -EINVAL;
1324 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1325 user_stats->peer_id = peer_id;
1326 user_stats->is_valid_peer_id = true;
1327 memcpy((void *)&user_stats->ack_ba, ptr,
1328 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1329 user_stats->tlv_flags |= BIT(tag);
1330 break;
1331 }
1332 return 0;
1333 }
1334
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1335 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1336 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1337 const void *ptr, void *data),
1338 void *data)
1339 {
1340 const struct htt_tlv *tlv;
1341 const void *begin = ptr;
1342 u16 tlv_tag, tlv_len;
1343 int ret = -EINVAL;
1344
1345 while (len > 0) {
1346 if (len < sizeof(*tlv)) {
1347 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1348 ptr - begin, len, sizeof(*tlv));
1349 return -EINVAL;
1350 }
1351 tlv = (struct htt_tlv *)ptr;
1352 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1353 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1354 ptr += sizeof(*tlv);
1355 len -= sizeof(*tlv);
1356
1357 if (tlv_len > len) {
1358 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1359 tlv_tag, ptr - begin, len, tlv_len);
1360 return -EINVAL;
1361 }
1362 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1363 if (ret == -ENOMEM)
1364 return ret;
1365
1366 ptr += tlv_len;
1367 len -= tlv_len;
1368 }
1369 return 0;
1370 }
1371
1372 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1373 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1374 struct htt_ppdu_stats *ppdu_stats, u8 user)
1375 {
1376 struct ath11k_base *ab = ar->ab;
1377 struct ath11k_peer *peer;
1378 struct ieee80211_sta *sta;
1379 struct ath11k_sta *arsta;
1380 struct htt_ppdu_stats_user_rate *user_rate;
1381 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1382 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1383 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1384 int ret;
1385 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1386 u32 succ_bytes = 0;
1387 u16 rate = 0, succ_pkts = 0;
1388 u32 tx_duration = 0;
1389 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1390 bool is_ampdu = false;
1391
1392 if (!usr_stats)
1393 return;
1394
1395 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1396 return;
1397
1398 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1399 is_ampdu =
1400 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1401
1402 if (usr_stats->tlv_flags &
1403 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1404 succ_bytes = usr_stats->ack_ba.success_bytes;
1405 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1406 usr_stats->ack_ba.info);
1407 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1408 usr_stats->ack_ba.info);
1409 }
1410
1411 if (common->fes_duration_us)
1412 tx_duration = common->fes_duration_us;
1413
1414 user_rate = &usr_stats->rate;
1415 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1416 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1417 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1418 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1419 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1420 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1421
1422 /* Note: If host configured fixed rates and in some other special
1423 * cases, the broadcast/management frames are sent in different rates.
1424 * Firmware rate's control to be skipped for this?
1425 */
1426
1427 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1428 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1429 return;
1430 }
1431
1432 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1433 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1434 return;
1435 }
1436
1437 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1438 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1439 mcs, nss);
1440 return;
1441 }
1442
1443 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1444 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1445 flags,
1446 &rate_idx,
1447 &rate);
1448 if (ret < 0)
1449 return;
1450 }
1451
1452 rcu_read_lock();
1453 spin_lock_bh(&ab->base_lock);
1454 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1455
1456 if (!peer || !peer->sta) {
1457 spin_unlock_bh(&ab->base_lock);
1458 rcu_read_unlock();
1459 return;
1460 }
1461
1462 sta = peer->sta;
1463 arsta = (struct ath11k_sta *)sta->drv_priv;
1464
1465 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1466
1467 switch (flags) {
1468 case WMI_RATE_PREAMBLE_OFDM:
1469 arsta->txrate.legacy = rate;
1470 break;
1471 case WMI_RATE_PREAMBLE_CCK:
1472 arsta->txrate.legacy = rate;
1473 break;
1474 case WMI_RATE_PREAMBLE_HT:
1475 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1476 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1477 if (sgi)
1478 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1479 break;
1480 case WMI_RATE_PREAMBLE_VHT:
1481 arsta->txrate.mcs = mcs;
1482 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1483 if (sgi)
1484 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1485 break;
1486 case WMI_RATE_PREAMBLE_HE:
1487 arsta->txrate.mcs = mcs;
1488 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1489 arsta->txrate.he_dcm = dcm;
1490 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1491 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1492 ((user_rate->ru_end -
1493 user_rate->ru_start) + 1);
1494 break;
1495 }
1496
1497 arsta->txrate.nss = nss;
1498
1499 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1500 arsta->tx_duration += tx_duration;
1501 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1502
1503 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1504 * So skip peer stats update for mgmt packets.
1505 */
1506 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1507 memset(peer_stats, 0, sizeof(*peer_stats));
1508 peer_stats->succ_pkts = succ_pkts;
1509 peer_stats->succ_bytes = succ_bytes;
1510 peer_stats->is_ampdu = is_ampdu;
1511 peer_stats->duration = tx_duration;
1512 peer_stats->ba_fails =
1513 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1514 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1515
1516 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1517 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1518 }
1519
1520 spin_unlock_bh(&ab->base_lock);
1521 rcu_read_unlock();
1522 }
1523
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1524 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1525 struct htt_ppdu_stats *ppdu_stats)
1526 {
1527 u8 user;
1528
1529 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1530 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1531 }
1532
1533 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1534 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1535 u32 ppdu_id)
1536 {
1537 struct htt_ppdu_stats_info *ppdu_info;
1538
1539 lockdep_assert_held(&ar->data_lock);
1540
1541 if (!list_empty(&ar->ppdu_stats_info)) {
1542 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1543 if (ppdu_info->ppdu_id == ppdu_id)
1544 return ppdu_info;
1545 }
1546
1547 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1548 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1549 typeof(*ppdu_info), list);
1550 list_del(&ppdu_info->list);
1551 ar->ppdu_stat_list_depth--;
1552 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1553 kfree(ppdu_info);
1554 }
1555 }
1556
1557 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1558 if (!ppdu_info)
1559 return NULL;
1560
1561 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1562 ar->ppdu_stat_list_depth++;
1563
1564 return ppdu_info;
1565 }
1566
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1567 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1568 struct sk_buff *skb)
1569 {
1570 struct ath11k_htt_ppdu_stats_msg *msg;
1571 struct htt_ppdu_stats_info *ppdu_info;
1572 struct ath11k *ar;
1573 int ret;
1574 u8 pdev_id;
1575 u32 ppdu_id, len;
1576
1577 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1578 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1579 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1580 ppdu_id = msg->ppdu_id;
1581
1582 rcu_read_lock();
1583 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1584 if (!ar) {
1585 ret = -EINVAL;
1586 goto out;
1587 }
1588
1589 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1590 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1591
1592 spin_lock_bh(&ar->data_lock);
1593 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1594 if (!ppdu_info) {
1595 ret = -EINVAL;
1596 goto out_unlock_data;
1597 }
1598
1599 ppdu_info->ppdu_id = ppdu_id;
1600 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1601 ath11k_htt_tlv_ppdu_stats_parse,
1602 (void *)ppdu_info);
1603 if (ret) {
1604 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1605 goto out_unlock_data;
1606 }
1607
1608 out_unlock_data:
1609 spin_unlock_bh(&ar->data_lock);
1610
1611 out:
1612 rcu_read_unlock();
1613
1614 return ret;
1615 }
1616
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1617 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1618 {
1619 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1620 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1621 struct ath11k *ar;
1622 u8 pdev_id;
1623
1624 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1625
1626 rcu_read_lock();
1627
1628 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1629 if (!ar) {
1630 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1631 goto out;
1632 }
1633
1634 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1635 ar->ab->pktlog_defs_checksum);
1636
1637 out:
1638 rcu_read_unlock();
1639 }
1640
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1641 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1642 struct sk_buff *skb)
1643 {
1644 u32 *data = (u32 *)skb->data;
1645 u8 pdev_id, ring_type, ring_id, pdev_idx;
1646 u16 hp, tp;
1647 u32 backpressure_time;
1648 struct ath11k_bp_stats *bp_stats;
1649
1650 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1651 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1652 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1653 ++data;
1654
1655 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1656 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1657 ++data;
1658
1659 backpressure_time = *data;
1660
1661 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1662 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1663
1664 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1665 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1666 return;
1667
1668 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1669 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1670 pdev_idx = DP_HW2SW_MACID(pdev_id);
1671
1672 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1673 return;
1674
1675 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1676 } else {
1677 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1678 ring_type);
1679 return;
1680 }
1681
1682 spin_lock_bh(&ab->base_lock);
1683 bp_stats->hp = hp;
1684 bp_stats->tp = tp;
1685 bp_stats->count++;
1686 bp_stats->jiffies = jiffies;
1687 spin_unlock_bh(&ab->base_lock);
1688 }
1689
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1690 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1691 struct sk_buff *skb)
1692 {
1693 struct ath11k_dp *dp = &ab->dp;
1694 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1695 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1696 u16 peer_id;
1697 u8 vdev_id;
1698 u8 mac_addr[ETH_ALEN];
1699 u16 peer_mac_h16;
1700 u16 ast_hash;
1701 u16 hw_peer_id;
1702
1703 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1704
1705 switch (type) {
1706 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1707 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1708 resp->version_msg.version);
1709 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1710 resp->version_msg.version);
1711 complete(&dp->htt_tgt_version_received);
1712 break;
1713 case HTT_T2H_MSG_TYPE_PEER_MAP:
1714 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1715 resp->peer_map_ev.info);
1716 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1717 resp->peer_map_ev.info);
1718 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1719 resp->peer_map_ev.info1);
1720 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1721 peer_mac_h16, mac_addr);
1722 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1723 break;
1724 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1725 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1726 resp->peer_map_ev.info);
1727 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1728 resp->peer_map_ev.info);
1729 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1730 resp->peer_map_ev.info1);
1731 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1732 peer_mac_h16, mac_addr);
1733 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1734 resp->peer_map_ev.info2);
1735 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1736 resp->peer_map_ev.info1);
1737 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1738 hw_peer_id);
1739 break;
1740 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1741 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1742 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1743 resp->peer_unmap_ev.info);
1744 ath11k_peer_unmap_event(ab, peer_id);
1745 break;
1746 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1747 ath11k_htt_pull_ppdu_stats(ab, skb);
1748 break;
1749 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1750 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1751 break;
1752 case HTT_T2H_MSG_TYPE_PKTLOG:
1753 ath11k_htt_pktlog(ab, skb);
1754 break;
1755 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1756 ath11k_htt_backpressure_event_handler(ab, skb);
1757 break;
1758 default:
1759 ath11k_warn(ab, "htt event %d not handled\n", type);
1760 break;
1761 }
1762
1763 dev_kfree_skb_any(skb);
1764 }
1765
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1766 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1767 struct sk_buff_head *msdu_list,
1768 struct sk_buff *first, struct sk_buff *last,
1769 u8 l3pad_bytes, int msdu_len)
1770 {
1771 struct ath11k_base *ab = ar->ab;
1772 struct sk_buff *skb;
1773 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1774 int buf_first_hdr_len, buf_first_len;
1775 struct hal_rx_desc *ldesc;
1776 int space_extra, rem_len, buf_len;
1777 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1778
1779 /* As the msdu is spread across multiple rx buffers,
1780 * find the offset to the start of msdu for computing
1781 * the length of the msdu in the first buffer.
1782 */
1783 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1784 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1785
1786 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1787 skb_put(first, buf_first_hdr_len + msdu_len);
1788 skb_pull(first, buf_first_hdr_len);
1789 return 0;
1790 }
1791
1792 ldesc = (struct hal_rx_desc *)last->data;
1793 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1794 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1795
1796 /* MSDU spans over multiple buffers because the length of the MSDU
1797 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1798 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1799 */
1800 skb_put(first, DP_RX_BUFFER_SIZE);
1801 skb_pull(first, buf_first_hdr_len);
1802
1803 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1804 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1805 */
1806 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1807
1808 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1809 if (space_extra > 0 &&
1810 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1811 /* Free up all buffers of the MSDU */
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1813 rxcb = ATH11K_SKB_RXCB(skb);
1814 if (!rxcb->is_continuation) {
1815 dev_kfree_skb_any(skb);
1816 break;
1817 }
1818 dev_kfree_skb_any(skb);
1819 }
1820 return -ENOMEM;
1821 }
1822
1823 rem_len = msdu_len - buf_first_len;
1824 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1825 rxcb = ATH11K_SKB_RXCB(skb);
1826 if (rxcb->is_continuation)
1827 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1828 else
1829 buf_len = rem_len;
1830
1831 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1832 WARN_ON_ONCE(1);
1833 dev_kfree_skb_any(skb);
1834 return -EINVAL;
1835 }
1836
1837 skb_put(skb, buf_len + hal_rx_desc_sz);
1838 skb_pull(skb, hal_rx_desc_sz);
1839 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1840 buf_len);
1841 dev_kfree_skb_any(skb);
1842
1843 rem_len -= buf_len;
1844 if (!rxcb->is_continuation)
1845 break;
1846 }
1847
1848 return 0;
1849 }
1850
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1851 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1852 struct sk_buff *first)
1853 {
1854 struct sk_buff *skb;
1855 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1856
1857 if (!rxcb->is_continuation)
1858 return first;
1859
1860 skb_queue_walk(msdu_list, skb) {
1861 rxcb = ATH11K_SKB_RXCB(skb);
1862 if (!rxcb->is_continuation)
1863 return skb;
1864 }
1865
1866 return NULL;
1867 }
1868
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1869 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1870 {
1871 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1872 struct rx_attention *rx_attention;
1873 bool ip_csum_fail, l4_csum_fail;
1874
1875 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1876 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1877 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1878
1879 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1880 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1881 }
1882
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1883 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1884 {
1885 switch (enctype) {
1886 case HAL_ENCRYPT_TYPE_OPEN:
1887 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1888 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1889 return 0;
1890 case HAL_ENCRYPT_TYPE_CCMP_128:
1891 return IEEE80211_CCMP_MIC_LEN;
1892 case HAL_ENCRYPT_TYPE_CCMP_256:
1893 return IEEE80211_CCMP_256_MIC_LEN;
1894 case HAL_ENCRYPT_TYPE_GCMP_128:
1895 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1896 return IEEE80211_GCMP_MIC_LEN;
1897 case HAL_ENCRYPT_TYPE_WEP_40:
1898 case HAL_ENCRYPT_TYPE_WEP_104:
1899 case HAL_ENCRYPT_TYPE_WEP_128:
1900 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1901 case HAL_ENCRYPT_TYPE_WAPI:
1902 break;
1903 }
1904
1905 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1906 return 0;
1907 }
1908
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1909 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1910 enum hal_encrypt_type enctype)
1911 {
1912 switch (enctype) {
1913 case HAL_ENCRYPT_TYPE_OPEN:
1914 return 0;
1915 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1916 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1917 return IEEE80211_TKIP_IV_LEN;
1918 case HAL_ENCRYPT_TYPE_CCMP_128:
1919 return IEEE80211_CCMP_HDR_LEN;
1920 case HAL_ENCRYPT_TYPE_CCMP_256:
1921 return IEEE80211_CCMP_256_HDR_LEN;
1922 case HAL_ENCRYPT_TYPE_GCMP_128:
1923 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1924 return IEEE80211_GCMP_HDR_LEN;
1925 case HAL_ENCRYPT_TYPE_WEP_40:
1926 case HAL_ENCRYPT_TYPE_WEP_104:
1927 case HAL_ENCRYPT_TYPE_WEP_128:
1928 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1929 case HAL_ENCRYPT_TYPE_WAPI:
1930 break;
1931 }
1932
1933 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1934 return 0;
1935 }
1936
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1937 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1938 enum hal_encrypt_type enctype)
1939 {
1940 switch (enctype) {
1941 case HAL_ENCRYPT_TYPE_OPEN:
1942 case HAL_ENCRYPT_TYPE_CCMP_128:
1943 case HAL_ENCRYPT_TYPE_CCMP_256:
1944 case HAL_ENCRYPT_TYPE_GCMP_128:
1945 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1946 return 0;
1947 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1948 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1949 return IEEE80211_TKIP_ICV_LEN;
1950 case HAL_ENCRYPT_TYPE_WEP_40:
1951 case HAL_ENCRYPT_TYPE_WEP_104:
1952 case HAL_ENCRYPT_TYPE_WEP_128:
1953 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1954 case HAL_ENCRYPT_TYPE_WAPI:
1955 break;
1956 }
1957
1958 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1959 return 0;
1960 }
1961
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1962 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1963 struct sk_buff *msdu,
1964 u8 *first_hdr,
1965 enum hal_encrypt_type enctype,
1966 struct ieee80211_rx_status *status)
1967 {
1968 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1969 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1970 struct ieee80211_hdr *hdr;
1971 size_t hdr_len;
1972 u8 da[ETH_ALEN];
1973 u8 sa[ETH_ALEN];
1974 u16 qos_ctl = 0;
1975 u8 *qos;
1976
1977 /* copy SA & DA and pull decapped header */
1978 hdr = (struct ieee80211_hdr *)msdu->data;
1979 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1980 ether_addr_copy(da, ieee80211_get_DA(hdr));
1981 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1982 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1983
1984 if (rxcb->is_first_msdu) {
1985 /* original 802.11 header is valid for the first msdu
1986 * hence we can reuse the same header
1987 */
1988 hdr = (struct ieee80211_hdr *)first_hdr;
1989 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1990
1991 /* Each A-MSDU subframe will be reported as a separate MSDU,
1992 * so strip the A-MSDU bit from QoS Ctl.
1993 */
1994 if (ieee80211_is_data_qos(hdr->frame_control)) {
1995 qos = ieee80211_get_qos_ctl(hdr);
1996 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1997 }
1998 } else {
1999 /* Rebuild qos header if this is a middle/last msdu */
2000 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2001
2002 /* Reset the order bit as the HT_Control header is stripped */
2003 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2004
2005 qos_ctl = rxcb->tid;
2006
2007 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2008 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2009
2010 /* TODO Add other QoS ctl fields when required */
2011
2012 /* copy decap header before overwriting for reuse below */
2013 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2014 }
2015
2016 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2017 memcpy(skb_push(msdu,
2018 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2019 (void *)hdr + hdr_len,
2020 ath11k_dp_rx_crypto_param_len(ar, enctype));
2021 }
2022
2023 if (!rxcb->is_first_msdu) {
2024 memcpy(skb_push(msdu,
2025 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2026 IEEE80211_QOS_CTL_LEN);
2027 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2028 return;
2029 }
2030
2031 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2032
2033 /* original 802.11 header has a different DA and in
2034 * case of 4addr it may also have different SA
2035 */
2036 hdr = (struct ieee80211_hdr *)msdu->data;
2037 ether_addr_copy(ieee80211_get_DA(hdr), da);
2038 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2039 }
2040
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2041 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2042 enum hal_encrypt_type enctype,
2043 struct ieee80211_rx_status *status,
2044 bool decrypted)
2045 {
2046 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2047 struct ieee80211_hdr *hdr;
2048 size_t hdr_len;
2049 size_t crypto_len;
2050
2051 if (!rxcb->is_first_msdu ||
2052 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2053 WARN_ON_ONCE(1);
2054 return;
2055 }
2056
2057 skb_trim(msdu, msdu->len - FCS_LEN);
2058
2059 if (!decrypted)
2060 return;
2061
2062 hdr = (void *)msdu->data;
2063
2064 /* Tail */
2065 if (status->flag & RX_FLAG_IV_STRIPPED) {
2066 skb_trim(msdu, msdu->len -
2067 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2068
2069 skb_trim(msdu, msdu->len -
2070 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2071 } else {
2072 /* MIC */
2073 if (status->flag & RX_FLAG_MIC_STRIPPED)
2074 skb_trim(msdu, msdu->len -
2075 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2076
2077 /* ICV */
2078 if (status->flag & RX_FLAG_ICV_STRIPPED)
2079 skb_trim(msdu, msdu->len -
2080 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2081 }
2082
2083 /* MMIC */
2084 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2085 !ieee80211_has_morefrags(hdr->frame_control) &&
2086 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2087 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2088
2089 /* Head */
2090 if (status->flag & RX_FLAG_IV_STRIPPED) {
2091 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2092 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2093
2094 memmove((void *)msdu->data + crypto_len,
2095 (void *)msdu->data, hdr_len);
2096 skb_pull(msdu, crypto_len);
2097 }
2098 }
2099
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2100 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2101 struct sk_buff *msdu,
2102 enum hal_encrypt_type enctype)
2103 {
2104 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2105 struct ieee80211_hdr *hdr;
2106 size_t hdr_len, crypto_len;
2107 void *rfc1042;
2108 bool is_amsdu;
2109
2110 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2111 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2112 rfc1042 = hdr;
2113
2114 if (rxcb->is_first_msdu) {
2115 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2116 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2117
2118 rfc1042 += hdr_len + crypto_len;
2119 }
2120
2121 if (is_amsdu)
2122 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2123
2124 return rfc1042;
2125 }
2126
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2127 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2128 struct sk_buff *msdu,
2129 u8 *first_hdr,
2130 enum hal_encrypt_type enctype,
2131 struct ieee80211_rx_status *status)
2132 {
2133 struct ieee80211_hdr *hdr;
2134 struct ethhdr *eth;
2135 size_t hdr_len;
2136 u8 da[ETH_ALEN];
2137 u8 sa[ETH_ALEN];
2138 void *rfc1042;
2139
2140 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2141 if (WARN_ON_ONCE(!rfc1042))
2142 return;
2143
2144 /* pull decapped header and copy SA & DA */
2145 eth = (struct ethhdr *)msdu->data;
2146 ether_addr_copy(da, eth->h_dest);
2147 ether_addr_copy(sa, eth->h_source);
2148 skb_pull(msdu, sizeof(struct ethhdr));
2149
2150 /* push rfc1042/llc/snap */
2151 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2152 sizeof(struct ath11k_dp_rfc1042_hdr));
2153
2154 /* push original 802.11 header */
2155 hdr = (struct ieee80211_hdr *)first_hdr;
2156 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2157
2158 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2159 memcpy(skb_push(msdu,
2160 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2161 (void *)hdr + hdr_len,
2162 ath11k_dp_rx_crypto_param_len(ar, enctype));
2163 }
2164
2165 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2166
2167 /* original 802.11 header has a different DA and in
2168 * case of 4addr it may also have different SA
2169 */
2170 hdr = (struct ieee80211_hdr *)msdu->data;
2171 ether_addr_copy(ieee80211_get_DA(hdr), da);
2172 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2173 }
2174
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2175 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2176 struct hal_rx_desc *rx_desc,
2177 enum hal_encrypt_type enctype,
2178 struct ieee80211_rx_status *status,
2179 bool decrypted)
2180 {
2181 u8 *first_hdr;
2182 u8 decap;
2183 struct ethhdr *ehdr;
2184
2185 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2186 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2187
2188 switch (decap) {
2189 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2190 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2191 enctype, status);
2192 break;
2193 case DP_RX_DECAP_TYPE_RAW:
2194 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2195 decrypted);
2196 break;
2197 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2198 ehdr = (struct ethhdr *)msdu->data;
2199
2200 /* mac80211 allows fast path only for authorized STA */
2201 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2202 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2203 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2204 enctype, status);
2205 break;
2206 }
2207
2208 /* PN for mcast packets will be validated in mac80211;
2209 * remove eth header and add 802.11 header.
2210 */
2211 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2212 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2213 enctype, status);
2214 break;
2215 case DP_RX_DECAP_TYPE_8023:
2216 /* TODO: Handle undecap for these formats */
2217 break;
2218 }
2219 }
2220
2221 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2222 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2223 {
2224 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2225 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2226 struct ath11k_peer *peer = NULL;
2227
2228 lockdep_assert_held(&ab->base_lock);
2229
2230 if (rxcb->peer_id)
2231 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2232
2233 if (peer)
2234 return peer;
2235
2236 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2237 return NULL;
2238
2239 peer = ath11k_peer_find_by_addr(ab,
2240 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2241 return peer;
2242 }
2243
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2244 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2245 struct sk_buff *msdu,
2246 struct hal_rx_desc *rx_desc,
2247 struct ieee80211_rx_status *rx_status)
2248 {
2249 bool fill_crypto_hdr;
2250 enum hal_encrypt_type enctype;
2251 bool is_decrypted = false;
2252 struct ath11k_skb_rxcb *rxcb;
2253 struct ieee80211_hdr *hdr;
2254 struct ath11k_peer *peer;
2255 struct rx_attention *rx_attention;
2256 u32 err_bitmap;
2257
2258 /* PN for multicast packets will be checked in mac80211 */
2259 rxcb = ATH11K_SKB_RXCB(msdu);
2260 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2261 rxcb->is_mcbc = fill_crypto_hdr;
2262
2263 if (rxcb->is_mcbc) {
2264 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2265 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2266 }
2267
2268 spin_lock_bh(&ar->ab->base_lock);
2269 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2270 if (peer) {
2271 if (rxcb->is_mcbc)
2272 enctype = peer->sec_type_grp;
2273 else
2274 enctype = peer->sec_type;
2275 } else {
2276 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2277 }
2278 spin_unlock_bh(&ar->ab->base_lock);
2279
2280 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2281 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2282 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2283 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2284
2285 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2286 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2287 RX_FLAG_MMIC_ERROR |
2288 RX_FLAG_DECRYPTED |
2289 RX_FLAG_IV_STRIPPED |
2290 RX_FLAG_MMIC_STRIPPED);
2291
2292 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2293 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2294 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2295 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2296
2297 if (is_decrypted) {
2298 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2299
2300 if (fill_crypto_hdr)
2301 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2302 RX_FLAG_ICV_STRIPPED;
2303 else
2304 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2305 RX_FLAG_PN_VALIDATED;
2306 }
2307
2308 ath11k_dp_rx_h_csum_offload(ar, msdu);
2309 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2310 enctype, rx_status, is_decrypted);
2311
2312 if (!is_decrypted || fill_crypto_hdr)
2313 return;
2314
2315 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2316 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2317 hdr = (void *)msdu->data;
2318 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2319 }
2320 }
2321
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2322 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2323 struct ieee80211_rx_status *rx_status)
2324 {
2325 struct ieee80211_supported_band *sband;
2326 enum rx_msdu_start_pkt_type pkt_type;
2327 u8 bw;
2328 u8 rate_mcs, nss;
2329 u8 sgi;
2330 bool is_cck, is_ldpc;
2331
2332 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2333 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2334 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2335 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2336 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2337
2338 switch (pkt_type) {
2339 case RX_MSDU_START_PKT_TYPE_11A:
2340 case RX_MSDU_START_PKT_TYPE_11B:
2341 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2342 sband = &ar->mac.sbands[rx_status->band];
2343 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2344 is_cck);
2345 break;
2346 case RX_MSDU_START_PKT_TYPE_11N:
2347 rx_status->encoding = RX_ENC_HT;
2348 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2349 ath11k_warn(ar->ab,
2350 "Received with invalid mcs in HT mode %d\n",
2351 rate_mcs);
2352 break;
2353 }
2354 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2355 if (sgi)
2356 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2357 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2358 break;
2359 case RX_MSDU_START_PKT_TYPE_11AC:
2360 rx_status->encoding = RX_ENC_VHT;
2361 rx_status->rate_idx = rate_mcs;
2362 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2363 ath11k_warn(ar->ab,
2364 "Received with invalid mcs in VHT mode %d\n",
2365 rate_mcs);
2366 break;
2367 }
2368 rx_status->nss = nss;
2369 if (sgi)
2370 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2371 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2372 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2373 if (is_ldpc)
2374 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2375 break;
2376 case RX_MSDU_START_PKT_TYPE_11AX:
2377 rx_status->rate_idx = rate_mcs;
2378 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2379 ath11k_warn(ar->ab,
2380 "Received with invalid mcs in HE mode %d\n",
2381 rate_mcs);
2382 break;
2383 }
2384 rx_status->encoding = RX_ENC_HE;
2385 rx_status->nss = nss;
2386 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2387 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2388 break;
2389 }
2390 }
2391
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2392 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2393 struct ieee80211_rx_status *rx_status)
2394 {
2395 u8 channel_num;
2396 u32 center_freq, meta_data;
2397 struct ieee80211_channel *channel;
2398
2399 rx_status->freq = 0;
2400 rx_status->rate_idx = 0;
2401 rx_status->nss = 0;
2402 rx_status->encoding = RX_ENC_LEGACY;
2403 rx_status->bw = RATE_INFO_BW_20;
2404
2405 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2406
2407 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2408 channel_num = meta_data;
2409 center_freq = meta_data >> 16;
2410
2411 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2412 center_freq <= ATH11K_MAX_6G_FREQ) {
2413 rx_status->band = NL80211_BAND_6GHZ;
2414 rx_status->freq = center_freq;
2415 } else if (channel_num >= 1 && channel_num <= 14) {
2416 rx_status->band = NL80211_BAND_2GHZ;
2417 } else if (channel_num >= 36 && channel_num <= 177) {
2418 rx_status->band = NL80211_BAND_5GHZ;
2419 } else {
2420 spin_lock_bh(&ar->data_lock);
2421 channel = ar->rx_channel;
2422 if (channel) {
2423 rx_status->band = channel->band;
2424 channel_num =
2425 ieee80211_frequency_to_channel(channel->center_freq);
2426 }
2427 spin_unlock_bh(&ar->data_lock);
2428 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2429 rx_desc, sizeof(struct hal_rx_desc));
2430 }
2431
2432 if (rx_status->band != NL80211_BAND_6GHZ)
2433 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2434 rx_status->band);
2435
2436 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2437 }
2438
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2439 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2440 struct sk_buff *msdu,
2441 struct ieee80211_rx_status *status)
2442 {
2443 static const struct ieee80211_radiotap_he known = {
2444 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2445 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2446 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2447 };
2448 struct ieee80211_rx_status *rx_status;
2449 struct ieee80211_radiotap_he *he = NULL;
2450 struct ieee80211_sta *pubsta = NULL;
2451 struct ath11k_peer *peer;
2452 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2453 u8 decap = DP_RX_DECAP_TYPE_RAW;
2454 bool is_mcbc = rxcb->is_mcbc;
2455 bool is_eapol = rxcb->is_eapol;
2456
2457 if (status->encoding == RX_ENC_HE &&
2458 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2459 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2460 he = skb_push(msdu, sizeof(known));
2461 memcpy(he, &known, sizeof(known));
2462 status->flag |= RX_FLAG_RADIOTAP_HE;
2463 }
2464
2465 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2466 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2467
2468 spin_lock_bh(&ar->ab->base_lock);
2469 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2470 if (peer && peer->sta)
2471 pubsta = peer->sta;
2472 spin_unlock_bh(&ar->ab->base_lock);
2473
2474 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2475 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2476 msdu,
2477 msdu->len,
2478 peer ? peer->addr : NULL,
2479 rxcb->tid,
2480 is_mcbc ? "mcast" : "ucast",
2481 rxcb->seq_no,
2482 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2483 (status->encoding == RX_ENC_HT) ? "ht" : "",
2484 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2485 (status->encoding == RX_ENC_HE) ? "he" : "",
2486 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2487 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2488 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2489 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2490 status->rate_idx,
2491 status->nss,
2492 status->freq,
2493 status->band, status->flag,
2494 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2495 !!(status->flag & RX_FLAG_MMIC_ERROR),
2496 !!(status->flag & RX_FLAG_AMSDU_MORE));
2497
2498 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2499 msdu->data, msdu->len);
2500
2501 rx_status = IEEE80211_SKB_RXCB(msdu);
2502 *rx_status = *status;
2503
2504 /* TODO: trace rx packet */
2505
2506 /* PN for multicast packets are not validate in HW,
2507 * so skip 802.3 rx path
2508 * Also, fast_rx expects the STA to be authorized, hence
2509 * eapol packets are sent in slow path.
2510 */
2511 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2512 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2513 rx_status->flag |= RX_FLAG_8023;
2514
2515 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2516 }
2517
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2518 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2519 struct sk_buff *msdu,
2520 struct sk_buff_head *msdu_list,
2521 struct ieee80211_rx_status *rx_status)
2522 {
2523 struct ath11k_base *ab = ar->ab;
2524 struct hal_rx_desc *rx_desc, *lrx_desc;
2525 struct rx_attention *rx_attention;
2526 struct ath11k_skb_rxcb *rxcb;
2527 struct sk_buff *last_buf;
2528 u8 l3_pad_bytes;
2529 u8 *hdr_status;
2530 u16 msdu_len;
2531 int ret;
2532 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2533
2534 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2535 if (!last_buf) {
2536 ath11k_warn(ab,
2537 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2538 ret = -EIO;
2539 goto free_out;
2540 }
2541
2542 rx_desc = (struct hal_rx_desc *)msdu->data;
2543 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2544 ath11k_warn(ar->ab, "msdu len not valid\n");
2545 ret = -EIO;
2546 goto free_out;
2547 }
2548
2549 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2550 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2551 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2552 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2553 ret = -EIO;
2554 goto free_out;
2555 }
2556
2557 rxcb = ATH11K_SKB_RXCB(msdu);
2558 rxcb->rx_desc = rx_desc;
2559 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2560 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2561
2562 if (rxcb->is_frag) {
2563 skb_pull(msdu, hal_rx_desc_sz);
2564 } else if (!rxcb->is_continuation) {
2565 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2566 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2567 ret = -EINVAL;
2568 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2569 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2570 sizeof(struct ieee80211_hdr));
2571 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2572 sizeof(struct hal_rx_desc));
2573 goto free_out;
2574 }
2575 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2576 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2577 } else {
2578 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2579 msdu, last_buf,
2580 l3_pad_bytes, msdu_len);
2581 if (ret) {
2582 ath11k_warn(ab,
2583 "failed to coalesce msdu rx buffer%d\n", ret);
2584 goto free_out;
2585 }
2586 }
2587
2588 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2589 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2590
2591 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2592
2593 return 0;
2594
2595 free_out:
2596 return ret;
2597 }
2598
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2599 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2600 struct napi_struct *napi,
2601 struct sk_buff_head *msdu_list,
2602 int mac_id)
2603 {
2604 struct sk_buff *msdu;
2605 struct ath11k *ar;
2606 struct ieee80211_rx_status rx_status = {0};
2607 int ret;
2608
2609 if (skb_queue_empty(msdu_list))
2610 return;
2611
2612 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2613 __skb_queue_purge(msdu_list);
2614 return;
2615 }
2616
2617 ar = ab->pdevs[mac_id].ar;
2618 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2619 __skb_queue_purge(msdu_list);
2620 return;
2621 }
2622
2623 while ((msdu = __skb_dequeue(msdu_list))) {
2624 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2625 if (unlikely(ret)) {
2626 ath11k_dbg(ab, ATH11K_DBG_DATA,
2627 "Unable to process msdu %d", ret);
2628 dev_kfree_skb_any(msdu);
2629 continue;
2630 }
2631
2632 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2633 }
2634 }
2635
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2636 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2637 struct napi_struct *napi, int budget)
2638 {
2639 struct ath11k_dp *dp = &ab->dp;
2640 struct dp_rxdma_ring *rx_ring;
2641 int num_buffs_reaped[MAX_RADIOS] = {0};
2642 struct sk_buff_head msdu_list[MAX_RADIOS];
2643 struct ath11k_skb_rxcb *rxcb;
2644 int total_msdu_reaped = 0;
2645 struct hal_srng *srng;
2646 struct sk_buff *msdu;
2647 bool done = false;
2648 int buf_id, mac_id;
2649 struct ath11k *ar;
2650 struct hal_reo_dest_ring *desc;
2651 enum hal_reo_dest_ring_push_reason push_reason;
2652 u32 cookie;
2653 int i;
2654
2655 for (i = 0; i < MAX_RADIOS; i++)
2656 __skb_queue_head_init(&msdu_list[i]);
2657
2658 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2659
2660 spin_lock_bh(&srng->lock);
2661
2662 try_again:
2663 ath11k_hal_srng_access_begin(ab, srng);
2664
2665 while (likely(desc =
2666 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2667 srng))) {
2668 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2669 desc->buf_addr_info.info1);
2670 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2671 cookie);
2672 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2673
2674 if (unlikely(buf_id == 0))
2675 continue;
2676
2677 ar = ab->pdevs[mac_id].ar;
2678 rx_ring = &ar->dp.rx_refill_buf_ring;
2679 spin_lock_bh(&rx_ring->idr_lock);
2680 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2681 if (unlikely(!msdu)) {
2682 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2683 buf_id);
2684 spin_unlock_bh(&rx_ring->idr_lock);
2685 continue;
2686 }
2687
2688 idr_remove(&rx_ring->bufs_idr, buf_id);
2689 spin_unlock_bh(&rx_ring->idr_lock);
2690
2691 rxcb = ATH11K_SKB_RXCB(msdu);
2692 dma_unmap_single(ab->dev, rxcb->paddr,
2693 msdu->len + skb_tailroom(msdu),
2694 DMA_FROM_DEVICE);
2695
2696 num_buffs_reaped[mac_id]++;
2697
2698 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2699 desc->info0);
2700 if (unlikely(push_reason !=
2701 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2702 dev_kfree_skb_any(msdu);
2703 ab->soc_stats.hal_reo_error[ring_id]++;
2704 continue;
2705 }
2706
2707 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2708 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2709 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2710 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2711 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2712 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2713 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2714 desc->rx_mpdu_info.meta_data);
2715 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2716 desc->rx_mpdu_info.info0);
2717 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2718 desc->info0);
2719
2720 rxcb->mac_id = mac_id;
2721 __skb_queue_tail(&msdu_list[mac_id], msdu);
2722
2723 if (rxcb->is_continuation) {
2724 done = false;
2725 } else {
2726 total_msdu_reaped++;
2727 done = true;
2728 }
2729
2730 if (total_msdu_reaped >= budget)
2731 break;
2732 }
2733
2734 /* Hw might have updated the head pointer after we cached it.
2735 * In this case, even though there are entries in the ring we'll
2736 * get rx_desc NULL. Give the read another try with updated cached
2737 * head pointer so that we can reap complete MPDU in the current
2738 * rx processing.
2739 */
2740 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2741 ath11k_hal_srng_access_end(ab, srng);
2742 goto try_again;
2743 }
2744
2745 ath11k_hal_srng_access_end(ab, srng);
2746
2747 spin_unlock_bh(&srng->lock);
2748
2749 if (unlikely(!total_msdu_reaped))
2750 goto exit;
2751
2752 for (i = 0; i < ab->num_radios; i++) {
2753 if (!num_buffs_reaped[i])
2754 continue;
2755
2756 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2757
2758 ar = ab->pdevs[i].ar;
2759 rx_ring = &ar->dp.rx_refill_buf_ring;
2760
2761 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2762 ab->hw_params.hal_params->rx_buf_rbm);
2763 }
2764 exit:
2765 return total_msdu_reaped;
2766 }
2767
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2768 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2769 struct hal_rx_mon_ppdu_info *ppdu_info)
2770 {
2771 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2772 u32 num_msdu;
2773 int i;
2774
2775 if (!rx_stats)
2776 return;
2777
2778 arsta->rssi_comb = ppdu_info->rssi_comb;
2779 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2780
2781 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2782 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2783
2784 rx_stats->num_msdu += num_msdu;
2785 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2786 ppdu_info->tcp_ack_msdu_count;
2787 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2788 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2789
2790 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2791 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2792 ppdu_info->nss = 1;
2793 ppdu_info->mcs = HAL_RX_MAX_MCS;
2794 ppdu_info->tid = IEEE80211_NUM_TIDS;
2795 }
2796
2797 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2798 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2799
2800 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2801 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2802
2803 if (ppdu_info->gi < HAL_RX_GI_MAX)
2804 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2805
2806 if (ppdu_info->bw < HAL_RX_BW_MAX)
2807 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2808
2809 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2810 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2811
2812 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2813 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2814
2815 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2816 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2817
2818 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2819 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2820
2821 if (ppdu_info->is_stbc)
2822 rx_stats->stbc_count += num_msdu;
2823
2824 if (ppdu_info->beamformed)
2825 rx_stats->beamformed_count += num_msdu;
2826
2827 if (ppdu_info->num_mpdu_fcs_ok > 1)
2828 rx_stats->ampdu_msdu_count += num_msdu;
2829 else
2830 rx_stats->non_ampdu_msdu_count += num_msdu;
2831
2832 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2833 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2834 rx_stats->dcm_count += ppdu_info->dcm;
2835 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2836
2837 arsta->rssi_comb = ppdu_info->rssi_comb;
2838
2839 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2840 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2841
2842 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2843 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2844
2845 rx_stats->rx_duration += ppdu_info->rx_duration;
2846 arsta->rx_duration = rx_stats->rx_duration;
2847 }
2848
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2849 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2850 struct dp_rxdma_ring *rx_ring,
2851 int *buf_id)
2852 {
2853 struct sk_buff *skb;
2854 dma_addr_t paddr;
2855
2856 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2857 DP_RX_BUFFER_ALIGN_SIZE);
2858
2859 if (!skb)
2860 goto fail_alloc_skb;
2861
2862 if (!IS_ALIGNED((unsigned long)skb->data,
2863 DP_RX_BUFFER_ALIGN_SIZE)) {
2864 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2865 skb->data);
2866 }
2867
2868 paddr = dma_map_single(ab->dev, skb->data,
2869 skb->len + skb_tailroom(skb),
2870 DMA_FROM_DEVICE);
2871 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2872 goto fail_free_skb;
2873
2874 spin_lock_bh(&rx_ring->idr_lock);
2875 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2876 rx_ring->bufs_max, GFP_ATOMIC);
2877 spin_unlock_bh(&rx_ring->idr_lock);
2878 if (*buf_id < 0)
2879 goto fail_dma_unmap;
2880
2881 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2882 return skb;
2883
2884 fail_dma_unmap:
2885 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2886 DMA_FROM_DEVICE);
2887 fail_free_skb:
2888 dev_kfree_skb_any(skb);
2889 fail_alloc_skb:
2890 return NULL;
2891 }
2892
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2893 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2894 struct dp_rxdma_ring *rx_ring,
2895 int req_entries,
2896 enum hal_rx_buf_return_buf_manager mgr)
2897 {
2898 struct hal_srng *srng;
2899 u32 *desc;
2900 struct sk_buff *skb;
2901 int num_free;
2902 int num_remain;
2903 int buf_id;
2904 u32 cookie;
2905 dma_addr_t paddr;
2906
2907 req_entries = min(req_entries, rx_ring->bufs_max);
2908
2909 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2910
2911 spin_lock_bh(&srng->lock);
2912
2913 ath11k_hal_srng_access_begin(ab, srng);
2914
2915 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2916
2917 req_entries = min(num_free, req_entries);
2918 num_remain = req_entries;
2919
2920 while (num_remain > 0) {
2921 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2922 &buf_id);
2923 if (!skb)
2924 break;
2925 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2926
2927 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2928 if (!desc)
2929 goto fail_desc_get;
2930
2931 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2932 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2933
2934 num_remain--;
2935
2936 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2937 }
2938
2939 ath11k_hal_srng_access_end(ab, srng);
2940
2941 spin_unlock_bh(&srng->lock);
2942
2943 return req_entries - num_remain;
2944
2945 fail_desc_get:
2946 spin_lock_bh(&rx_ring->idr_lock);
2947 idr_remove(&rx_ring->bufs_idr, buf_id);
2948 spin_unlock_bh(&rx_ring->idr_lock);
2949 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2950 DMA_FROM_DEVICE);
2951 dev_kfree_skb_any(skb);
2952 ath11k_hal_srng_access_end(ab, srng);
2953 spin_unlock_bh(&srng->lock);
2954
2955 return req_entries - num_remain;
2956 }
2957
2958 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2959
2960 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2961 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2962 struct hal_tlv_hdr *tlv)
2963 {
2964 struct hal_rx_ppdu_start *ppdu_start;
2965 u16 ppdu_id_diff, ppdu_id, tlv_len;
2966 u8 *ptr;
2967
2968 /* PPDU id is part of second tlv, move ptr to second tlv */
2969 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2970 ptr = (u8 *)tlv;
2971 ptr += sizeof(*tlv) + tlv_len;
2972 tlv = (struct hal_tlv_hdr *)ptr;
2973
2974 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2975 return;
2976
2977 ptr += sizeof(*tlv);
2978 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2979 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2980 __le32_to_cpu(ppdu_start->info0));
2981
2982 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2983 pmon->buf_state = DP_MON_STATUS_LEAD;
2984 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2985 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2986 pmon->buf_state = DP_MON_STATUS_LAG;
2987 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2988 pmon->buf_state = DP_MON_STATUS_LAG;
2989 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2990 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2991 pmon->buf_state = DP_MON_STATUS_LEAD;
2992 }
2993 }
2994
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2995 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2996 int *budget, struct sk_buff_head *skb_list)
2997 {
2998 struct ath11k *ar;
2999 const struct ath11k_hw_hal_params *hal_params;
3000 struct ath11k_pdev_dp *dp;
3001 struct dp_rxdma_ring *rx_ring;
3002 struct ath11k_mon_data *pmon;
3003 struct hal_srng *srng;
3004 void *rx_mon_status_desc;
3005 struct sk_buff *skb;
3006 struct ath11k_skb_rxcb *rxcb;
3007 struct hal_tlv_hdr *tlv;
3008 u32 cookie;
3009 int buf_id, srng_id;
3010 dma_addr_t paddr;
3011 u8 rbm;
3012 int num_buffs_reaped = 0;
3013
3014 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3015 dp = &ar->dp;
3016 pmon = &dp->mon_data;
3017 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3018 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3019
3020 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3021
3022 spin_lock_bh(&srng->lock);
3023
3024 ath11k_hal_srng_access_begin(ab, srng);
3025 while (*budget) {
3026 *budget -= 1;
3027 rx_mon_status_desc =
3028 ath11k_hal_srng_src_peek(ab, srng);
3029 if (!rx_mon_status_desc) {
3030 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3031 break;
3032 }
3033
3034 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3035 &cookie, &rbm);
3036 if (paddr) {
3037 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3038
3039 spin_lock_bh(&rx_ring->idr_lock);
3040 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3041 spin_unlock_bh(&rx_ring->idr_lock);
3042
3043 if (!skb) {
3044 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3045 buf_id);
3046 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3047 goto move_next;
3048 }
3049
3050 rxcb = ATH11K_SKB_RXCB(skb);
3051
3052 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3053 skb->len + skb_tailroom(skb),
3054 DMA_FROM_DEVICE);
3055
3056 tlv = (struct hal_tlv_hdr *)skb->data;
3057 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3058 HAL_RX_STATUS_BUFFER_DONE) {
3059 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3060 FIELD_GET(HAL_TLV_HDR_TAG,
3061 tlv->tl), buf_id);
3062 /* If done status is missing, hold onto status
3063 * ring until status is done for this status
3064 * ring buffer.
3065 * Keep HP in mon_status_ring unchanged,
3066 * and break from here.
3067 * Check status for same buffer for next time
3068 */
3069 pmon->buf_state = DP_MON_STATUS_NO_DMA;
3070 break;
3071 }
3072
3073 spin_lock_bh(&rx_ring->idr_lock);
3074 idr_remove(&rx_ring->bufs_idr, buf_id);
3075 spin_unlock_bh(&rx_ring->idr_lock);
3076 if (ab->hw_params.full_monitor_mode) {
3077 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3078 if (paddr == pmon->mon_status_paddr)
3079 pmon->buf_state = DP_MON_STATUS_MATCH;
3080 }
3081
3082 dma_unmap_single(ab->dev, rxcb->paddr,
3083 skb->len + skb_tailroom(skb),
3084 DMA_FROM_DEVICE);
3085
3086 __skb_queue_tail(skb_list, skb);
3087 } else {
3088 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3089 }
3090 move_next:
3091 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3092 &buf_id);
3093
3094 if (!skb) {
3095 hal_params = ab->hw_params.hal_params;
3096 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3097 hal_params->rx_buf_rbm);
3098 num_buffs_reaped++;
3099 break;
3100 }
3101 rxcb = ATH11K_SKB_RXCB(skb);
3102
3103 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3104 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3105
3106 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3107 cookie,
3108 ab->hw_params.hal_params->rx_buf_rbm);
3109 ath11k_hal_srng_src_get_next_entry(ab, srng);
3110 num_buffs_reaped++;
3111 }
3112 ath11k_hal_srng_access_end(ab, srng);
3113 spin_unlock_bh(&srng->lock);
3114
3115 return num_buffs_reaped;
3116 }
3117
ath11k_dp_rx_frag_timer(struct timer_list * timer)3118 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3119 {
3120 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3121
3122 spin_lock_bh(&rx_tid->ab->base_lock);
3123 if (rx_tid->last_frag_no &&
3124 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3125 spin_unlock_bh(&rx_tid->ab->base_lock);
3126 return;
3127 }
3128 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3129 spin_unlock_bh(&rx_tid->ab->base_lock);
3130 }
3131
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3132 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3133 {
3134 struct ath11k_base *ab = ar->ab;
3135 struct crypto_shash *tfm;
3136 struct ath11k_peer *peer;
3137 struct dp_rx_tid *rx_tid;
3138 int i;
3139
3140 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3141 if (IS_ERR(tfm)) {
3142 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3143 PTR_ERR(tfm));
3144 return PTR_ERR(tfm);
3145 }
3146
3147 spin_lock_bh(&ab->base_lock);
3148
3149 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3150 if (!peer) {
3151 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3152 spin_unlock_bh(&ab->base_lock);
3153 crypto_free_shash(tfm);
3154 return -ENOENT;
3155 }
3156
3157 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3158 rx_tid = &peer->rx_tid[i];
3159 rx_tid->ab = ab;
3160 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3161 skb_queue_head_init(&rx_tid->rx_frags);
3162 }
3163
3164 peer->tfm_mmic = tfm;
3165 peer->dp_setup_done = true;
3166 spin_unlock_bh(&ab->base_lock);
3167
3168 return 0;
3169 }
3170
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3171 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3172 struct ieee80211_hdr *hdr, u8 *data,
3173 size_t data_len, u8 *mic)
3174 {
3175 SHASH_DESC_ON_STACK(desc, tfm);
3176 u8 mic_hdr[16] = {0};
3177 u8 tid = 0;
3178 int ret;
3179
3180 if (!tfm)
3181 return -EINVAL;
3182
3183 desc->tfm = tfm;
3184
3185 ret = crypto_shash_setkey(tfm, key, 8);
3186 if (ret)
3187 goto out;
3188
3189 ret = crypto_shash_init(desc);
3190 if (ret)
3191 goto out;
3192
3193 /* TKIP MIC header */
3194 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3195 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3196 if (ieee80211_is_data_qos(hdr->frame_control))
3197 tid = ieee80211_get_tid(hdr);
3198 mic_hdr[12] = tid;
3199
3200 ret = crypto_shash_update(desc, mic_hdr, 16);
3201 if (ret)
3202 goto out;
3203 ret = crypto_shash_update(desc, data, data_len);
3204 if (ret)
3205 goto out;
3206 ret = crypto_shash_final(desc, mic);
3207 out:
3208 shash_desc_zero(desc);
3209 return ret;
3210 }
3211
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3212 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3213 struct sk_buff *msdu)
3214 {
3215 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3216 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3217 struct ieee80211_key_conf *key_conf;
3218 struct ieee80211_hdr *hdr;
3219 u8 mic[IEEE80211_CCMP_MIC_LEN];
3220 int head_len, tail_len, ret;
3221 size_t data_len;
3222 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3223 u8 *key, *data;
3224 u8 key_idx;
3225
3226 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3227 HAL_ENCRYPT_TYPE_TKIP_MIC)
3228 return 0;
3229
3230 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3231 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3232 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3233 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3234
3235 if (!is_multicast_ether_addr(hdr->addr1))
3236 key_idx = peer->ucast_keyidx;
3237 else
3238 key_idx = peer->mcast_keyidx;
3239
3240 key_conf = peer->keys[key_idx];
3241
3242 data = msdu->data + head_len;
3243 data_len = msdu->len - head_len - tail_len;
3244 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3245
3246 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3247 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3248 goto mic_fail;
3249
3250 return 0;
3251
3252 mic_fail:
3253 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3254 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3255
3256 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3257 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3258 skb_pull(msdu, hal_rx_desc_sz);
3259
3260 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3261 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3262 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3263 ieee80211_rx(ar->hw, msdu);
3264 return -EINVAL;
3265 }
3266
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3267 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3268 enum hal_encrypt_type enctype, u32 flags)
3269 {
3270 struct ieee80211_hdr *hdr;
3271 size_t hdr_len;
3272 size_t crypto_len;
3273 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3274
3275 if (!flags)
3276 return;
3277
3278 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3279
3280 if (flags & RX_FLAG_MIC_STRIPPED)
3281 skb_trim(msdu, msdu->len -
3282 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3283
3284 if (flags & RX_FLAG_ICV_STRIPPED)
3285 skb_trim(msdu, msdu->len -
3286 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3287
3288 if (flags & RX_FLAG_IV_STRIPPED) {
3289 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3290 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3291
3292 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3293 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3294 skb_pull(msdu, crypto_len);
3295 }
3296 }
3297
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3298 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3299 struct ath11k_peer *peer,
3300 struct dp_rx_tid *rx_tid,
3301 struct sk_buff **defrag_skb)
3302 {
3303 struct hal_rx_desc *rx_desc;
3304 struct sk_buff *skb, *first_frag, *last_frag;
3305 struct ieee80211_hdr *hdr;
3306 struct rx_attention *rx_attention;
3307 enum hal_encrypt_type enctype;
3308 bool is_decrypted = false;
3309 int msdu_len = 0;
3310 int extra_space;
3311 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3312
3313 first_frag = skb_peek(&rx_tid->rx_frags);
3314 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3315
3316 skb_queue_walk(&rx_tid->rx_frags, skb) {
3317 flags = 0;
3318 rx_desc = (struct hal_rx_desc *)skb->data;
3319 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3320
3321 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3322 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3323 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3324 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3325 }
3326
3327 if (is_decrypted) {
3328 if (skb != first_frag)
3329 flags |= RX_FLAG_IV_STRIPPED;
3330 if (skb != last_frag)
3331 flags |= RX_FLAG_ICV_STRIPPED |
3332 RX_FLAG_MIC_STRIPPED;
3333 }
3334
3335 /* RX fragments are always raw packets */
3336 if (skb != last_frag)
3337 skb_trim(skb, skb->len - FCS_LEN);
3338 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3339
3340 if (skb != first_frag)
3341 skb_pull(skb, hal_rx_desc_sz +
3342 ieee80211_hdrlen(hdr->frame_control));
3343 msdu_len += skb->len;
3344 }
3345
3346 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3347 if (extra_space > 0 &&
3348 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3349 return -ENOMEM;
3350
3351 __skb_unlink(first_frag, &rx_tid->rx_frags);
3352 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3353 skb_put_data(first_frag, skb->data, skb->len);
3354 dev_kfree_skb_any(skb);
3355 }
3356
3357 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3358 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3359 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3360
3361 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3362 first_frag = NULL;
3363
3364 *defrag_skb = first_frag;
3365 return 0;
3366 }
3367
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3368 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3369 struct sk_buff *defrag_skb)
3370 {
3371 struct ath11k_base *ab = ar->ab;
3372 struct ath11k_pdev_dp *dp = &ar->dp;
3373 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3374 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3375 struct hal_reo_entrance_ring *reo_ent_ring;
3376 struct hal_reo_dest_ring *reo_dest_ring;
3377 struct dp_link_desc_bank *link_desc_banks;
3378 struct hal_rx_msdu_link *msdu_link;
3379 struct hal_rx_msdu_details *msdu0;
3380 struct hal_srng *srng;
3381 dma_addr_t paddr;
3382 u32 desc_bank, msdu_info, mpdu_info;
3383 u32 dst_idx, cookie, hal_rx_desc_sz;
3384 int ret, buf_id;
3385
3386 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3387 link_desc_banks = ab->dp.link_desc_banks;
3388 reo_dest_ring = rx_tid->dst_ring_desc;
3389
3390 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3391 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3392 (paddr - link_desc_banks[desc_bank].paddr));
3393 msdu0 = &msdu_link->msdu_link[0];
3394 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3395 memset(msdu0, 0, sizeof(*msdu0));
3396
3397 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3398 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3399 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3400 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3401 defrag_skb->len - hal_rx_desc_sz) |
3402 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3403 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3404 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3405 msdu0->rx_msdu_info.info0 = msdu_info;
3406
3407 /* change msdu len in hal rx desc */
3408 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3409
3410 paddr = dma_map_single(ab->dev, defrag_skb->data,
3411 defrag_skb->len + skb_tailroom(defrag_skb),
3412 DMA_TO_DEVICE);
3413 if (dma_mapping_error(ab->dev, paddr))
3414 return -ENOMEM;
3415
3416 spin_lock_bh(&rx_refill_ring->idr_lock);
3417 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3418 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3419 spin_unlock_bh(&rx_refill_ring->idr_lock);
3420 if (buf_id < 0) {
3421 ret = -ENOMEM;
3422 goto err_unmap_dma;
3423 }
3424
3425 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3426 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3427 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3428
3429 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3430 ab->hw_params.hal_params->rx_buf_rbm);
3431
3432 /* Fill mpdu details into reo entrance ring */
3433 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3434
3435 spin_lock_bh(&srng->lock);
3436 ath11k_hal_srng_access_begin(ab, srng);
3437
3438 reo_ent_ring = (struct hal_reo_entrance_ring *)
3439 ath11k_hal_srng_src_get_next_entry(ab, srng);
3440 if (!reo_ent_ring) {
3441 ath11k_hal_srng_access_end(ab, srng);
3442 spin_unlock_bh(&srng->lock);
3443 ret = -ENOSPC;
3444 goto err_free_idr;
3445 }
3446 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3447
3448 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3449 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3450 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3451
3452 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3453 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3454 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3455 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3456 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3457 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3458 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3459
3460 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3461 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3462 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3463 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3464 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3465 reo_dest_ring->info0)) |
3466 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3467 ath11k_hal_srng_access_end(ab, srng);
3468 spin_unlock_bh(&srng->lock);
3469
3470 return 0;
3471
3472 err_free_idr:
3473 spin_lock_bh(&rx_refill_ring->idr_lock);
3474 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3475 spin_unlock_bh(&rx_refill_ring->idr_lock);
3476 err_unmap_dma:
3477 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3478 DMA_TO_DEVICE);
3479 return ret;
3480 }
3481
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3482 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3483 struct sk_buff *a, struct sk_buff *b)
3484 {
3485 int frag1, frag2;
3486
3487 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3488 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3489
3490 return frag1 - frag2;
3491 }
3492
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3493 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3494 struct sk_buff_head *frag_list,
3495 struct sk_buff *cur_frag)
3496 {
3497 struct sk_buff *skb;
3498 int cmp;
3499
3500 skb_queue_walk(frag_list, skb) {
3501 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3502 if (cmp < 0)
3503 continue;
3504 __skb_queue_before(frag_list, skb, cur_frag);
3505 return;
3506 }
3507 __skb_queue_tail(frag_list, cur_frag);
3508 }
3509
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3510 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3511 {
3512 struct ieee80211_hdr *hdr;
3513 u64 pn = 0;
3514 u8 *ehdr;
3515 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3516
3517 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3518 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3519
3520 pn = ehdr[0];
3521 pn |= (u64)ehdr[1] << 8;
3522 pn |= (u64)ehdr[4] << 16;
3523 pn |= (u64)ehdr[5] << 24;
3524 pn |= (u64)ehdr[6] << 32;
3525 pn |= (u64)ehdr[7] << 40;
3526
3527 return pn;
3528 }
3529
3530 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3531 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3532 {
3533 enum hal_encrypt_type encrypt_type;
3534 struct sk_buff *first_frag, *skb;
3535 struct hal_rx_desc *desc;
3536 u64 last_pn;
3537 u64 cur_pn;
3538
3539 first_frag = skb_peek(&rx_tid->rx_frags);
3540 desc = (struct hal_rx_desc *)first_frag->data;
3541
3542 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3543 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3544 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3545 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3546 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3547 return true;
3548
3549 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3550 skb_queue_walk(&rx_tid->rx_frags, skb) {
3551 if (skb == first_frag)
3552 continue;
3553
3554 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3555 if (cur_pn != last_pn + 1)
3556 return false;
3557 last_pn = cur_pn;
3558 }
3559 return true;
3560 }
3561
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3562 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3563 struct sk_buff *msdu,
3564 u32 *ring_desc)
3565 {
3566 struct ath11k_base *ab = ar->ab;
3567 struct hal_rx_desc *rx_desc;
3568 struct ath11k_peer *peer;
3569 struct dp_rx_tid *rx_tid;
3570 struct sk_buff *defrag_skb = NULL;
3571 u32 peer_id;
3572 u16 seqno, frag_no;
3573 u8 tid;
3574 int ret = 0;
3575 bool more_frags;
3576 bool is_mcbc;
3577
3578 rx_desc = (struct hal_rx_desc *)msdu->data;
3579 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3580 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3581 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3582 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3583 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3584 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3585
3586 /* Multicast/Broadcast fragments are not expected */
3587 if (is_mcbc)
3588 return -EINVAL;
3589
3590 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3591 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3592 tid > IEEE80211_NUM_TIDS)
3593 return -EINVAL;
3594
3595 /* received unfragmented packet in reo
3596 * exception ring, this shouldn't happen
3597 * as these packets typically come from
3598 * reo2sw srngs.
3599 */
3600 if (WARN_ON_ONCE(!frag_no && !more_frags))
3601 return -EINVAL;
3602
3603 spin_lock_bh(&ab->base_lock);
3604 peer = ath11k_peer_find_by_id(ab, peer_id);
3605 if (!peer) {
3606 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3607 peer_id);
3608 ret = -ENOENT;
3609 goto out_unlock;
3610 }
3611 if (!peer->dp_setup_done) {
3612 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3613 peer->addr, peer_id);
3614 ret = -ENOENT;
3615 goto out_unlock;
3616 }
3617
3618 rx_tid = &peer->rx_tid[tid];
3619
3620 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3621 skb_queue_empty(&rx_tid->rx_frags)) {
3622 /* Flush stored fragments and start a new sequence */
3623 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3624 rx_tid->cur_sn = seqno;
3625 }
3626
3627 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3628 /* Fragment already present */
3629 ret = -EINVAL;
3630 goto out_unlock;
3631 }
3632
3633 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3634 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3635 else
3636 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3637
3638 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3639 if (!more_frags)
3640 rx_tid->last_frag_no = frag_no;
3641
3642 if (frag_no == 0) {
3643 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3644 sizeof(*rx_tid->dst_ring_desc),
3645 GFP_ATOMIC);
3646 if (!rx_tid->dst_ring_desc) {
3647 ret = -ENOMEM;
3648 goto out_unlock;
3649 }
3650 } else {
3651 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3652 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3653 }
3654
3655 if (!rx_tid->last_frag_no ||
3656 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3657 mod_timer(&rx_tid->frag_timer, jiffies +
3658 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3659 goto out_unlock;
3660 }
3661
3662 spin_unlock_bh(&ab->base_lock);
3663 del_timer_sync(&rx_tid->frag_timer);
3664 spin_lock_bh(&ab->base_lock);
3665
3666 peer = ath11k_peer_find_by_id(ab, peer_id);
3667 if (!peer)
3668 goto err_frags_cleanup;
3669
3670 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3671 goto err_frags_cleanup;
3672
3673 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3674 goto err_frags_cleanup;
3675
3676 if (!defrag_skb)
3677 goto err_frags_cleanup;
3678
3679 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3680 goto err_frags_cleanup;
3681
3682 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3683 goto out_unlock;
3684
3685 err_frags_cleanup:
3686 dev_kfree_skb_any(defrag_skb);
3687 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3688 out_unlock:
3689 spin_unlock_bh(&ab->base_lock);
3690 return ret;
3691 }
3692
3693 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3694 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3695 {
3696 struct ath11k_pdev_dp *dp = &ar->dp;
3697 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3698 struct sk_buff *msdu;
3699 struct ath11k_skb_rxcb *rxcb;
3700 struct hal_rx_desc *rx_desc;
3701 u8 *hdr_status;
3702 u16 msdu_len;
3703 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3704
3705 spin_lock_bh(&rx_ring->idr_lock);
3706 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3707 if (!msdu) {
3708 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3709 buf_id);
3710 spin_unlock_bh(&rx_ring->idr_lock);
3711 return -EINVAL;
3712 }
3713
3714 idr_remove(&rx_ring->bufs_idr, buf_id);
3715 spin_unlock_bh(&rx_ring->idr_lock);
3716
3717 rxcb = ATH11K_SKB_RXCB(msdu);
3718 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3719 msdu->len + skb_tailroom(msdu),
3720 DMA_FROM_DEVICE);
3721
3722 if (drop) {
3723 dev_kfree_skb_any(msdu);
3724 return 0;
3725 }
3726
3727 rcu_read_lock();
3728 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3729 dev_kfree_skb_any(msdu);
3730 goto exit;
3731 }
3732
3733 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3734 dev_kfree_skb_any(msdu);
3735 goto exit;
3736 }
3737
3738 rx_desc = (struct hal_rx_desc *)msdu->data;
3739 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3740 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3741 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3742 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3743 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3744 sizeof(struct ieee80211_hdr));
3745 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3746 sizeof(struct hal_rx_desc));
3747 dev_kfree_skb_any(msdu);
3748 goto exit;
3749 }
3750
3751 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3752
3753 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3754 dev_kfree_skb_any(msdu);
3755 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3756 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3757 }
3758 exit:
3759 rcu_read_unlock();
3760 return 0;
3761 }
3762
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3763 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3764 int budget)
3765 {
3766 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3767 struct dp_link_desc_bank *link_desc_banks;
3768 enum hal_rx_buf_return_buf_manager rbm;
3769 int tot_n_bufs_reaped, quota, ret, i;
3770 int n_bufs_reaped[MAX_RADIOS] = {0};
3771 struct dp_rxdma_ring *rx_ring;
3772 struct dp_srng *reo_except;
3773 u32 desc_bank, num_msdus;
3774 struct hal_srng *srng;
3775 struct ath11k_dp *dp;
3776 void *link_desc_va;
3777 int buf_id, mac_id;
3778 struct ath11k *ar;
3779 dma_addr_t paddr;
3780 u32 *desc;
3781 bool is_frag;
3782 u8 drop = 0;
3783
3784 tot_n_bufs_reaped = 0;
3785 quota = budget;
3786
3787 dp = &ab->dp;
3788 reo_except = &dp->reo_except_ring;
3789 link_desc_banks = dp->link_desc_banks;
3790
3791 srng = &ab->hal.srng_list[reo_except->ring_id];
3792
3793 spin_lock_bh(&srng->lock);
3794
3795 ath11k_hal_srng_access_begin(ab, srng);
3796
3797 while (budget &&
3798 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3799 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3800
3801 ab->soc_stats.err_ring_pkts++;
3802 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3803 &desc_bank);
3804 if (ret) {
3805 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3806 ret);
3807 continue;
3808 }
3809 link_desc_va = link_desc_banks[desc_bank].vaddr +
3810 (paddr - link_desc_banks[desc_bank].paddr);
3811 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3812 &rbm);
3813 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3814 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3815 ab->soc_stats.invalid_rbm++;
3816 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3817 ath11k_dp_rx_link_desc_return(ab, desc,
3818 HAL_WBM_REL_BM_ACT_REL_MSDU);
3819 continue;
3820 }
3821
3822 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3823
3824 /* Process only rx fragments with one msdu per link desc below, and drop
3825 * msdu's indicated due to error reasons.
3826 */
3827 if (!is_frag || num_msdus > 1) {
3828 drop = 1;
3829 /* Return the link desc back to wbm idle list */
3830 ath11k_dp_rx_link_desc_return(ab, desc,
3831 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3832 }
3833
3834 for (i = 0; i < num_msdus; i++) {
3835 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3836 msdu_cookies[i]);
3837
3838 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3839 msdu_cookies[i]);
3840
3841 ar = ab->pdevs[mac_id].ar;
3842
3843 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3844 n_bufs_reaped[mac_id]++;
3845 tot_n_bufs_reaped++;
3846 }
3847 }
3848
3849 if (tot_n_bufs_reaped >= quota) {
3850 tot_n_bufs_reaped = quota;
3851 goto exit;
3852 }
3853
3854 budget = quota - tot_n_bufs_reaped;
3855 }
3856
3857 exit:
3858 ath11k_hal_srng_access_end(ab, srng);
3859
3860 spin_unlock_bh(&srng->lock);
3861
3862 for (i = 0; i < ab->num_radios; i++) {
3863 if (!n_bufs_reaped[i])
3864 continue;
3865
3866 ar = ab->pdevs[i].ar;
3867 rx_ring = &ar->dp.rx_refill_buf_ring;
3868
3869 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3870 ab->hw_params.hal_params->rx_buf_rbm);
3871 }
3872
3873 return tot_n_bufs_reaped;
3874 }
3875
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3876 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3877 int msdu_len,
3878 struct sk_buff_head *msdu_list)
3879 {
3880 struct sk_buff *skb, *tmp;
3881 struct ath11k_skb_rxcb *rxcb;
3882 int n_buffs;
3883
3884 n_buffs = DIV_ROUND_UP(msdu_len,
3885 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3886
3887 skb_queue_walk_safe(msdu_list, skb, tmp) {
3888 rxcb = ATH11K_SKB_RXCB(skb);
3889 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3890 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3891 if (!n_buffs)
3892 break;
3893 __skb_unlink(skb, msdu_list);
3894 dev_kfree_skb_any(skb);
3895 n_buffs--;
3896 }
3897 }
3898 }
3899
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3900 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3901 struct ieee80211_rx_status *status,
3902 struct sk_buff_head *msdu_list)
3903 {
3904 u16 msdu_len;
3905 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3906 struct rx_attention *rx_attention;
3907 u8 l3pad_bytes;
3908 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3909 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3910
3911 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3912
3913 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3914 /* First buffer will be freed by the caller, so deduct it's length */
3915 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3916 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3917 return -EINVAL;
3918 }
3919
3920 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3921 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3922 ath11k_warn(ar->ab,
3923 "msdu_done bit not set in null_q_des processing\n");
3924 __skb_queue_purge(msdu_list);
3925 return -EIO;
3926 }
3927
3928 /* Handle NULL queue descriptor violations arising out a missing
3929 * REO queue for a given peer or a given TID. This typically
3930 * may happen if a packet is received on a QOS enabled TID before the
3931 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3932 * it may also happen for MC/BC frames if they are not routed to the
3933 * non-QOS TID queue, in the absence of any other default TID queue.
3934 * This error can show up both in a REO destination or WBM release ring.
3935 */
3936
3937 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3938 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3939
3940 if (rxcb->is_frag) {
3941 skb_pull(msdu, hal_rx_desc_sz);
3942 } else {
3943 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3944
3945 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3946 return -EINVAL;
3947
3948 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3949 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3950 }
3951 ath11k_dp_rx_h_ppdu(ar, desc, status);
3952
3953 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3954
3955 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3956
3957 /* Please note that caller will having the access to msdu and completing
3958 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3959 */
3960
3961 return 0;
3962 }
3963
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3964 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3965 struct ieee80211_rx_status *status,
3966 struct sk_buff_head *msdu_list)
3967 {
3968 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3969 bool drop = false;
3970
3971 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3972
3973 switch (rxcb->err_code) {
3974 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3975 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3976 drop = true;
3977 break;
3978 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3979 /* TODO: Do not drop PN failed packets in the driver;
3980 * instead, it is good to drop such packets in mac80211
3981 * after incrementing the replay counters.
3982 */
3983 fallthrough;
3984 default:
3985 /* TODO: Review other errors and process them to mac80211
3986 * as appropriate.
3987 */
3988 drop = true;
3989 break;
3990 }
3991
3992 return drop;
3993 }
3994
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3995 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3996 struct ieee80211_rx_status *status)
3997 {
3998 u16 msdu_len;
3999 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4000 u8 l3pad_bytes;
4001 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4002 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4003
4004 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4005 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4006
4007 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4008 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4009 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4010 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4011
4012 ath11k_dp_rx_h_ppdu(ar, desc, status);
4013
4014 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4015 RX_FLAG_DECRYPTED);
4016
4017 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4018 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4019 }
4020
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4021 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4022 struct ieee80211_rx_status *status)
4023 {
4024 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4025 bool drop = false;
4026
4027 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4028
4029 switch (rxcb->err_code) {
4030 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4031 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4032 break;
4033 default:
4034 /* TODO: Review other rxdma error code to check if anything is
4035 * worth reporting to mac80211
4036 */
4037 drop = true;
4038 break;
4039 }
4040
4041 return drop;
4042 }
4043
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4044 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4045 struct napi_struct *napi,
4046 struct sk_buff *msdu,
4047 struct sk_buff_head *msdu_list)
4048 {
4049 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4050 struct ieee80211_rx_status rxs = {0};
4051 bool drop = true;
4052
4053 switch (rxcb->err_rel_src) {
4054 case HAL_WBM_REL_SRC_MODULE_REO:
4055 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4056 break;
4057 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4058 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4059 break;
4060 default:
4061 /* msdu will get freed */
4062 break;
4063 }
4064
4065 if (drop) {
4066 dev_kfree_skb_any(msdu);
4067 return;
4068 }
4069
4070 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4071 }
4072
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4073 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4074 struct napi_struct *napi, int budget)
4075 {
4076 struct ath11k *ar;
4077 struct ath11k_dp *dp = &ab->dp;
4078 struct dp_rxdma_ring *rx_ring;
4079 struct hal_rx_wbm_rel_info err_info;
4080 struct hal_srng *srng;
4081 struct sk_buff *msdu;
4082 struct sk_buff_head msdu_list[MAX_RADIOS];
4083 struct ath11k_skb_rxcb *rxcb;
4084 u32 *rx_desc;
4085 int buf_id, mac_id;
4086 int num_buffs_reaped[MAX_RADIOS] = {0};
4087 int total_num_buffs_reaped = 0;
4088 int ret, i;
4089
4090 for (i = 0; i < ab->num_radios; i++)
4091 __skb_queue_head_init(&msdu_list[i]);
4092
4093 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4094
4095 spin_lock_bh(&srng->lock);
4096
4097 ath11k_hal_srng_access_begin(ab, srng);
4098
4099 while (budget) {
4100 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4101 if (!rx_desc)
4102 break;
4103
4104 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4105 if (ret) {
4106 ath11k_warn(ab,
4107 "failed to parse rx error in wbm_rel ring desc %d\n",
4108 ret);
4109 continue;
4110 }
4111
4112 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4113 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4114
4115 ar = ab->pdevs[mac_id].ar;
4116 rx_ring = &ar->dp.rx_refill_buf_ring;
4117
4118 spin_lock_bh(&rx_ring->idr_lock);
4119 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4120 if (!msdu) {
4121 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4122 buf_id, mac_id);
4123 spin_unlock_bh(&rx_ring->idr_lock);
4124 continue;
4125 }
4126
4127 idr_remove(&rx_ring->bufs_idr, buf_id);
4128 spin_unlock_bh(&rx_ring->idr_lock);
4129
4130 rxcb = ATH11K_SKB_RXCB(msdu);
4131 dma_unmap_single(ab->dev, rxcb->paddr,
4132 msdu->len + skb_tailroom(msdu),
4133 DMA_FROM_DEVICE);
4134
4135 num_buffs_reaped[mac_id]++;
4136 total_num_buffs_reaped++;
4137 budget--;
4138
4139 if (err_info.push_reason !=
4140 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4141 dev_kfree_skb_any(msdu);
4142 continue;
4143 }
4144
4145 rxcb->err_rel_src = err_info.err_rel_src;
4146 rxcb->err_code = err_info.err_code;
4147 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4148 __skb_queue_tail(&msdu_list[mac_id], msdu);
4149 }
4150
4151 ath11k_hal_srng_access_end(ab, srng);
4152
4153 spin_unlock_bh(&srng->lock);
4154
4155 if (!total_num_buffs_reaped)
4156 goto done;
4157
4158 for (i = 0; i < ab->num_radios; i++) {
4159 if (!num_buffs_reaped[i])
4160 continue;
4161
4162 ar = ab->pdevs[i].ar;
4163 rx_ring = &ar->dp.rx_refill_buf_ring;
4164
4165 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4166 ab->hw_params.hal_params->rx_buf_rbm);
4167 }
4168
4169 rcu_read_lock();
4170 for (i = 0; i < ab->num_radios; i++) {
4171 if (!rcu_dereference(ab->pdevs_active[i])) {
4172 __skb_queue_purge(&msdu_list[i]);
4173 continue;
4174 }
4175
4176 ar = ab->pdevs[i].ar;
4177
4178 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4179 __skb_queue_purge(&msdu_list[i]);
4180 continue;
4181 }
4182
4183 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4184 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4185 }
4186 rcu_read_unlock();
4187 done:
4188 return total_num_buffs_reaped;
4189 }
4190
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4191 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4192 {
4193 struct ath11k *ar;
4194 struct dp_srng *err_ring;
4195 struct dp_rxdma_ring *rx_ring;
4196 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4197 struct hal_srng *srng;
4198 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4199 enum hal_rx_buf_return_buf_manager rbm;
4200 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4201 struct ath11k_skb_rxcb *rxcb;
4202 struct sk_buff *skb;
4203 struct hal_reo_entrance_ring *entr_ring;
4204 void *desc;
4205 int num_buf_freed = 0;
4206 int quota = budget;
4207 dma_addr_t paddr;
4208 u32 desc_bank;
4209 void *link_desc_va;
4210 int num_msdus;
4211 int i;
4212 int buf_id;
4213
4214 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4215 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4216 mac_id)];
4217 rx_ring = &ar->dp.rx_refill_buf_ring;
4218
4219 srng = &ab->hal.srng_list[err_ring->ring_id];
4220
4221 spin_lock_bh(&srng->lock);
4222
4223 ath11k_hal_srng_access_begin(ab, srng);
4224
4225 while (quota-- &&
4226 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4227 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4228
4229 entr_ring = (struct hal_reo_entrance_ring *)desc;
4230 rxdma_err_code =
4231 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4232 entr_ring->info1);
4233 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4234
4235 link_desc_va = link_desc_banks[desc_bank].vaddr +
4236 (paddr - link_desc_banks[desc_bank].paddr);
4237 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4238 msdu_cookies, &rbm);
4239
4240 for (i = 0; i < num_msdus; i++) {
4241 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4242 msdu_cookies[i]);
4243
4244 spin_lock_bh(&rx_ring->idr_lock);
4245 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4246 if (!skb) {
4247 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4248 buf_id);
4249 spin_unlock_bh(&rx_ring->idr_lock);
4250 continue;
4251 }
4252
4253 idr_remove(&rx_ring->bufs_idr, buf_id);
4254 spin_unlock_bh(&rx_ring->idr_lock);
4255
4256 rxcb = ATH11K_SKB_RXCB(skb);
4257 dma_unmap_single(ab->dev, rxcb->paddr,
4258 skb->len + skb_tailroom(skb),
4259 DMA_FROM_DEVICE);
4260 dev_kfree_skb_any(skb);
4261
4262 num_buf_freed++;
4263 }
4264
4265 ath11k_dp_rx_link_desc_return(ab, desc,
4266 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4267 }
4268
4269 ath11k_hal_srng_access_end(ab, srng);
4270
4271 spin_unlock_bh(&srng->lock);
4272
4273 if (num_buf_freed)
4274 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4275 ab->hw_params.hal_params->rx_buf_rbm);
4276
4277 return budget - quota;
4278 }
4279
ath11k_dp_process_reo_status(struct ath11k_base * ab)4280 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4281 {
4282 struct ath11k_dp *dp = &ab->dp;
4283 struct hal_srng *srng;
4284 struct dp_reo_cmd *cmd, *tmp;
4285 bool found = false;
4286 u32 *reo_desc;
4287 u16 tag;
4288 struct hal_reo_status reo_status;
4289
4290 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4291
4292 memset(&reo_status, 0, sizeof(reo_status));
4293
4294 spin_lock_bh(&srng->lock);
4295
4296 ath11k_hal_srng_access_begin(ab, srng);
4297
4298 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4299 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4300
4301 switch (tag) {
4302 case HAL_REO_GET_QUEUE_STATS_STATUS:
4303 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4304 &reo_status);
4305 break;
4306 case HAL_REO_FLUSH_QUEUE_STATUS:
4307 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4308 &reo_status);
4309 break;
4310 case HAL_REO_FLUSH_CACHE_STATUS:
4311 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4312 &reo_status);
4313 break;
4314 case HAL_REO_UNBLOCK_CACHE_STATUS:
4315 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4316 &reo_status);
4317 break;
4318 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4319 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4320 &reo_status);
4321 break;
4322 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4323 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4324 &reo_status);
4325 break;
4326 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4327 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4328 &reo_status);
4329 break;
4330 default:
4331 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4332 continue;
4333 }
4334
4335 spin_lock_bh(&dp->reo_cmd_lock);
4336 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4337 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4338 found = true;
4339 list_del(&cmd->list);
4340 break;
4341 }
4342 }
4343 spin_unlock_bh(&dp->reo_cmd_lock);
4344
4345 if (found) {
4346 cmd->handler(dp, (void *)&cmd->data,
4347 reo_status.uniform_hdr.cmd_status);
4348 kfree(cmd);
4349 }
4350
4351 found = false;
4352 }
4353
4354 ath11k_hal_srng_access_end(ab, srng);
4355
4356 spin_unlock_bh(&srng->lock);
4357 }
4358
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4359 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4360 {
4361 struct ath11k *ar = ab->pdevs[mac_id].ar;
4362
4363 ath11k_dp_rx_pdev_srng_free(ar);
4364 ath11k_dp_rxdma_pdev_buf_free(ar);
4365 }
4366
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4367 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4368 {
4369 struct ath11k *ar = ab->pdevs[mac_id].ar;
4370 struct ath11k_pdev_dp *dp = &ar->dp;
4371 u32 ring_id;
4372 int i;
4373 int ret;
4374
4375 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4376 if (ret) {
4377 ath11k_warn(ab, "failed to setup rx srngs\n");
4378 return ret;
4379 }
4380
4381 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4382 if (ret) {
4383 ath11k_warn(ab, "failed to setup rxdma ring\n");
4384 return ret;
4385 }
4386
4387 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4388 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4389 if (ret) {
4390 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4391 ret);
4392 return ret;
4393 }
4394
4395 if (ab->hw_params.rx_mac_buf_ring) {
4396 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4397 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4398 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4399 mac_id + i, HAL_RXDMA_BUF);
4400 if (ret) {
4401 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4402 i, ret);
4403 return ret;
4404 }
4405 }
4406 }
4407
4408 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4409 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4410 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4411 mac_id + i, HAL_RXDMA_DST);
4412 if (ret) {
4413 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4414 i, ret);
4415 return ret;
4416 }
4417 }
4418
4419 if (!ab->hw_params.rxdma1_enable)
4420 goto config_refill_ring;
4421
4422 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4423 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4424 mac_id, HAL_RXDMA_MONITOR_BUF);
4425 if (ret) {
4426 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4427 ret);
4428 return ret;
4429 }
4430 ret = ath11k_dp_tx_htt_srng_setup(ab,
4431 dp->rxdma_mon_dst_ring.ring_id,
4432 mac_id, HAL_RXDMA_MONITOR_DST);
4433 if (ret) {
4434 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4435 ret);
4436 return ret;
4437 }
4438 ret = ath11k_dp_tx_htt_srng_setup(ab,
4439 dp->rxdma_mon_desc_ring.ring_id,
4440 mac_id, HAL_RXDMA_MONITOR_DESC);
4441 if (ret) {
4442 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4443 ret);
4444 return ret;
4445 }
4446
4447 config_refill_ring:
4448 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4449 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4450 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4451 HAL_RXDMA_MONITOR_STATUS);
4452 if (ret) {
4453 ath11k_warn(ab,
4454 "failed to configure mon_status_refill_ring%d %d\n",
4455 i, ret);
4456 return ret;
4457 }
4458 }
4459
4460 return 0;
4461 }
4462
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4463 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4464 {
4465 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4466 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4467 *total_len -= *frag_len;
4468 } else {
4469 *frag_len = *total_len;
4470 *total_len = 0;
4471 }
4472 }
4473
4474 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4475 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4476 void *p_last_buf_addr_info,
4477 u8 mac_id)
4478 {
4479 struct ath11k_pdev_dp *dp = &ar->dp;
4480 struct dp_srng *dp_srng;
4481 void *hal_srng;
4482 void *src_srng_desc;
4483 int ret = 0;
4484
4485 if (ar->ab->hw_params.rxdma1_enable) {
4486 dp_srng = &dp->rxdma_mon_desc_ring;
4487 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4488 } else {
4489 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4490 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4491 }
4492
4493 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4494
4495 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4496
4497 if (src_srng_desc) {
4498 struct ath11k_buffer_addr *src_desc =
4499 (struct ath11k_buffer_addr *)src_srng_desc;
4500
4501 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4502 } else {
4503 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4504 "Monitor Link Desc Ring %d Full", mac_id);
4505 ret = -ENOMEM;
4506 }
4507
4508 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4509 return ret;
4510 }
4511
4512 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4513 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4514 dma_addr_t *paddr, u32 *sw_cookie,
4515 u8 *rbm,
4516 void **pp_buf_addr_info)
4517 {
4518 struct hal_rx_msdu_link *msdu_link =
4519 (struct hal_rx_msdu_link *)rx_msdu_link_desc;
4520 struct ath11k_buffer_addr *buf_addr_info;
4521
4522 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4523
4524 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4525
4526 *pp_buf_addr_info = (void *)buf_addr_info;
4527 }
4528
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4529 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4530 {
4531 if (skb->len > len) {
4532 skb_trim(skb, len);
4533 } else {
4534 if (skb_tailroom(skb) < len - skb->len) {
4535 if ((pskb_expand_head(skb, 0,
4536 len - skb->len - skb_tailroom(skb),
4537 GFP_ATOMIC))) {
4538 dev_kfree_skb_any(skb);
4539 return -ENOMEM;
4540 }
4541 }
4542 skb_put(skb, (len - skb->len));
4543 }
4544 return 0;
4545 }
4546
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4547 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4548 void *msdu_link_desc,
4549 struct hal_rx_msdu_list *msdu_list,
4550 u16 *num_msdus)
4551 {
4552 struct hal_rx_msdu_details *msdu_details = NULL;
4553 struct rx_msdu_desc *msdu_desc_info = NULL;
4554 struct hal_rx_msdu_link *msdu_link = NULL;
4555 int i;
4556 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4557 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4558 u8 tmp = 0;
4559
4560 msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4561 msdu_details = &msdu_link->msdu_link[0];
4562
4563 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4564 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4565 msdu_details[i].buf_addr_info.info0) == 0) {
4566 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4567 msdu_desc_info->info0 |= last;
4568 ;
4569 break;
4570 }
4571 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4572
4573 if (!i)
4574 msdu_desc_info->info0 |= first;
4575 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4576 msdu_desc_info->info0 |= last;
4577 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4578 msdu_list->msdu_info[i].msdu_len =
4579 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4580 msdu_list->sw_cookie[i] =
4581 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4582 msdu_details[i].buf_addr_info.info1);
4583 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4584 msdu_details[i].buf_addr_info.info1);
4585 msdu_list->rbm[i] = tmp;
4586 }
4587 *num_msdus = i;
4588 }
4589
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4590 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4591 u32 *rx_bufs_used)
4592 {
4593 u32 ret = 0;
4594
4595 if ((*ppdu_id < msdu_ppdu_id) &&
4596 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4597 *ppdu_id = msdu_ppdu_id;
4598 ret = msdu_ppdu_id;
4599 } else if ((*ppdu_id > msdu_ppdu_id) &&
4600 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4601 /* mon_dst is behind than mon_status
4602 * skip dst_ring and free it
4603 */
4604 *rx_bufs_used += 1;
4605 *ppdu_id = msdu_ppdu_id;
4606 ret = msdu_ppdu_id;
4607 }
4608 return ret;
4609 }
4610
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4611 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4612 bool *is_frag, u32 *total_len,
4613 u32 *frag_len, u32 *msdu_cnt)
4614 {
4615 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4616 if (!*is_frag) {
4617 *total_len = info->msdu_len;
4618 *is_frag = true;
4619 }
4620 ath11k_dp_mon_set_frag_len(total_len,
4621 frag_len);
4622 } else {
4623 if (*is_frag) {
4624 ath11k_dp_mon_set_frag_len(total_len,
4625 frag_len);
4626 } else {
4627 *frag_len = info->msdu_len;
4628 }
4629 *is_frag = false;
4630 *msdu_cnt -= 1;
4631 }
4632 }
4633
4634 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4635 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4636 void *ring_entry, struct sk_buff **head_msdu,
4637 struct sk_buff **tail_msdu, u32 *npackets,
4638 u32 *ppdu_id)
4639 {
4640 struct ath11k_pdev_dp *dp = &ar->dp;
4641 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4642 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4643 struct sk_buff *msdu = NULL, *last = NULL;
4644 struct hal_rx_msdu_list msdu_list;
4645 void *p_buf_addr_info, *p_last_buf_addr_info;
4646 struct hal_rx_desc *rx_desc;
4647 void *rx_msdu_link_desc;
4648 dma_addr_t paddr;
4649 u16 num_msdus = 0;
4650 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4651 u32 rx_bufs_used = 0, i = 0;
4652 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4653 u32 total_len = 0, frag_len = 0;
4654 bool is_frag, is_first_msdu;
4655 bool drop_mpdu = false;
4656 struct ath11k_skb_rxcb *rxcb;
4657 struct hal_reo_entrance_ring *ent_desc =
4658 (struct hal_reo_entrance_ring *)ring_entry;
4659 int buf_id;
4660 u32 rx_link_buf_info[2];
4661 u8 rbm;
4662
4663 if (!ar->ab->hw_params.rxdma1_enable)
4664 rx_ring = &dp->rx_refill_buf_ring;
4665
4666 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4667 &sw_cookie,
4668 &p_last_buf_addr_info, &rbm,
4669 &msdu_cnt);
4670
4671 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4672 ent_desc->info1) ==
4673 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4674 u8 rxdma_err =
4675 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4676 ent_desc->info1);
4677 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4678 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4679 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4680 drop_mpdu = true;
4681 pmon->rx_mon_stats.dest_mpdu_drop++;
4682 }
4683 }
4684
4685 is_frag = false;
4686 is_first_msdu = true;
4687
4688 do {
4689 if (pmon->mon_last_linkdesc_paddr == paddr) {
4690 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4691 return rx_bufs_used;
4692 }
4693
4694 if (ar->ab->hw_params.rxdma1_enable)
4695 rx_msdu_link_desc =
4696 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4697 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4698 else
4699 rx_msdu_link_desc =
4700 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4701 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4702
4703 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4704 &num_msdus);
4705
4706 for (i = 0; i < num_msdus; i++) {
4707 u32 l2_hdr_offset;
4708
4709 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4710 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4711 "i %d last_cookie %d is same\n",
4712 i, pmon->mon_last_buf_cookie);
4713 drop_mpdu = true;
4714 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4715 continue;
4716 }
4717 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4718 msdu_list.sw_cookie[i]);
4719
4720 spin_lock_bh(&rx_ring->idr_lock);
4721 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4722 spin_unlock_bh(&rx_ring->idr_lock);
4723 if (!msdu) {
4724 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4725 "msdu_pop: invalid buf_id %d\n", buf_id);
4726 break;
4727 }
4728 rxcb = ATH11K_SKB_RXCB(msdu);
4729 if (!rxcb->unmapped) {
4730 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4731 msdu->len +
4732 skb_tailroom(msdu),
4733 DMA_FROM_DEVICE);
4734 rxcb->unmapped = 1;
4735 }
4736 if (drop_mpdu) {
4737 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4738 "i %d drop msdu %p *ppdu_id %x\n",
4739 i, msdu, *ppdu_id);
4740 dev_kfree_skb_any(msdu);
4741 msdu = NULL;
4742 goto next_msdu;
4743 }
4744
4745 rx_desc = (struct hal_rx_desc *)msdu->data;
4746
4747 rx_pkt_offset = sizeof(struct hal_rx_desc);
4748 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4749
4750 if (is_first_msdu) {
4751 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4752 drop_mpdu = true;
4753 dev_kfree_skb_any(msdu);
4754 msdu = NULL;
4755 pmon->mon_last_linkdesc_paddr = paddr;
4756 goto next_msdu;
4757 }
4758
4759 msdu_ppdu_id =
4760 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4761
4762 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4763 ppdu_id,
4764 &rx_bufs_used)) {
4765 if (rx_bufs_used) {
4766 drop_mpdu = true;
4767 dev_kfree_skb_any(msdu);
4768 msdu = NULL;
4769 goto next_msdu;
4770 }
4771 return rx_bufs_used;
4772 }
4773 pmon->mon_last_linkdesc_paddr = paddr;
4774 is_first_msdu = false;
4775 }
4776 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4777 &is_frag, &total_len,
4778 &frag_len, &msdu_cnt);
4779 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4780
4781 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4782
4783 if (!(*head_msdu))
4784 *head_msdu = msdu;
4785 else if (last)
4786 last->next = msdu;
4787
4788 last = msdu;
4789 next_msdu:
4790 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4791 rx_bufs_used++;
4792 spin_lock_bh(&rx_ring->idr_lock);
4793 idr_remove(&rx_ring->bufs_idr, buf_id);
4794 spin_unlock_bh(&rx_ring->idr_lock);
4795 }
4796
4797 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4798
4799 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4800 &sw_cookie, &rbm,
4801 &p_buf_addr_info);
4802
4803 if (ar->ab->hw_params.rxdma1_enable) {
4804 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4805 p_last_buf_addr_info,
4806 dp->mac_id))
4807 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4808 "dp_rx_monitor_link_desc_return failed");
4809 } else {
4810 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4811 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4812 }
4813
4814 p_last_buf_addr_info = p_buf_addr_info;
4815
4816 } while (paddr && msdu_cnt);
4817
4818 if (last)
4819 last->next = NULL;
4820
4821 *tail_msdu = msdu;
4822
4823 if (msdu_cnt == 0)
4824 *npackets = 1;
4825
4826 return rx_bufs_used;
4827 }
4828
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4829 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4830 {
4831 u32 rx_pkt_offset, l2_hdr_offset;
4832
4833 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4834 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4835 (struct hal_rx_desc *)msdu->data);
4836 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4837 }
4838
4839 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4840 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4841 u32 mac_id, struct sk_buff *head_msdu,
4842 struct sk_buff *last_msdu,
4843 struct ieee80211_rx_status *rxs, bool *fcs_err)
4844 {
4845 struct ath11k_base *ab = ar->ab;
4846 struct sk_buff *msdu, *prev_buf;
4847 struct hal_rx_desc *rx_desc;
4848 char *hdr_desc;
4849 u8 *dest, decap_format;
4850 struct ieee80211_hdr_3addr *wh;
4851 struct rx_attention *rx_attention;
4852 u32 err_bitmap;
4853
4854 if (!head_msdu)
4855 goto err_merge_fail;
4856
4857 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4858 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4859 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4860
4861 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4862 *fcs_err = true;
4863
4864 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4865 return NULL;
4866
4867 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4868
4869 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4870
4871 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4872 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4873
4874 prev_buf = head_msdu;
4875 msdu = head_msdu->next;
4876
4877 while (msdu) {
4878 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4879
4880 prev_buf = msdu;
4881 msdu = msdu->next;
4882 }
4883
4884 prev_buf->next = NULL;
4885
4886 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4887 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4888 u8 qos_pkt = 0;
4889
4890 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4891 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4892
4893 /* Base size */
4894 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4895
4896 if (ieee80211_is_data_qos(wh->frame_control))
4897 qos_pkt = 1;
4898
4899 msdu = head_msdu;
4900
4901 while (msdu) {
4902 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4903 if (qos_pkt) {
4904 dest = skb_push(msdu, sizeof(__le16));
4905 if (!dest)
4906 goto err_merge_fail;
4907 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4908 }
4909 prev_buf = msdu;
4910 msdu = msdu->next;
4911 }
4912 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4913 if (!dest)
4914 goto err_merge_fail;
4915
4916 ath11k_dbg(ab, ATH11K_DBG_DATA,
4917 "mpdu_buf %p mpdu_buf->len %u",
4918 prev_buf, prev_buf->len);
4919 } else {
4920 ath11k_dbg(ab, ATH11K_DBG_DATA,
4921 "decap format %d is not supported!\n",
4922 decap_format);
4923 goto err_merge_fail;
4924 }
4925
4926 return head_msdu;
4927
4928 err_merge_fail:
4929 return NULL;
4930 }
4931
4932 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4933 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4934 u8 *rtap_buf)
4935 {
4936 u32 rtap_len = 0;
4937
4938 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4939 rtap_len += 2;
4940
4941 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4942 rtap_len += 2;
4943
4944 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4945 rtap_len += 2;
4946
4947 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
4948 rtap_len += 2;
4949
4950 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
4951 rtap_len += 2;
4952
4953 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
4954 }
4955
4956 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4957 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
4958 u8 *rtap_buf)
4959 {
4960 u32 rtap_len = 0;
4961
4962 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
4963 rtap_len += 2;
4964
4965 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
4966 rtap_len += 2;
4967
4968 rtap_buf[rtap_len] = rx_status->he_RU[0];
4969 rtap_len += 1;
4970
4971 rtap_buf[rtap_len] = rx_status->he_RU[1];
4972 rtap_len += 1;
4973
4974 rtap_buf[rtap_len] = rx_status->he_RU[2];
4975 rtap_len += 1;
4976
4977 rtap_buf[rtap_len] = rx_status->he_RU[3];
4978 }
4979
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)4980 static void ath11k_update_radiotap(struct ath11k *ar,
4981 struct hal_rx_mon_ppdu_info *ppduinfo,
4982 struct sk_buff *mon_skb,
4983 struct ieee80211_rx_status *rxs)
4984 {
4985 struct ieee80211_supported_band *sband;
4986 u8 *ptr = NULL;
4987
4988 rxs->flag |= RX_FLAG_MACTIME_START;
4989 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
4990
4991 if (ppduinfo->nss)
4992 rxs->nss = ppduinfo->nss;
4993
4994 if (ppduinfo->he_mu_flags) {
4995 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
4996 rxs->encoding = RX_ENC_HE;
4997 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
4998 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
4999 } else if (ppduinfo->he_flags) {
5000 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5001 rxs->encoding = RX_ENC_HE;
5002 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5003 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5004 rxs->rate_idx = ppduinfo->rate;
5005 } else if (ppduinfo->vht_flags) {
5006 rxs->encoding = RX_ENC_VHT;
5007 rxs->rate_idx = ppduinfo->rate;
5008 } else if (ppduinfo->ht_flags) {
5009 rxs->encoding = RX_ENC_HT;
5010 rxs->rate_idx = ppduinfo->rate;
5011 } else {
5012 rxs->encoding = RX_ENC_LEGACY;
5013 sband = &ar->mac.sbands[rxs->band];
5014 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5015 ppduinfo->cck_flag);
5016 }
5017
5018 rxs->mactime = ppduinfo->tsft;
5019 }
5020
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5021 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5022 struct sk_buff *head_msdu,
5023 struct hal_rx_mon_ppdu_info *ppduinfo,
5024 struct sk_buff *tail_msdu,
5025 struct napi_struct *napi)
5026 {
5027 struct ath11k_pdev_dp *dp = &ar->dp;
5028 struct sk_buff *mon_skb, *skb_next, *header;
5029 struct ieee80211_rx_status *rxs = &dp->rx_status;
5030 bool fcs_err = false;
5031
5032 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5033 tail_msdu, rxs, &fcs_err);
5034
5035 if (!mon_skb)
5036 goto mon_deliver_fail;
5037
5038 header = mon_skb;
5039
5040 rxs->flag = 0;
5041
5042 if (fcs_err)
5043 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5044
5045 do {
5046 skb_next = mon_skb->next;
5047 if (!skb_next)
5048 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5049 else
5050 rxs->flag |= RX_FLAG_AMSDU_MORE;
5051
5052 if (mon_skb == header) {
5053 header = NULL;
5054 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5055 } else {
5056 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5057 }
5058 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5059 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5060
5061 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5062 mon_skb = skb_next;
5063 } while (mon_skb);
5064 rxs->flag = 0;
5065
5066 return 0;
5067
5068 mon_deliver_fail:
5069 mon_skb = head_msdu;
5070 while (mon_skb) {
5071 skb_next = mon_skb->next;
5072 dev_kfree_skb_any(mon_skb);
5073 mon_skb = skb_next;
5074 }
5075 return -EINVAL;
5076 }
5077
5078 /* The destination ring processing is stuck if the destination is not
5079 * moving while status ring moves 16 PPDU. The destination ring processing
5080 * skips this destination ring PPDU as a workaround.
5081 */
5082 #define MON_DEST_RING_STUCK_MAX_CNT 16
5083
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5084 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5085 u32 quota, struct napi_struct *napi)
5086 {
5087 struct ath11k_pdev_dp *dp = &ar->dp;
5088 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5089 const struct ath11k_hw_hal_params *hal_params;
5090 void *ring_entry;
5091 void *mon_dst_srng;
5092 u32 ppdu_id;
5093 u32 rx_bufs_used;
5094 u32 ring_id;
5095 struct ath11k_pdev_mon_stats *rx_mon_stats;
5096 u32 npackets = 0;
5097 u32 mpdu_rx_bufs_used;
5098
5099 if (ar->ab->hw_params.rxdma1_enable)
5100 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5101 else
5102 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5103
5104 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5105
5106 if (!mon_dst_srng) {
5107 ath11k_warn(ar->ab,
5108 "HAL Monitor Destination Ring Init Failed -- %p",
5109 mon_dst_srng);
5110 return;
5111 }
5112
5113 spin_lock_bh(&pmon->mon_lock);
5114
5115 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5116
5117 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5118 rx_bufs_used = 0;
5119 rx_mon_stats = &pmon->rx_mon_stats;
5120
5121 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5122 struct sk_buff *head_msdu, *tail_msdu;
5123
5124 head_msdu = NULL;
5125 tail_msdu = NULL;
5126
5127 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5128 &head_msdu,
5129 &tail_msdu,
5130 &npackets, &ppdu_id);
5131
5132 rx_bufs_used += mpdu_rx_bufs_used;
5133
5134 if (mpdu_rx_bufs_used) {
5135 dp->mon_dest_ring_stuck_cnt = 0;
5136 } else {
5137 dp->mon_dest_ring_stuck_cnt++;
5138 rx_mon_stats->dest_mon_not_reaped++;
5139 }
5140
5141 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5142 rx_mon_stats->dest_mon_stuck++;
5143 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5144 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5145 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5146 dp->mon_dest_ring_stuck_cnt,
5147 rx_mon_stats->dest_mon_not_reaped,
5148 rx_mon_stats->dest_mon_stuck);
5149 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5150 continue;
5151 }
5152
5153 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5154 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5155 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5156 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5157 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5158 rx_mon_stats->dest_mon_not_reaped,
5159 rx_mon_stats->dest_mon_stuck);
5160 break;
5161 }
5162 if (head_msdu && tail_msdu) {
5163 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5164 &pmon->mon_ppdu_info,
5165 tail_msdu, napi);
5166 rx_mon_stats->dest_mpdu_done++;
5167 }
5168
5169 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5170 mon_dst_srng);
5171 }
5172 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5173
5174 spin_unlock_bh(&pmon->mon_lock);
5175
5176 if (rx_bufs_used) {
5177 rx_mon_stats->dest_ppdu_done++;
5178 hal_params = ar->ab->hw_params.hal_params;
5179
5180 if (ar->ab->hw_params.rxdma1_enable)
5181 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5182 &dp->rxdma_mon_buf_ring,
5183 rx_bufs_used,
5184 hal_params->rx_buf_rbm);
5185 else
5186 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5187 &dp->rx_refill_buf_ring,
5188 rx_bufs_used,
5189 hal_params->rx_buf_rbm);
5190 }
5191 }
5192
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5193 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5194 struct napi_struct *napi, int budget)
5195 {
5196 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5197 enum hal_rx_mon_status hal_status;
5198 struct sk_buff *skb;
5199 struct sk_buff_head skb_list;
5200 struct ath11k_peer *peer;
5201 struct ath11k_sta *arsta;
5202 int num_buffs_reaped = 0;
5203 u32 rx_buf_sz;
5204 u16 log_type;
5205 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5206 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5207 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5208
5209 __skb_queue_head_init(&skb_list);
5210
5211 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5212 &skb_list);
5213 if (!num_buffs_reaped)
5214 goto exit;
5215
5216 memset(ppdu_info, 0, sizeof(*ppdu_info));
5217 ppdu_info->peer_id = HAL_INVALID_PEERID;
5218
5219 while ((skb = __skb_dequeue(&skb_list))) {
5220 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5221 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5222 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5223 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5224 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5225 rx_buf_sz = DP_RX_BUFFER_SIZE;
5226 } else {
5227 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5228 rx_buf_sz = 0;
5229 }
5230
5231 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5232 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5233
5234 memset(ppdu_info, 0, sizeof(*ppdu_info));
5235 ppdu_info->peer_id = HAL_INVALID_PEERID;
5236 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5237
5238 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5239 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5240 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5241 rx_mon_stats->status_ppdu_done++;
5242 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5243 if (!ab->hw_params.full_monitor_mode) {
5244 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5245 budget, napi);
5246 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5247 }
5248 }
5249
5250 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5251 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5252 dev_kfree_skb_any(skb);
5253 continue;
5254 }
5255
5256 rcu_read_lock();
5257 spin_lock_bh(&ab->base_lock);
5258 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5259
5260 if (!peer || !peer->sta) {
5261 ath11k_dbg(ab, ATH11K_DBG_DATA,
5262 "failed to find the peer with peer_id %d\n",
5263 ppdu_info->peer_id);
5264 goto next_skb;
5265 }
5266
5267 arsta = (struct ath11k_sta *)peer->sta->drv_priv;
5268 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5269
5270 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5271 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5272
5273 next_skb:
5274 spin_unlock_bh(&ab->base_lock);
5275 rcu_read_unlock();
5276
5277 dev_kfree_skb_any(skb);
5278 memset(ppdu_info, 0, sizeof(*ppdu_info));
5279 ppdu_info->peer_id = HAL_INVALID_PEERID;
5280 }
5281 exit:
5282 return num_buffs_reaped;
5283 }
5284
5285 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5286 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5287 void *ring_entry, struct sk_buff **head_msdu,
5288 struct sk_buff **tail_msdu,
5289 struct hal_sw_mon_ring_entries *sw_mon_entries)
5290 {
5291 struct ath11k_pdev_dp *dp = &ar->dp;
5292 struct ath11k_mon_data *pmon = &dp->mon_data;
5293 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5294 struct sk_buff *msdu = NULL, *last = NULL;
5295 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5296 struct hal_rx_msdu_list msdu_list;
5297 struct hal_rx_desc *rx_desc;
5298 struct ath11k_skb_rxcb *rxcb;
5299 void *rx_msdu_link_desc;
5300 void *p_buf_addr_info, *p_last_buf_addr_info;
5301 int buf_id, i = 0;
5302 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5303 u32 rx_bufs_used = 0, msdu_cnt = 0;
5304 u32 total_len = 0, frag_len = 0, sw_cookie;
5305 u16 num_msdus = 0;
5306 u8 rxdma_err, rbm;
5307 bool is_frag, is_first_msdu;
5308 bool drop_mpdu = false;
5309
5310 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5311
5312 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5313 sw_mon_entries->end_of_ppdu = false;
5314 sw_mon_entries->drop_ppdu = false;
5315 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5316 msdu_cnt = sw_mon_entries->msdu_cnt;
5317
5318 sw_mon_entries->end_of_ppdu =
5319 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5320 if (sw_mon_entries->end_of_ppdu)
5321 return rx_bufs_used;
5322
5323 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5324 sw_desc->info0) ==
5325 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5326 rxdma_err =
5327 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5328 sw_desc->info0);
5329 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5330 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5331 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5332 pmon->rx_mon_stats.dest_mpdu_drop++;
5333 drop_mpdu = true;
5334 }
5335 }
5336
5337 is_frag = false;
5338 is_first_msdu = true;
5339
5340 do {
5341 rx_msdu_link_desc =
5342 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5343 (sw_mon_entries->mon_dst_paddr -
5344 pmon->link_desc_banks[sw_cookie].paddr);
5345
5346 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5347 &num_msdus);
5348
5349 for (i = 0; i < num_msdus; i++) {
5350 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5351 msdu_list.sw_cookie[i]);
5352
5353 spin_lock_bh(&rx_ring->idr_lock);
5354 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5355 if (!msdu) {
5356 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5357 "full mon msdu_pop: invalid buf_id %d\n",
5358 buf_id);
5359 spin_unlock_bh(&rx_ring->idr_lock);
5360 break;
5361 }
5362 idr_remove(&rx_ring->bufs_idr, buf_id);
5363 spin_unlock_bh(&rx_ring->idr_lock);
5364
5365 rxcb = ATH11K_SKB_RXCB(msdu);
5366 if (!rxcb->unmapped) {
5367 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5368 msdu->len +
5369 skb_tailroom(msdu),
5370 DMA_FROM_DEVICE);
5371 rxcb->unmapped = 1;
5372 }
5373 if (drop_mpdu) {
5374 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5375 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5376 i, msdu, sw_mon_entries->ppdu_id);
5377 dev_kfree_skb_any(msdu);
5378 msdu_cnt--;
5379 goto next_msdu;
5380 }
5381
5382 rx_desc = (struct hal_rx_desc *)msdu->data;
5383
5384 rx_pkt_offset = sizeof(struct hal_rx_desc);
5385 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5386
5387 if (is_first_msdu) {
5388 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5389 drop_mpdu = true;
5390 dev_kfree_skb_any(msdu);
5391 msdu = NULL;
5392 goto next_msdu;
5393 }
5394 is_first_msdu = false;
5395 }
5396
5397 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5398 &is_frag, &total_len,
5399 &frag_len, &msdu_cnt);
5400
5401 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5402
5403 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5404
5405 if (!(*head_msdu))
5406 *head_msdu = msdu;
5407 else if (last)
5408 last->next = msdu;
5409
5410 last = msdu;
5411 next_msdu:
5412 rx_bufs_used++;
5413 }
5414
5415 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5416 &sw_mon_entries->mon_dst_paddr,
5417 &sw_mon_entries->mon_dst_sw_cookie,
5418 &rbm,
5419 &p_buf_addr_info);
5420
5421 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5422 p_last_buf_addr_info,
5423 dp->mac_id))
5424 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5425 "full mon: dp_rx_monitor_link_desc_return failed\n");
5426
5427 p_last_buf_addr_info = p_buf_addr_info;
5428
5429 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5430
5431 if (last)
5432 last->next = NULL;
5433
5434 *tail_msdu = msdu;
5435
5436 return rx_bufs_used;
5437 }
5438
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5439 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5440 struct dp_full_mon_mpdu *mon_mpdu,
5441 struct sk_buff *head,
5442 struct sk_buff *tail)
5443 {
5444 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5445 if (!mon_mpdu)
5446 return -ENOMEM;
5447
5448 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5449 mon_mpdu->head = head;
5450 mon_mpdu->tail = tail;
5451
5452 return 0;
5453 }
5454
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5455 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5456 struct dp_full_mon_mpdu *mon_mpdu)
5457 {
5458 struct dp_full_mon_mpdu *tmp;
5459 struct sk_buff *tmp_msdu, *skb_next;
5460
5461 if (list_empty(&dp->dp_full_mon_mpdu_list))
5462 return;
5463
5464 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5465 list_del(&mon_mpdu->list);
5466
5467 tmp_msdu = mon_mpdu->head;
5468 while (tmp_msdu) {
5469 skb_next = tmp_msdu->next;
5470 dev_kfree_skb_any(tmp_msdu);
5471 tmp_msdu = skb_next;
5472 }
5473
5474 kfree(mon_mpdu);
5475 }
5476 }
5477
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5478 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5479 int mac_id,
5480 struct ath11k_mon_data *pmon,
5481 struct napi_struct *napi)
5482 {
5483 struct ath11k_pdev_mon_stats *rx_mon_stats;
5484 struct dp_full_mon_mpdu *tmp;
5485 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5486 struct sk_buff *head_msdu, *tail_msdu;
5487 struct ath11k_base *ab = ar->ab;
5488 struct ath11k_dp *dp = &ab->dp;
5489 int ret;
5490
5491 rx_mon_stats = &pmon->rx_mon_stats;
5492
5493 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5494 list_del(&mon_mpdu->list);
5495 head_msdu = mon_mpdu->head;
5496 tail_msdu = mon_mpdu->tail;
5497 if (head_msdu && tail_msdu) {
5498 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5499 &pmon->mon_ppdu_info,
5500 tail_msdu, napi);
5501 rx_mon_stats->dest_mpdu_done++;
5502 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5503 }
5504 kfree(mon_mpdu);
5505 }
5506
5507 return ret;
5508 }
5509
5510 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5511 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5512 struct napi_struct *napi, int budget)
5513 {
5514 struct ath11k *ar = ab->pdevs[mac_id].ar;
5515 struct ath11k_pdev_dp *dp = &ar->dp;
5516 struct ath11k_mon_data *pmon = &dp->mon_data;
5517 struct hal_sw_mon_ring_entries *sw_mon_entries;
5518 int quota = 0, work = 0, count;
5519
5520 sw_mon_entries = &pmon->sw_mon_entries;
5521
5522 while (pmon->hold_mon_dst_ring) {
5523 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5524 napi, 1);
5525 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5526 count = sw_mon_entries->status_buf_count;
5527 if (count > 1) {
5528 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5529 napi, count);
5530 }
5531
5532 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5533 pmon, napi);
5534 pmon->hold_mon_dst_ring = false;
5535 } else if (!pmon->mon_status_paddr ||
5536 pmon->buf_state == DP_MON_STATUS_LEAD) {
5537 sw_mon_entries->drop_ppdu = true;
5538 pmon->hold_mon_dst_ring = false;
5539 }
5540
5541 if (!quota)
5542 break;
5543
5544 work += quota;
5545 }
5546
5547 if (sw_mon_entries->drop_ppdu)
5548 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5549
5550 return work;
5551 }
5552
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5553 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5554 struct napi_struct *napi, int budget)
5555 {
5556 struct ath11k *ar = ab->pdevs[mac_id].ar;
5557 struct ath11k_pdev_dp *dp = &ar->dp;
5558 struct ath11k_mon_data *pmon = &dp->mon_data;
5559 struct hal_sw_mon_ring_entries *sw_mon_entries;
5560 struct ath11k_pdev_mon_stats *rx_mon_stats;
5561 struct sk_buff *head_msdu, *tail_msdu;
5562 void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5563 void *ring_entry;
5564 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5565 int quota = 0, ret;
5566 bool break_dst_ring = false;
5567
5568 spin_lock_bh(&pmon->mon_lock);
5569
5570 sw_mon_entries = &pmon->sw_mon_entries;
5571 rx_mon_stats = &pmon->rx_mon_stats;
5572
5573 if (pmon->hold_mon_dst_ring) {
5574 spin_unlock_bh(&pmon->mon_lock);
5575 goto reap_status_ring;
5576 }
5577
5578 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5579 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5580 head_msdu = NULL;
5581 tail_msdu = NULL;
5582
5583 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5584 &head_msdu,
5585 &tail_msdu,
5586 sw_mon_entries);
5587 rx_bufs_used += mpdu_rx_bufs_used;
5588
5589 if (!sw_mon_entries->end_of_ppdu) {
5590 if (head_msdu) {
5591 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5592 pmon->mon_mpdu,
5593 head_msdu,
5594 tail_msdu);
5595 if (ret)
5596 break_dst_ring = true;
5597 }
5598
5599 goto next_entry;
5600 } else {
5601 if (!sw_mon_entries->ppdu_id &&
5602 !sw_mon_entries->mon_status_paddr) {
5603 break_dst_ring = true;
5604 goto next_entry;
5605 }
5606 }
5607
5608 rx_mon_stats->dest_ppdu_done++;
5609 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5610 pmon->buf_state = DP_MON_STATUS_LAG;
5611 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5612 pmon->hold_mon_dst_ring = true;
5613 next_entry:
5614 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5615 mon_dst_srng);
5616 if (break_dst_ring)
5617 break;
5618 }
5619
5620 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5621 spin_unlock_bh(&pmon->mon_lock);
5622
5623 if (rx_bufs_used) {
5624 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5625 &dp->rxdma_mon_buf_ring,
5626 rx_bufs_used,
5627 HAL_RX_BUF_RBM_SW3_BM);
5628 }
5629
5630 reap_status_ring:
5631 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5632 napi, budget);
5633
5634 return quota;
5635 }
5636
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5637 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5638 struct napi_struct *napi, int budget)
5639 {
5640 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5641 int ret = 0;
5642
5643 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5644 ab->hw_params.full_monitor_mode)
5645 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5646 else
5647 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5648
5649 return ret;
5650 }
5651
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5652 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5653 {
5654 struct ath11k_pdev_dp *dp = &ar->dp;
5655 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5656
5657 skb_queue_head_init(&pmon->rx_status_q);
5658
5659 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5660
5661 memset(&pmon->rx_mon_stats, 0,
5662 sizeof(pmon->rx_mon_stats));
5663 return 0;
5664 }
5665
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5666 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5667 {
5668 struct ath11k_pdev_dp *dp = &ar->dp;
5669 struct ath11k_mon_data *pmon = &dp->mon_data;
5670 struct hal_srng *mon_desc_srng = NULL;
5671 struct dp_srng *dp_srng;
5672 int ret = 0;
5673 u32 n_link_desc = 0;
5674
5675 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5676 if (ret) {
5677 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5678 return ret;
5679 }
5680
5681 /* if rxdma1_enable is false, no need to setup
5682 * rxdma_mon_desc_ring.
5683 */
5684 if (!ar->ab->hw_params.rxdma1_enable)
5685 return 0;
5686
5687 dp_srng = &dp->rxdma_mon_desc_ring;
5688 n_link_desc = dp_srng->size /
5689 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5690 mon_desc_srng =
5691 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5692
5693 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5694 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5695 n_link_desc);
5696 if (ret) {
5697 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5698 return ret;
5699 }
5700 pmon->mon_last_linkdesc_paddr = 0;
5701 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5702 spin_lock_init(&pmon->mon_lock);
5703
5704 return 0;
5705 }
5706
ath11k_dp_mon_link_free(struct ath11k * ar)5707 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5708 {
5709 struct ath11k_pdev_dp *dp = &ar->dp;
5710 struct ath11k_mon_data *pmon = &dp->mon_data;
5711
5712 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5713 HAL_RXDMA_MONITOR_DESC,
5714 &dp->rxdma_mon_desc_ring);
5715 return 0;
5716 }
5717
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5718 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5719 {
5720 ath11k_dp_mon_link_free(ar);
5721 return 0;
5722 }
5723
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5724 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5725 {
5726 /* start reap timer */
5727 mod_timer(&ab->mon_reap_timer,
5728 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5729
5730 return 0;
5731 }
5732
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5733 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5734 {
5735 int ret;
5736
5737 if (stop_timer)
5738 del_timer_sync(&ab->mon_reap_timer);
5739
5740 /* reap all the monitor related rings */
5741 ret = ath11k_dp_purge_mon_ring(ab);
5742 if (ret) {
5743 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5744 return ret;
5745 }
5746
5747 return 0;
5748 }
5749