xref: /openbmc/linux/drivers/usb/phy/phy-mv-usb.h (revision 361ff6c1)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
4  */
5 
6 #ifndef	__MV_USB_OTG_CONTROLLER__
7 #define	__MV_USB_OTG_CONTROLLER__
8 
9 #include <linux/types.h>
10 
11 /* Command Register Bit Masks */
12 #define USBCMD_RUN_STOP			(0x00000001)
13 #define USBCMD_CTRL_RESET		(0x00000002)
14 
15 /* otgsc Register Bit Masks */
16 #define OTGSC_CTRL_VUSB_DISCHARGE		0x00000001
17 #define OTGSC_CTRL_VUSB_CHARGE			0x00000002
18 #define OTGSC_CTRL_OTG_TERM			0x00000008
19 #define OTGSC_CTRL_DATA_PULSING			0x00000010
20 #define OTGSC_STS_USB_ID			0x00000100
21 #define OTGSC_STS_A_VBUS_VALID			0x00000200
22 #define OTGSC_STS_A_SESSION_VALID		0x00000400
23 #define OTGSC_STS_B_SESSION_VALID		0x00000800
24 #define OTGSC_STS_B_SESSION_END			0x00001000
25 #define OTGSC_STS_1MS_TOGGLE			0x00002000
26 #define OTGSC_STS_DATA_PULSING			0x00004000
27 #define OTGSC_INTSTS_USB_ID			0x00010000
28 #define OTGSC_INTSTS_A_VBUS_VALID		0x00020000
29 #define OTGSC_INTSTS_A_SESSION_VALID		0x00040000
30 #define OTGSC_INTSTS_B_SESSION_VALID		0x00080000
31 #define OTGSC_INTSTS_B_SESSION_END		0x00100000
32 #define OTGSC_INTSTS_1MS			0x00200000
33 #define OTGSC_INTSTS_DATA_PULSING		0x00400000
34 #define OTGSC_INTR_USB_ID			0x01000000
35 #define OTGSC_INTR_A_VBUS_VALID			0x02000000
36 #define OTGSC_INTR_A_SESSION_VALID		0x04000000
37 #define OTGSC_INTR_B_SESSION_VALID		0x08000000
38 #define OTGSC_INTR_B_SESSION_END		0x10000000
39 #define OTGSC_INTR_1MS_TIMER			0x20000000
40 #define OTGSC_INTR_DATA_PULSING			0x40000000
41 
42 #define CAPLENGTH_MASK		(0xff)
43 
44 /* Timer's interval, unit 10ms */
45 #define T_A_WAIT_VRISE		100
46 #define T_A_WAIT_BCON		2000
47 #define T_A_AIDL_BDIS		100
48 #define T_A_BIDL_ADIS		20
49 #define T_B_ASE0_BRST		400
50 #define T_B_SE0_SRP		300
51 #define T_B_SRP_FAIL		2000
52 #define T_B_DATA_PLS		10
53 #define T_B_SRP_INIT		100
54 #define T_A_SRP_RSPNS		10
55 #define T_A_DRV_RSM		5
56 
57 enum otg_function {
58 	OTG_B_DEVICE = 0,
59 	OTG_A_DEVICE
60 };
61 
62 enum mv_otg_timer {
63 	A_WAIT_BCON_TIMER = 0,
64 	OTG_TIMER_NUM
65 };
66 
67 /* PXA OTG state machine */
68 struct mv_otg_ctrl {
69 	/* internal variables */
70 	u8 a_set_b_hnp_en;	/* A-Device set b_hnp_en */
71 	u8 b_srp_done;
72 	u8 b_hnp_en;
73 
74 	/* OTG inputs */
75 	u8 a_bus_drop;
76 	u8 a_bus_req;
77 	u8 a_clr_err;
78 	u8 a_bus_resume;
79 	u8 a_bus_suspend;
80 	u8 a_conn;
81 	u8 a_sess_vld;
82 	u8 a_srp_det;
83 	u8 a_vbus_vld;
84 	u8 b_bus_req;		/* B-Device Require Bus */
85 	u8 b_bus_resume;
86 	u8 b_bus_suspend;
87 	u8 b_conn;
88 	u8 b_se0_srp;
89 	u8 b_sess_end;
90 	u8 b_sess_vld;
91 	u8 id;
92 	u8 a_suspend_req;
93 
94 	/*Timer event */
95 	u8 a_aidl_bdis_timeout;
96 	u8 b_ase0_brst_timeout;
97 	u8 a_bidl_adis_timeout;
98 	u8 a_wait_bcon_timeout;
99 
100 	struct timer_list timer[OTG_TIMER_NUM];
101 };
102 
103 #define VUSBHS_MAX_PORTS	8
104 
105 struct mv_otg_regs {
106 	u32 usbcmd;		/* Command register */
107 	u32 usbsts;		/* Status register */
108 	u32 usbintr;		/* Interrupt enable */
109 	u32 frindex;		/* Frame index */
110 	u32 reserved1[1];
111 	u32 deviceaddr;		/* Device Address */
112 	u32 eplistaddr;		/* Endpoint List Address */
113 	u32 ttctrl;		/* HOST TT status and control */
114 	u32 burstsize;		/* Programmable Burst Size */
115 	u32 txfilltuning;	/* Host Transmit Pre-Buffer Packet Tuning */
116 	u32 reserved[4];
117 	u32 epnak;		/* Endpoint NAK */
118 	u32 epnaken;		/* Endpoint NAK Enable */
119 	u32 configflag;		/* Configured Flag register */
120 	u32 portsc[VUSBHS_MAX_PORTS];	/* Port Status/Control x, x = 1..8 */
121 	u32 otgsc;
122 	u32 usbmode;		/* USB Host/Device mode */
123 	u32 epsetupstat;	/* Endpoint Setup Status */
124 	u32 epprime;		/* Endpoint Initialize */
125 	u32 epflush;		/* Endpoint De-initialize */
126 	u32 epstatus;		/* Endpoint Status */
127 	u32 epcomplete;		/* Endpoint Interrupt On Complete */
128 	u32 epctrlx[16];	/* Endpoint Control, where x = 0.. 15 */
129 	u32 mcr;		/* Mux Control */
130 	u32 isr;		/* Interrupt Status */
131 	u32 ier;		/* Interrupt Enable */
132 };
133 
134 struct mv_otg {
135 	struct usb_phy phy;
136 	struct mv_otg_ctrl otg_ctrl;
137 
138 	/* base address */
139 	void __iomem *phy_regs;
140 	void __iomem *cap_regs;
141 	struct mv_otg_regs __iomem *op_regs;
142 
143 	struct platform_device *pdev;
144 	int irq;
145 	u32 irq_status;
146 	u32 irq_en;
147 
148 	struct delayed_work work;
149 	struct workqueue_struct *qwork;
150 
151 	spinlock_t wq_lock;
152 
153 	struct mv_usb_platform_data *pdata;
154 
155 	unsigned int active;
156 	unsigned int clock_gating;
157 	struct clk *clk;
158 };
159 
160 #endif
161