1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #ifndef _R819XU_PHYREG_H 8 #define _R819XU_PHYREG_H 9 10 #define RF_DATA 0x1d4 11 12 #define rPMAC_Reset 0x100 13 #define rPMAC_TxStart 0x104 14 #define rPMAC_TxLegacySIG 0x108 15 #define rPMAC_TxHTSIG1 0x10c 16 #define rPMAC_TxHTSIG2 0x110 17 #define rPMAC_PHYDebug 0x114 18 #define rPMAC_TxPacketNum 0x118 19 #define rPMAC_TxIdle 0x11c 20 #define rPMAC_TxMACHeader0 0x120 21 #define rPMAC_TxMACHeader1 0x124 22 #define rPMAC_TxMACHeader2 0x128 23 #define rPMAC_TxMACHeader3 0x12c 24 #define rPMAC_TxMACHeader4 0x130 25 #define rPMAC_TxMACHeader5 0x134 26 #define rPMAC_TxDataType 0x138 27 #define rPMAC_TxRandomSeed 0x13c 28 #define rPMAC_CCKPLCPPreamble 0x140 29 #define rPMAC_CCKPLCPHeader 0x144 30 #define rPMAC_CCKCRC16 0x148 31 #define rPMAC_OFDMRxCRC32OK 0x170 32 #define rPMAC_OFDMRxCRC32Er 0x174 33 #define rPMAC_OFDMRxParityEr 0x178 34 #define rPMAC_OFDMRxCRC8Er 0x17c 35 #define rPMAC_CCKCRxRC16Er 0x180 36 #define rPMAC_CCKCRxRC32Er 0x184 37 #define rPMAC_CCKCRxRC32OK 0x188 38 #define rPMAC_TxStatus 0x18c 39 40 #define MCS_TXAGC 0x340 41 #define CCK_TXAGC 0x348 42 43 /* Mac block on/off control register */ 44 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 45 #define rFPGA0_TxInfo 0x804 46 #define rFPGA0_PSDFunction 0x808 47 #define rFPGA0_TxGainStage 0x80c 48 #define rFPGA0_RFTiming1 0x810 49 #define rFPGA0_RFTiming2 0x814 50 #define rFPGA0_XA_HSSIParameter2 0x824 51 #define rFPGA0_XB_HSSIParameter2 0x82c 52 #define rFPGA0_XA_LSSIParameter 0x840 53 #define rFPGA0_XB_LSSIParameter 0x844 54 #define rFPGA0_RFWakeUpParameter 0x850 55 #define rFPGA0_RFSleepUpParameter 0x854 56 #define rFPGA0_XA_RFInterfaceOE 0x860 57 #define rFPGA0_XB_RFInterfaceOE 0x864 58 #define rFPGA0_XAB_RFInterfaceSW 0x870 59 #define rFPGA0_AnalogParameter1 0x880 60 #define rFPGA0_AnalogParameter2 0x884 61 #define rFPGA0_AnalogParameter3 0x888 62 #define rFPGA0_AnalogParameter4 0x88c 63 #define rFPGA0_XA_LSSIReadBack 0x8a0 64 #define rFPGA0_XB_LSSIReadBack 0x8a4 65 #define rFPGA0_PSDReport 0x8b4 66 67 /* Page 9 - RF mode & OFDM TxSC */ 68 #define rFPGA1_RFMOD 0x900 69 #define rFPGA1_TxBlock 0x904 70 #define rFPGA1_DebugSelect 0x908 71 #define rFPGA1_TxInfo 0x90c 72 73 #define rCCK0_System 0xa00 74 #define rCCK0_AFESetting 0xa04 75 #define rCCK0_CCA 0xa08 76 /* AGC default value, saturation level */ 77 #define rCCK0_RxAGC1 0xa0c 78 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 79 #define rCCK0_RxHP 0xa14 80 /* Timing recovery & channel estimation threshold */ 81 #define rCCK0_DSPParameter1 0xa18 82 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 83 #define rCCK0_TxFilter1 0xa20 84 #define rCCK0_TxFilter2 0xa24 85 #define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */ 86 #define rCCK0_FalseAlarmReport 0xa2c 87 #define rCCK0_TRSSIReport 0xa50 88 #define rCCK0_RxReport 0xa54 89 #define rCCK0_FACounterLower 0xa5c 90 #define rCCK0_FACounterUpper 0xa58 91 92 #define rOFDM0_LSTF 0xc00 93 #define rOFDM0_TRxPathEnable 0xc04 94 #define rOFDM0_TRMuxPar 0xc08 95 #define rOFDM0_TRSWIsolation 0xc0c 96 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ 97 #define rOFDM0_RxDetector2 0xc34 /* SBD */ 98 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync */ 99 /* PD, SBD, Frame Sync & Short-GI */ 100 #define rOFDM0_RxDetector4 0xc3c 101 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 102 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 103 #define rOFDM0_CCADropThreshold 0xc48 104 #define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */ 105 #define rOFDM0_XAAGCCore1 0xc50 106 #define rOFDM0_XBAGCCore1 0xc58 107 #define rOFDM0_XCAGCCore1 0xc60 108 #define rOFDM0_XDAGCCore1 0xc68 109 #define rOFDM0_AGCParameter1 0xc70 110 #define rOFDM0_AGCParameter2 0xc74 111 #define rOFDM0_AGCRSSITable 0xc78 112 #define rOFDM0_HTSTFAGC 0xc7c 113 #define rOFDM0_XATxIQImbalance 0xc80 114 #define rOFDM0_XATxAFE 0xc84 115 #define rOFDM0_XCTxIQImbalance 0xc90 116 #define rOFDM0_RxHPParameter 0xce0 117 #define rOFDM0_TxPseudoNoiseWgt 0xce4 118 #define rOFDM0_FrameSync 0xcf0 119 #define rOFDM0_DFSReport 0xcf4 120 #define rOFDM0_TxCoeff1 0xca4 121 #define rOFDM0_TxCoeff2 0xca8 122 #define rOFDM0_TxCoeff3 0xcac 123 #define rOFDM0_TxCoeff4 0xcb0 124 #define rOFDM0_TxCoeff5 0xcb4 125 #define rOFDM0_TxCoeff6 0xcb8 126 127 #define rOFDM1_LSTF 0xd00 128 #define rOFDM1_TRxPathEnable 0xd04 129 #define rOFDM1_CFO 0xd08 130 #define rOFDM1_CSI1 0xd10 131 #define rOFDM1_SBD 0xd14 132 #define rOFDM1_CSI2 0xd18 133 #define rOFDM1_CFOTracking 0xd2c 134 #define rOFDM1_TRxMesaure1 0xd34 135 #define rOFDM1_IntfDet 0xd3c 136 #define rOFDM1_PseudoNoiseStateAB 0xd50 137 #define rOFDM1_PseudoNoiseStateCD 0xd54 138 #define rOFDM1_RxPseudoNoiseWgt 0xd58 139 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 140 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 141 #define rOFDM_PHYCounter3 0xda8 /* MCS not supported */ 142 #define rOFDM_ShortCFOAB 0xdac 143 #define rOFDM_ShortCFOCD 0xdb0 144 #define rOFDM_LongCFOAB 0xdb4 145 #define rOFDM_LongCFOCD 0xdb8 146 #define rOFDM_TailCFOAB 0xdbc 147 #define rOFDM_TailCFOCD 0xdc0 148 #define rOFDM_PWMeasure1 0xdc4 149 #define rOFDM_PWMeasure2 0xdc8 150 #define rOFDM_BWReport 0xdcc 151 #define rOFDM_AGCReport 0xdd0 152 #define rOFDM_RxSNR 0xdd4 153 #define rOFDM_RxEVMCSI 0xdd8 154 #define rOFDM_SIGReport 0xddc 155 156 #define rTxAGC_Rate18_06 0xe00 157 #define rTxAGC_Rate54_24 0xe04 158 #define rTxAGC_CCK_Mcs32 0xe08 159 #define rTxAGC_Mcs03_Mcs00 0xe10 160 #define rTxAGC_Mcs07_Mcs04 0xe14 161 #define rTxAGC_Mcs11_Mcs08 0xe18 162 #define rTxAGC_Mcs15_Mcs12 0xe1c 163 164 #define rZebra1_HSSIEnable 0x0 165 #define rZebra1_TRxEnable1 0x1 166 #define rZebra1_TRxEnable2 0x2 167 #define rZebra1_AGC 0x4 168 #define rZebra1_ChargePump 0x5 169 #define rZebra1_Channel 0x7 170 #define rZebra1_TxGain 0x8 171 #define rZebra1_TxLPF 0x9 172 #define rZebra1_RxLPF 0xb 173 #define rZebra1_RxHPFCorner 0xc 174 175 /* Zebra 4 */ 176 #define rGlobalCtrl 0 177 #define rRTL8256_TxLPF 19 178 #define rRTL8256_RxLPF 11 179 180 /* RTL8258 */ 181 #define rRTL8258_TxLPF 0x11 182 #define rRTL8258_RxLPF 0x13 183 #define rRTL8258_RSSILPF 0xa 184 185 /* Bit Mask - Page 1*/ 186 #define bBBResetB 0x100 187 #define bGlobalResetB 0x200 188 #define bOFDMTxStart 0x4 189 #define bCCKTxStart 0x8 190 #define bCRC32Debug 0x100 191 #define bPMACLoopback 0x10 192 #define bTxLSIG 0xffffff 193 #define bOFDMTxRate 0xf 194 #define bOFDMTxReserved 0x10 195 #define bOFDMTxLength 0x1ffe0 196 #define bOFDMTxParity 0x20000 197 #define bTxHTSIG1 0xffffff 198 #define bTxHTMCSRate 0x7f 199 #define bTxHTBW 0x80 200 #define bTxHTLength 0xffff00 201 #define bTxHTSIG2 0xffffff 202 #define bTxHTSmoothing 0x1 203 #define bTxHTSounding 0x2 204 #define bTxHTReserved 0x4 205 #define bTxHTAggreation 0x8 206 #define bTxHTSTBC 0x30 207 #define bTxHTAdvanceCoding 0x40 208 #define bTxHTShortGI 0x80 209 #define bTxHTNumberHT_LTF 0x300 210 #define bTxHTCRC8 0x3fc00 211 #define bCounterReset 0x10000 212 #define bNumOfOFDMTx 0xffff 213 #define bNumOfCCKTx 0xffff0000 214 #define bTxIdleInterval 0xffff 215 #define bOFDMService 0xffff0000 216 #define bTxMACHeader 0xffffffff 217 #define bTxDataInit 0xff 218 #define bTxHTMode 0x100 219 #define bTxDataType 0x30000 220 #define bTxRandomSeed 0xffffffff 221 #define bCCKTxPreamble 0x1 222 #define bCCKTxSFD 0xffff0000 223 #define bCCKTxSIG 0xff 224 #define bCCKTxService 0xff00 225 #define bCCKLengthExt 0x8000 226 #define bCCKTxLength 0xffff0000 227 #define bCCKTxCRC16 0xffff 228 #define bCCKTxStatus 0x1 229 #define bOFDMTxStatus 0x2 230 /* Bit Mask - Page 8 */ 231 #define bRFMOD 0x1 232 #define bJapanMode 0x2 233 #define bCCKTxSC 0x30 234 #define bCCKEn 0x1000000 235 #define bOFDMEn 0x2000000 236 #define bOFDMRxADCPhase 0x10000 237 #define bOFDMTxDACPhase 0x40000 238 #define bXATxAGC 0x3f 239 #define bXBTxAGC 0xf00 240 #define bXCTxAGC 0xf000 241 #define bXDTxAGC 0xf0000 242 #define bPAStart 0xf0000000 243 #define bTRStart 0x00f00000 244 #define bRFStart 0x0000f000 245 #define bBBStart 0x000000f0 246 #define bBBCCKStart 0x0000000f 247 /* Bit Mask - rFPGA0_RFTiming2 */ 248 #define bPAEnd 0xf 249 #define bTREnd 0x0f000000 250 #define bRFEnd 0x000f0000 251 /* T2R */ 252 #define bCCAMask 0x000000f0 253 #define bR2RCCAMask 0x00000f00 254 #define bHSSI_R2TDelay 0xf8000000 255 #define bHSSI_T2RDelay 0xf80000 256 /* Channel gain at continue TX. */ 257 #define bContTxHSSI 0x400 258 #define bIGFromCCK 0x200 259 #define bAGCAddress 0x3f 260 #define bRxHPTx 0x7000 261 #define bRxHPT2R 0x38000 262 #define bRxHPCCKIni 0xc0000 263 #define bAGCTxCode 0xc00000 264 #define bAGCRxCode 0x300000 265 #define b3WireDataLength 0x800 266 #define b3WireAddressLength 0x400 267 #define b3WireRFPowerDown 0x1 268 /*#define bHWSISelect 0x8 */ 269 #define b2GPAPEPolarity 0x80000000 270 #define bRFSW_TxDefaultAnt 0x3 271 #define bRFSW_TxOptionAnt 0x30 272 #define bRFSW_RxDefaultAnt 0x300 273 #define bRFSW_RxOptionAnt 0x3000 274 #define bRFSI_3WireData 0x1 275 #define bRFSI_3WireClock 0x2 276 #define bRFSI_3WireLoad 0x4 277 #define bRFSI_3WireRW 0x8 278 /* 3-wire total control */ 279 #define bRFSI_3Wire 0xf 280 #define bRFSI_RFENV 0x10 281 #define bRFSI_TRSW 0x20 282 #define bRFSI_TRSWB 0x40 283 #define bRFSI_ANTSW 0x100 284 #define bRFSI_ANTSWB 0x200 285 #define bRFSI_PAPE 0x400 286 #define bBandSelect 0x1 287 #define bHTSIG2_GI 0x80 288 #define bHTSIG2_Smoothing 0x01 289 #define bHTSIG2_Sounding 0x02 290 #define bHTSIG2_Aggreaton 0x08 291 #define bHTSIG2_STBC 0x30 292 #define bHTSIG2_AdvCoding 0x40 293 #define bHTSIG2_NumOfHTLTF 0x300 294 #define bHTSIG2_CRC8 0x3fc 295 #define bHTSIG1_MCS 0x7f 296 #define bHTSIG1_BandWidth 0x80 297 #define bHTSIG1_HTLength 0xffff 298 #define bLSIG_Rate 0xf 299 #define bLSIG_Reserved 0x10 300 #define bLSIG_Length 0x1fffe 301 #define bLSIG_Parity 0x20 302 #define bCCKRxPhase 0x4 303 #define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */ 304 #define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */ 305 #define bLSSIReadBackData 0xfff 306 #define bLSSIReadOKFlag 0x1000 307 #define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */ 308 309 #define bRegulator0Standby 0x1 310 #define bRegulatorPLLStandby 0x2 311 #define bRegulator1Standby 0x4 312 #define bPLLPowerUp 0x8 313 #define bDPLLPowerUp 0x10 314 #define bDA10PowerUp 0x20 315 #define bAD7PowerUp 0x200 316 #define bDA6PowerUp 0x2000 317 #define bXtalPowerUp 0x4000 318 #define b40MDClkPowerUP 0x8000 319 #define bDA6DebugMode 0x20000 320 #define bDA6Swing 0x380000 321 #define bADClkPhase 0x4000000 322 #define b80MClkDelay 0x18000000 323 #define bAFEWatchDogEnable 0x20000000 324 #define bXtalCap 0x0f000000 325 #define bXtalCap01 0xc0000000 326 #define bXtalCap23 0x3 327 #define bXtalCap92x 0x0f000000 328 #define bIntDifClkEnable 0x400 329 #define bExtSigClkEnable 0x800 330 #define bBandgapMbiasPowerUp 0x10000 331 #define bAD11SHGain 0xc0000 332 #define bAD11InputRange 0x700000 333 #define bAD11OPCurrent 0x3800000 334 #define bIPathLoopback 0x4000000 335 #define bQPathLoopback 0x8000000 336 #define bAFELoopback 0x10000000 337 #define bDA10Swing 0x7e0 338 #define bDA10Reverse 0x800 339 #define bDAClkSource 0x1000 340 #define bAD7InputRange 0x6000 341 #define bAD7Gain 0x38000 342 #define bAD7OutputCMMode 0x40000 343 #define bAD7InputCMMode 0x380000 344 #define bAD7Current 0xc00000 345 #define bRegulatorAdjust 0x7000000 346 #define bAD11PowerUpAtTx 0x1 347 #define bDA10PSAtTx 0x10 348 #define bAD11PowerUpAtRx 0x100 349 #define bDA10PSAtRx 0x1000 350 351 #define bCCKRxAGCFormat 0x200 352 353 #define bPSDFFTSamplepPoint 0xc000 354 #define bPSDAverageNum 0x3000 355 #define bIQPathControl 0xc00 356 #define bPSDFreq 0x3ff 357 #define bPSDAntennaPath 0x30 358 #define bPSDIQSwitch 0x40 359 #define bPSDRxTrigger 0x400000 360 #define bPSDTxTrigger 0x80000000 361 #define bPSDSineToneScale 0x7f000000 362 #define bPSDReport 0xffff 363 364 /* Page 8 */ 365 #define bOFDMTxSC 0x30000000 366 #define bCCKTxOn 0x1 367 #define bOFDMTxOn 0x2 368 /* Reset debug page and also HWord, LWord */ 369 #define bDebugPage 0xfff 370 /* Reset debug page and LWord */ 371 #define bDebugItem 0xff 372 #define bAntL 0x10 373 #define bAntNonHT 0x100 374 #define bAntHT1 0x1000 375 #define bAntHT2 0x10000 376 #define bAntHT1S1 0x100000 377 #define bAntNonHTS1 0x1000000 378 379 /* Page a */ 380 #define bCCKBBMode 0x3 381 #define bCCKTxPowerSaving 0x80 382 #define bCCKRxPowerSaving 0x40 383 #define bCCKSideBand 0x10 384 #define bCCKScramble 0x8 385 #define bCCKAntDiversity 0x8000 386 #define bCCKCarrierRecovery 0x4000 387 #define bCCKTxRate 0x3000 388 #define bCCKDCCancel 0x0800 389 #define bCCKISICancel 0x0400 390 #define bCCKMatchFilter 0x0200 391 #define bCCKEqualizer 0x0100 392 #define bCCKPreambleDetect 0x800000 393 #define bCCKFastFalseCCA 0x400000 394 #define bCCKChEstStart 0x300000 395 #define bCCKCCACount 0x080000 396 #define bCCKcs_lim 0x070000 397 #define bCCKBistMode 0x80000000 398 #define bCCKCCAMask 0x40000000 399 #define bCCKTxDACPhase 0x4 400 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 401 #define bCCKr_cp_mode0 0x0100 402 #define bCCKTxDCOffset 0xf0 403 #define bCCKRxDCOffset 0xf 404 #define bCCKCCAMode 0xc000 405 #define bCCKFalseCS_lim 0x3f00 406 #define bCCKCS_ratio 0xc00000 407 #define bCCKCorgBit_sel 0x300000 408 #define bCCKPD_lim 0x0f0000 409 #define bCCKNewCCA 0x80000000 410 #define bCCKRxHPofIG 0x8000 411 #define bCCKRxIG 0x7f00 412 #define bCCKLNAPolarity 0x800000 413 #define bCCKRx1stGain 0x7f0000 414 /* CCK Rx Initial gain polarity */ 415 #define bCCKRFExtend 0x20000000 416 #define bCCKRxAGCSatLevel 0x1f000000 417 #define bCCKRxAGCSatCount 0xe0 418 /* AGCSAmp_dly */ 419 #define bCCKRxRFSettle 0x1f 420 #define bCCKFixedRxAGC 0x8000 421 /*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 422 #define bCCKAntennaPolarity 0x2000 423 #define bCCKTxFilterType 0x0c00 424 #define bCCKRxAGCReportType 0x0300 425 #define bCCKRxDAGCEn 0x80000000 426 #define bCCKRxDAGCPeriod 0x20000000 427 #define bCCKRxDAGCSatLevel 0x1f000000 428 #define bCCKTimingRecovery 0x800000 429 #define bCCKTxC0 0x3f0000 430 #define bCCKTxC1 0x3f000000 431 #define bCCKTxC2 0x3f 432 #define bCCKTxC3 0x3f00 433 #define bCCKTxC4 0x3f0000 434 #define bCCKTxC5 0x3f000000 435 #define bCCKTxC6 0x3f 436 #define bCCKTxC7 0x3f00 437 #define bCCKDebugPort 0xff0000 438 #define bCCKDACDebug 0x0f000000 439 #define bCCKFalseAlarmEnable 0x8000 440 #define bCCKFalseAlarmRead 0x4000 441 #define bCCKTRSSI 0x7f 442 #define bCCKRxAGCReport 0xfe 443 #define bCCKRxReport_AntSel 0x80000000 444 #define bCCKRxReport_MFOff 0x40000000 445 #define bCCKRxRxReport_SQLoss 0x20000000 446 #define bCCKRxReport_Pktloss 0x10000000 447 #define bCCKRxReport_Lockedbit 0x08000000 448 #define bCCKRxReport_RateError 0x04000000 449 #define bCCKRxReport_RxRate 0x03000000 450 #define bCCKRxFACounterLower 0xff 451 #define bCCKRxFACounterUpper 0xff000000 452 #define bCCKRxHPAGCStart 0xe000 453 #define bCCKRxHPAGCFinal 0x1c00 454 455 #define bCCKRxFalseAlarmEnable 0x8000 456 #define bCCKFACounterFreeze 0x4000 457 458 #define bCCKTxPathSel 0x10000000 459 #define bCCKDefaultRxPath 0xc000000 460 #define bCCKOptionRxPath 0x3000000 461 462 /* Page c */ 463 #define bNumOfSTF 0x3 464 #define bShift_L 0xc0 465 #define bGI_TH 0xc 466 #define bRxPathA 0x1 467 #define bRxPathB 0x2 468 #define bRxPathC 0x4 469 #define bRxPathD 0x8 470 #define bTxPathA 0x1 471 #define bTxPathB 0x2 472 #define bTxPathC 0x4 473 #define bTxPathD 0x8 474 #define bTRSSIFreq 0x200 475 #define bADCBackoff 0x3000 476 #define bDFIRBackoff 0xc000 477 #define bTRSSILatchPhase 0x10000 478 #define bRxIDCOffset 0xff 479 #define bRxQDCOffset 0xff00 480 #define bRxDFIRMode 0x1800000 481 #define bRxDCNFType 0xe000000 482 #define bRXIQImb_A 0x3ff 483 #define bRXIQImb_B 0xfc00 484 #define bRXIQImb_C 0x3f0000 485 #define bRXIQImb_D 0xffc00000 486 #define bDC_dc_Notch 0x60000 487 #define bRxNBINotch 0x1f000000 488 #define bPD_TH 0xf 489 #define bPD_TH_Opt2 0xc000 490 #define bPWED_TH 0x700 491 #define bIfMF_Win_L 0x800 492 #define bPD_Option 0x1000 493 #define bMF_Win_L 0xe000 494 #define bBW_Search_L 0x30000 495 #define bwin_enh_L 0xc0000 496 #define bBW_TH 0x700000 497 #define bED_TH2 0x3800000 498 #define bBW_option 0x4000000 499 #define bRatio_TH 0x18000000 500 #define bWindow_L 0xe0000000 501 #define bSBD_Option 0x1 502 #define bFrame_TH 0x1c 503 #define bFS_Option 0x60 504 #define bDC_Slope_check 0x80 505 #define bFGuard_Counter_DC_L 0xe00 506 #define bFrame_Weight_Short 0x7000 507 #define bSub_Tune 0xe00000 508 #define bFrame_DC_Length 0xe000000 509 #define bSBD_start_offset 0x30000000 510 #define bFrame_TH_2 0x7 511 #define bFrame_GI2_TH 0x38 512 #define bGI2_Sync_en 0x40 513 #define bSarch_Short_Early 0x300 514 #define bSarch_Short_Late 0xc00 515 #define bSarch_GI2_Late 0x70000 516 #define bCFOAntSum 0x1 517 #define bCFOAcc 0x2 518 #define bCFOStartOffset 0xc 519 #define bCFOLookBack 0x70 520 #define bCFOSumWeight 0x80 521 #define bDAGCEnable 0x10000 522 #define bTXIQImb_A 0x3ff 523 #define bTXIQImb_B 0xfc00 524 #define bTXIQImb_C 0x3f0000 525 #define bTXIQImb_D 0xffc00000 526 #define bTxIDCOffset 0xff 527 #define bTxQDCOffset 0xff00 528 #define bTxDFIRMode 0x10000 529 #define bTxPesudoNoiseOn 0x4000000 530 #define bTxPesudoNoise_A 0xff 531 #define bTxPesudoNoise_B 0xff00 532 #define bTxPesudoNoise_C 0xff0000 533 #define bTxPesudoNoise_D 0xff000000 534 #define bCCADropOption 0x20000 535 #define bCCADropThres 0xfff00000 536 #define bEDCCA_H 0xf 537 #define bEDCCA_L 0xf0 538 #define bLambda_ED 0x300 539 #define bRxInitialGain 0x7f 540 #define bRxAntDivEn 0x80 541 #define bRxAGCAddressForLNA 0x7f00 542 #define bRxHighPowerFlow 0x8000 543 #define bRxAGCFreezeThres 0xc0000 544 #define bRxFreezeStep_AGC1 0x300000 545 #define bRxFreezeStep_AGC2 0xc00000 546 #define bRxFreezeStep_AGC3 0x3000000 547 #define bRxFreezeStep_AGC0 0xc000000 548 #define bRxRssi_Cmp_En 0x10000000 549 #define bRxQuickAGCEn 0x20000000 550 #define bRxAGCFreezeThresMode 0x40000000 551 #define bRxOverFlowCheckType 0x80000000 552 #define bRxAGCShift 0x7f 553 #define bTRSW_Tri_Only 0x80 554 #define bPowerThres 0x300 555 #define bRxAGCEn 0x1 556 #define bRxAGCTogetherEn 0x2 557 #define bRxAGCMin 0x4 558 #define bRxHP_Ini 0x7 559 #define bRxHP_TRLNA 0x70 560 #define bRxHP_RSSI 0x700 561 #define bRxHP_BBP1 0x7000 562 #define bRxHP_BBP2 0x70000 563 #define bRxHP_BBP3 0x700000 564 /* The threshold for high power */ 565 #define bRSSI_H 0x7f0000 566 /* The threshold for ant diversity */ 567 #define bRSSI_Gen 0x7f000000 568 #define bRxSettle_TRSW 0x7 569 #define bRxSettle_LNA 0x38 570 #define bRxSettle_RSSI 0x1c0 571 #define bRxSettle_BBP 0xe00 572 #define bRxSettle_RxHP 0x7000 573 #define bRxSettle_AntSW_RSSI 0x38000 574 #define bRxSettle_AntSW 0xc0000 575 #define bRxProcessTime_DAGC 0x300000 576 #define bRxSettle_HSSI 0x400000 577 #define bRxProcessTime_BBPPW 0x800000 578 #define bRxAntennaPowerShift 0x3000000 579 #define bRSSITableSelect 0xc000000 580 #define bRxHP_Final 0x7000000 581 #define bRxHTSettle_BBP 0x7 582 #define bRxHTSettle_HSSI 0x8 583 #define bRxHTSettle_RxHP 0x70 584 #define bRxHTSettle_BBPPW 0x80 585 #define bRxHTSettle_Idle 0x300 586 #define bRxHTSettle_Reserved 0x1c00 587 #define bRxHTRxHPEn 0x8000 588 #define bRxHTAGCFreezeThres 0x30000 589 #define bRxHTAGCTogetherEn 0x40000 590 #define bRxHTAGCMin 0x80000 591 #define bRxHTAGCEn 0x100000 592 #define bRxHTDAGCEn 0x200000 593 #define bRxHTRxHP_BBP 0x1c00000 594 #define bRxHTRxHP_Final 0xe0000000 595 #define bRxPWRatioTH 0x3 596 #define bRxPWRatioEn 0x4 597 #define bRxMFHold 0x3800 598 #define bRxPD_Delay_TH1 0x38 599 #define bRxPD_Delay_TH2 0x1c0 600 #define bRxPD_DC_COUNT_MAX 0x600 601 /*#define bRxMF_Hold 0x3800*/ 602 #define bRxPD_Delay_TH 0x8000 603 #define bRxProcess_Delay 0xf0000 604 #define bRxSearchrange_GI2_Early 0x700000 605 #define bRxFrame_Guard_Counter_L 0x3800000 606 #define bRxSGI_Guard_L 0xc000000 607 #define bRxSGI_Search_L 0x30000000 608 #define bRxSGI_TH 0xc0000000 609 #define bDFSCnt0 0xff 610 #define bDFSCnt1 0xff00 611 #define bDFSFlag 0xf0000 612 613 #define bMFWeightSum 0x300000 614 #define bMinIdxTH 0x7f000000 615 616 #define bDAFormat 0x40000 617 618 #define bTxChEmuEnable 0x01000000 619 620 #define bTRSWIsolation_A 0x7f 621 #define bTRSWIsolation_B 0x7f00 622 #define bTRSWIsolation_C 0x7f0000 623 #define bTRSWIsolation_D 0x7f000000 624 625 #define bExtLNAGain 0x7c00 626 627 /* Page d */ 628 #define bSTBCEn 0x4 629 #define bAntennaMapping 0x10 630 #define bNss 0x20 631 #define bCFOAntSumD 0x200 632 #define bPHYCounterReset 0x8000000 633 #define bCFOReportGet 0x4000000 634 #define bOFDMContinueTx 0x10000000 635 #define bOFDMSingleCarrier 0x20000000 636 #define bOFDMSingleTone 0x40000000 637 /* #define bRxPath1 0x01 638 * #define bRxPath2 0x02 639 * #define bRxPath3 0x04 640 * #define bRxPath4 0x08 641 * #define bTxPath1 0x10 642 * #define bTxPath2 0x20 643 */ 644 #define bHTDetect 0x100 645 #define bCFOEn 0x10000 646 #define bCFOValue 0xfff00000 647 #define bSigTone_Re 0x3f 648 #define bSigTone_Im 0x7f00 649 #define bCounter_CCA 0xffff 650 #define bCounter_ParityFail 0xffff0000 651 #define bCounter_RateIllegal 0xffff 652 #define bCounter_CRC8Fail 0xffff0000 653 #define bCounter_MCSNoSupport 0xffff 654 #define bCounter_FastSync 0xffff 655 #define bShortCFO 0xfff 656 #define bShortCFOTLength 12 /* total */ 657 #define bShortCFOFLength 11 /* fraction */ 658 #define bLongCFO 0x7ff 659 #define bLongCFOTLength 11 660 #define bLongCFOFLength 11 661 #define bTailCFO 0x1fff 662 #define bTailCFOTLength 13 663 #define bTailCFOFLength 12 664 665 #define bmax_en_pwdB 0xffff 666 #define bCC_power_dB 0xffff0000 667 #define bnoise_pwdB 0xffff 668 #define bPowerMeasTLength 10 669 #define bPowerMeasFLength 3 670 #define bRx_HT_BW 0x1 671 #define bRxSC 0x6 672 #define bRx_HT 0x8 673 674 #define bNB_intf_det_on 0x1 675 #define bIntf_win_len_cfg 0x30 676 #define bNB_Intf_TH_cfg 0x1c0 677 678 #define bRFGain 0x3f 679 #define bTableSel 0x40 680 #define bTRSW 0x80 681 682 #define bRxSNR_A 0xff 683 #define bRxSNR_B 0xff00 684 #define bRxSNR_C 0xff0000 685 #define bRxSNR_D 0xff000000 686 #define bSNREVMTLength 8 687 #define bSNREVMFLength 1 688 689 #define bCSI1st 0xff 690 #define bCSI2nd 0xff00 691 #define bRxEVM1st 0xff0000 692 #define bRxEVM2nd 0xff000000 693 694 #define bSIGEVM 0xff 695 #define bPWDB 0xff00 696 #define bSGIEN 0x10000 697 698 #define bSFactorQAM1 0xf 699 #define bSFactorQAM2 0xf0 700 #define bSFactorQAM3 0xf00 701 #define bSFactorQAM4 0xf000 702 #define bSFactorQAM5 0xf0000 703 #define bSFactorQAM6 0xf0000 704 #define bSFactorQAM7 0xf00000 705 #define bSFactorQAM8 0xf000000 706 #define bSFactorQAM9 0xf0000000 707 #define bCSIScheme 0x100000 708 709 #define bNoiseLvlTopSet 0x3 710 #define bChSmooth 0x4 711 #define bChSmoothCfg1 0x38 712 #define bChSmoothCfg2 0x1c0 713 #define bChSmoothCfg3 0xe00 714 #define bChSmoothCfg4 0x7000 715 #define bMRCMode 0x800000 716 #define bTHEVMCfg 0x7000000 717 718 #define bLoopFitType 0x1 719 #define bUpdCFO 0x40 720 #define bUpdCFOOffData 0x80 721 #define bAdvUpdCFO 0x100 722 #define bAdvTimeCtrl 0x800 723 #define bUpdClko 0x1000 724 #define bFC 0x6000 725 #define bTrackingMode 0x8000 726 #define bPhCmpEnable 0x10000 727 #define bUpdClkoLTF 0x20000 728 #define bComChCFO 0x40000 729 #define bCSIEstiMode 0x80000 730 #define bAdvUpdEqz 0x100000 731 #define bUChCfg 0x7000000 732 #define bUpdEqz 0x8000000 733 734 /* Page e */ 735 #define bTxAGCRate18_06 0x7f7f7f7f 736 #define bTxAGCRate54_24 0x7f7f7f7f 737 #define bTxAGCRateMCS32 0x7f 738 #define bTxAGCRateCCK 0x7f00 739 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 740 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 741 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 742 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 743 744 #define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */ 745 #define bRxPesudoNoise_A 0xff 746 #define bRxPesudoNoise_B 0xff00 747 #define bRxPesudoNoise_C 0xff0000 748 #define bRxPesudoNoise_D 0xff000000 749 #define bPesudoNoiseState_A 0xffff 750 #define bPesudoNoiseState_B 0xffff0000 751 #define bPesudoNoiseState_C 0xffff 752 #define bPesudoNoiseState_D 0xffff0000 753 754 /* RF Zebra 1 */ 755 #define bZebra1_HSSIEnable 0x8 756 #define bZebra1_TRxControl 0xc00 757 #define bZebra1_TRxGainSetting 0x07f 758 #define bZebra1_RxCorner 0xc00 759 #define bZebra1_TxChargePump 0x38 760 #define bZebra1_RxChargePump 0x7 761 #define bZebra1_ChannelNum 0xf80 762 #define bZebra1_TxLPFBW 0x400 763 #define bZebra1_RxLPFBW 0x600 764 765 /* Zebra4 */ 766 #define bRTL8256RegModeCtrl1 0x100 767 #define bRTL8256RegModeCtrl0 0x40 768 #define bRTL8256_TxLPFBW 0x18 769 #define bRTL8256_RxLPFBW 0x600 770 771 /* RTL8258 */ 772 #define bRTL8258_TxLPFBW 0xc 773 #define bRTL8258_RxLPFBW 0xc00 774 #define bRTL8258_RSSILPFBW 0xc0 775 776 /* byte enable for sb_write */ 777 #define bByte0 0x1 778 #define bByte1 0x2 779 #define bByte2 0x4 780 #define bByte3 0x8 781 #define bWord0 0x3 782 #define bWord1 0xc 783 #define bDWord 0xf 784 785 /* for PutRegsetting & GetRegSetting BitMask */ 786 #define bMaskByte0 0xff 787 #define bMaskByte1 0xff00 788 #define bMaskByte2 0xff0000 789 #define bMaskByte3 0xff000000 790 #define bMaskHWord 0xffff0000 791 #define bMaskLWord 0x0000ffff 792 #define bMaskDWord 0xffffffff 793 794 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 795 #define bMask12Bits 0xfff 796 797 #define bEnable 0x1 798 #define bDisable 0x0 799 800 #define LeftAntenna 0x0 801 #define RightAntenna 0x1 802 803 #define tCheckTxStatus 500 /* 500 ms */ 804 #define tUpdateRxCounter 100 /* 100 ms */ 805 806 #define rateCCK 0 807 #define rateOFDM 1 808 #define rateHT 2 809 810 #define bPMAC_End 0x1ff /* define Register-End */ 811 #define bFPGAPHY0_End 0x8ff 812 #define bFPGAPHY1_End 0x9ff 813 #define bCCKPHY0_End 0xaff 814 #define bOFDMPHY0_End 0xcff 815 #define bOFDMPHY1_End 0xdff 816 817 #define bPMACControl 0x0 818 #define bWMACControl 0x1 819 #define bWNICControl 0x2 820 821 #define PathA 0x0 822 #define PathB 0x1 823 #define PathC 0x2 824 #define PathD 0x3 825 826 #define rRTL8256RxMixerPole 0xb 827 #define bZebraRxMixerPole 0x6 828 #define rRTL8256TxBBOPBias 0x9 829 #define bRTL8256TxBBOPBias 0x400 830 #define rRTL8256TxBBBW 19 831 #define bRTL8256TxBBBW 0x18 832 833 #endif 834