1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/export.h>
22 #include <linux/gpio.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_data/b53.h>
26 #include <linux/phy.h>
27 #include <linux/phylink.h>
28 #include <linux/etherdevice.h>
29 #include <linux/if_bridge.h>
30 #include <linux/if_vlan.h>
31 #include <net/dsa.h>
32
33 #include "b53_regs.h"
34 #include "b53_priv.h"
35
36 struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40 };
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 };
77
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124 };
125
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 };
166
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224 };
225
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
230
b53_do_vlan_op(struct b53_device * dev,u8 op)231 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
232 {
233 unsigned int i;
234
235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
236
237 for (i = 0; i < 10; i++) {
238 u8 vta;
239
240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
241 if (!(vta & VTA_START_CMD))
242 return 0;
243
244 usleep_range(100, 200);
245 }
246
247 return -EIO;
248 }
249
b53_set_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
251 struct b53_vlan *vlan)
252 {
253 if (is5325(dev)) {
254 u32 entry = 0;
255
256 if (vlan->members) {
257 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
258 VA_UNTAG_S_25) | vlan->members;
259 if (dev->core_rev >= 3)
260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
261 else
262 entry |= VA_VALID_25;
263 }
264
265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
267 VTA_RW_STATE_WR | VTA_RW_OP_EN);
268 } else if (is5365(dev)) {
269 u16 entry = 0;
270
271 if (vlan->members)
272 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
274
275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
277 VTA_RW_STATE_WR | VTA_RW_OP_EN);
278 } else {
279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
281 (vlan->untag << VTE_UNTAG_S) | vlan->members);
282
283 b53_do_vlan_op(dev, VTA_CMD_WRITE);
284 }
285
286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
287 vid, vlan->members, vlan->untag);
288 }
289
b53_get_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
291 struct b53_vlan *vlan)
292 {
293 if (is5325(dev)) {
294 u32 entry = 0;
295
296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
297 VTA_RW_STATE_RD | VTA_RW_OP_EN);
298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
299
300 if (dev->core_rev >= 3)
301 vlan->valid = !!(entry & VA_VALID_25_R4);
302 else
303 vlan->valid = !!(entry & VA_VALID_25);
304 vlan->members = entry & VA_MEMBER_MASK;
305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
306
307 } else if (is5365(dev)) {
308 u16 entry = 0;
309
310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
311 VTA_RW_STATE_WR | VTA_RW_OP_EN);
312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
313
314 vlan->valid = !!(entry & VA_VALID_65);
315 vlan->members = entry & VA_MEMBER_MASK;
316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
317 } else {
318 u32 entry = 0;
319
320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
321 b53_do_vlan_op(dev, VTA_CMD_READ);
322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
323 vlan->members = entry & VTE_MEMBERS;
324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
325 vlan->valid = true;
326 }
327 }
328
b53_set_forwarding(struct b53_device * dev,int enable)329 static void b53_set_forwarding(struct b53_device *dev, int enable)
330 {
331 u8 mgmt;
332
333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
334
335 if (enable)
336 mgmt |= SM_SW_FWD_EN;
337 else
338 mgmt &= ~SM_SW_FWD_EN;
339
340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
341
342 /* Include IMP port in dumb forwarding mode
343 */
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347
348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
349 * frames should be flooded or not.
350 */
351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
354 }
355
b53_enable_vlan(struct b53_device * dev,int port,bool enable,bool enable_filtering)356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
357 bool enable_filtering)
358 {
359 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
360
361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
364
365 if (is5325(dev) || is5365(dev)) {
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
368 } else if (is63xx(dev)) {
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
371 } else {
372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
374 }
375
376 vc1 &= ~VC1_RX_MCST_FWD_EN;
377
378 if (enable) {
379 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
380 vc1 |= VC1_RX_MCST_UNTAG_EN;
381 vc4 &= ~VC4_ING_VID_CHECK_MASK;
382 if (enable_filtering) {
383 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
384 vc5 |= VC5_DROP_VTABLE_MISS;
385 } else {
386 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S;
387 vc5 &= ~VC5_DROP_VTABLE_MISS;
388 }
389
390 if (is5325(dev))
391 vc0 &= ~VC0_RESERVED_1;
392
393 if (is5325(dev) || is5365(dev))
394 vc1 |= VC1_RX_MCST_TAG_EN;
395
396 } else {
397 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
398 vc1 &= ~VC1_RX_MCST_UNTAG_EN;
399 vc4 &= ~VC4_ING_VID_CHECK_MASK;
400 vc5 &= ~VC5_DROP_VTABLE_MISS;
401
402 if (is5325(dev) || is5365(dev))
403 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
404 else
405 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
406
407 if (is5325(dev) || is5365(dev))
408 vc1 &= ~VC1_RX_MCST_TAG_EN;
409 }
410
411 if (!is5325(dev) && !is5365(dev))
412 vc5 &= ~VC5_VID_FFF_EN;
413
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
416
417 if (is5325(dev) || is5365(dev)) {
418 /* enable the high 8 bit vid check on 5325 */
419 if (is5325(dev) && enable)
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
421 VC3_HIGH_8BIT_EN);
422 else
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
424
425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
427 } else if (is63xx(dev)) {
428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
431 } else {
432 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
433 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
434 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
435 }
436
437 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
438
439 dev->vlan_enabled = enable;
440
441 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
442 port, enable, enable_filtering);
443 }
444
b53_set_jumbo(struct b53_device * dev,bool enable,bool allow_10_100)445 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
446 {
447 u32 port_mask = 0;
448 u16 max_size = JMS_MIN_SIZE;
449
450 if (is5325(dev) || is5365(dev))
451 return -EINVAL;
452
453 if (enable) {
454 port_mask = dev->enabled_ports;
455 max_size = JMS_MAX_SIZE;
456 if (allow_10_100)
457 port_mask |= JPM_10_100_JUMBO_EN;
458 }
459
460 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
461 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
462 }
463
b53_flush_arl(struct b53_device * dev,u8 mask)464 static int b53_flush_arl(struct b53_device *dev, u8 mask)
465 {
466 unsigned int i;
467
468 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
469 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
470
471 for (i = 0; i < 10; i++) {
472 u8 fast_age_ctrl;
473
474 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
475 &fast_age_ctrl);
476
477 if (!(fast_age_ctrl & FAST_AGE_DONE))
478 goto out;
479
480 msleep(1);
481 }
482
483 return -ETIMEDOUT;
484 out:
485 /* Only age dynamic entries (default behavior) */
486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
487 return 0;
488 }
489
b53_fast_age_port(struct b53_device * dev,int port)490 static int b53_fast_age_port(struct b53_device *dev, int port)
491 {
492 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
493
494 return b53_flush_arl(dev, FAST_AGE_PORT);
495 }
496
b53_fast_age_vlan(struct b53_device * dev,u16 vid)497 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
498 {
499 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
500
501 return b53_flush_arl(dev, FAST_AGE_VLAN);
502 }
503
b53_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)504 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
505 {
506 struct b53_device *dev = ds->priv;
507 unsigned int i;
508 u16 pvlan;
509
510 /* Enable the IMP port to be in the same VLAN as the other ports
511 * on a per-port basis such that we only have Port i and IMP in
512 * the same VLAN.
513 */
514 b53_for_each_port(dev, i) {
515 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
516 pvlan |= BIT(cpu_port);
517 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
518 }
519 }
520 EXPORT_SYMBOL(b53_imp_vlan_setup);
521
b53_port_set_ucast_flood(struct b53_device * dev,int port,bool unicast)522 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
523 bool unicast)
524 {
525 u16 uc;
526
527 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
528 if (unicast)
529 uc |= BIT(port);
530 else
531 uc &= ~BIT(port);
532 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
533 }
534
b53_port_set_mcast_flood(struct b53_device * dev,int port,bool multicast)535 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
536 bool multicast)
537 {
538 u16 mc;
539
540 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
541 if (multicast)
542 mc |= BIT(port);
543 else
544 mc &= ~BIT(port);
545 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
546
547 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
548 if (multicast)
549 mc |= BIT(port);
550 else
551 mc &= ~BIT(port);
552 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
553 }
554
b53_port_set_learning(struct b53_device * dev,int port,bool learning)555 static void b53_port_set_learning(struct b53_device *dev, int port,
556 bool learning)
557 {
558 u16 reg;
559
560 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
561 if (learning)
562 reg &= ~BIT(port);
563 else
564 reg |= BIT(port);
565 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
566 }
567
b53_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)568 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
569 {
570 struct b53_device *dev = ds->priv;
571 unsigned int cpu_port;
572 int ret = 0;
573 u16 pvlan;
574
575 if (!dsa_is_user_port(ds, port))
576 return 0;
577
578 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
579
580 b53_port_set_ucast_flood(dev, port, true);
581 b53_port_set_mcast_flood(dev, port, true);
582 b53_port_set_learning(dev, port, false);
583
584 if (dev->ops->irq_enable)
585 ret = dev->ops->irq_enable(dev, port);
586 if (ret)
587 return ret;
588
589 /* Clear the Rx and Tx disable bits and set to no spanning tree */
590 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
591
592 /* Set this port, and only this one to be in the default VLAN,
593 * if member of a bridge, restore its membership prior to
594 * bringing down this port.
595 */
596 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
597 pvlan &= ~0x1ff;
598 pvlan |= BIT(port);
599 pvlan |= dev->ports[port].vlan_ctl_mask;
600 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
601
602 b53_imp_vlan_setup(ds, cpu_port);
603
604 /* If EEE was enabled, restore it */
605 if (dev->ports[port].eee.eee_enabled)
606 b53_eee_enable_set(ds, port, true);
607
608 return 0;
609 }
610 EXPORT_SYMBOL(b53_enable_port);
611
b53_disable_port(struct dsa_switch * ds,int port)612 void b53_disable_port(struct dsa_switch *ds, int port)
613 {
614 struct b53_device *dev = ds->priv;
615 u8 reg;
616
617 /* Disable Tx/Rx for the port */
618 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
619 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
620 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
621
622 if (dev->ops->irq_disable)
623 dev->ops->irq_disable(dev, port);
624 }
625 EXPORT_SYMBOL(b53_disable_port);
626
b53_brcm_hdr_setup(struct dsa_switch * ds,int port)627 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
628 {
629 struct b53_device *dev = ds->priv;
630 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
631 u8 hdr_ctl, val;
632 u16 reg;
633
634 /* Resolve which bit controls the Broadcom tag */
635 switch (port) {
636 case 8:
637 val = BRCM_HDR_P8_EN;
638 break;
639 case 7:
640 val = BRCM_HDR_P7_EN;
641 break;
642 case 5:
643 val = BRCM_HDR_P5_EN;
644 break;
645 default:
646 val = 0;
647 break;
648 }
649
650 /* Enable management mode if tagging is requested */
651 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
652 if (tag_en)
653 hdr_ctl |= SM_SW_FWD_MODE;
654 else
655 hdr_ctl &= ~SM_SW_FWD_MODE;
656 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
657
658 /* Configure the appropriate IMP port */
659 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
660 if (port == 8)
661 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
662 else if (port == 5)
663 hdr_ctl |= GC_FRM_MGMT_PORT_M;
664 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
665
666 /* Enable Broadcom tags for IMP port */
667 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
668 if (tag_en)
669 hdr_ctl |= val;
670 else
671 hdr_ctl &= ~val;
672 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
673
674 /* Registers below are only accessible on newer devices */
675 if (!is58xx(dev))
676 return;
677
678 /* Enable reception Broadcom tag for CPU TX (switch RX) to
679 * allow us to tag outgoing frames
680 */
681 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
682 if (tag_en)
683 reg &= ~BIT(port);
684 else
685 reg |= BIT(port);
686 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
687
688 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
689 * allow delivering frames to the per-port net_devices
690 */
691 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
692 if (tag_en)
693 reg &= ~BIT(port);
694 else
695 reg |= BIT(port);
696 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
697 }
698 EXPORT_SYMBOL(b53_brcm_hdr_setup);
699
b53_enable_cpu_port(struct b53_device * dev,int port)700 static void b53_enable_cpu_port(struct b53_device *dev, int port)
701 {
702 u8 port_ctrl;
703
704 /* BCM5325 CPU port is at 8 */
705 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
706 port = B53_CPU_PORT;
707
708 port_ctrl = PORT_CTRL_RX_BCST_EN |
709 PORT_CTRL_RX_MCST_EN |
710 PORT_CTRL_RX_UCST_EN;
711 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
712
713 b53_brcm_hdr_setup(dev->ds, port);
714
715 b53_port_set_ucast_flood(dev, port, true);
716 b53_port_set_mcast_flood(dev, port, true);
717 b53_port_set_learning(dev, port, false);
718 }
719
b53_enable_mib(struct b53_device * dev)720 static void b53_enable_mib(struct b53_device *dev)
721 {
722 u8 gc;
723
724 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
725 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
726 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
727 }
728
b53_enable_stp(struct b53_device * dev)729 static void b53_enable_stp(struct b53_device *dev)
730 {
731 u8 gc;
732
733 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
734 gc |= GC_RX_BPDU_EN;
735 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
736 }
737
b53_default_pvid(struct b53_device * dev)738 static u16 b53_default_pvid(struct b53_device *dev)
739 {
740 if (is5325(dev) || is5365(dev))
741 return 1;
742 else
743 return 0;
744 }
745
b53_vlan_port_needs_forced_tagged(struct dsa_switch * ds,int port)746 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
747 {
748 struct b53_device *dev = ds->priv;
749
750 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
751 }
752
b53_configure_vlan(struct dsa_switch * ds)753 int b53_configure_vlan(struct dsa_switch *ds)
754 {
755 struct b53_device *dev = ds->priv;
756 struct b53_vlan vl = { 0 };
757 struct b53_vlan *v;
758 int i, def_vid;
759 u16 vid;
760
761 def_vid = b53_default_pvid(dev);
762
763 /* clear all vlan entries */
764 if (is5325(dev) || is5365(dev)) {
765 for (i = def_vid; i < dev->num_vlans; i++)
766 b53_set_vlan_entry(dev, i, &vl);
767 } else {
768 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
769 }
770
771 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
772
773 /* Create an untagged VLAN entry for the default PVID in case
774 * CONFIG_VLAN_8021Q is disabled and there are no calls to
775 * dsa_slave_vlan_rx_add_vid() to create the default VLAN
776 * entry. Do this only when the tagging protocol is not
777 * DSA_TAG_PROTO_NONE
778 */
779 b53_for_each_port(dev, i) {
780 v = &dev->vlans[def_vid];
781 v->members |= BIT(i);
782 if (!b53_vlan_port_needs_forced_tagged(ds, i))
783 v->untag = v->members;
784 b53_write16(dev, B53_VLAN_PAGE,
785 B53_VLAN_PORT_DEF_TAG(i), def_vid);
786 }
787
788 /* Upon initial call we have not set-up any VLANs, but upon
789 * system resume, we need to restore all VLAN entries.
790 */
791 for (vid = def_vid; vid < dev->num_vlans; vid++) {
792 v = &dev->vlans[vid];
793
794 if (!v->members)
795 continue;
796
797 b53_set_vlan_entry(dev, vid, v);
798 b53_fast_age_vlan(dev, vid);
799 }
800
801 return 0;
802 }
803 EXPORT_SYMBOL(b53_configure_vlan);
804
b53_switch_reset_gpio(struct b53_device * dev)805 static void b53_switch_reset_gpio(struct b53_device *dev)
806 {
807 int gpio = dev->reset_gpio;
808
809 if (gpio < 0)
810 return;
811
812 /* Reset sequence: RESET low(50ms)->high(20ms)
813 */
814 gpio_set_value(gpio, 0);
815 mdelay(50);
816
817 gpio_set_value(gpio, 1);
818 mdelay(20);
819
820 dev->current_page = 0xff;
821 }
822
b53_switch_reset(struct b53_device * dev)823 static int b53_switch_reset(struct b53_device *dev)
824 {
825 unsigned int timeout = 1000;
826 u8 mgmt, reg;
827
828 b53_switch_reset_gpio(dev);
829
830 if (is539x(dev)) {
831 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
832 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
833 }
834
835 /* This is specific to 58xx devices here, do not use is58xx() which
836 * covers the larger Starfigther 2 family, including 7445/7278 which
837 * still use this driver as a library and need to perform the reset
838 * earlier.
839 */
840 if (dev->chip_id == BCM58XX_DEVICE_ID ||
841 dev->chip_id == BCM583XX_DEVICE_ID) {
842 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
843 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
844 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
845
846 do {
847 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
848 if (!(reg & SW_RST))
849 break;
850
851 usleep_range(1000, 2000);
852 } while (timeout-- > 0);
853
854 if (timeout == 0) {
855 dev_err(dev->dev,
856 "Timeout waiting for SW_RST to clear!\n");
857 return -ETIMEDOUT;
858 }
859 }
860
861 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
862
863 if (!(mgmt & SM_SW_FWD_EN)) {
864 mgmt &= ~SM_SW_FWD_MODE;
865 mgmt |= SM_SW_FWD_EN;
866
867 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
868 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
869
870 if (!(mgmt & SM_SW_FWD_EN)) {
871 dev_err(dev->dev, "Failed to enable switch!\n");
872 return -EINVAL;
873 }
874 }
875
876 b53_enable_mib(dev);
877 b53_enable_stp(dev);
878
879 return b53_flush_arl(dev, FAST_AGE_STATIC);
880 }
881
b53_phy_read16(struct dsa_switch * ds,int addr,int reg)882 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
883 {
884 struct b53_device *priv = ds->priv;
885 u16 value = 0;
886 int ret;
887
888 if (priv->ops->phy_read16)
889 ret = priv->ops->phy_read16(priv, addr, reg, &value);
890 else
891 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
892 reg * 2, &value);
893
894 return ret ? ret : value;
895 }
896
b53_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)897 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
898 {
899 struct b53_device *priv = ds->priv;
900
901 if (priv->ops->phy_write16)
902 return priv->ops->phy_write16(priv, addr, reg, val);
903
904 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
905 }
906
b53_reset_switch(struct b53_device * priv)907 static int b53_reset_switch(struct b53_device *priv)
908 {
909 /* reset vlans */
910 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
911 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
912
913 priv->serdes_lane = B53_INVALID_LANE;
914
915 return b53_switch_reset(priv);
916 }
917
b53_apply_config(struct b53_device * priv)918 static int b53_apply_config(struct b53_device *priv)
919 {
920 /* disable switching */
921 b53_set_forwarding(priv, 0);
922
923 b53_configure_vlan(priv->ds);
924
925 /* enable switching */
926 b53_set_forwarding(priv, 1);
927
928 return 0;
929 }
930
b53_reset_mib(struct b53_device * priv)931 static void b53_reset_mib(struct b53_device *priv)
932 {
933 u8 gc;
934
935 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
936
937 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
938 msleep(1);
939 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
940 msleep(1);
941 }
942
b53_get_mib(struct b53_device * dev)943 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
944 {
945 if (is5365(dev))
946 return b53_mibs_65;
947 else if (is63xx(dev))
948 return b53_mibs_63xx;
949 else if (is58xx(dev))
950 return b53_mibs_58xx;
951 else
952 return b53_mibs;
953 }
954
b53_get_mib_size(struct b53_device * dev)955 static unsigned int b53_get_mib_size(struct b53_device *dev)
956 {
957 if (is5365(dev))
958 return B53_MIBS_65_SIZE;
959 else if (is63xx(dev))
960 return B53_MIBS_63XX_SIZE;
961 else if (is58xx(dev))
962 return B53_MIBS_58XX_SIZE;
963 else
964 return B53_MIBS_SIZE;
965 }
966
b53_get_phy_device(struct dsa_switch * ds,int port)967 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
968 {
969 /* These ports typically do not have built-in PHYs */
970 switch (port) {
971 case B53_CPU_PORT_25:
972 case 7:
973 case B53_CPU_PORT:
974 return NULL;
975 }
976
977 return mdiobus_get_phy(ds->slave_mii_bus, port);
978 }
979
b53_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)980 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
981 uint8_t *data)
982 {
983 struct b53_device *dev = ds->priv;
984 const struct b53_mib_desc *mibs = b53_get_mib(dev);
985 unsigned int mib_size = b53_get_mib_size(dev);
986 struct phy_device *phydev;
987 unsigned int i;
988
989 if (stringset == ETH_SS_STATS) {
990 for (i = 0; i < mib_size; i++)
991 strscpy(data + i * ETH_GSTRING_LEN,
992 mibs[i].name, ETH_GSTRING_LEN);
993 } else if (stringset == ETH_SS_PHY_STATS) {
994 phydev = b53_get_phy_device(ds, port);
995 if (!phydev)
996 return;
997
998 phy_ethtool_get_strings(phydev, data);
999 }
1000 }
1001 EXPORT_SYMBOL(b53_get_strings);
1002
b53_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1003 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
1004 {
1005 struct b53_device *dev = ds->priv;
1006 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1007 unsigned int mib_size = b53_get_mib_size(dev);
1008 const struct b53_mib_desc *s;
1009 unsigned int i;
1010 u64 val = 0;
1011
1012 if (is5365(dev) && port == 5)
1013 port = 8;
1014
1015 mutex_lock(&dev->stats_mutex);
1016
1017 for (i = 0; i < mib_size; i++) {
1018 s = &mibs[i];
1019
1020 if (s->size == 8) {
1021 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1022 } else {
1023 u32 val32;
1024
1025 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1026 &val32);
1027 val = val32;
1028 }
1029 data[i] = (u64)val;
1030 }
1031
1032 mutex_unlock(&dev->stats_mutex);
1033 }
1034 EXPORT_SYMBOL(b53_get_ethtool_stats);
1035
b53_get_ethtool_phy_stats(struct dsa_switch * ds,int port,uint64_t * data)1036 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1037 {
1038 struct phy_device *phydev;
1039
1040 phydev = b53_get_phy_device(ds, port);
1041 if (!phydev)
1042 return;
1043
1044 phy_ethtool_get_stats(phydev, NULL, data);
1045 }
1046 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1047
b53_get_sset_count(struct dsa_switch * ds,int port,int sset)1048 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1049 {
1050 struct b53_device *dev = ds->priv;
1051 struct phy_device *phydev;
1052
1053 if (sset == ETH_SS_STATS) {
1054 return b53_get_mib_size(dev);
1055 } else if (sset == ETH_SS_PHY_STATS) {
1056 phydev = b53_get_phy_device(ds, port);
1057 if (!phydev)
1058 return 0;
1059
1060 return phy_ethtool_get_sset_count(phydev);
1061 }
1062
1063 return 0;
1064 }
1065 EXPORT_SYMBOL(b53_get_sset_count);
1066
1067 enum b53_devlink_resource_id {
1068 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1069 };
1070
b53_devlink_vlan_table_get(void * priv)1071 static u64 b53_devlink_vlan_table_get(void *priv)
1072 {
1073 struct b53_device *dev = priv;
1074 struct b53_vlan *vl;
1075 unsigned int i;
1076 u64 count = 0;
1077
1078 for (i = 0; i < dev->num_vlans; i++) {
1079 vl = &dev->vlans[i];
1080 if (vl->members)
1081 count++;
1082 }
1083
1084 return count;
1085 }
1086
b53_setup_devlink_resources(struct dsa_switch * ds)1087 int b53_setup_devlink_resources(struct dsa_switch *ds)
1088 {
1089 struct devlink_resource_size_params size_params;
1090 struct b53_device *dev = ds->priv;
1091 int err;
1092
1093 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1094 dev->num_vlans,
1095 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1096
1097 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1098 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1099 DEVLINK_RESOURCE_ID_PARENT_TOP,
1100 &size_params);
1101 if (err)
1102 goto out;
1103
1104 dsa_devlink_resource_occ_get_register(ds,
1105 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1106 b53_devlink_vlan_table_get, dev);
1107
1108 return 0;
1109 out:
1110 dsa_devlink_resources_unregister(ds);
1111 return err;
1112 }
1113 EXPORT_SYMBOL(b53_setup_devlink_resources);
1114
b53_setup(struct dsa_switch * ds)1115 static int b53_setup(struct dsa_switch *ds)
1116 {
1117 struct b53_device *dev = ds->priv;
1118 unsigned int port;
1119 int ret;
1120
1121 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1122 * which forces the CPU port to be tagged in all VLANs.
1123 */
1124 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1125
1126 ret = b53_reset_switch(dev);
1127 if (ret) {
1128 dev_err(ds->dev, "failed to reset switch\n");
1129 return ret;
1130 }
1131
1132 b53_reset_mib(dev);
1133
1134 ret = b53_apply_config(dev);
1135 if (ret) {
1136 dev_err(ds->dev, "failed to apply configuration\n");
1137 return ret;
1138 }
1139
1140 /* Configure IMP/CPU port, disable all other ports. Enabled
1141 * ports will be configured with .port_enable
1142 */
1143 for (port = 0; port < dev->num_ports; port++) {
1144 if (dsa_is_cpu_port(ds, port))
1145 b53_enable_cpu_port(dev, port);
1146 else
1147 b53_disable_port(ds, port);
1148 }
1149
1150 return b53_setup_devlink_resources(ds);
1151 }
1152
b53_teardown(struct dsa_switch * ds)1153 static void b53_teardown(struct dsa_switch *ds)
1154 {
1155 dsa_devlink_resources_unregister(ds);
1156 }
1157
b53_force_link(struct b53_device * dev,int port,int link)1158 static void b53_force_link(struct b53_device *dev, int port, int link)
1159 {
1160 u8 reg, val, off;
1161
1162 /* Override the port settings */
1163 if (port == dev->imp_port) {
1164 off = B53_PORT_OVERRIDE_CTRL;
1165 val = PORT_OVERRIDE_EN;
1166 } else {
1167 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1168 val = GMII_PO_EN;
1169 }
1170
1171 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1172 reg |= val;
1173 if (link)
1174 reg |= PORT_OVERRIDE_LINK;
1175 else
1176 reg &= ~PORT_OVERRIDE_LINK;
1177 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1178 }
1179
b53_force_port_config(struct b53_device * dev,int port,int speed,int duplex,bool tx_pause,bool rx_pause)1180 static void b53_force_port_config(struct b53_device *dev, int port,
1181 int speed, int duplex,
1182 bool tx_pause, bool rx_pause)
1183 {
1184 u8 reg, val, off;
1185
1186 /* Override the port settings */
1187 if (port == dev->imp_port) {
1188 off = B53_PORT_OVERRIDE_CTRL;
1189 val = PORT_OVERRIDE_EN;
1190 } else {
1191 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1192 val = GMII_PO_EN;
1193 }
1194
1195 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1196 reg |= val;
1197 if (duplex == DUPLEX_FULL)
1198 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1199 else
1200 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1201
1202 switch (speed) {
1203 case 2000:
1204 reg |= PORT_OVERRIDE_SPEED_2000M;
1205 fallthrough;
1206 case SPEED_1000:
1207 reg |= PORT_OVERRIDE_SPEED_1000M;
1208 break;
1209 case SPEED_100:
1210 reg |= PORT_OVERRIDE_SPEED_100M;
1211 break;
1212 case SPEED_10:
1213 reg |= PORT_OVERRIDE_SPEED_10M;
1214 break;
1215 default:
1216 dev_err(dev->dev, "unknown speed: %d\n", speed);
1217 return;
1218 }
1219
1220 if (rx_pause)
1221 reg |= PORT_OVERRIDE_RX_FLOW;
1222 if (tx_pause)
1223 reg |= PORT_OVERRIDE_TX_FLOW;
1224
1225 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1226 }
1227
b53_adjust_63xx_rgmii(struct dsa_switch * ds,int port,phy_interface_t interface)1228 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1229 phy_interface_t interface)
1230 {
1231 struct b53_device *dev = ds->priv;
1232 u8 rgmii_ctrl = 0, off;
1233
1234 if (port == dev->imp_port)
1235 off = B53_RGMII_CTRL_IMP;
1236 else
1237 off = B53_RGMII_CTRL_P(port);
1238
1239 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1240 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1241
1242 if (port != dev->imp_port) {
1243 if (is63268(dev))
1244 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1245
1246 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1247 }
1248
1249 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1250
1251 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1252 phy_modes(interface));
1253 }
1254
b53_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)1255 static void b53_adjust_link(struct dsa_switch *ds, int port,
1256 struct phy_device *phydev)
1257 {
1258 struct b53_device *dev = ds->priv;
1259 struct ethtool_eee *p = &dev->ports[port].eee;
1260 u8 rgmii_ctrl = 0, reg = 0, off;
1261 bool tx_pause = false;
1262 bool rx_pause = false;
1263
1264 if (!phy_is_pseudo_fixed_link(phydev))
1265 return;
1266
1267 /* Enable flow control on BCM5301x's CPU port */
1268 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1269 tx_pause = rx_pause = true;
1270
1271 if (phydev->pause) {
1272 if (phydev->asym_pause)
1273 tx_pause = true;
1274 rx_pause = true;
1275 }
1276
1277 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1278 tx_pause, rx_pause);
1279 b53_force_link(dev, port, phydev->link);
1280
1281 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1282 b53_adjust_63xx_rgmii(ds, port, phydev->interface);
1283
1284 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1285 if (port == dev->imp_port)
1286 off = B53_RGMII_CTRL_IMP;
1287 else
1288 off = B53_RGMII_CTRL_P(port);
1289
1290 /* Configure the port RGMII clock delay by DLL disabled and
1291 * tx_clk aligned timing (restoring to reset defaults)
1292 */
1293 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1294 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1295 RGMII_CTRL_TIMING_SEL);
1296
1297 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1298 * sure that we enable the port TX clock internal delay to
1299 * account for this internal delay that is inserted, otherwise
1300 * the switch won't be able to receive correctly.
1301 *
1302 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1303 * any delay neither on transmission nor reception, so the
1304 * BCM53125 must also be configured accordingly to account for
1305 * the lack of delay and introduce
1306 *
1307 * The BCM53125 switch has its RX clock and TX clock control
1308 * swapped, hence the reason why we modify the TX clock path in
1309 * the "RGMII" case
1310 */
1311 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1312 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1313 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1314 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1315 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1316 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1317
1318 dev_info(ds->dev, "Configured port %d for %s\n", port,
1319 phy_modes(phydev->interface));
1320 }
1321
1322 /* configure MII port if necessary */
1323 if (is5325(dev)) {
1324 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1325 ®);
1326
1327 /* reverse mii needs to be enabled */
1328 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1329 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1330 reg | PORT_OVERRIDE_RV_MII_25);
1331 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1332 ®);
1333
1334 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1335 dev_err(ds->dev,
1336 "Failed to enable reverse MII mode\n");
1337 return;
1338 }
1339 }
1340 }
1341
1342 /* Re-negotiate EEE if it was enabled already */
1343 p->eee_enabled = b53_eee_init(ds, port, phydev);
1344 }
1345
b53_port_event(struct dsa_switch * ds,int port)1346 void b53_port_event(struct dsa_switch *ds, int port)
1347 {
1348 struct b53_device *dev = ds->priv;
1349 bool link;
1350 u16 sts;
1351
1352 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1353 link = !!(sts & BIT(port));
1354 dsa_port_phylink_mac_change(ds, port, link);
1355 }
1356 EXPORT_SYMBOL(b53_port_event);
1357
b53_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1358 static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1359 struct phylink_config *config)
1360 {
1361 struct b53_device *dev = ds->priv;
1362
1363 /* Internal ports need GMII for PHYLIB */
1364 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1365
1366 /* These switches appear to support MII and RevMII too, but beyond
1367 * this, the code gives very few clues. FIXME: We probably need more
1368 * interface modes here.
1369 *
1370 * According to b53_srab_mux_init(), ports 3..5 can support:
1371 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1372 * However, the interface mode read from the MUX configuration is
1373 * not passed back to DSA, so phylink uses NA.
1374 * DT can specify RGMII for ports 0, 1.
1375 * For MDIO, port 8 can be RGMII_TXID.
1376 */
1377 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1378 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1379
1380 /* BCM63xx RGMII ports support RGMII */
1381 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
1382 phy_interface_set_rgmii(config->supported_interfaces);
1383
1384 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1385 MAC_10 | MAC_100;
1386
1387 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1388 * Note: the original code also exclulded Gigagbit for MII, RevMII
1389 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1390 * so will be excluded by the generic validator implementation.
1391 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1392 */
1393 if (!(is5325(dev) || is5365(dev)))
1394 config->mac_capabilities |= MAC_1000;
1395
1396 /* Get the implementation specific capabilities */
1397 if (dev->ops->phylink_get_caps)
1398 dev->ops->phylink_get_caps(dev, port, config);
1399 }
1400
b53_phylink_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)1401 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1402 int port,
1403 phy_interface_t interface)
1404 {
1405 struct b53_device *dev = ds->priv;
1406
1407 if (!dev->ops->phylink_mac_select_pcs)
1408 return NULL;
1409
1410 return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1411 }
1412
b53_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)1413 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1414 unsigned int mode,
1415 const struct phylink_link_state *state)
1416 {
1417 }
1418 EXPORT_SYMBOL(b53_phylink_mac_config);
1419
b53_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1420 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1421 unsigned int mode,
1422 phy_interface_t interface)
1423 {
1424 struct b53_device *dev = ds->priv;
1425
1426 if (mode == MLO_AN_PHY)
1427 return;
1428
1429 if (mode == MLO_AN_FIXED) {
1430 b53_force_link(dev, port, false);
1431 return;
1432 }
1433
1434 if (phy_interface_mode_is_8023z(interface) &&
1435 dev->ops->serdes_link_set)
1436 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1437 }
1438 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1439
b53_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1440 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1441 unsigned int mode,
1442 phy_interface_t interface,
1443 struct phy_device *phydev,
1444 int speed, int duplex,
1445 bool tx_pause, bool rx_pause)
1446 {
1447 struct b53_device *dev = ds->priv;
1448
1449 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1450 b53_adjust_63xx_rgmii(ds, port, interface);
1451
1452 if (mode == MLO_AN_PHY)
1453 return;
1454
1455 if (mode == MLO_AN_FIXED) {
1456 b53_force_port_config(dev, port, speed, duplex,
1457 tx_pause, rx_pause);
1458 b53_force_link(dev, port, true);
1459 return;
1460 }
1461
1462 if (phy_interface_mode_is_8023z(interface) &&
1463 dev->ops->serdes_link_set)
1464 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1465 }
1466 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1467
b53_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1468 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1469 struct netlink_ext_ack *extack)
1470 {
1471 struct b53_device *dev = ds->priv;
1472
1473 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1474
1475 return 0;
1476 }
1477 EXPORT_SYMBOL(b53_vlan_filtering);
1478
b53_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1479 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1480 const struct switchdev_obj_port_vlan *vlan)
1481 {
1482 struct b53_device *dev = ds->priv;
1483
1484 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1485 return -EOPNOTSUPP;
1486
1487 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1488 * receiving VLAN tagged frames at all, we can still allow the port to
1489 * be configured for egress untagged.
1490 */
1491 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1492 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1493 return -EINVAL;
1494
1495 if (vlan->vid >= dev->num_vlans)
1496 return -ERANGE;
1497
1498 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1499
1500 return 0;
1501 }
1502
b53_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1503 int b53_vlan_add(struct dsa_switch *ds, int port,
1504 const struct switchdev_obj_port_vlan *vlan,
1505 struct netlink_ext_ack *extack)
1506 {
1507 struct b53_device *dev = ds->priv;
1508 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1509 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1510 struct b53_vlan *vl;
1511 u16 old_pvid, new_pvid;
1512 int err;
1513
1514 err = b53_vlan_prepare(ds, port, vlan);
1515 if (err)
1516 return err;
1517
1518 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &old_pvid);
1519 if (pvid)
1520 new_pvid = vlan->vid;
1521 else if (!pvid && vlan->vid == old_pvid)
1522 new_pvid = b53_default_pvid(dev);
1523 else
1524 new_pvid = old_pvid;
1525
1526 vl = &dev->vlans[vlan->vid];
1527
1528 b53_get_vlan_entry(dev, vlan->vid, vl);
1529
1530 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1531 untagged = true;
1532
1533 vl->members |= BIT(port);
1534 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1535 vl->untag |= BIT(port);
1536 else
1537 vl->untag &= ~BIT(port);
1538
1539 b53_set_vlan_entry(dev, vlan->vid, vl);
1540 b53_fast_age_vlan(dev, vlan->vid);
1541
1542 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) {
1543 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1544 new_pvid);
1545 b53_fast_age_vlan(dev, old_pvid);
1546 }
1547
1548 return 0;
1549 }
1550 EXPORT_SYMBOL(b53_vlan_add);
1551
b53_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1552 int b53_vlan_del(struct dsa_switch *ds, int port,
1553 const struct switchdev_obj_port_vlan *vlan)
1554 {
1555 struct b53_device *dev = ds->priv;
1556 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1557 struct b53_vlan *vl;
1558 u16 pvid;
1559
1560 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1561
1562 vl = &dev->vlans[vlan->vid];
1563
1564 b53_get_vlan_entry(dev, vlan->vid, vl);
1565
1566 vl->members &= ~BIT(port);
1567
1568 if (pvid == vlan->vid)
1569 pvid = b53_default_pvid(dev);
1570
1571 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1572 vl->untag &= ~(BIT(port));
1573
1574 b53_set_vlan_entry(dev, vlan->vid, vl);
1575 b53_fast_age_vlan(dev, vlan->vid);
1576
1577 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1578 b53_fast_age_vlan(dev, pvid);
1579
1580 return 0;
1581 }
1582 EXPORT_SYMBOL(b53_vlan_del);
1583
1584 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
b53_arl_op_wait(struct b53_device * dev)1585 static int b53_arl_op_wait(struct b53_device *dev)
1586 {
1587 unsigned int timeout = 10;
1588 u8 reg;
1589
1590 do {
1591 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1592 if (!(reg & ARLTBL_START_DONE))
1593 return 0;
1594
1595 usleep_range(1000, 2000);
1596 } while (timeout--);
1597
1598 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1599
1600 return -ETIMEDOUT;
1601 }
1602
b53_arl_rw_op(struct b53_device * dev,unsigned int op)1603 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1604 {
1605 u8 reg;
1606
1607 if (op > ARLTBL_RW)
1608 return -EINVAL;
1609
1610 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1611 reg |= ARLTBL_START_DONE;
1612 if (op)
1613 reg |= ARLTBL_RW;
1614 else
1615 reg &= ~ARLTBL_RW;
1616 if (dev->vlan_enabled)
1617 reg &= ~ARLTBL_IVL_SVL_SELECT;
1618 else
1619 reg |= ARLTBL_IVL_SVL_SELECT;
1620 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1621
1622 return b53_arl_op_wait(dev);
1623 }
1624
b53_arl_read(struct b53_device * dev,u64 mac,u16 vid,struct b53_arl_entry * ent,u8 * idx)1625 static int b53_arl_read(struct b53_device *dev, u64 mac,
1626 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1627 {
1628 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1629 unsigned int i;
1630 int ret;
1631
1632 ret = b53_arl_op_wait(dev);
1633 if (ret)
1634 return ret;
1635
1636 bitmap_zero(free_bins, dev->num_arl_bins);
1637
1638 /* Read the bins */
1639 for (i = 0; i < dev->num_arl_bins; i++) {
1640 u64 mac_vid;
1641 u32 fwd_entry;
1642
1643 b53_read64(dev, B53_ARLIO_PAGE,
1644 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1645 b53_read32(dev, B53_ARLIO_PAGE,
1646 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1647 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1648
1649 if (!(fwd_entry & ARLTBL_VALID)) {
1650 set_bit(i, free_bins);
1651 continue;
1652 }
1653 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1654 continue;
1655 if (dev->vlan_enabled &&
1656 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1657 continue;
1658 *idx = i;
1659 return 0;
1660 }
1661
1662 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1663 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1664 }
1665
b53_arl_op(struct b53_device * dev,int op,int port,const unsigned char * addr,u16 vid,bool is_valid)1666 static int b53_arl_op(struct b53_device *dev, int op, int port,
1667 const unsigned char *addr, u16 vid, bool is_valid)
1668 {
1669 struct b53_arl_entry ent;
1670 u32 fwd_entry;
1671 u64 mac, mac_vid = 0;
1672 u8 idx = 0;
1673 int ret;
1674
1675 /* Convert the array into a 64-bit MAC */
1676 mac = ether_addr_to_u64(addr);
1677
1678 /* Perform a read for the given MAC and VID */
1679 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1680 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1681
1682 /* Issue a read operation for this MAC */
1683 ret = b53_arl_rw_op(dev, 1);
1684 if (ret)
1685 return ret;
1686
1687 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1688
1689 /* If this is a read, just finish now */
1690 if (op)
1691 return ret;
1692
1693 switch (ret) {
1694 case -ETIMEDOUT:
1695 return ret;
1696 case -ENOSPC:
1697 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1698 addr, vid);
1699 return is_valid ? ret : 0;
1700 case -ENOENT:
1701 /* We could not find a matching MAC, so reset to a new entry */
1702 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1703 addr, vid, idx);
1704 fwd_entry = 0;
1705 break;
1706 default:
1707 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1708 addr, vid, idx);
1709 break;
1710 }
1711
1712 /* For multicast address, the port is a bitmask and the validity
1713 * is determined by having at least one port being still active
1714 */
1715 if (!is_multicast_ether_addr(addr)) {
1716 ent.port = port;
1717 ent.is_valid = is_valid;
1718 } else {
1719 if (is_valid)
1720 ent.port |= BIT(port);
1721 else
1722 ent.port &= ~BIT(port);
1723
1724 ent.is_valid = !!(ent.port);
1725 }
1726
1727 ent.vid = vid;
1728 ent.is_static = true;
1729 ent.is_age = false;
1730 memcpy(ent.mac, addr, ETH_ALEN);
1731 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1732
1733 b53_write64(dev, B53_ARLIO_PAGE,
1734 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1735 b53_write32(dev, B53_ARLIO_PAGE,
1736 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1737
1738 return b53_arl_rw_op(dev, 0);
1739 }
1740
b53_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1741 int b53_fdb_add(struct dsa_switch *ds, int port,
1742 const unsigned char *addr, u16 vid,
1743 struct dsa_db db)
1744 {
1745 struct b53_device *priv = ds->priv;
1746 int ret;
1747
1748 /* 5325 and 5365 require some more massaging, but could
1749 * be supported eventually
1750 */
1751 if (is5325(priv) || is5365(priv))
1752 return -EOPNOTSUPP;
1753
1754 mutex_lock(&priv->arl_mutex);
1755 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1756 mutex_unlock(&priv->arl_mutex);
1757
1758 return ret;
1759 }
1760 EXPORT_SYMBOL(b53_fdb_add);
1761
b53_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1762 int b53_fdb_del(struct dsa_switch *ds, int port,
1763 const unsigned char *addr, u16 vid,
1764 struct dsa_db db)
1765 {
1766 struct b53_device *priv = ds->priv;
1767 int ret;
1768
1769 mutex_lock(&priv->arl_mutex);
1770 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1771 mutex_unlock(&priv->arl_mutex);
1772
1773 return ret;
1774 }
1775 EXPORT_SYMBOL(b53_fdb_del);
1776
b53_arl_search_wait(struct b53_device * dev)1777 static int b53_arl_search_wait(struct b53_device *dev)
1778 {
1779 unsigned int timeout = 1000;
1780 u8 reg;
1781
1782 do {
1783 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1784 if (!(reg & ARL_SRCH_STDN))
1785 return 0;
1786
1787 if (reg & ARL_SRCH_VLID)
1788 return 0;
1789
1790 usleep_range(1000, 2000);
1791 } while (timeout--);
1792
1793 return -ETIMEDOUT;
1794 }
1795
b53_arl_search_rd(struct b53_device * dev,u8 idx,struct b53_arl_entry * ent)1796 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1797 struct b53_arl_entry *ent)
1798 {
1799 u64 mac_vid;
1800 u32 fwd_entry;
1801
1802 b53_read64(dev, B53_ARLIO_PAGE,
1803 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1804 b53_read32(dev, B53_ARLIO_PAGE,
1805 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1806 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1807 }
1808
b53_fdb_copy(int port,const struct b53_arl_entry * ent,dsa_fdb_dump_cb_t * cb,void * data)1809 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1810 dsa_fdb_dump_cb_t *cb, void *data)
1811 {
1812 if (!ent->is_valid)
1813 return 0;
1814
1815 if (port != ent->port)
1816 return 0;
1817
1818 return cb(ent->mac, ent->vid, ent->is_static, data);
1819 }
1820
b53_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1821 int b53_fdb_dump(struct dsa_switch *ds, int port,
1822 dsa_fdb_dump_cb_t *cb, void *data)
1823 {
1824 struct b53_device *priv = ds->priv;
1825 struct b53_arl_entry results[2];
1826 unsigned int count = 0;
1827 int ret;
1828 u8 reg;
1829
1830 mutex_lock(&priv->arl_mutex);
1831
1832 /* Start search operation */
1833 reg = ARL_SRCH_STDN;
1834 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1835
1836 do {
1837 ret = b53_arl_search_wait(priv);
1838 if (ret)
1839 break;
1840
1841 b53_arl_search_rd(priv, 0, &results[0]);
1842 ret = b53_fdb_copy(port, &results[0], cb, data);
1843 if (ret)
1844 break;
1845
1846 if (priv->num_arl_bins > 2) {
1847 b53_arl_search_rd(priv, 1, &results[1]);
1848 ret = b53_fdb_copy(port, &results[1], cb, data);
1849 if (ret)
1850 break;
1851
1852 if (!results[0].is_valid && !results[1].is_valid)
1853 break;
1854 }
1855
1856 } while (count++ < b53_max_arl_entries(priv) / 2);
1857
1858 mutex_unlock(&priv->arl_mutex);
1859
1860 return 0;
1861 }
1862 EXPORT_SYMBOL(b53_fdb_dump);
1863
b53_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1864 int b53_mdb_add(struct dsa_switch *ds, int port,
1865 const struct switchdev_obj_port_mdb *mdb,
1866 struct dsa_db db)
1867 {
1868 struct b53_device *priv = ds->priv;
1869 int ret;
1870
1871 /* 5325 and 5365 require some more massaging, but could
1872 * be supported eventually
1873 */
1874 if (is5325(priv) || is5365(priv))
1875 return -EOPNOTSUPP;
1876
1877 mutex_lock(&priv->arl_mutex);
1878 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1879 mutex_unlock(&priv->arl_mutex);
1880
1881 return ret;
1882 }
1883 EXPORT_SYMBOL(b53_mdb_add);
1884
b53_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1885 int b53_mdb_del(struct dsa_switch *ds, int port,
1886 const struct switchdev_obj_port_mdb *mdb,
1887 struct dsa_db db)
1888 {
1889 struct b53_device *priv = ds->priv;
1890 int ret;
1891
1892 mutex_lock(&priv->arl_mutex);
1893 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1894 mutex_unlock(&priv->arl_mutex);
1895 if (ret)
1896 dev_err(ds->dev, "failed to delete MDB entry\n");
1897
1898 return ret;
1899 }
1900 EXPORT_SYMBOL(b53_mdb_del);
1901
b53_br_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1902 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1903 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1904 {
1905 struct b53_device *dev = ds->priv;
1906 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1907 u16 pvlan, reg;
1908 unsigned int i;
1909
1910 /* On 7278, port 7 which connects to the ASP should only receive
1911 * traffic from matching CFP rules.
1912 */
1913 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1914 return -EINVAL;
1915
1916 /* Make this port leave the all VLANs join since we will have proper
1917 * VLAN entries from now on
1918 */
1919 if (is58xx(dev)) {
1920 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1921 reg &= ~BIT(port);
1922 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1923 reg &= ~BIT(cpu_port);
1924 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1925 }
1926
1927 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1928
1929 b53_for_each_port(dev, i) {
1930 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1931 continue;
1932
1933 /* Add this local port to the remote port VLAN control
1934 * membership and update the remote port bitmask
1935 */
1936 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1937 reg |= BIT(port);
1938 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1939 dev->ports[i].vlan_ctl_mask = reg;
1940
1941 pvlan |= BIT(i);
1942 }
1943
1944 /* Configure the local port VLAN control membership to include
1945 * remote ports and update the local port bitmask
1946 */
1947 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1948 dev->ports[port].vlan_ctl_mask = pvlan;
1949
1950 return 0;
1951 }
1952 EXPORT_SYMBOL(b53_br_join);
1953
b53_br_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1954 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1955 {
1956 struct b53_device *dev = ds->priv;
1957 struct b53_vlan *vl;
1958 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1959 unsigned int i;
1960 u16 pvlan, reg, pvid;
1961
1962 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1963
1964 b53_for_each_port(dev, i) {
1965 /* Don't touch the remaining ports */
1966 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1967 continue;
1968
1969 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1970 reg &= ~BIT(port);
1971 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1972 dev->ports[port].vlan_ctl_mask = reg;
1973
1974 /* Prevent self removal to preserve isolation */
1975 if (port != i)
1976 pvlan &= ~BIT(i);
1977 }
1978
1979 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1980 dev->ports[port].vlan_ctl_mask = pvlan;
1981
1982 pvid = b53_default_pvid(dev);
1983 vl = &dev->vlans[pvid];
1984
1985 /* Make this port join all VLANs without VLAN entries */
1986 if (is58xx(dev)) {
1987 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1988 reg |= BIT(port);
1989 if (!(reg & BIT(cpu_port)))
1990 reg |= BIT(cpu_port);
1991 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1992 }
1993
1994 b53_get_vlan_entry(dev, pvid, vl);
1995 vl->members |= BIT(port) | BIT(cpu_port);
1996 vl->untag |= BIT(port) | BIT(cpu_port);
1997 b53_set_vlan_entry(dev, pvid, vl);
1998 }
1999 EXPORT_SYMBOL(b53_br_leave);
2000
b53_br_set_stp_state(struct dsa_switch * ds,int port,u8 state)2001 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
2002 {
2003 struct b53_device *dev = ds->priv;
2004 u8 hw_state;
2005 u8 reg;
2006
2007 switch (state) {
2008 case BR_STATE_DISABLED:
2009 hw_state = PORT_CTRL_DIS_STATE;
2010 break;
2011 case BR_STATE_LISTENING:
2012 hw_state = PORT_CTRL_LISTEN_STATE;
2013 break;
2014 case BR_STATE_LEARNING:
2015 hw_state = PORT_CTRL_LEARN_STATE;
2016 break;
2017 case BR_STATE_FORWARDING:
2018 hw_state = PORT_CTRL_FWD_STATE;
2019 break;
2020 case BR_STATE_BLOCKING:
2021 hw_state = PORT_CTRL_BLOCK_STATE;
2022 break;
2023 default:
2024 dev_err(ds->dev, "invalid STP state: %d\n", state);
2025 return;
2026 }
2027
2028 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2029 reg &= ~PORT_CTRL_STP_STATE_MASK;
2030 reg |= hw_state;
2031 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2032 }
2033 EXPORT_SYMBOL(b53_br_set_stp_state);
2034
b53_br_fast_age(struct dsa_switch * ds,int port)2035 void b53_br_fast_age(struct dsa_switch *ds, int port)
2036 {
2037 struct b53_device *dev = ds->priv;
2038
2039 if (b53_fast_age_port(dev, port))
2040 dev_err(ds->dev, "fast ageing failed\n");
2041 }
2042 EXPORT_SYMBOL(b53_br_fast_age);
2043
b53_br_flags_pre(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2044 int b53_br_flags_pre(struct dsa_switch *ds, int port,
2045 struct switchdev_brport_flags flags,
2046 struct netlink_ext_ack *extack)
2047 {
2048 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2049 return -EINVAL;
2050
2051 return 0;
2052 }
2053 EXPORT_SYMBOL(b53_br_flags_pre);
2054
b53_br_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2055 int b53_br_flags(struct dsa_switch *ds, int port,
2056 struct switchdev_brport_flags flags,
2057 struct netlink_ext_ack *extack)
2058 {
2059 if (flags.mask & BR_FLOOD)
2060 b53_port_set_ucast_flood(ds->priv, port,
2061 !!(flags.val & BR_FLOOD));
2062 if (flags.mask & BR_MCAST_FLOOD)
2063 b53_port_set_mcast_flood(ds->priv, port,
2064 !!(flags.val & BR_MCAST_FLOOD));
2065 if (flags.mask & BR_LEARNING)
2066 b53_port_set_learning(ds->priv, port,
2067 !!(flags.val & BR_LEARNING));
2068
2069 return 0;
2070 }
2071 EXPORT_SYMBOL(b53_br_flags);
2072
b53_possible_cpu_port(struct dsa_switch * ds,int port)2073 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2074 {
2075 /* Broadcom switches will accept enabling Broadcom tags on the
2076 * following ports: 5, 7 and 8, any other port is not supported
2077 */
2078 switch (port) {
2079 case B53_CPU_PORT_25:
2080 case 7:
2081 case B53_CPU_PORT:
2082 return true;
2083 }
2084
2085 return false;
2086 }
2087
b53_can_enable_brcm_tags(struct dsa_switch * ds,int port,enum dsa_tag_protocol tag_protocol)2088 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2089 enum dsa_tag_protocol tag_protocol)
2090 {
2091 bool ret = b53_possible_cpu_port(ds, port);
2092
2093 if (!ret) {
2094 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2095 port);
2096 return ret;
2097 }
2098
2099 switch (tag_protocol) {
2100 case DSA_TAG_PROTO_BRCM:
2101 case DSA_TAG_PROTO_BRCM_PREPEND:
2102 dev_warn(ds->dev,
2103 "Port %d is stacked to Broadcom tag switch\n", port);
2104 ret = false;
2105 break;
2106 default:
2107 ret = true;
2108 break;
2109 }
2110
2111 return ret;
2112 }
2113
b53_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mprot)2114 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2115 enum dsa_tag_protocol mprot)
2116 {
2117 struct b53_device *dev = ds->priv;
2118
2119 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2120 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2121 goto out;
2122 }
2123
2124 /* Older models require a different 6 byte tag */
2125 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2126 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2127 goto out;
2128 }
2129
2130 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2131 * which requires us to use the prepended Broadcom tag type
2132 */
2133 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2134 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2135 goto out;
2136 }
2137
2138 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2139 out:
2140 return dev->tag_protocol;
2141 }
2142 EXPORT_SYMBOL(b53_get_tag_protocol);
2143
b53_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2144 int b53_mirror_add(struct dsa_switch *ds, int port,
2145 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2146 struct netlink_ext_ack *extack)
2147 {
2148 struct b53_device *dev = ds->priv;
2149 u16 reg, loc;
2150
2151 if (ingress)
2152 loc = B53_IG_MIR_CTL;
2153 else
2154 loc = B53_EG_MIR_CTL;
2155
2156 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2157 reg |= BIT(port);
2158 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2159
2160 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2161 reg &= ~CAP_PORT_MASK;
2162 reg |= mirror->to_local_port;
2163 reg |= MIRROR_EN;
2164 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2165
2166 return 0;
2167 }
2168 EXPORT_SYMBOL(b53_mirror_add);
2169
b53_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2170 void b53_mirror_del(struct dsa_switch *ds, int port,
2171 struct dsa_mall_mirror_tc_entry *mirror)
2172 {
2173 struct b53_device *dev = ds->priv;
2174 bool loc_disable = false, other_loc_disable = false;
2175 u16 reg, loc;
2176
2177 if (mirror->ingress)
2178 loc = B53_IG_MIR_CTL;
2179 else
2180 loc = B53_EG_MIR_CTL;
2181
2182 /* Update the desired ingress/egress register */
2183 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2184 reg &= ~BIT(port);
2185 if (!(reg & MIRROR_MASK))
2186 loc_disable = true;
2187 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2188
2189 /* Now look at the other one to know if we can disable mirroring
2190 * entirely
2191 */
2192 if (mirror->ingress)
2193 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2194 else
2195 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2196 if (!(reg & MIRROR_MASK))
2197 other_loc_disable = true;
2198
2199 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2200 /* Both no longer have ports, let's disable mirroring */
2201 if (loc_disable && other_loc_disable) {
2202 reg &= ~MIRROR_EN;
2203 reg &= ~mirror->to_local_port;
2204 }
2205 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2206 }
2207 EXPORT_SYMBOL(b53_mirror_del);
2208
b53_eee_enable_set(struct dsa_switch * ds,int port,bool enable)2209 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2210 {
2211 struct b53_device *dev = ds->priv;
2212 u16 reg;
2213
2214 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2215 if (enable)
2216 reg |= BIT(port);
2217 else
2218 reg &= ~BIT(port);
2219 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2220 }
2221 EXPORT_SYMBOL(b53_eee_enable_set);
2222
2223
2224 /* Returns 0 if EEE was not enabled, or 1 otherwise
2225 */
b53_eee_init(struct dsa_switch * ds,int port,struct phy_device * phy)2226 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2227 {
2228 int ret;
2229
2230 ret = phy_init_eee(phy, false);
2231 if (ret)
2232 return 0;
2233
2234 b53_eee_enable_set(ds, port, true);
2235
2236 return 1;
2237 }
2238 EXPORT_SYMBOL(b53_eee_init);
2239
b53_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2240 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2241 {
2242 struct b53_device *dev = ds->priv;
2243 struct ethtool_eee *p = &dev->ports[port].eee;
2244 u16 reg;
2245
2246 if (is5325(dev) || is5365(dev))
2247 return -EOPNOTSUPP;
2248
2249 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2250 e->eee_enabled = p->eee_enabled;
2251 e->eee_active = !!(reg & BIT(port));
2252
2253 return 0;
2254 }
2255 EXPORT_SYMBOL(b53_get_mac_eee);
2256
b53_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2257 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2258 {
2259 struct b53_device *dev = ds->priv;
2260 struct ethtool_eee *p = &dev->ports[port].eee;
2261
2262 if (is5325(dev) || is5365(dev))
2263 return -EOPNOTSUPP;
2264
2265 p->eee_enabled = e->eee_enabled;
2266 b53_eee_enable_set(ds, port, e->eee_enabled);
2267
2268 return 0;
2269 }
2270 EXPORT_SYMBOL(b53_set_mac_eee);
2271
b53_change_mtu(struct dsa_switch * ds,int port,int mtu)2272 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2273 {
2274 struct b53_device *dev = ds->priv;
2275 bool enable_jumbo;
2276 bool allow_10_100;
2277
2278 if (is5325(dev) || is5365(dev))
2279 return 0;
2280
2281 if (!dsa_is_cpu_port(ds, port))
2282 return 0;
2283
2284 enable_jumbo = (mtu > ETH_DATA_LEN);
2285 allow_10_100 = !is63xx(dev);
2286
2287 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2288 }
2289
b53_get_max_mtu(struct dsa_switch * ds,int port)2290 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2291 {
2292 struct b53_device *dev = ds->priv;
2293
2294 if (is5325(dev) || is5365(dev))
2295 return B53_MAX_MTU_25;
2296
2297 return B53_MAX_MTU;
2298 }
2299
2300 static const struct dsa_switch_ops b53_switch_ops = {
2301 .get_tag_protocol = b53_get_tag_protocol,
2302 .setup = b53_setup,
2303 .teardown = b53_teardown,
2304 .get_strings = b53_get_strings,
2305 .get_ethtool_stats = b53_get_ethtool_stats,
2306 .get_sset_count = b53_get_sset_count,
2307 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2308 .phy_read = b53_phy_read16,
2309 .phy_write = b53_phy_write16,
2310 .adjust_link = b53_adjust_link,
2311 .phylink_get_caps = b53_phylink_get_caps,
2312 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2313 .phylink_mac_config = b53_phylink_mac_config,
2314 .phylink_mac_link_down = b53_phylink_mac_link_down,
2315 .phylink_mac_link_up = b53_phylink_mac_link_up,
2316 .port_enable = b53_enable_port,
2317 .port_disable = b53_disable_port,
2318 .get_mac_eee = b53_get_mac_eee,
2319 .set_mac_eee = b53_set_mac_eee,
2320 .port_bridge_join = b53_br_join,
2321 .port_bridge_leave = b53_br_leave,
2322 .port_pre_bridge_flags = b53_br_flags_pre,
2323 .port_bridge_flags = b53_br_flags,
2324 .port_stp_state_set = b53_br_set_stp_state,
2325 .port_fast_age = b53_br_fast_age,
2326 .port_vlan_filtering = b53_vlan_filtering,
2327 .port_vlan_add = b53_vlan_add,
2328 .port_vlan_del = b53_vlan_del,
2329 .port_fdb_dump = b53_fdb_dump,
2330 .port_fdb_add = b53_fdb_add,
2331 .port_fdb_del = b53_fdb_del,
2332 .port_mirror_add = b53_mirror_add,
2333 .port_mirror_del = b53_mirror_del,
2334 .port_mdb_add = b53_mdb_add,
2335 .port_mdb_del = b53_mdb_del,
2336 .port_max_mtu = b53_get_max_mtu,
2337 .port_change_mtu = b53_change_mtu,
2338 };
2339
2340 struct b53_chip_data {
2341 u32 chip_id;
2342 const char *dev_name;
2343 u16 vlans;
2344 u16 enabled_ports;
2345 u8 imp_port;
2346 u8 cpu_port;
2347 u8 vta_regs[3];
2348 u8 arl_bins;
2349 u16 arl_buckets;
2350 u8 duplex_reg;
2351 u8 jumbo_pm_reg;
2352 u8 jumbo_size_reg;
2353 };
2354
2355 #define B53_VTA_REGS \
2356 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2357 #define B53_VTA_REGS_9798 \
2358 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2359 #define B53_VTA_REGS_63XX \
2360 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2361
2362 static const struct b53_chip_data b53_switch_chips[] = {
2363 {
2364 .chip_id = BCM5325_DEVICE_ID,
2365 .dev_name = "BCM5325",
2366 .vlans = 16,
2367 .enabled_ports = 0x3f,
2368 .arl_bins = 2,
2369 .arl_buckets = 1024,
2370 .imp_port = 5,
2371 .duplex_reg = B53_DUPLEX_STAT_FE,
2372 },
2373 {
2374 .chip_id = BCM5365_DEVICE_ID,
2375 .dev_name = "BCM5365",
2376 .vlans = 256,
2377 .enabled_ports = 0x3f,
2378 .arl_bins = 2,
2379 .arl_buckets = 1024,
2380 .imp_port = 5,
2381 .duplex_reg = B53_DUPLEX_STAT_FE,
2382 },
2383 {
2384 .chip_id = BCM5389_DEVICE_ID,
2385 .dev_name = "BCM5389",
2386 .vlans = 4096,
2387 .enabled_ports = 0x11f,
2388 .arl_bins = 4,
2389 .arl_buckets = 1024,
2390 .imp_port = 8,
2391 .vta_regs = B53_VTA_REGS,
2392 .duplex_reg = B53_DUPLEX_STAT_GE,
2393 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2394 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2395 },
2396 {
2397 .chip_id = BCM5395_DEVICE_ID,
2398 .dev_name = "BCM5395",
2399 .vlans = 4096,
2400 .enabled_ports = 0x11f,
2401 .arl_bins = 4,
2402 .arl_buckets = 1024,
2403 .imp_port = 8,
2404 .vta_regs = B53_VTA_REGS,
2405 .duplex_reg = B53_DUPLEX_STAT_GE,
2406 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2407 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2408 },
2409 {
2410 .chip_id = BCM5397_DEVICE_ID,
2411 .dev_name = "BCM5397",
2412 .vlans = 4096,
2413 .enabled_ports = 0x11f,
2414 .arl_bins = 4,
2415 .arl_buckets = 1024,
2416 .imp_port = 8,
2417 .vta_regs = B53_VTA_REGS_9798,
2418 .duplex_reg = B53_DUPLEX_STAT_GE,
2419 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2420 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2421 },
2422 {
2423 .chip_id = BCM5398_DEVICE_ID,
2424 .dev_name = "BCM5398",
2425 .vlans = 4096,
2426 .enabled_ports = 0x17f,
2427 .arl_bins = 4,
2428 .arl_buckets = 1024,
2429 .imp_port = 8,
2430 .vta_regs = B53_VTA_REGS_9798,
2431 .duplex_reg = B53_DUPLEX_STAT_GE,
2432 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2433 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2434 },
2435 {
2436 .chip_id = BCM53115_DEVICE_ID,
2437 .dev_name = "BCM53115",
2438 .vlans = 4096,
2439 .enabled_ports = 0x11f,
2440 .arl_bins = 4,
2441 .arl_buckets = 1024,
2442 .vta_regs = B53_VTA_REGS,
2443 .imp_port = 8,
2444 .duplex_reg = B53_DUPLEX_STAT_GE,
2445 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2446 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2447 },
2448 {
2449 .chip_id = BCM53125_DEVICE_ID,
2450 .dev_name = "BCM53125",
2451 .vlans = 4096,
2452 .enabled_ports = 0x1ff,
2453 .arl_bins = 4,
2454 .arl_buckets = 1024,
2455 .imp_port = 8,
2456 .vta_regs = B53_VTA_REGS,
2457 .duplex_reg = B53_DUPLEX_STAT_GE,
2458 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2459 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2460 },
2461 {
2462 .chip_id = BCM53128_DEVICE_ID,
2463 .dev_name = "BCM53128",
2464 .vlans = 4096,
2465 .enabled_ports = 0x1ff,
2466 .arl_bins = 4,
2467 .arl_buckets = 1024,
2468 .imp_port = 8,
2469 .vta_regs = B53_VTA_REGS,
2470 .duplex_reg = B53_DUPLEX_STAT_GE,
2471 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2472 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2473 },
2474 {
2475 .chip_id = BCM63XX_DEVICE_ID,
2476 .dev_name = "BCM63xx",
2477 .vlans = 4096,
2478 .enabled_ports = 0, /* pdata must provide them */
2479 .arl_bins = 4,
2480 .arl_buckets = 1024,
2481 .imp_port = 8,
2482 .vta_regs = B53_VTA_REGS_63XX,
2483 .duplex_reg = B53_DUPLEX_STAT_63XX,
2484 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2485 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2486 },
2487 {
2488 .chip_id = BCM63268_DEVICE_ID,
2489 .dev_name = "BCM63268",
2490 .vlans = 4096,
2491 .enabled_ports = 0, /* pdata must provide them */
2492 .arl_bins = 4,
2493 .arl_buckets = 1024,
2494 .imp_port = 8,
2495 .vta_regs = B53_VTA_REGS_63XX,
2496 .duplex_reg = B53_DUPLEX_STAT_63XX,
2497 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2498 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2499 },
2500 {
2501 .chip_id = BCM53010_DEVICE_ID,
2502 .dev_name = "BCM53010",
2503 .vlans = 4096,
2504 .enabled_ports = 0x1bf,
2505 .arl_bins = 4,
2506 .arl_buckets = 1024,
2507 .imp_port = 8,
2508 .vta_regs = B53_VTA_REGS,
2509 .duplex_reg = B53_DUPLEX_STAT_GE,
2510 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2511 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2512 },
2513 {
2514 .chip_id = BCM53011_DEVICE_ID,
2515 .dev_name = "BCM53011",
2516 .vlans = 4096,
2517 .enabled_ports = 0x1bf,
2518 .arl_bins = 4,
2519 .arl_buckets = 1024,
2520 .imp_port = 8,
2521 .vta_regs = B53_VTA_REGS,
2522 .duplex_reg = B53_DUPLEX_STAT_GE,
2523 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2524 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2525 },
2526 {
2527 .chip_id = BCM53012_DEVICE_ID,
2528 .dev_name = "BCM53012",
2529 .vlans = 4096,
2530 .enabled_ports = 0x1bf,
2531 .arl_bins = 4,
2532 .arl_buckets = 1024,
2533 .imp_port = 8,
2534 .vta_regs = B53_VTA_REGS,
2535 .duplex_reg = B53_DUPLEX_STAT_GE,
2536 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2537 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2538 },
2539 {
2540 .chip_id = BCM53018_DEVICE_ID,
2541 .dev_name = "BCM53018",
2542 .vlans = 4096,
2543 .enabled_ports = 0x1bf,
2544 .arl_bins = 4,
2545 .arl_buckets = 1024,
2546 .imp_port = 8,
2547 .vta_regs = B53_VTA_REGS,
2548 .duplex_reg = B53_DUPLEX_STAT_GE,
2549 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2550 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2551 },
2552 {
2553 .chip_id = BCM53019_DEVICE_ID,
2554 .dev_name = "BCM53019",
2555 .vlans = 4096,
2556 .enabled_ports = 0x1bf,
2557 .arl_bins = 4,
2558 .arl_buckets = 1024,
2559 .imp_port = 8,
2560 .vta_regs = B53_VTA_REGS,
2561 .duplex_reg = B53_DUPLEX_STAT_GE,
2562 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2563 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2564 },
2565 {
2566 .chip_id = BCM58XX_DEVICE_ID,
2567 .dev_name = "BCM585xx/586xx/88312",
2568 .vlans = 4096,
2569 .enabled_ports = 0x1ff,
2570 .arl_bins = 4,
2571 .arl_buckets = 1024,
2572 .imp_port = 8,
2573 .vta_regs = B53_VTA_REGS,
2574 .duplex_reg = B53_DUPLEX_STAT_GE,
2575 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2576 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2577 },
2578 {
2579 .chip_id = BCM583XX_DEVICE_ID,
2580 .dev_name = "BCM583xx/11360",
2581 .vlans = 4096,
2582 .enabled_ports = 0x103,
2583 .arl_bins = 4,
2584 .arl_buckets = 1024,
2585 .imp_port = 8,
2586 .vta_regs = B53_VTA_REGS,
2587 .duplex_reg = B53_DUPLEX_STAT_GE,
2588 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2589 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2590 },
2591 /* Starfighter 2 */
2592 {
2593 .chip_id = BCM4908_DEVICE_ID,
2594 .dev_name = "BCM4908",
2595 .vlans = 4096,
2596 .enabled_ports = 0x1bf,
2597 .arl_bins = 4,
2598 .arl_buckets = 256,
2599 .imp_port = 8,
2600 .vta_regs = B53_VTA_REGS,
2601 .duplex_reg = B53_DUPLEX_STAT_GE,
2602 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2603 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2604 },
2605 {
2606 .chip_id = BCM7445_DEVICE_ID,
2607 .dev_name = "BCM7445",
2608 .vlans = 4096,
2609 .enabled_ports = 0x1ff,
2610 .arl_bins = 4,
2611 .arl_buckets = 1024,
2612 .imp_port = 8,
2613 .vta_regs = B53_VTA_REGS,
2614 .duplex_reg = B53_DUPLEX_STAT_GE,
2615 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2616 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2617 },
2618 {
2619 .chip_id = BCM7278_DEVICE_ID,
2620 .dev_name = "BCM7278",
2621 .vlans = 4096,
2622 .enabled_ports = 0x1ff,
2623 .arl_bins = 4,
2624 .arl_buckets = 256,
2625 .imp_port = 8,
2626 .vta_regs = B53_VTA_REGS,
2627 .duplex_reg = B53_DUPLEX_STAT_GE,
2628 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2629 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2630 },
2631 {
2632 .chip_id = BCM53134_DEVICE_ID,
2633 .dev_name = "BCM53134",
2634 .vlans = 4096,
2635 .enabled_ports = 0x12f,
2636 .imp_port = 8,
2637 .cpu_port = B53_CPU_PORT,
2638 .vta_regs = B53_VTA_REGS,
2639 .arl_bins = 4,
2640 .arl_buckets = 1024,
2641 .duplex_reg = B53_DUPLEX_STAT_GE,
2642 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2643 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2644 },
2645 };
2646
b53_switch_init(struct b53_device * dev)2647 static int b53_switch_init(struct b53_device *dev)
2648 {
2649 unsigned int i;
2650 int ret;
2651
2652 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2653 const struct b53_chip_data *chip = &b53_switch_chips[i];
2654
2655 if (chip->chip_id == dev->chip_id) {
2656 if (!dev->enabled_ports)
2657 dev->enabled_ports = chip->enabled_ports;
2658 dev->name = chip->dev_name;
2659 dev->duplex_reg = chip->duplex_reg;
2660 dev->vta_regs[0] = chip->vta_regs[0];
2661 dev->vta_regs[1] = chip->vta_regs[1];
2662 dev->vta_regs[2] = chip->vta_regs[2];
2663 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2664 dev->imp_port = chip->imp_port;
2665 dev->num_vlans = chip->vlans;
2666 dev->num_arl_bins = chip->arl_bins;
2667 dev->num_arl_buckets = chip->arl_buckets;
2668 break;
2669 }
2670 }
2671
2672 /* check which BCM5325x version we have */
2673 if (is5325(dev)) {
2674 u8 vc4;
2675
2676 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2677
2678 /* check reserved bits */
2679 switch (vc4 & 3) {
2680 case 1:
2681 /* BCM5325E */
2682 break;
2683 case 3:
2684 /* BCM5325F - do not use port 4 */
2685 dev->enabled_ports &= ~BIT(4);
2686 break;
2687 default:
2688 /* On the BCM47XX SoCs this is the supported internal switch.*/
2689 #ifndef CONFIG_BCM47XX
2690 /* BCM5325M */
2691 return -EINVAL;
2692 #else
2693 break;
2694 #endif
2695 }
2696 }
2697
2698 dev->num_ports = fls(dev->enabled_ports);
2699
2700 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2701
2702 /* Include non standard CPU port built-in PHYs to be probed */
2703 if (is539x(dev) || is531x5(dev)) {
2704 for (i = 0; i < dev->num_ports; i++) {
2705 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2706 !b53_possible_cpu_port(dev->ds, i))
2707 dev->ds->phys_mii_mask |= BIT(i);
2708 }
2709 }
2710
2711 dev->ports = devm_kcalloc(dev->dev,
2712 dev->num_ports, sizeof(struct b53_port),
2713 GFP_KERNEL);
2714 if (!dev->ports)
2715 return -ENOMEM;
2716
2717 dev->vlans = devm_kcalloc(dev->dev,
2718 dev->num_vlans, sizeof(struct b53_vlan),
2719 GFP_KERNEL);
2720 if (!dev->vlans)
2721 return -ENOMEM;
2722
2723 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2724 if (dev->reset_gpio >= 0) {
2725 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2726 GPIOF_OUT_INIT_HIGH, "robo_reset");
2727 if (ret)
2728 return ret;
2729 }
2730
2731 return 0;
2732 }
2733
b53_switch_alloc(struct device * base,const struct b53_io_ops * ops,void * priv)2734 struct b53_device *b53_switch_alloc(struct device *base,
2735 const struct b53_io_ops *ops,
2736 void *priv)
2737 {
2738 struct dsa_switch *ds;
2739 struct b53_device *dev;
2740
2741 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2742 if (!ds)
2743 return NULL;
2744
2745 ds->dev = base;
2746
2747 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2748 if (!dev)
2749 return NULL;
2750
2751 ds->priv = dev;
2752 dev->dev = base;
2753
2754 dev->ds = ds;
2755 dev->priv = priv;
2756 dev->ops = ops;
2757 ds->ops = &b53_switch_ops;
2758 dev->vlan_enabled = true;
2759 /* Let DSA handle the case were multiple bridges span the same switch
2760 * device and different VLAN awareness settings are requested, which
2761 * would be breaking filtering semantics for any of the other bridge
2762 * devices. (not hardware supported)
2763 */
2764 ds->vlan_filtering_is_global = true;
2765
2766 mutex_init(&dev->reg_mutex);
2767 mutex_init(&dev->stats_mutex);
2768 mutex_init(&dev->arl_mutex);
2769
2770 return dev;
2771 }
2772 EXPORT_SYMBOL(b53_switch_alloc);
2773
b53_switch_detect(struct b53_device * dev)2774 int b53_switch_detect(struct b53_device *dev)
2775 {
2776 u32 id32;
2777 u16 tmp;
2778 u8 id8;
2779 int ret;
2780
2781 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2782 if (ret)
2783 return ret;
2784
2785 switch (id8) {
2786 case 0:
2787 /* BCM5325 and BCM5365 do not have this register so reads
2788 * return 0. But the read operation did succeed, so assume this
2789 * is one of them.
2790 *
2791 * Next check if we can write to the 5325's VTA register; for
2792 * 5365 it is read only.
2793 */
2794 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2795 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2796
2797 if (tmp == 0xf)
2798 dev->chip_id = BCM5325_DEVICE_ID;
2799 else
2800 dev->chip_id = BCM5365_DEVICE_ID;
2801 break;
2802 case BCM5389_DEVICE_ID:
2803 case BCM5395_DEVICE_ID:
2804 case BCM5397_DEVICE_ID:
2805 case BCM5398_DEVICE_ID:
2806 dev->chip_id = id8;
2807 break;
2808 default:
2809 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2810 if (ret)
2811 return ret;
2812
2813 switch (id32) {
2814 case BCM53115_DEVICE_ID:
2815 case BCM53125_DEVICE_ID:
2816 case BCM53128_DEVICE_ID:
2817 case BCM53010_DEVICE_ID:
2818 case BCM53011_DEVICE_ID:
2819 case BCM53012_DEVICE_ID:
2820 case BCM53018_DEVICE_ID:
2821 case BCM53019_DEVICE_ID:
2822 case BCM53134_DEVICE_ID:
2823 dev->chip_id = id32;
2824 break;
2825 default:
2826 dev_err(dev->dev,
2827 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2828 id8, id32);
2829 return -ENODEV;
2830 }
2831 }
2832
2833 if (dev->chip_id == BCM5325_DEVICE_ID)
2834 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2835 &dev->core_rev);
2836 else
2837 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2838 &dev->core_rev);
2839 }
2840 EXPORT_SYMBOL(b53_switch_detect);
2841
b53_switch_register(struct b53_device * dev)2842 int b53_switch_register(struct b53_device *dev)
2843 {
2844 int ret;
2845
2846 if (dev->pdata) {
2847 dev->chip_id = dev->pdata->chip_id;
2848 dev->enabled_ports = dev->pdata->enabled_ports;
2849 }
2850
2851 if (!dev->chip_id && b53_switch_detect(dev))
2852 return -EINVAL;
2853
2854 ret = b53_switch_init(dev);
2855 if (ret)
2856 return ret;
2857
2858 dev_info(dev->dev, "found switch: %s, rev %i\n",
2859 dev->name, dev->core_rev);
2860
2861 return dsa_register_switch(dev->ds);
2862 }
2863 EXPORT_SYMBOL(b53_switch_register);
2864
2865 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2866 MODULE_DESCRIPTION("B53 switch library");
2867 MODULE_LICENSE("Dual BSD/GPL");
2868