xref: /openbmc/linux/sound/soc/meson/axg-frddr.c (revision af8e6bbf)
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
5 
6 /*
7  * This driver implements the frontend playback DAI of AXG and G12A based SoCs
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/regmap.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <sound/pcm_params.h>
16 #include <sound/soc.h>
17 #include <sound/soc-dai.h>
18 
19 #include "axg-fifo.h"
20 
21 #define CTRL0_FRDDR_PP_MODE		BIT(30)
22 #define CTRL0_SEL1_EN_SHIFT		3
23 #define CTRL0_SEL2_SHIFT		4
24 #define CTRL0_SEL2_EN_SHIFT		7
25 #define CTRL0_SEL3_SHIFT		8
26 #define CTRL0_SEL3_EN_SHIFT		11
27 #define CTRL1_FRDDR_FORCE_FINISH	BIT(12)
28 #define CTRL2_SEL1_SHIFT		0
29 #define CTRL2_SEL1_EN_SHIFT		4
30 #define CTRL2_SEL2_SHIFT		8
31 #define CTRL2_SEL2_EN_SHIFT		12
32 #define CTRL2_SEL3_SHIFT		16
33 #define CTRL2_SEL3_EN_SHIFT		20
34 
g12a_frddr_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)35 static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream,
36 				  struct snd_soc_dai *dai)
37 {
38 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
39 
40 	/* Reset the read pointer to the FIFO_INIT_ADDR */
41 	regmap_update_bits(fifo->map, FIFO_CTRL1,
42 			   CTRL1_FRDDR_FORCE_FINISH, 0);
43 	regmap_update_bits(fifo->map, FIFO_CTRL1,
44 			   CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
45 	regmap_update_bits(fifo->map, FIFO_CTRL1,
46 			   CTRL1_FRDDR_FORCE_FINISH, 0);
47 
48 	return 0;
49 }
50 
axg_frddr_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)51 static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream,
52 				   struct snd_pcm_hw_params *params,
53 				   struct snd_soc_dai *dai)
54 {
55 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
56 	unsigned int period, depth, val;
57 
58 	period = params_period_bytes(params);
59 
60 	/* Trim the FIFO depth if the period is small to improve latency */
61 	depth = min(period, fifo->depth);
62 	val = (depth / AXG_FIFO_BURST) - 1;
63 	regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH,
64 			   FIELD_PREP(CTRL1_FRDDR_DEPTH, val));
65 
66 	return 0;
67 }
68 
axg_frddr_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)69 static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
70 				 struct snd_soc_dai *dai)
71 {
72 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
73 	int ret;
74 
75 	/* Enable pclk to access registers and clock the fifo ip */
76 	ret = clk_prepare_enable(fifo->pclk);
77 	if (ret)
78 		return ret;
79 
80 	/* Apply single buffer mode to the interface */
81 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
82 
83 	return 0;
84 }
85 
axg_frddr_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)86 static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
87 				   struct snd_soc_dai *dai)
88 {
89 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
90 
91 	clk_disable_unprepare(fifo->pclk);
92 }
93 
axg_frddr_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * dai)94 static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
95 			     struct snd_soc_dai *dai)
96 {
97 	return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
98 }
99 
100 static const struct snd_soc_dai_ops axg_frddr_ops = {
101 	.hw_params	= axg_frddr_dai_hw_params,
102 	.startup	= axg_frddr_dai_startup,
103 	.shutdown	= axg_frddr_dai_shutdown,
104 	.pcm_new	= axg_frddr_pcm_new,
105 };
106 
107 static struct snd_soc_dai_driver axg_frddr_dai_drv = {
108 	.name = "FRDDR",
109 	.playback = {
110 		.stream_name	= "Playback",
111 		.channels_min	= 1,
112 		.channels_max	= AXG_FIFO_CH_MAX,
113 		.rates		= AXG_FIFO_RATES,
114 		.formats	= AXG_FIFO_FORMATS,
115 	},
116 	.ops		= &axg_frddr_ops,
117 };
118 
119 static const char * const axg_frddr_sel_texts[] = {
120 	"OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", "OUT 5", "OUT 6", "OUT 7",
121 };
122 
123 static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
124 			    axg_frddr_sel_texts);
125 
126 static const struct snd_kcontrol_new axg_frddr_out_demux =
127 	SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
128 
129 static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
130 	SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
131 			   &axg_frddr_out_demux),
132 	SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
133 	SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
134 	SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
135 	SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
136 	SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
137 	SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
138 	SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
139 	SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
140 };
141 
142 static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
143 	{ "SINK SEL", NULL, "Playback" },
144 	{ "OUT 0", "OUT 0",  "SINK SEL" },
145 	{ "OUT 1", "OUT 1",  "SINK SEL" },
146 	{ "OUT 2", "OUT 2",  "SINK SEL" },
147 	{ "OUT 3", "OUT 3",  "SINK SEL" },
148 	{ "OUT 4", "OUT 4",  "SINK SEL" },
149 	{ "OUT 5", "OUT 5",  "SINK SEL" },
150 	{ "OUT 6", "OUT 6",  "SINK SEL" },
151 	{ "OUT 7", "OUT 7",  "SINK SEL" },
152 };
153 
154 static const struct snd_soc_component_driver axg_frddr_component_drv = {
155 	.dapm_widgets		= axg_frddr_dapm_widgets,
156 	.num_dapm_widgets	= ARRAY_SIZE(axg_frddr_dapm_widgets),
157 	.dapm_routes		= axg_frddr_dapm_routes,
158 	.num_dapm_routes	= ARRAY_SIZE(axg_frddr_dapm_routes),
159 	.open			= axg_fifo_pcm_open,
160 	.close			= axg_fifo_pcm_close,
161 	.hw_params		= axg_fifo_pcm_hw_params,
162 	.hw_free		= axg_fifo_pcm_hw_free,
163 	.pointer		= axg_fifo_pcm_pointer,
164 	.trigger		= axg_fifo_pcm_trigger,
165 	.legacy_dai_naming	= 1,
166 };
167 
168 static const struct axg_fifo_match_data axg_frddr_match_data = {
169 	.field_threshold	= REG_FIELD(FIFO_CTRL1, 16, 23),
170 	.component_drv		= &axg_frddr_component_drv,
171 	.dai_drv		= &axg_frddr_dai_drv
172 };
173 
174 static const struct snd_soc_dai_ops g12a_frddr_ops = {
175 	.prepare	= g12a_frddr_dai_prepare,
176 	.hw_params	= axg_frddr_dai_hw_params,
177 	.startup	= axg_frddr_dai_startup,
178 	.shutdown	= axg_frddr_dai_shutdown,
179 	.pcm_new	= axg_frddr_pcm_new,
180 };
181 
182 static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
183 	.name = "FRDDR",
184 	.playback = {
185 		.stream_name	= "Playback",
186 		.channels_min	= 1,
187 		.channels_max	= AXG_FIFO_CH_MAX,
188 		.rates		= AXG_FIFO_RATES,
189 		.formats	= AXG_FIFO_FORMATS,
190 	},
191 	.ops		= &g12a_frddr_ops,
192 };
193 
194 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
195 			    axg_frddr_sel_texts);
196 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT,
197 			    axg_frddr_sel_texts);
198 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT,
199 			    axg_frddr_sel_texts);
200 
201 static const struct snd_kcontrol_new g12a_frddr_out1_demux =
202 	SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum);
203 static const struct snd_kcontrol_new g12a_frddr_out2_demux =
204 	SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum);
205 static const struct snd_kcontrol_new g12a_frddr_out3_demux =
206 	SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum);
207 
208 static const struct snd_kcontrol_new g12a_frddr_out1_enable =
209 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
210 				    CTRL0_SEL1_EN_SHIFT, 1, 0);
211 static const struct snd_kcontrol_new g12a_frddr_out2_enable =
212 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
213 				    CTRL0_SEL2_EN_SHIFT, 1, 0);
214 static const struct snd_kcontrol_new g12a_frddr_out3_enable =
215 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
216 				    CTRL0_SEL3_EN_SHIFT, 1, 0);
217 
218 static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = {
219 	SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
220 	SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
221 	SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
222 	SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
223 			    &g12a_frddr_out1_enable),
224 	SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
225 			    &g12a_frddr_out2_enable),
226 	SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
227 			    &g12a_frddr_out3_enable),
228 	SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
229 			   &g12a_frddr_out1_demux),
230 	SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
231 			   &g12a_frddr_out2_demux),
232 	SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
233 			   &g12a_frddr_out3_demux),
234 	SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
235 	SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
236 	SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
237 	SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
238 	SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
239 	SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
240 	SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
241 	SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
242 };
243 
244 static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = {
245 	{ "SRC 1", NULL, "Playback" },
246 	{ "SRC 2", NULL, "Playback" },
247 	{ "SRC 3", NULL, "Playback" },
248 	{ "SRC 1 EN", "Switch", "SRC 1" },
249 	{ "SRC 2 EN", "Switch", "SRC 2" },
250 	{ "SRC 3 EN", "Switch", "SRC 3" },
251 	{ "SINK 1 SEL", NULL, "SRC 1 EN" },
252 	{ "SINK 2 SEL", NULL, "SRC 2 EN" },
253 	{ "SINK 3 SEL", NULL, "SRC 3 EN" },
254 	{ "OUT 0", "OUT 0", "SINK 1 SEL" },
255 	{ "OUT 1", "OUT 1", "SINK 1 SEL" },
256 	{ "OUT 2", "OUT 2", "SINK 1 SEL" },
257 	{ "OUT 3", "OUT 3", "SINK 1 SEL" },
258 	{ "OUT 4", "OUT 4", "SINK 1 SEL" },
259 	{ "OUT 5", "OUT 5", "SINK 1 SEL" },
260 	{ "OUT 6", "OUT 6", "SINK 1 SEL" },
261 	{ "OUT 7", "OUT 7", "SINK 1 SEL" },
262 	{ "OUT 0", "OUT 0", "SINK 2 SEL" },
263 	{ "OUT 1", "OUT 1", "SINK 2 SEL" },
264 	{ "OUT 2", "OUT 2", "SINK 2 SEL" },
265 	{ "OUT 3", "OUT 3", "SINK 2 SEL" },
266 	{ "OUT 4", "OUT 4", "SINK 2 SEL" },
267 	{ "OUT 5", "OUT 5", "SINK 2 SEL" },
268 	{ "OUT 6", "OUT 6", "SINK 2 SEL" },
269 	{ "OUT 7", "OUT 7", "SINK 2 SEL" },
270 	{ "OUT 0", "OUT 0", "SINK 3 SEL" },
271 	{ "OUT 1", "OUT 1", "SINK 3 SEL" },
272 	{ "OUT 2", "OUT 2", "SINK 3 SEL" },
273 	{ "OUT 3", "OUT 3", "SINK 3 SEL" },
274 	{ "OUT 4", "OUT 4", "SINK 3 SEL" },
275 	{ "OUT 5", "OUT 5", "SINK 3 SEL" },
276 	{ "OUT 6", "OUT 6", "SINK 3 SEL" },
277 	{ "OUT 7", "OUT 7", "SINK 3 SEL" },
278 };
279 
280 static const struct snd_soc_component_driver g12a_frddr_component_drv = {
281 	.dapm_widgets		= g12a_frddr_dapm_widgets,
282 	.num_dapm_widgets	= ARRAY_SIZE(g12a_frddr_dapm_widgets),
283 	.dapm_routes		= g12a_frddr_dapm_routes,
284 	.num_dapm_routes	= ARRAY_SIZE(g12a_frddr_dapm_routes),
285 	.open			= axg_fifo_pcm_open,
286 	.close			= axg_fifo_pcm_close,
287 	.hw_params		= g12a_fifo_pcm_hw_params,
288 	.hw_free		= axg_fifo_pcm_hw_free,
289 	.pointer		= axg_fifo_pcm_pointer,
290 	.trigger		= axg_fifo_pcm_trigger,
291 	.legacy_dai_naming	= 1,
292 };
293 
294 static const struct axg_fifo_match_data g12a_frddr_match_data = {
295 	.field_threshold	= REG_FIELD(FIFO_CTRL1, 16, 23),
296 	.component_drv		= &g12a_frddr_component_drv,
297 	.dai_drv		= &g12a_frddr_dai_drv
298 };
299 
300 /* On SM1, the output selection in on CTRL2 */
301 static const struct snd_kcontrol_new sm1_frddr_out1_enable =
302 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
303 				    CTRL2_SEL1_EN_SHIFT, 1, 0);
304 static const struct snd_kcontrol_new sm1_frddr_out2_enable =
305 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
306 				    CTRL2_SEL2_EN_SHIFT, 1, 0);
307 static const struct snd_kcontrol_new sm1_frddr_out3_enable =
308 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
309 				    CTRL2_SEL3_EN_SHIFT, 1, 0);
310 
311 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel1_enum, FIFO_CTRL2, CTRL2_SEL1_SHIFT,
312 			    axg_frddr_sel_texts);
313 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel2_enum, FIFO_CTRL2, CTRL2_SEL2_SHIFT,
314 			    axg_frddr_sel_texts);
315 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel3_enum, FIFO_CTRL2, CTRL2_SEL3_SHIFT,
316 			    axg_frddr_sel_texts);
317 
318 static const struct snd_kcontrol_new sm1_frddr_out1_demux =
319 	SOC_DAPM_ENUM("Output Src 1", sm1_frddr_sel1_enum);
320 static const struct snd_kcontrol_new sm1_frddr_out2_demux =
321 	SOC_DAPM_ENUM("Output Src 2", sm1_frddr_sel2_enum);
322 static const struct snd_kcontrol_new sm1_frddr_out3_demux =
323 	SOC_DAPM_ENUM("Output Src 3", sm1_frddr_sel3_enum);
324 
325 static const struct snd_soc_dapm_widget sm1_frddr_dapm_widgets[] = {
326 	SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
327 	SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
328 	SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
329 	SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
330 			    &sm1_frddr_out1_enable),
331 	SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
332 			    &sm1_frddr_out2_enable),
333 	SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
334 			    &sm1_frddr_out3_enable),
335 	SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
336 			   &sm1_frddr_out1_demux),
337 	SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
338 			   &sm1_frddr_out2_demux),
339 	SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
340 			   &sm1_frddr_out3_demux),
341 	SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
342 	SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
343 	SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
344 	SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
345 	SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
346 	SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
347 	SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
348 	SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
349 };
350 
351 static const struct snd_soc_component_driver sm1_frddr_component_drv = {
352 	.dapm_widgets		= sm1_frddr_dapm_widgets,
353 	.num_dapm_widgets	= ARRAY_SIZE(sm1_frddr_dapm_widgets),
354 	.dapm_routes		= g12a_frddr_dapm_routes,
355 	.num_dapm_routes	= ARRAY_SIZE(g12a_frddr_dapm_routes),
356 	.open			= axg_fifo_pcm_open,
357 	.close			= axg_fifo_pcm_close,
358 	.hw_params		= g12a_fifo_pcm_hw_params,
359 	.hw_free		= axg_fifo_pcm_hw_free,
360 	.pointer		= axg_fifo_pcm_pointer,
361 	.trigger		= axg_fifo_pcm_trigger,
362 	.legacy_dai_naming	= 1,
363 };
364 
365 static const struct axg_fifo_match_data sm1_frddr_match_data = {
366 	.field_threshold	= REG_FIELD(FIFO_CTRL1, 16, 23),
367 	.component_drv		= &sm1_frddr_component_drv,
368 	.dai_drv		= &g12a_frddr_dai_drv
369 };
370 
371 static const struct of_device_id axg_frddr_of_match[] = {
372 	{
373 		.compatible = "amlogic,axg-frddr",
374 		.data = &axg_frddr_match_data,
375 	}, {
376 		.compatible = "amlogic,g12a-frddr",
377 		.data = &g12a_frddr_match_data,
378 	}, {
379 		.compatible = "amlogic,sm1-frddr",
380 		.data = &sm1_frddr_match_data,
381 	}, {}
382 };
383 MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
384 
385 static struct platform_driver axg_frddr_pdrv = {
386 	.probe = axg_fifo_probe,
387 	.driver = {
388 		.name = "axg-frddr",
389 		.of_match_table = axg_frddr_of_match,
390 	},
391 };
392 module_platform_driver(axg_frddr_pdrv);
393 
394 MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");
395 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
396 MODULE_LICENSE("GPL v2");
397