1 /*
2 * QEMU AVR CPU
3 *
4 * Copyright (c) 2019-2020 Michael Rolnik
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
25 #include "exec/translation-block.h"
26 #include "cpu.h"
27 #include "disas/dis-asm.h"
28 #include "tcg/debug-assert.h"
29 #include "hw/qdev-properties.h"
30
avr_cpu_set_pc(CPUState * cs,vaddr value)31 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33 AVRCPU *cpu = AVR_CPU(cs);
34
35 cpu->env.pc_w = value / 2; /* internally PC points to words */
36 }
37
avr_cpu_get_pc(CPUState * cs)38 static vaddr avr_cpu_get_pc(CPUState *cs)
39 {
40 AVRCPU *cpu = AVR_CPU(cs);
41
42 return cpu->env.pc_w * 2;
43 }
44
avr_cpu_has_work(CPUState * cs)45 static bool avr_cpu_has_work(CPUState *cs)
46 {
47 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
48 && cpu_interrupts_enabled(cpu_env(cs));
49 }
50
avr_cpu_mmu_index(CPUState * cs,bool ifetch)51 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
52 {
53 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
54 }
55
avr_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)56 static void avr_cpu_synchronize_from_tb(CPUState *cs,
57 const TranslationBlock *tb)
58 {
59 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
60 cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */
61 }
62
avr_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)63 static void avr_restore_state_to_opc(CPUState *cs,
64 const TranslationBlock *tb,
65 const uint64_t *data)
66 {
67 cpu_env(cs)->pc_w = data[0];
68 }
69
avr_cpu_reset_hold(Object * obj,ResetType type)70 static void avr_cpu_reset_hold(Object *obj, ResetType type)
71 {
72 CPUState *cs = CPU(obj);
73 AVRCPU *cpu = AVR_CPU(cs);
74 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj);
75 CPUAVRState *env = &cpu->env;
76
77 if (mcc->parent_phases.hold) {
78 mcc->parent_phases.hold(obj, type);
79 }
80
81 env->pc_w = 0;
82 env->sregI = 1;
83 env->sregC = 0;
84 env->sregZ = 0;
85 env->sregN = 0;
86 env->sregV = 0;
87 env->sregS = 0;
88 env->sregH = 0;
89 env->sregT = 0;
90
91 env->rampD = 0;
92 env->rampX = 0;
93 env->rampY = 0;
94 env->rampZ = 0;
95 env->eind = 0;
96 env->sp = cpu->init_sp;
97
98 env->skip = 0;
99
100 memset(env->r, 0, sizeof(env->r));
101 }
102
avr_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)103 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
104 {
105 info->endian = BFD_ENDIAN_LITTLE;
106 info->mach = bfd_arch_avr;
107 info->print_insn = avr_print_insn;
108 }
109
avr_cpu_realizefn(DeviceState * dev,Error ** errp)110 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
111 {
112 CPUState *cs = CPU(dev);
113 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
114 Error *local_err = NULL;
115
116 cpu_exec_realizefn(cs, &local_err);
117 if (local_err != NULL) {
118 error_propagate(errp, local_err);
119 return;
120 }
121 qemu_init_vcpu(cs);
122 cpu_reset(cs);
123
124 mcc->parent_realize(dev, errp);
125 }
126
avr_cpu_set_int(void * opaque,int irq,int level)127 static void avr_cpu_set_int(void *opaque, int irq, int level)
128 {
129 AVRCPU *cpu = opaque;
130 CPUAVRState *env = &cpu->env;
131 CPUState *cs = CPU(cpu);
132 uint64_t mask = (1ull << irq);
133
134 if (level) {
135 env->intsrc |= mask;
136 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
137 } else {
138 env->intsrc &= ~mask;
139 if (env->intsrc == 0) {
140 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
141 }
142 }
143 }
144
avr_cpu_initfn(Object * obj)145 static void avr_cpu_initfn(Object *obj)
146 {
147 AVRCPU *cpu = AVR_CPU(obj);
148
149 /* Set the number of interrupts supported by the CPU. */
150 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
151 sizeof(cpu->env.intsrc) * 8);
152 }
153
154 static const Property avr_cpu_properties[] = {
155 DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0),
156 };
157
avr_cpu_class_by_name(const char * cpu_model)158 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
159 {
160 return object_class_by_name(cpu_model);
161 }
162
avr_cpu_dump_state(CPUState * cs,FILE * f,int flags)163 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
164 {
165 CPUAVRState *env = cpu_env(cs);
166 int i;
167
168 qemu_fprintf(f, "\n");
169 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */
170 qemu_fprintf(f, "SP: %04x\n", env->sp);
171 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
172 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
173 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
174 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
175 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
176 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
177 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
178 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
179 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
180 env->sregI ? 'I' : '-',
181 env->sregT ? 'T' : '-',
182 env->sregH ? 'H' : '-',
183 env->sregS ? 'S' : '-',
184 env->sregV ? 'V' : '-',
185 env->sregN ? '-' : 'N', /* Zf has negative logic */
186 env->sregZ ? 'Z' : '-',
187 env->sregC ? 'I' : '-');
188 qemu_fprintf(f, "SKIP: %02x\n", env->skip);
189
190 qemu_fprintf(f, "\n");
191 for (i = 0; i < ARRAY_SIZE(env->r); i++) {
192 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
193
194 if ((i % 8) == 7) {
195 qemu_fprintf(f, "\n");
196 }
197 }
198 qemu_fprintf(f, "\n");
199 }
200
201 #include "hw/core/sysemu-cpu-ops.h"
202
203 static const struct SysemuCPUOps avr_sysemu_ops = {
204 .has_work = avr_cpu_has_work,
205 .get_phys_page_debug = avr_cpu_get_phys_page_debug,
206 };
207
208 #include "accel/tcg/cpu-ops.h"
209
210 static const TCGCPUOps avr_tcg_ops = {
211 .initialize = avr_cpu_tcg_init,
212 .translate_code = avr_cpu_translate_code,
213 .synchronize_from_tb = avr_cpu_synchronize_from_tb,
214 .restore_state_to_opc = avr_restore_state_to_opc,
215 .cpu_exec_interrupt = avr_cpu_exec_interrupt,
216 .cpu_exec_halt = avr_cpu_has_work,
217 .tlb_fill = avr_cpu_tlb_fill,
218 .do_interrupt = avr_cpu_do_interrupt,
219 };
220
avr_cpu_class_init(ObjectClass * oc,void * data)221 static void avr_cpu_class_init(ObjectClass *oc, void *data)
222 {
223 DeviceClass *dc = DEVICE_CLASS(oc);
224 CPUClass *cc = CPU_CLASS(oc);
225 AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
226 ResettableClass *rc = RESETTABLE_CLASS(oc);
227
228 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
229
230 device_class_set_props(dc, avr_cpu_properties);
231
232 resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
233 &mcc->parent_phases);
234
235 cc->class_by_name = avr_cpu_class_by_name;
236
237 cc->mmu_index = avr_cpu_mmu_index;
238 cc->dump_state = avr_cpu_dump_state;
239 cc->set_pc = avr_cpu_set_pc;
240 cc->get_pc = avr_cpu_get_pc;
241 dc->vmsd = &vms_avr_cpu;
242 cc->sysemu_ops = &avr_sysemu_ops;
243 cc->disas_set_info = avr_cpu_disas_set_info;
244 cc->gdb_read_register = avr_cpu_gdb_read_register;
245 cc->gdb_write_register = avr_cpu_gdb_write_register;
246 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
247 cc->gdb_core_xml_file = "avr-cpu.xml";
248 cc->tcg_ops = &avr_tcg_ops;
249 }
250
251 /*
252 * Setting features of AVR core type avr5
253 * --------------------------------------
254 *
255 * This type of AVR core is present in the following AVR MCUs:
256 *
257 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
258 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
259 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
260 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
261 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
262 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
263 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
264 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
265 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
266 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
267 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
268 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
269 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
270 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
271 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
272 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
273 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
274 */
avr_avr5_initfn(Object * obj)275 static void avr_avr5_initfn(Object *obj)
276 {
277 CPUAVRState *env = cpu_env(CPU(obj));
278
279 set_avr_feature(env, AVR_FEATURE_LPM);
280 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
281 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
282 set_avr_feature(env, AVR_FEATURE_SRAM);
283 set_avr_feature(env, AVR_FEATURE_BREAK);
284
285 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
286 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
287 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
288 set_avr_feature(env, AVR_FEATURE_LPMX);
289 set_avr_feature(env, AVR_FEATURE_MOVW);
290 set_avr_feature(env, AVR_FEATURE_MUL);
291 }
292
293 /*
294 * Setting features of AVR core type avr51
295 * --------------------------------------
296 *
297 * This type of AVR core is present in the following AVR MCUs:
298 *
299 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
300 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
301 * at90usb1287
302 */
avr_avr51_initfn(Object * obj)303 static void avr_avr51_initfn(Object *obj)
304 {
305 CPUAVRState *env = cpu_env(CPU(obj));
306
307 set_avr_feature(env, AVR_FEATURE_LPM);
308 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
309 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
310 set_avr_feature(env, AVR_FEATURE_SRAM);
311 set_avr_feature(env, AVR_FEATURE_BREAK);
312
313 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
314 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
315 set_avr_feature(env, AVR_FEATURE_RAMPZ);
316 set_avr_feature(env, AVR_FEATURE_ELPMX);
317 set_avr_feature(env, AVR_FEATURE_ELPM);
318 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
319 set_avr_feature(env, AVR_FEATURE_LPMX);
320 set_avr_feature(env, AVR_FEATURE_MOVW);
321 set_avr_feature(env, AVR_FEATURE_MUL);
322 }
323
324 /*
325 * Setting features of AVR core type avr6
326 * --------------------------------------
327 *
328 * This type of AVR core is present in the following AVR MCUs:
329 *
330 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
331 */
avr_avr6_initfn(Object * obj)332 static void avr_avr6_initfn(Object *obj)
333 {
334 CPUAVRState *env = cpu_env(CPU(obj));
335
336 set_avr_feature(env, AVR_FEATURE_LPM);
337 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
338 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
339 set_avr_feature(env, AVR_FEATURE_SRAM);
340 set_avr_feature(env, AVR_FEATURE_BREAK);
341
342 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
343 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
344 set_avr_feature(env, AVR_FEATURE_RAMPZ);
345 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
346 set_avr_feature(env, AVR_FEATURE_ELPMX);
347 set_avr_feature(env, AVR_FEATURE_ELPM);
348 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
349 set_avr_feature(env, AVR_FEATURE_LPMX);
350 set_avr_feature(env, AVR_FEATURE_MOVW);
351 set_avr_feature(env, AVR_FEATURE_MUL);
352 }
353
354 typedef struct AVRCPUInfo {
355 const char *name;
356 void (*initfn)(Object *obj);
357 } AVRCPUInfo;
358
359
360 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
361 { \
362 .parent = TYPE_AVR_CPU, \
363 .instance_init = initfn, \
364 .name = AVR_CPU_TYPE_NAME(model), \
365 }
366
367 static const TypeInfo avr_cpu_type_info[] = {
368 {
369 .name = TYPE_AVR_CPU,
370 .parent = TYPE_CPU,
371 .instance_size = sizeof(AVRCPU),
372 .instance_align = __alignof(AVRCPU),
373 .instance_init = avr_cpu_initfn,
374 .class_size = sizeof(AVRCPUClass),
375 .class_init = avr_cpu_class_init,
376 .abstract = true,
377 },
378 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
379 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
380 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
381 };
382
383 DEFINE_TYPES(avr_cpu_type_info)
384