1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright (C) 2016 Grinn
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/litesom.h>
12 #include <asm/arch/mx6ul_pins.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/io.h>
19 #include <common.h>
20 #include <fsl_esdhc.h>
21 #include <linux/sizes.h>
22 #include <linux/fb.h>
23 #include <miiphy.h>
24 #include <mmc.h>
25 #include <netdev.h>
26 #include <spl.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33
34 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
36 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
39 PAD_CTL_SPEED_HIGH | \
40 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
41
42 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
44
45 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46
47 static iomux_v3_cfg_t const uart1_pads[] = {
48 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
49 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
50 };
51
52 static iomux_v3_cfg_t const sd_pads[] = {
53 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59
60 /* CD */
61 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
62 };
63
setup_iomux_uart(void)64 static void setup_iomux_uart(void)
65 {
66 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
67 }
68
69 #ifdef CONFIG_FSL_ESDHC
70 static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
71
72 #define SD_CD_GPIO IMX_GPIO_NR(1, 19)
73
mmc_get_env_devno(void)74 static int mmc_get_env_devno(void)
75 {
76 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
77 int dev_no;
78 u32 bootsel;
79
80 bootsel = (soc_sbmr & 0x000000FF) >> 6;
81
82 /* If not boot from sd/mmc, use default value */
83 if (bootsel != 1)
84 return CONFIG_SYS_MMC_ENV_DEV;
85
86 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
87 dev_no = (soc_sbmr & 0x00001800) >> 11;
88
89 return dev_no;
90 }
91
board_mmc_getcd(struct mmc * mmc)92 int board_mmc_getcd(struct mmc *mmc)
93 {
94 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
95 int ret = 0;
96
97 switch (cfg->esdhc_base) {
98 case USDHC1_BASE_ADDR:
99 ret = !gpio_get_value(SD_CD_GPIO);
100 break;
101 case USDHC2_BASE_ADDR:
102 ret = 1;
103 break;
104 }
105
106 return ret;
107 }
108
board_mmc_init(bd_t * bis)109 int board_mmc_init(bd_t *bis)
110 {
111 int ret;
112
113 /* SD */
114 imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
115 gpio_direction_input(SD_CD_GPIO);
116 sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
117
118 ret = fsl_esdhc_initialize(bis, &sd_cfg);
119 if (ret) {
120 printf("Warning: failed to initialize mmc dev 0 (SD)\n");
121 return ret;
122 }
123
124 return litesom_mmc_init(bis);
125 }
126
check_mmc_autodetect(void)127 static int check_mmc_autodetect(void)
128 {
129 char *autodetect_str = env_get("mmcautodetect");
130
131 if ((autodetect_str != NULL) &&
132 (strcmp(autodetect_str, "yes") == 0)) {
133 return 1;
134 }
135
136 return 0;
137 }
138
board_late_mmc_init(void)139 void board_late_mmc_init(void)
140 {
141 char cmd[32];
142 char mmcblk[32];
143 u32 dev_no = mmc_get_env_devno();
144
145 if (!check_mmc_autodetect())
146 return;
147
148 env_set_ulong("mmcdev", dev_no);
149
150 /* Set mmcblk env */
151 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
152 dev_no);
153 env_set("mmcroot", mmcblk);
154
155 sprintf(cmd, "mmc dev %d", dev_no);
156 run_command(cmd, 0);
157 }
158 #endif
159
160 #ifdef CONFIG_FEC_MXC
setup_fec(void)161 static int setup_fec(void)
162 {
163 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
164 int ret;
165
166 /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
167 set gpr1[17]*/
168 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
169 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
170
171 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
172 if (ret)
173 return ret;
174
175 enable_enet_clk(1);
176
177 return 0;
178 }
179 #endif
180
board_early_init_f(void)181 int board_early_init_f(void)
182 {
183 setup_iomux_uart();
184
185 return 0;
186 }
187
board_init(void)188 int board_init(void)
189 {
190 /* Address of boot parameters */
191 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
192
193 #ifdef CONFIG_FEC_MXC
194 setup_fec();
195 #endif
196
197 return 0;
198 }
199
200 #ifdef CONFIG_CMD_BMODE
201 static const struct boot_mode board_boot_modes[] = {
202 /* 4 bit bus width */
203 {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
204 {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
205 {NULL, 0},
206 };
207 #endif
208
board_late_init(void)209 int board_late_init(void)
210 {
211 #ifdef CONFIG_CMD_BMODE
212 add_board_boot_modes(board_boot_modes);
213 #endif
214
215 #ifdef CONFIG_ENV_IS_IN_MMC
216 board_late_mmc_init();
217 #endif
218
219 return 0;
220 }
221
checkboard(void)222 int checkboard(void)
223 {
224 puts("Board: Grinn liteBoard\n");
225
226 return 0;
227 }
228
229 #ifdef CONFIG_SPL_BUILD
board_boot_order(u32 * spl_boot_list)230 void board_boot_order(u32 *spl_boot_list)
231 {
232 struct src *psrc = (struct src *)SRC_BASE_ADDR;
233 unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
234 unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
235 unsigned port = (reg >> 11) & 0x1;
236
237 if (port == 0) {
238 spl_boot_list[0] = BOOT_DEVICE_MMC1;
239 spl_boot_list[1] = BOOT_DEVICE_MMC2;
240 } else {
241 spl_boot_list[0] = BOOT_DEVICE_MMC2;
242 spl_boot_list[1] = BOOT_DEVICE_MMC1;
243 }
244 }
245
board_init_f(ulong dummy)246 void board_init_f(ulong dummy)
247 {
248 litesom_init_f();
249 }
250 #endif
251