xref: /openbmc/linux/include/sound/vx_core.h (revision f8ae2d29)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Driver for Digigram VX soundcards
4  *
5  * Hardware core part
6  *
7  * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
8  */
9 
10 #ifndef __SOUND_VX_COMMON_H
11 #define __SOUND_VX_COMMON_H
12 
13 #include <sound/pcm.h>
14 #include <sound/hwdep.h>
15 #include <linux/interrupt.h>
16 
17 struct firmware;
18 struct device;
19 
20 #define VX_DRIVER_VERSION	0x010000	/* 1.0.0 */
21 
22 /*
23  */
24 #define SIZE_MAX_CMD    0x10
25 #define SIZE_MAX_STATUS 0x10
26 
27 struct vx_rmh {
28 	u16	LgCmd;		/* length of the command to send (WORDs) */
29 	u16	LgStat;		/* length of the status received (WORDs) */
30 	u32	Cmd[SIZE_MAX_CMD];
31 	u32	Stat[SIZE_MAX_STATUS];
32 	u16	DspStat;	/* status type, RMP_SSIZE_XXX */
33 };
34 
35 typedef u64 pcx_time_t;
36 
37 #define VX_MAX_PIPES	16
38 #define VX_MAX_PERIODS	32
39 #define VX_MAX_CODECS	2
40 
41 struct vx_ibl_info {
42 	int size;	/* the current IBL size (0 = query) in bytes */
43 	int max_size;	/* max. IBL size in bytes */
44 	int min_size;	/* min. IBL size in bytes */
45 	int granularity;	/* granularity */
46 };
47 
48 struct vx_pipe {
49 	int number;
50 	unsigned int is_capture: 1;
51 	unsigned int data_mode: 1;
52 	unsigned int running: 1;
53 	unsigned int prepared: 1;
54 	int channels;
55 	unsigned int differed_type;
56 	pcx_time_t pcx_time;
57 	struct snd_pcm_substream *substream;
58 
59 	int hbuf_size;		/* H-buffer size in bytes */
60 	int buffer_bytes;	/* the ALSA pcm buffer size in bytes */
61 	int period_bytes;	/* the ALSA pcm period size in bytes */
62 	int hw_ptr;		/* the current hardware pointer in bytes */
63 	int position;		/* the current position in frames (playback only) */
64 	int transferred;	/* the transferred size (per period) in frames */
65 	int align;		/* size of alignment */
66 	u64 cur_count;		/* current sample position (for playback) */
67 
68 	unsigned int references;     /* an output pipe may be used for monitoring and/or playback */
69 	struct vx_pipe *monitoring_pipe;  /* pointer to the monitoring pipe (capture pipe only)*/
70 };
71 
72 struct vx_core;
73 
74 struct snd_vx_ops {
75 	/* low-level i/o */
76 	unsigned char (*in8)(struct vx_core *chip, int reg);
77 	unsigned int (*in32)(struct vx_core *chip, int reg);
78 	void (*out8)(struct vx_core *chip, int reg, unsigned char val);
79 	void (*out32)(struct vx_core *chip, int reg, unsigned int val);
80 	/* irq */
81 	int (*test_and_ack)(struct vx_core *chip);
82 	void (*validate_irq)(struct vx_core *chip, int enable);
83 	/* codec */
84 	void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
85 	void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
86 	void (*reset_codec)(struct vx_core *chip);
87 	void (*change_audio_source)(struct vx_core *chip, int src);
88 	void (*set_clock_source)(struct vx_core *chp, int src);
89 	/* chip init */
90 	int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
91 	void (*reset_dsp)(struct vx_core *chip);
92 	void (*reset_board)(struct vx_core *chip, int cold_reset);
93 	int (*add_controls)(struct vx_core *chip);
94 	/* pcm */
95 	void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
96 			  struct vx_pipe *pipe, int count);
97 	void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
98 			  struct vx_pipe *pipe, int count);
99 };
100 
101 struct snd_vx_hardware {
102 	const char *name;
103 	int type;	/* VX_TYPE_XXX */
104 
105 	/* hardware specs */
106 	unsigned int num_codecs;
107 	unsigned int num_ins;
108 	unsigned int num_outs;
109 	unsigned int output_level_max;
110 	const unsigned int *output_level_db_scale;
111 };
112 
113 /* hwdep id string */
114 #define SND_VX_HWDEP_ID		"VX Loader"
115 
116 /* hardware type */
117 enum {
118 	/* VX222 PCI */
119 	VX_TYPE_BOARD,		/* old VX222 PCI */
120 	VX_TYPE_V2,		/* VX222 V2 PCI */
121 	VX_TYPE_MIC,		/* VX222 Mic PCI */
122 	/* VX-pocket */
123 	VX_TYPE_VXPOCKET,	/* VXpocket V2 */
124 	VX_TYPE_VXP440,		/* VXpocket 440 */
125 	VX_TYPE_NUMS
126 };
127 
128 /* chip status */
129 enum {
130 	VX_STAT_XILINX_LOADED	= (1 << 0),	/* devices are registered */
131 	VX_STAT_DEVICE_INIT	= (1 << 1),	/* devices are registered */
132 	VX_STAT_CHIP_INIT	= (1 << 2),	/* all operational */
133 	VX_STAT_IN_SUSPEND	= (1 << 10),	/* in suspend phase */
134 	VX_STAT_IS_STALE	= (1 << 15)	/* device is stale */
135 };
136 
137 /* min/max values for analog output for old codecs */
138 #define VX_ANALOG_OUT_LEVEL_MAX		0xe3
139 
140 struct vx_core {
141 	/* ALSA stuff */
142 	struct snd_card *card;
143 	struct snd_pcm *pcm[VX_MAX_CODECS];
144 	int type;	/* VX_TYPE_XXX */
145 
146 	int irq;
147 	/* ports are defined externally */
148 
149 	/* low-level functions */
150 	const struct snd_vx_hardware *hw;
151 	const struct snd_vx_ops *ops;
152 
153 	struct mutex lock;
154 
155 	unsigned int chip_status;
156 	unsigned int pcm_running;
157 
158 	struct device *dev;
159 	struct snd_hwdep *hwdep;
160 
161 	struct vx_rmh irq_rmh;	/* RMH used in interrupts */
162 
163 	unsigned int audio_info; /* see VX_AUDIO_INFO */
164 	unsigned int audio_ins;
165 	unsigned int audio_outs;
166 	struct vx_pipe **playback_pipes;
167 	struct vx_pipe **capture_pipes;
168 
169 	/* clock and audio sources */
170 	unsigned int audio_source;	/* current audio input source */
171 	unsigned int audio_source_target;
172 	unsigned int clock_mode;	/* clock mode (VX_CLOCK_MODE_XXX) */
173 	unsigned int clock_source;	/* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
174 	unsigned int freq;		/* current frequency */
175 	unsigned int freq_detected;	/* detected frequency from digital in */
176 	unsigned int uer_detected;	/* VX_UER_MODE_XXX */
177 	unsigned int uer_bits;	/* IEC958 status bits */
178 	struct vx_ibl_info ibl;	/* IBL information */
179 
180 	/* mixer setting */
181 	int output_level[VX_MAX_CODECS][2];	/* analog output level */
182 	int audio_gain[2][4];			/* digital audio level (playback/capture) */
183 	unsigned char audio_active[4];		/* mute/unmute on digital playback */
184 	int audio_monitor[4];			/* playback hw-monitor level */
185 	unsigned char audio_monitor_active[4];	/* playback hw-monitor mute/unmute */
186 
187 	struct mutex mixer_mutex;
188 
189 	const struct firmware *firmware[4]; /* loaded firmware data */
190 };
191 
192 
193 /*
194  * constructor
195  */
196 struct vx_core *snd_vx_create(struct snd_card *card,
197 			      const struct snd_vx_hardware *hw,
198 			      const struct snd_vx_ops *ops, int extra_size);
199 int snd_vx_setup_firmware(struct vx_core *chip);
200 int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
201 int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
202 int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
203 
204 void snd_vx_free_firmware(struct vx_core *chip);
205 
206 /*
207  * interrupt handler; exported for pcmcia
208  */
209 irqreturn_t snd_vx_irq_handler(int irq, void *dev);
210 irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev);
211 
212 /*
213  * lowlevel functions
214  */
vx_test_and_ack(struct vx_core * chip)215 static inline int vx_test_and_ack(struct vx_core *chip)
216 {
217 	return chip->ops->test_and_ack(chip);
218 }
219 
vx_validate_irq(struct vx_core * chip,int enable)220 static inline void vx_validate_irq(struct vx_core *chip, int enable)
221 {
222 	chip->ops->validate_irq(chip, enable);
223 }
224 
snd_vx_inb(struct vx_core * chip,int reg)225 static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
226 {
227 	return chip->ops->in8(chip, reg);
228 }
229 
snd_vx_inl(struct vx_core * chip,int reg)230 static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
231 {
232 	return chip->ops->in32(chip, reg);
233 }
234 
snd_vx_outb(struct vx_core * chip,int reg,unsigned char val)235 static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
236 {
237 	chip->ops->out8(chip, reg, val);
238 }
239 
snd_vx_outl(struct vx_core * chip,int reg,unsigned int val)240 static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
241 {
242 	chip->ops->out32(chip, reg, val);
243 }
244 
245 #define vx_inb(chip,reg)	snd_vx_inb(chip, VX_##reg)
246 #define vx_outb(chip,reg,val)	snd_vx_outb(chip, VX_##reg,val)
247 #define vx_inl(chip,reg)	snd_vx_inl(chip, VX_##reg)
248 #define vx_outl(chip,reg,val)	snd_vx_outl(chip, VX_##reg,val)
249 
vx_reset_dsp(struct vx_core * chip)250 static inline void vx_reset_dsp(struct vx_core *chip)
251 {
252 	chip->ops->reset_dsp(chip);
253 }
254 
255 int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
256 int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
257 int vx_send_rih(struct vx_core *chip, int cmd);
258 int vx_send_rih_nolock(struct vx_core *chip, int cmd);
259 
260 void vx_reset_codec(struct vx_core *chip, int cold_reset);
261 
262 /*
263  * check the bit on the specified register
264  * returns zero if a bit matches, or a negative error code.
265  * exported for vxpocket driver
266  */
267 int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
268 #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
269 #define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
270 #define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
271 
272 
273 /*
274  * pseudo-DMA transfer
275  */
vx_pseudo_dma_write(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)276 static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
277 				       struct vx_pipe *pipe, int count)
278 {
279 	chip->ops->dma_write(chip, runtime, pipe, count);
280 }
281 
vx_pseudo_dma_read(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)282 static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
283 				      struct vx_pipe *pipe, int count)
284 {
285 	chip->ops->dma_read(chip, runtime, pipe, count);
286 }
287 
288 
289 
290 /* error with hardware code,
291  * the return value is -(VX_ERR_MASK | actual-hw-error-code)
292  */
293 #define VX_ERR_MASK	0x1000000
294 #define vx_get_error(err)	(-(err) & ~VX_ERR_MASK)
295 
296 
297 /*
298  * pcm stuff
299  */
300 int snd_vx_pcm_new(struct vx_core *chip);
301 void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
302 
303 /*
304  * mixer stuff
305  */
306 int snd_vx_mixer_new(struct vx_core *chip);
307 void vx_toggle_dac_mute(struct vx_core *chip, int mute);
308 int vx_sync_audio_source(struct vx_core *chip);
309 int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
310 
311 /*
312  * IEC958 & clock stuff
313  */
314 void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
315 int vx_set_clock(struct vx_core *chip, unsigned int freq);
316 void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
317 int vx_change_frequency(struct vx_core *chip);
318 
319 
320 /*
321  * PM
322  */
323 int snd_vx_suspend(struct vx_core *card);
324 int snd_vx_resume(struct vx_core *card);
325 
326 /*
327  * hardware constants
328  */
329 
330 #define vx_has_new_dsp(chip)	((chip)->type != VX_TYPE_BOARD)
331 #define vx_is_pcmcia(chip)	((chip)->type >= VX_TYPE_VXPOCKET)
332 
333 /* audio input source */
334 enum {
335 	VX_AUDIO_SRC_DIGITAL,
336 	VX_AUDIO_SRC_LINE,
337 	VX_AUDIO_SRC_MIC
338 };
339 
340 /* clock source */
341 enum {
342 	INTERNAL_QUARTZ,
343 	UER_SYNC
344 };
345 
346 /* clock mode */
347 enum {
348 	VX_CLOCK_MODE_AUTO,	/* depending on the current audio source */
349 	VX_CLOCK_MODE_INTERNAL,	/* fixed to internal quartz */
350 	VX_CLOCK_MODE_EXTERNAL	/* fixed to UER sync */
351 };
352 
353 /* SPDIF/UER type */
354 enum {
355 	VX_UER_MODE_CONSUMER,
356 	VX_UER_MODE_PROFESSIONAL,
357 	VX_UER_MODE_NOT_PRESENT,
358 };
359 
360 /* register indices */
361 enum {
362 	VX_ICR,
363 	VX_CVR,
364 	VX_ISR,
365 	VX_IVR,
366 	VX_RXH,
367 	VX_TXH = VX_RXH,
368 	VX_RXM,
369 	VX_TXM = VX_RXM,
370 	VX_RXL,
371 	VX_TXL = VX_RXL,
372 	VX_DMA,
373 	VX_CDSP,
374 	VX_RFREQ,
375 	VX_RUER_V2,
376 	VX_GAIN,
377 	VX_DATA = VX_GAIN,
378 	VX_MEMIRQ,
379 	VX_ACQ,
380 	VX_BIT0,
381 	VX_BIT1,
382 	VX_MIC0,
383 	VX_MIC1,
384 	VX_MIC2,
385 	VX_MIC3,
386 	VX_PLX0,
387 	VX_PLX1,
388 	VX_PLX2,
389 
390 	VX_LOFREQ,  // V2: ACQ, VP: RFREQ
391 	VX_HIFREQ,  // V2: BIT0, VP: RUER_V2
392 	VX_CSUER,   // V2: BIT1, VP: BIT0
393 	VX_RUER,    // V2: RUER_V2, VP: BIT1
394 
395 	VX_REG_MAX,
396 
397 	/* aliases for VX board */
398 	VX_RESET_DMA = VX_ISR,
399 	VX_CFG = VX_RFREQ,
400 	VX_STATUS = VX_MEMIRQ,
401 	VX_SELMIC = VX_MIC0,
402 	VX_COMPOT = VX_MIC1,
403 	VX_SCOMPR = VX_MIC2,
404 	VX_GLIMIT = VX_MIC3,
405 	VX_INTCSR = VX_PLX0,
406 	VX_CNTRL = VX_PLX1,
407 	VX_GPIOC = VX_PLX2,
408 
409 	/* aliases for VXPOCKET board */
410 	VX_MICRO = VX_MEMIRQ,
411 	VX_CODEC2 = VX_MEMIRQ,
412 	VX_DIALOG = VX_ACQ,
413 
414 };
415 
416 /* RMH status type */
417 enum {
418 	RMH_SSIZE_FIXED = 0,	/* status size given by the driver (in LgStat) */
419 	RMH_SSIZE_ARG = 1,	/* status size given in the LSB byte */
420 	RMH_SSIZE_MASK = 2,	/* status size given in bitmask */
421 };
422 
423 
424 /* bits for ICR register */
425 #define ICR_HF1		0x10
426 #define ICR_HF0		0x08
427 #define ICR_TREQ	0x02	/* Interrupt mode + HREQ set on for transfer (->DSP) request */
428 #define ICR_RREQ	0x01	/* Interrupt mode + RREQ set on for transfer (->PC) request */
429 
430 /* bits for CVR register */
431 #define CVR_HC		0x80
432 
433 /* bits for ISR register */
434 #define ISR_HF3		0x10
435 #define ISR_HF2		0x08
436 #define ISR_CHK		0x10
437 #define ISR_ERR		0x08
438 #define ISR_TX_READY	0x04
439 #define ISR_TX_EMPTY	0x02
440 #define ISR_RX_FULL	0x01
441 
442 /* Constants used to access the DATA register */
443 #define VX_DATA_CODEC_MASK	0x80
444 #define VX_DATA_XICOR_MASK	0x80
445 
446 /* Constants used to access the CSUER register (both for VX2 and VXP) */
447 #define VX_SUER_FREQ_MASK		0x0c
448 #define VX_SUER_FREQ_32KHz_MASK		0x0c
449 #define VX_SUER_FREQ_44KHz_MASK		0x00
450 #define VX_SUER_FREQ_48KHz_MASK		0x04
451 #define VX_SUER_DATA_PRESENT_MASK	0x02
452 #define VX_SUER_CLOCK_PRESENT_MASK	0x01
453 
454 #define VX_CUER_HH_BITC_SEL_MASK	0x08
455 #define VX_CUER_MH_BITC_SEL_MASK	0x04
456 #define VX_CUER_ML_BITC_SEL_MASK	0x02
457 #define VX_CUER_LL_BITC_SEL_MASK	0x01
458 
459 #define XX_UER_CBITS_OFFSET_MASK	0x1f
460 
461 
462 /* bits for audio_info */
463 #define VX_AUDIO_INFO_REAL_TIME	(1<<0)	/* real-time processing available */
464 #define VX_AUDIO_INFO_OFFLINE	(1<<1)	/* offline processing available */
465 #define VX_AUDIO_INFO_MPEG1	(1<<5)
466 #define VX_AUDIO_INFO_MPEG2	(1<<6)
467 #define VX_AUDIO_INFO_LINEAR_8	(1<<7)
468 #define VX_AUDIO_INFO_LINEAR_16	(1<<8)
469 #define VX_AUDIO_INFO_LINEAR_24	(1<<9)
470 
471 /* DSP Interrupt Request values */
472 #define VXP_IRQ_OFFSET		0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
473 /* call with vx_send_irq_dsp() */
474 #define IRQ_MESS_WRITE_END          0x30
475 #define IRQ_MESS_WRITE_NEXT         0x32
476 #define IRQ_MESS_READ_NEXT          0x34
477 #define IRQ_MESS_READ_END           0x36
478 #define IRQ_MESSAGE                 0x38
479 #define IRQ_RESET_CHK               0x3A
480 #define IRQ_CONNECT_STREAM_NEXT     0x26
481 #define IRQ_CONNECT_STREAM_END      0x28
482 #define IRQ_PAUSE_START_CONNECT     0x2A
483 #define IRQ_END_CONNECTION          0x2C
484 
485 /* Is there async. events pending ( IT Source Test ) */
486 #define ASYNC_EVENTS_PENDING            0x008000
487 #define HBUFFER_EVENTS_PENDING          0x004000   // Not always accurate
488 #define NOTIF_EVENTS_PENDING            0x002000
489 #define TIME_CODE_EVENT_PENDING         0x001000
490 #define FREQUENCY_CHANGE_EVENT_PENDING  0x000800
491 #define END_OF_BUFFER_EVENTS_PENDING    0x000400
492 #define FATAL_DSP_ERROR                 0xff0000
493 
494 /* Stream Format Header Defines */
495 #define HEADER_FMT_BASE			0xFED00000
496 #define HEADER_FMT_MONO			0x000000C0
497 #define HEADER_FMT_INTEL		0x00008000
498 #define HEADER_FMT_16BITS		0x00002000
499 #define HEADER_FMT_24BITS		0x00004000
500 #define HEADER_FMT_UPTO11		0x00000200	/* frequency is less or equ. to 11k.*/
501 #define HEADER_FMT_UPTO32		0x00000100	/* frequency is over 11k and less then 32k.*/
502 
503 /* Constants used to access the Codec */
504 #define XX_CODEC_SELECTOR               0x20
505 /* codec commands */
506 #define XX_CODEC_ADC_CONTROL_REGISTER   0x01
507 #define XX_CODEC_DAC_CONTROL_REGISTER   0x02
508 #define XX_CODEC_LEVEL_LEFT_REGISTER    0x03
509 #define XX_CODEC_LEVEL_RIGHT_REGISTER   0x04
510 #define XX_CODEC_PORT_MODE_REGISTER     0x05
511 #define XX_CODEC_STATUS_REPORT_REGISTER 0x06
512 #define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
513 
514 /*
515  * Audio-level control values
516  */
517 #define CVAL_M110DB		0x000	/* -110dB */
518 #define CVAL_M99DB		0x02C
519 #define CVAL_M21DB		0x163
520 #define CVAL_M18DB		0x16F
521 #define CVAL_M10DB		0x18F
522 #define CVAL_0DB		0x1B7
523 #define CVAL_18DB		0x1FF	/* +18dB */
524 #define CVAL_MAX		0x1FF
525 
526 #define AUDIO_IO_HAS_MUTE_LEVEL			0x400000
527 #define AUDIO_IO_HAS_MUTE_MONITORING_1		0x200000
528 #define AUDIO_IO_HAS_MUTE_MONITORING_2		0x100000
529 #define VALID_AUDIO_IO_DIGITAL_LEVEL		0x01
530 #define VALID_AUDIO_IO_MONITORING_LEVEL		0x02
531 #define VALID_AUDIO_IO_MUTE_LEVEL		0x04
532 #define VALID_AUDIO_IO_MUTE_MONITORING_1	0x08
533 #define VALID_AUDIO_IO_MUTE_MONITORING_2	0x10
534 
535 
536 #endif /* __SOUND_VX_COMMON_H */
537